1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2017 Intel Deutschland GmbH
9 * Copyright(c) 2018 - 2019 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
22 * Copyright(c) 2017 Intel Deutschland GmbH
23 * Copyright(c) 2018 - 2019 Intel Corporation
24 * All rights reserved.
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions
30 * * Redistributions of source code must retain the above copyright
31 * notice, this list of conditions and the following disclaimer.
32 * * Redistributions in binary form must reproduce the above copyright
33 * notice, this list of conditions and the following disclaimer in
34 * the documentation and/or other materials provided with the
36 * * Neither the name Intel Corporation nor the names of its
37 * contributors may be used to endorse or promote products derived
38 * from this software without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
52 *****************************************************************************/
54 #include <linux/tcp.h>
56 #include "iwl-debug.h"
60 #include "fw/api/tx.h"
63 * iwl_pcie_gen2_tx_stop - Stop all Tx DMA channels
65 void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans)
67 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
71 * This function can be called before the op_mode disabled the
72 * queues. This happens when we have an rfkill interrupt.
73 * Since we stop Tx altogether - mark the queues as stopped.
75 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
76 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
78 /* Unmap DMA from host system and free skb's */
79 for (txq_id = 0; txq_id < ARRAY_SIZE(trans_pcie->txq); txq_id++) {
80 if (!trans_pcie->txq[txq_id])
82 iwl_pcie_gen2_txq_unmap(trans, txq_id);
87 * iwl_pcie_txq_update_byte_tbl - Set up entry in Tx byte-count array
89 static void iwl_pcie_gen2_update_byte_tbl(struct iwl_trans_pcie *trans_pcie,
90 struct iwl_txq *txq, u16 byte_cnt,
93 struct iwlagn_scd_bc_tbl *scd_bc_tbl = txq->bc_tbl.addr;
94 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
95 struct iwl_gen3_bc_tbl *scd_bc_tbl_gen3 = txq->bc_tbl.addr;
96 int idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
97 u8 filled_tfd_size, num_fetch_chunks;
101 if (WARN(idx >= txq->n_window, "%d >= %d\n", idx, txq->n_window))
104 filled_tfd_size = offsetof(struct iwl_tfh_tfd, tbs) +
105 num_tbs * sizeof(struct iwl_tfh_tb);
107 * filled_tfd_size contains the number of filled bytes in the TFD.
108 * Dividing it by 64 will give the number of chunks to fetch
109 * to SRAM- 0 for one chunk, 1 for 2 and so on.
110 * If, for example, TFD contains only 3 TBs then 32 bytes
111 * of the TFD are used, and only one chunk of 64 bytes should
114 num_fetch_chunks = DIV_ROUND_UP(filled_tfd_size, 64) - 1;
116 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
117 /* Starting from AX210, the HW expects bytes */
118 WARN_ON(trans_pcie->bc_table_dword);
119 WARN_ON(len > 0x3FFF);
120 bc_ent = cpu_to_le16(len | (num_fetch_chunks << 14));
121 scd_bc_tbl_gen3->tfd_offset[idx] = bc_ent;
123 /* Before AX210, the HW expects DW */
124 WARN_ON(!trans_pcie->bc_table_dword);
125 len = DIV_ROUND_UP(len, 4);
126 WARN_ON(len > 0xFFF);
127 bc_ent = cpu_to_le16(len | (num_fetch_chunks << 12));
128 scd_bc_tbl->tfd_offset[idx] = bc_ent;
133 * iwl_pcie_gen2_txq_inc_wr_ptr - Send new write index to hardware
135 void iwl_pcie_gen2_txq_inc_wr_ptr(struct iwl_trans *trans,
138 lockdep_assert_held(&txq->lock);
140 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq->id, txq->write_ptr);
143 * if not in power-save mode, uCode will never sleep when we're
144 * trying to tx (during RFKILL, we're not trying to tx).
146 iwl_write32(trans, HBUS_TARG_WRPTR, txq->write_ptr | (txq->id << 16));
149 static u8 iwl_pcie_gen2_get_num_tbs(struct iwl_trans *trans,
150 struct iwl_tfh_tfd *tfd)
152 return le16_to_cpu(tfd->num_tbs) & 0x1f;
155 static void iwl_pcie_gen2_tfd_unmap(struct iwl_trans *trans,
156 struct iwl_cmd_meta *meta,
157 struct iwl_tfh_tfd *tfd)
159 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
162 /* Sanity check on number of chunks */
163 num_tbs = iwl_pcie_gen2_get_num_tbs(trans, tfd);
165 if (num_tbs > trans_pcie->max_tbs) {
166 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
170 /* first TB is never freed - it's the bidirectional DMA data */
171 for (i = 1; i < num_tbs; i++) {
172 if (meta->tbs & BIT(i))
173 dma_unmap_page(trans->dev,
174 le64_to_cpu(tfd->tbs[i].addr),
175 le16_to_cpu(tfd->tbs[i].tb_len),
178 dma_unmap_single(trans->dev,
179 le64_to_cpu(tfd->tbs[i].addr),
180 le16_to_cpu(tfd->tbs[i].tb_len),
187 static void iwl_pcie_gen2_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
189 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
190 * idx is bounded by n_window
192 int idx = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
194 lockdep_assert_held(&txq->lock);
196 iwl_pcie_gen2_tfd_unmap(trans, &txq->entries[idx].meta,
197 iwl_pcie_get_tfd(trans, txq, idx));
203 skb = txq->entries[idx].skb;
205 /* Can be called from irqs-disabled context
206 * If skb is not NULL, it means that the whole queue is being
207 * freed and that the queue is not empty - free the skb
210 iwl_op_mode_free_skb(trans->op_mode, skb);
211 txq->entries[idx].skb = NULL;
216 static int iwl_pcie_gen2_set_tb(struct iwl_trans *trans,
217 struct iwl_tfh_tfd *tfd, dma_addr_t addr,
220 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
221 int idx = iwl_pcie_gen2_get_num_tbs(trans, tfd);
222 struct iwl_tfh_tb *tb;
224 if (WARN_ON(idx >= IWL_TFH_NUM_TBS))
228 /* Each TFD can point to a maximum max_tbs Tx buffers */
229 if (le16_to_cpu(tfd->num_tbs) >= trans_pcie->max_tbs) {
230 IWL_ERR(trans, "Error can not send more than %d chunks\n",
231 trans_pcie->max_tbs);
235 put_unaligned_le64(addr, &tb->addr);
236 tb->tb_len = cpu_to_le16(len);
238 tfd->num_tbs = cpu_to_le16(idx + 1);
243 static int iwl_pcie_gen2_build_amsdu(struct iwl_trans *trans,
245 struct iwl_tfh_tfd *tfd, int start_len,
246 u8 hdr_len, struct iwl_device_cmd *dev_cmd)
249 struct iwl_tx_cmd_gen2 *tx_cmd = (void *)dev_cmd->payload;
250 struct ieee80211_hdr *hdr = (void *)skb->data;
251 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
252 unsigned int mss = skb_shinfo(skb)->gso_size;
253 u16 length, amsdu_pad;
255 struct iwl_tso_hdr_page *hdr_page;
258 trace_iwlwifi_dev_tx(trans->dev, skb, tfd, sizeof(*tfd),
259 &dev_cmd->hdr, start_len, 0);
261 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
262 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
263 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len;
266 /* total amount of header we may need for this A-MSDU */
267 hdr_room = DIV_ROUND_UP(total_len, mss) *
268 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr));
270 /* Our device supports 9 segments at most, it will fit in 1 page */
271 hdr_page = get_page_hdr(trans, hdr_room, skb);
275 start_hdr = hdr_page->pos;
278 * Pull the ieee80211 header to be able to use TSO core,
279 * we will restore it for the tx_status flow.
281 skb_pull(skb, hdr_len);
284 * Remove the length of all the headers that we don't actually
285 * have in the MPDU by themselves, but that we duplicate into
286 * all the different MSDUs inside the A-MSDU.
288 le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen);
290 tso_start(skb, &tso);
293 /* this is the data left for this subframe */
294 unsigned int data_left = min_t(unsigned int, mss, total_len);
295 struct sk_buff *csum_skb = NULL;
298 u8 *subf_hdrs_start = hdr_page->pos;
300 total_len -= data_left;
302 memset(hdr_page->pos, 0, amsdu_pad);
303 hdr_page->pos += amsdu_pad;
304 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
306 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
307 hdr_page->pos += ETH_ALEN;
308 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
309 hdr_page->pos += ETH_ALEN;
311 length = snap_ip_tcp_hdrlen + data_left;
312 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
313 hdr_page->pos += sizeof(length);
316 * This will copy the SNAP as well which will be considered
319 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
321 hdr_page->pos += snap_ip_tcp_hdrlen;
323 tb_len = hdr_page->pos - start_hdr;
324 tb_phys = dma_map_single(trans->dev, start_hdr,
325 tb_len, DMA_TO_DEVICE);
326 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
327 dev_kfree_skb(csum_skb);
330 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb_len);
331 trace_iwlwifi_dev_tx_tb(trans->dev, skb, start_hdr,
333 /* add this subframe's headers' length to the tx_cmd */
334 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start);
336 /* prepare the start_hdr for the next subframe */
337 start_hdr = hdr_page->pos;
339 /* put the payload */
341 tb_len = min_t(unsigned int, tso.size, data_left);
342 tb_phys = dma_map_single(trans->dev, tso.data,
343 tb_len, DMA_TO_DEVICE);
344 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
345 dev_kfree_skb(csum_skb);
348 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb_len);
349 trace_iwlwifi_dev_tx_tb(trans->dev, skb, tso.data,
353 tso_build_data(skb, &tso, tb_len);
357 /* re -add the WiFi header */
358 skb_push(skb, hdr_len);
368 iwl_tfh_tfd *iwl_pcie_gen2_build_tx_amsdu(struct iwl_trans *trans,
370 struct iwl_device_cmd *dev_cmd,
372 struct iwl_cmd_meta *out_meta,
376 int idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
377 struct iwl_tfh_tfd *tfd = iwl_pcie_get_tfd(trans, txq, idx);
382 tb_phys = iwl_pcie_get_first_tb_dma(txq, idx);
384 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, IWL_FIRST_TB_SIZE);
387 * The second TB (tb1) points to the remainder of the TX command
388 * and the 802.11 header - dword aligned size
389 * (This calculation modifies the TX command, so do it before the
390 * setup of the first TB)
392 len = tx_cmd_len + sizeof(struct iwl_cmd_header) + hdr_len -
395 /* do not align A-MSDU to dword as the subframe header aligns it */
397 /* map the data for TB1 */
398 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
399 tb_phys = dma_map_single(trans->dev, tb1_addr, len, DMA_TO_DEVICE);
400 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
402 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, len);
404 if (iwl_pcie_gen2_build_amsdu(trans, skb, tfd,
405 len + IWL_FIRST_TB_SIZE,
409 /* building the A-MSDU might have changed this data, memcpy it now */
410 memcpy(&txq->first_tb_bufs[idx], dev_cmd, IWL_FIRST_TB_SIZE);
414 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd);
418 static int iwl_pcie_gen2_tx_add_frags(struct iwl_trans *trans,
420 struct iwl_tfh_tfd *tfd,
421 struct iwl_cmd_meta *out_meta)
425 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
426 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
430 if (!skb_frag_size(frag))
433 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
434 skb_frag_size(frag), DMA_TO_DEVICE);
436 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
438 tb_idx = iwl_pcie_gen2_set_tb(trans, tfd, tb_phys,
439 skb_frag_size(frag));
440 trace_iwlwifi_dev_tx_tb(trans->dev, skb, skb_frag_address(frag),
441 tb_phys, skb_frag_size(frag));
445 out_meta->tbs |= BIT(tb_idx);
452 iwl_tfh_tfd *iwl_pcie_gen2_build_tx(struct iwl_trans *trans,
454 struct iwl_device_cmd *dev_cmd,
456 struct iwl_cmd_meta *out_meta,
461 int idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
462 struct iwl_tfh_tfd *tfd = iwl_pcie_get_tfd(trans, txq, idx);
464 int len, tb1_len, tb2_len;
466 struct sk_buff *frag;
468 tb_phys = iwl_pcie_get_first_tb_dma(txq, idx);
470 /* The first TB points to bi-directional DMA data */
471 memcpy(&txq->first_tb_bufs[idx], dev_cmd, IWL_FIRST_TB_SIZE);
473 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, IWL_FIRST_TB_SIZE);
476 * The second TB (tb1) points to the remainder of the TX command
477 * and the 802.11 header - dword aligned size
478 * (This calculation modifies the TX command, so do it before the
479 * setup of the first TB)
481 len = tx_cmd_len + sizeof(struct iwl_cmd_header) + hdr_len -
485 tb1_len = ALIGN(len, 4);
489 /* map the data for TB1 */
490 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
491 tb_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
492 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
494 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb1_len);
495 trace_iwlwifi_dev_tx(trans->dev, skb, tfd, sizeof(*tfd), &dev_cmd->hdr,
496 IWL_FIRST_TB_SIZE + tb1_len, hdr_len);
498 /* set up TFD's third entry to point to remainder of skb's head */
499 tb2_len = skb_headlen(skb) - hdr_len;
502 tb_phys = dma_map_single(trans->dev, skb->data + hdr_len,
503 tb2_len, DMA_TO_DEVICE);
504 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
506 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb2_len);
507 trace_iwlwifi_dev_tx_tb(trans->dev, skb, skb->data + hdr_len,
511 if (iwl_pcie_gen2_tx_add_frags(trans, skb, tfd, out_meta))
514 skb_walk_frags(skb, frag) {
515 tb_phys = dma_map_single(trans->dev, frag->data,
516 skb_headlen(frag), DMA_TO_DEVICE);
517 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
519 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, skb_headlen(frag));
520 trace_iwlwifi_dev_tx_tb(trans->dev, skb, frag->data,
521 tb_phys, skb_headlen(frag));
522 if (iwl_pcie_gen2_tx_add_frags(trans, frag, tfd, out_meta))
529 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd);
534 struct iwl_tfh_tfd *iwl_pcie_gen2_build_tfd(struct iwl_trans *trans,
536 struct iwl_device_cmd *dev_cmd,
538 struct iwl_cmd_meta *out_meta)
540 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
541 int idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
542 struct iwl_tfh_tfd *tfd = iwl_pcie_get_tfd(trans, txq, idx);
546 /* There must be data left over for TB1 or this code must be changed */
547 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd_gen2) < IWL_FIRST_TB_SIZE);
549 memset(tfd, 0, sizeof(*tfd));
551 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
552 len = sizeof(struct iwl_tx_cmd_gen2);
554 len = sizeof(struct iwl_tx_cmd_gen3);
556 amsdu = ieee80211_is_data_qos(hdr->frame_control) &&
557 (*ieee80211_get_qos_ctl(hdr) &
558 IEEE80211_QOS_CTL_A_MSDU_PRESENT);
560 hdr_len = ieee80211_hdrlen(hdr->frame_control);
563 * Only build A-MSDUs here if doing so by GSO, otherwise it may be
564 * an A-MSDU for other reasons, e.g. NAN or an A-MSDU having been
565 * built in the higher layers already.
567 if (amsdu && skb_shinfo(skb)->gso_size)
568 return iwl_pcie_gen2_build_tx_amsdu(trans, txq, dev_cmd, skb,
569 out_meta, hdr_len, len);
571 return iwl_pcie_gen2_build_tx(trans, txq, dev_cmd, skb, out_meta,
572 hdr_len, len, !amsdu);
575 int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
576 struct iwl_device_cmd *dev_cmd, int txq_id)
578 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
579 struct iwl_cmd_meta *out_meta;
580 struct iwl_txq *txq = trans_pcie->txq[txq_id];
585 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
586 "TX on unused queue %d\n", txq_id))
589 if (skb_is_nonlinear(skb) &&
590 skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) &&
591 __skb_linearize(skb))
594 spin_lock(&txq->lock);
596 if (iwl_queue_space(trans, txq) < txq->high_mark) {
597 iwl_stop_queue(trans, txq);
599 /* don't put the packet on the ring, if there is no room */
600 if (unlikely(iwl_queue_space(trans, txq) < 3)) {
601 struct iwl_device_cmd **dev_cmd_ptr;
603 dev_cmd_ptr = (void *)((u8 *)skb->cb +
604 trans_pcie->dev_cmd_offs);
606 *dev_cmd_ptr = dev_cmd;
607 __skb_queue_tail(&txq->overflow_q, skb);
608 spin_unlock(&txq->lock);
613 idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
615 /* Set up driver data for this TFD */
616 txq->entries[idx].skb = skb;
617 txq->entries[idx].cmd = dev_cmd;
619 dev_cmd->hdr.sequence =
620 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
623 /* Set up first empty entry in queue's array of Tx/cmd buffers */
624 out_meta = &txq->entries[idx].meta;
627 tfd = iwl_pcie_gen2_build_tfd(trans, txq, dev_cmd, skb, out_meta);
629 spin_unlock(&txq->lock);
633 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
634 struct iwl_tx_cmd_gen3 *tx_cmd_gen3 =
635 (void *)dev_cmd->payload;
637 cmd_len = le16_to_cpu(tx_cmd_gen3->len);
639 struct iwl_tx_cmd_gen2 *tx_cmd_gen2 =
640 (void *)dev_cmd->payload;
642 cmd_len = le16_to_cpu(tx_cmd_gen2->len);
645 /* Set up entry for this TFD in Tx byte-count array */
646 iwl_pcie_gen2_update_byte_tbl(trans_pcie, txq, cmd_len,
647 iwl_pcie_gen2_get_num_tbs(trans, tfd));
649 /* start timer if queue currently empty */
650 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
651 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
653 /* Tell device the write index *just past* this latest filled TFD */
654 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
655 iwl_pcie_gen2_txq_inc_wr_ptr(trans, txq);
657 * At this point the frame is "transmitted" successfully
658 * and we will get a TX status notification eventually.
660 spin_unlock(&txq->lock);
664 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
667 * iwl_pcie_gen2_enqueue_hcmd - enqueue a uCode command
668 * @priv: device private data point
669 * @cmd: a pointer to the ucode command structure
671 * The function returns < 0 values to indicate the operation
672 * failed. On success, it returns the index (>= 0) of command in the
675 static int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans,
676 struct iwl_host_cmd *cmd)
678 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
679 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
680 struct iwl_device_cmd *out_cmd;
681 struct iwl_cmd_meta *out_meta;
683 void *dup_buf = NULL;
684 dma_addr_t phys_addr;
686 u16 copy_size, cmd_size, tb0_size;
687 bool had_nocopy = false;
688 u8 group_id = iwl_cmd_groupid(cmd->id);
689 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
690 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
691 struct iwl_tfh_tfd *tfd;
693 copy_size = sizeof(struct iwl_cmd_header_wide);
694 cmd_size = sizeof(struct iwl_cmd_header_wide);
696 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
697 cmddata[i] = cmd->data[i];
698 cmdlen[i] = cmd->len[i];
703 /* need at least IWL_FIRST_TB_SIZE copied */
704 if (copy_size < IWL_FIRST_TB_SIZE) {
705 int copy = IWL_FIRST_TB_SIZE - copy_size;
707 if (copy > cmdlen[i])
714 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
716 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
720 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
722 * This is also a chunk that isn't copied
723 * to the static buffer so set had_nocopy.
727 /* only allowed once */
728 if (WARN_ON(dup_buf)) {
733 dup_buf = kmemdup(cmddata[i], cmdlen[i],
738 /* NOCOPY must not be followed by normal! */
739 if (WARN_ON(had_nocopy)) {
743 copy_size += cmdlen[i];
745 cmd_size += cmd->len[i];
749 * If any of the command structures end up being larger than the
750 * TFD_MAX_PAYLOAD_SIZE and they aren't dynamically allocated into
751 * separate TFDs, then we will need to increase the size of the buffers
753 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
754 "Command %s (%#x) is too large (%d bytes)\n",
755 iwl_get_cmd_string(trans, cmd->id), cmd->id, copy_size)) {
760 spin_lock_bh(&txq->lock);
762 idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
763 tfd = iwl_pcie_get_tfd(trans, txq, txq->write_ptr);
764 memset(tfd, 0, sizeof(*tfd));
766 if (iwl_queue_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
767 spin_unlock_bh(&txq->lock);
769 IWL_ERR(trans, "No space in command queue\n");
770 iwl_op_mode_cmd_queue_full(trans->op_mode);
775 out_cmd = txq->entries[idx].cmd;
776 out_meta = &txq->entries[idx].meta;
778 /* re-initialize to NULL */
779 memset(out_meta, 0, sizeof(*out_meta));
780 if (cmd->flags & CMD_WANT_SKB)
781 out_meta->source = cmd;
783 /* set up the header */
784 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
785 out_cmd->hdr_wide.group_id = group_id;
786 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
787 out_cmd->hdr_wide.length =
788 cpu_to_le16(cmd_size - sizeof(struct iwl_cmd_header_wide));
789 out_cmd->hdr_wide.reserved = 0;
790 out_cmd->hdr_wide.sequence =
791 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
792 INDEX_TO_SEQ(txq->write_ptr));
794 cmd_pos = sizeof(struct iwl_cmd_header_wide);
795 copy_size = sizeof(struct iwl_cmd_header_wide);
797 /* and copy the data that needs to be copied */
798 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
804 /* copy everything if not nocopy/dup */
805 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
806 IWL_HCMD_DFL_DUP))) {
809 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
816 * Otherwise we need at least IWL_FIRST_TB_SIZE copied
817 * in total (for bi-directional DMA), but copy up to what
818 * we can fit into the payload for debug dump purposes.
820 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
822 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
825 /* However, treat copy_size the proper way, we need it below */
826 if (copy_size < IWL_FIRST_TB_SIZE) {
827 copy = IWL_FIRST_TB_SIZE - copy_size;
829 if (copy > cmd->len[i])
836 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
837 iwl_get_cmd_string(trans, cmd->id), group_id,
838 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
839 cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue);
841 /* start the TFD with the minimum copy bytes */
842 tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
843 memcpy(&txq->first_tb_bufs[idx], out_cmd, tb0_size);
844 iwl_pcie_gen2_set_tb(trans, tfd, iwl_pcie_get_first_tb_dma(txq, idx),
847 /* map first command fragment, if any remains */
848 if (copy_size > tb0_size) {
849 phys_addr = dma_map_single(trans->dev,
850 (u8 *)out_cmd + tb0_size,
851 copy_size - tb0_size,
853 if (dma_mapping_error(trans->dev, phys_addr)) {
855 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd);
858 iwl_pcie_gen2_set_tb(trans, tfd, phys_addr,
859 copy_size - tb0_size);
862 /* map the remaining (adjusted) nocopy/dup fragments */
863 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
864 const void *data = cmddata[i];
868 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
871 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
873 phys_addr = dma_map_single(trans->dev, (void *)data,
874 cmdlen[i], DMA_TO_DEVICE);
875 if (dma_mapping_error(trans->dev, phys_addr)) {
877 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd);
880 iwl_pcie_gen2_set_tb(trans, tfd, phys_addr, cmdlen[i]);
883 BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE);
884 out_meta->flags = cmd->flags;
885 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
886 kzfree(txq->entries[idx].free_buf);
887 txq->entries[idx].free_buf = dup_buf;
889 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
891 /* start timer if queue currently empty */
892 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
893 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
895 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
896 /* Increment and update queue's write index */
897 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
898 iwl_pcie_gen2_txq_inc_wr_ptr(trans, txq);
899 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
902 spin_unlock_bh(&txq->lock);
909 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
911 static int iwl_pcie_gen2_send_hcmd_sync(struct iwl_trans *trans,
912 struct iwl_host_cmd *cmd)
914 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
915 const char *cmd_str = iwl_get_cmd_string(trans, cmd->id);
916 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
920 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", cmd_str);
922 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
924 "Command %s: a command is already active!\n", cmd_str))
927 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", cmd_str);
929 cmd_idx = iwl_pcie_gen2_enqueue_hcmd(trans, cmd);
932 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
933 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
938 ret = wait_event_timeout(trans_pcie->wait_command_queue,
939 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
941 HOST_COMPLETE_TIMEOUT);
943 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
944 cmd_str, jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
946 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
947 txq->read_ptr, txq->write_ptr);
949 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
950 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
954 iwl_trans_pcie_sync_nmi(trans);
958 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
959 IWL_ERR(trans, "FW error in SYNC CMD %s\n", cmd_str);
965 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
966 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
967 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
972 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
973 IWL_ERR(trans, "Error: Response NULL in '%s'\n", cmd_str);
981 if (cmd->flags & CMD_WANT_SKB) {
983 * Cancel the CMD_WANT_SKB flag for the cmd in the
984 * TX cmd queue. Otherwise in case the cmd comes
985 * in later, it will possibly set an invalid
986 * address (cmd->meta.source).
988 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
993 cmd->resp_pkt = NULL;
999 int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans,
1000 struct iwl_host_cmd *cmd)
1002 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1003 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1004 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1009 if (cmd->flags & CMD_ASYNC) {
1012 /* An asynchronous command can not expect an SKB to be set. */
1013 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1016 ret = iwl_pcie_gen2_enqueue_hcmd(trans, cmd);
1019 "Error sending %s: enqueue_hcmd failed: %d\n",
1020 iwl_get_cmd_string(trans, cmd->id), ret);
1026 return iwl_pcie_gen2_send_hcmd_sync(trans, cmd);
1030 * iwl_pcie_gen2_txq_unmap - Unmap any remaining DMA mappings and free skb's
1032 void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id)
1034 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1035 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1037 spin_lock_bh(&txq->lock);
1038 while (txq->write_ptr != txq->read_ptr) {
1039 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
1040 txq_id, txq->read_ptr);
1042 if (txq_id != trans_pcie->cmd_queue) {
1043 int idx = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
1044 struct sk_buff *skb = txq->entries[idx].skb;
1046 if (WARN_ON_ONCE(!skb))
1049 iwl_pcie_free_tso_page(trans_pcie, skb);
1051 iwl_pcie_gen2_free_tfd(trans, txq);
1052 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr);
1055 while (!skb_queue_empty(&txq->overflow_q)) {
1056 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
1058 iwl_op_mode_free_skb(trans->op_mode, skb);
1061 spin_unlock_bh(&txq->lock);
1063 /* just in case - this queue may have been stopped */
1064 iwl_wake_queue(trans, txq);
1067 void iwl_pcie_gen2_txq_free_memory(struct iwl_trans *trans,
1068 struct iwl_txq *txq)
1070 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1071 struct device *dev = trans->dev;
1073 /* De-alloc circular buffer of TFDs */
1075 dma_free_coherent(dev,
1076 trans_pcie->tfd_size * txq->n_window,
1077 txq->tfds, txq->dma_addr);
1078 dma_free_coherent(dev,
1079 sizeof(*txq->first_tb_bufs) * txq->n_window,
1080 txq->first_tb_bufs, txq->first_tb_dma);
1083 kfree(txq->entries);
1084 iwl_pcie_free_dma_ptr(trans, &txq->bc_tbl);
1089 * iwl_pcie_txq_free - Deallocate DMA queue.
1090 * @txq: Transmit queue to deallocate.
1092 * Empty queue by removing and destroying all BD's.
1094 * 0-fill, but do not free "txq" descriptor structure.
1096 static void iwl_pcie_gen2_txq_free(struct iwl_trans *trans, int txq_id)
1098 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1099 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1105 iwl_pcie_gen2_txq_unmap(trans, txq_id);
1107 /* De-alloc array of command/tx buffers */
1108 if (txq_id == trans_pcie->cmd_queue)
1109 for (i = 0; i < txq->n_window; i++) {
1110 kzfree(txq->entries[i].cmd);
1111 kzfree(txq->entries[i].free_buf);
1113 del_timer_sync(&txq->stuck_timer);
1115 iwl_pcie_gen2_txq_free_memory(trans, txq);
1117 trans_pcie->txq[txq_id] = NULL;
1119 clear_bit(txq_id, trans_pcie->queue_used);
1122 int iwl_trans_pcie_dyn_txq_alloc_dma(struct iwl_trans *trans,
1123 struct iwl_txq **intxq, int size,
1124 unsigned int timeout)
1128 struct iwl_txq *txq;
1129 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
1132 ret = iwl_pcie_alloc_dma_ptr(trans, &txq->bc_tbl,
1133 (trans->trans_cfg->device_family >=
1134 IWL_DEVICE_FAMILY_AX210) ?
1135 sizeof(struct iwl_gen3_bc_tbl) :
1136 sizeof(struct iwlagn_scd_bc_tbl));
1138 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
1143 ret = iwl_pcie_txq_alloc(trans, txq, size, false);
1145 IWL_ERR(trans, "Tx queue alloc failed\n");
1148 ret = iwl_pcie_txq_init(trans, txq, size, false);
1150 IWL_ERR(trans, "Tx queue init failed\n");
1154 txq->wd_timeout = msecs_to_jiffies(timeout);
1160 iwl_pcie_gen2_txq_free_memory(trans, txq);
1164 int iwl_trans_pcie_txq_alloc_response(struct iwl_trans *trans,
1165 struct iwl_txq *txq,
1166 struct iwl_host_cmd *hcmd)
1168 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1169 struct iwl_tx_queue_cfg_rsp *rsp;
1173 if (WARN_ON(iwl_rx_packet_payload_len(hcmd->resp_pkt) !=
1176 goto error_free_resp;
1179 rsp = (void *)hcmd->resp_pkt->data;
1180 qid = le16_to_cpu(rsp->queue_number);
1181 wr_ptr = le16_to_cpu(rsp->write_pointer);
1183 if (qid >= ARRAY_SIZE(trans_pcie->txq)) {
1184 WARN_ONCE(1, "queue index %d unsupported", qid);
1186 goto error_free_resp;
1189 if (test_and_set_bit(qid, trans_pcie->queue_used)) {
1190 WARN_ONCE(1, "queue %d already used", qid);
1192 goto error_free_resp;
1196 trans_pcie->txq[qid] = txq;
1197 wr_ptr &= (trans->trans_cfg->base_params->max_tfd_queue_size - 1);
1199 /* Place first TFD at index corresponding to start sequence number */
1200 txq->read_ptr = wr_ptr;
1201 txq->write_ptr = wr_ptr;
1203 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d\n", qid);
1205 iwl_free_resp(hcmd);
1209 iwl_free_resp(hcmd);
1210 iwl_pcie_gen2_txq_free_memory(trans, txq);
1214 int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans,
1215 __le16 flags, u8 sta_id, u8 tid,
1216 int cmd_id, int size,
1217 unsigned int timeout)
1219 struct iwl_txq *txq = NULL;
1220 struct iwl_tx_queue_cfg_cmd cmd = {
1225 struct iwl_host_cmd hcmd = {
1227 .len = { sizeof(cmd) },
1229 .flags = CMD_WANT_SKB,
1233 ret = iwl_trans_pcie_dyn_txq_alloc_dma(trans, &txq, size, timeout);
1237 cmd.tfdq_addr = cpu_to_le64(txq->dma_addr);
1238 cmd.byte_cnt_addr = cpu_to_le64(txq->bc_tbl.dma);
1239 cmd.cb_size = cpu_to_le32(TFD_QUEUE_CB_SIZE(size));
1241 ret = iwl_trans_send_cmd(trans, &hcmd);
1245 return iwl_trans_pcie_txq_alloc_response(trans, txq, &hcmd);
1248 iwl_pcie_gen2_txq_free_memory(trans, txq);
1252 void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue)
1254 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1257 * Upon HW Rfkill - we stop the device, and then stop the queues
1258 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1259 * allow the op_mode to call txq_disable after it already called
1262 if (!test_and_clear_bit(queue, trans_pcie->queue_used)) {
1263 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1264 "queue %d not used", queue);
1268 iwl_pcie_gen2_txq_unmap(trans, queue);
1270 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", queue);
1273 void iwl_pcie_gen2_tx_free(struct iwl_trans *trans)
1275 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1278 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
1280 /* Free all TX queues */
1281 for (i = 0; i < ARRAY_SIZE(trans_pcie->txq); i++) {
1282 if (!trans_pcie->txq[i])
1285 iwl_pcie_gen2_txq_free(trans, i);
1289 int iwl_pcie_gen2_tx_init(struct iwl_trans *trans, int txq_id, int queue_size)
1291 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1292 struct iwl_txq *queue;
1295 /* alloc and init the tx queue */
1296 if (!trans_pcie->txq[txq_id]) {
1297 queue = kzalloc(sizeof(*queue), GFP_KERNEL);
1299 IWL_ERR(trans, "Not enough memory for tx queue\n");
1302 trans_pcie->txq[txq_id] = queue;
1303 ret = iwl_pcie_txq_alloc(trans, queue, queue_size, true);
1305 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
1309 queue = trans_pcie->txq[txq_id];
1312 ret = iwl_pcie_txq_init(trans, queue, queue_size,
1313 (txq_id == trans_pcie->cmd_queue));
1315 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
1318 trans_pcie->txq[txq_id]->id = txq_id;
1319 set_bit(txq_id, trans_pcie->queue_used);
1324 iwl_pcie_gen2_tx_free(trans);