1 /******************************************************************************
3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
5 * Copyright(c) 2016 Intel Deutschland GmbH
7 * Portions of this file are derived from the ipw3945 project, as well
8 * as portions of the ieee80211 subsystem header files.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
23 * The full GNU General Public License is included in this distribution in the
24 * file called LICENSE.
26 * Contact Information:
27 * Intel Linux Wireless <linuxwifi@intel.com>
28 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *****************************************************************************/
31 #include <linux/etherdevice.h>
32 #include <linux/ieee80211.h>
33 #include <linux/slab.h>
34 #include <linux/sched.h>
35 #include <linux/pm_runtime.h>
36 #include <net/ip6_checksum.h>
39 #include "iwl-debug.h"
44 #include "iwl-op-mode.h"
46 /* FIXME: need to abstract out TX command (once we know what it looks like) */
47 #include "dvm/commands.h"
49 #define IWL_TX_CRC_SIZE 4
50 #define IWL_TX_DELIMITER_SIZE 4
52 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
57 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
58 * of buffer descriptors, each of which points to one or more data buffers for
59 * the device to read from or fill. Driver and device exchange status of each
60 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
61 * entries in each circular buffer, to protect against confusing empty and full
64 * The device reads or writes the data in the queues via the device's several
65 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
67 * For Tx queue, there are low mark and high mark limits. If, after queuing
68 * the packet for Tx, free space become < low mark, Tx queue stopped. When
69 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
72 ***************************************************/
74 static int iwl_queue_space(const struct iwl_txq *q)
80 * To avoid ambiguity between empty and completely full queues, there
81 * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
82 * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
83 * to reserve any queue entries for this purpose.
85 if (q->n_window < TFD_QUEUE_SIZE_MAX)
88 max = TFD_QUEUE_SIZE_MAX - 1;
91 * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
92 * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
94 used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
96 if (WARN_ON(used > max))
103 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
105 static int iwl_queue_init(struct iwl_txq *q, int slots_num, u32 id)
107 q->n_window = slots_num;
110 /* slots_num must be power-of-two size, otherwise
111 * get_cmd_index is broken. */
112 if (WARN_ON(!is_power_of_2(slots_num)))
115 q->low_mark = q->n_window / 4;
119 q->high_mark = q->n_window / 8;
120 if (q->high_mark < 2)
129 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
130 struct iwl_dma_ptr *ptr, size_t size)
132 if (WARN_ON(ptr->addr))
135 ptr->addr = dma_alloc_coherent(trans->dev, size,
136 &ptr->dma, GFP_KERNEL);
143 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
144 struct iwl_dma_ptr *ptr)
146 if (unlikely(!ptr->addr))
149 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
150 memset(ptr, 0, sizeof(*ptr));
153 static void iwl_pcie_txq_stuck_timer(unsigned long data)
155 struct iwl_txq *txq = (void *)data;
156 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
157 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
159 spin_lock(&txq->lock);
160 /* check if triggered erroneously */
161 if (txq->read_ptr == txq->write_ptr) {
162 spin_unlock(&txq->lock);
165 spin_unlock(&txq->lock);
167 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->id,
168 jiffies_to_msecs(txq->wd_timeout));
170 iwl_trans_pcie_log_scd_error(trans, txq);
172 iwl_force_nmi(trans);
176 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
178 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
179 struct iwl_txq *txq, u16 byte_cnt,
182 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
183 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
184 int write_ptr = txq->write_ptr;
185 int txq_id = txq->id;
187 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
189 struct iwl_tx_cmd *tx_cmd =
190 (void *)txq->entries[txq->write_ptr].cmd->payload;
192 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
194 sec_ctl = tx_cmd->sec_ctl;
196 switch (sec_ctl & TX_CMD_SEC_MSK) {
198 len += IEEE80211_CCMP_MIC_LEN;
200 case TX_CMD_SEC_TKIP:
201 len += IEEE80211_TKIP_ICV_LEN;
204 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
207 if (trans_pcie->bc_table_dword)
208 len = DIV_ROUND_UP(len, 4);
210 if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
213 if (trans->cfg->use_tfh) {
214 u8 filled_tfd_size = offsetof(struct iwl_tfh_tfd, tbs) +
215 num_tbs * sizeof(struct iwl_tfh_tb);
217 * filled_tfd_size contains the number of filled bytes in the
219 * Dividing it by 64 will give the number of chunks to fetch
220 * to SRAM- 0 for one chunk, 1 for 2 and so on.
221 * If, for example, TFD contains only 3 TBs then 32 bytes
222 * of the TFD are used, and only one chunk of 64 bytes should
225 u8 num_fetch_chunks = DIV_ROUND_UP(filled_tfd_size, 64) - 1;
227 bc_ent = cpu_to_le16(len | (num_fetch_chunks << 12));
229 u8 sta_id = tx_cmd->sta_id;
231 bc_ent = cpu_to_le16(len | (sta_id << 12));
234 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
236 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
238 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
241 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
244 struct iwl_trans_pcie *trans_pcie =
245 IWL_TRANS_GET_PCIE_TRANS(trans);
246 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
247 int txq_id = txq->id;
248 int read_ptr = txq->read_ptr;
251 struct iwl_tx_cmd *tx_cmd =
252 (void *)txq->entries[read_ptr].cmd->payload;
254 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
256 if (txq_id != trans_pcie->cmd_queue)
257 sta_id = tx_cmd->sta_id;
259 bc_ent = cpu_to_le16(1 | (sta_id << 12));
261 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
263 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
265 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
269 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
271 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
274 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
276 int txq_id = txq->id;
278 lockdep_assert_held(&txq->lock);
281 * explicitly wake up the NIC if:
282 * 1. shadow registers aren't enabled
283 * 2. NIC is woken up for CMD regardless of shadow outside this function
284 * 3. there is a chance that the NIC is asleep
286 if (!trans->cfg->base_params->shadow_reg_enable &&
287 txq_id != trans_pcie->cmd_queue &&
288 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
290 * wake up nic if it's powered down ...
291 * uCode will wake up, and interrupt us again, so next
292 * time we'll skip this part.
294 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
296 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
297 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
299 iwl_set_bit(trans, CSR_GP_CNTRL,
300 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
301 txq->need_update = true;
307 * if not in power-save mode, uCode will never sleep when we're
308 * trying to tx (during RFKILL, we're not trying to tx).
310 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr);
312 iwl_write32(trans, HBUS_TARG_WRPTR,
313 txq->write_ptr | (txq_id << 8));
316 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
318 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
321 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
322 struct iwl_txq *txq = &trans_pcie->txq[i];
324 spin_lock_bh(&txq->lock);
325 if (trans_pcie->txq[i].need_update) {
326 iwl_pcie_txq_inc_wr_ptr(trans, txq);
327 trans_pcie->txq[i].need_update = false;
329 spin_unlock_bh(&txq->lock);
333 static inline void *iwl_pcie_get_tfd(struct iwl_trans_pcie *trans_pcie,
334 struct iwl_txq *txq, int idx)
336 return txq->tfds + trans_pcie->tfd_size * idx;
339 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans,
343 if (trans->cfg->use_tfh) {
344 struct iwl_tfh_tfd *tfd = _tfd;
345 struct iwl_tfh_tb *tb = &tfd->tbs[idx];
347 return (dma_addr_t)(le64_to_cpu(tb->addr));
349 struct iwl_tfd *tfd = _tfd;
350 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
351 dma_addr_t addr = get_unaligned_le32(&tb->lo);
354 if (sizeof(dma_addr_t) <= sizeof(u32))
357 hi_len = le16_to_cpu(tb->hi_n_len) & 0xF;
360 * shift by 16 twice to avoid warnings on 32-bit
361 * (where this code never runs anyway due to the
362 * if statement above)
364 return addr | ((hi_len << 16) << 16);
368 static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd,
369 u8 idx, dma_addr_t addr, u16 len)
371 if (trans->cfg->use_tfh) {
372 struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
373 struct iwl_tfh_tb *tb = &tfd_fh->tbs[idx];
375 put_unaligned_le64(addr, &tb->addr);
376 tb->tb_len = cpu_to_le16(len);
378 tfd_fh->num_tbs = cpu_to_le16(idx + 1);
380 struct iwl_tfd *tfd_fh = (void *)tfd;
381 struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx];
383 u16 hi_n_len = len << 4;
385 put_unaligned_le32(addr, &tb->lo);
386 if (sizeof(dma_addr_t) > sizeof(u32))
387 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
389 tb->hi_n_len = cpu_to_le16(hi_n_len);
391 tfd_fh->num_tbs = idx + 1;
395 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd)
397 if (trans->cfg->use_tfh) {
398 struct iwl_tfh_tfd *tfd = _tfd;
400 return le16_to_cpu(tfd->num_tbs) & 0x1f;
402 struct iwl_tfd *tfd = _tfd;
404 return tfd->num_tbs & 0x1f;
408 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
409 struct iwl_cmd_meta *meta,
410 struct iwl_txq *txq, int index)
412 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
414 void *tfd = iwl_pcie_get_tfd(trans_pcie, txq, index);
416 /* Sanity check on number of chunks */
417 num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
419 if (num_tbs >= trans_pcie->max_tbs) {
420 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
421 /* @todo issue fatal error, it is quite serious situation */
425 /* first TB is never freed - it's the bidirectional DMA data */
427 for (i = 1; i < num_tbs; i++) {
428 if (meta->tbs & BIT(i))
429 dma_unmap_page(trans->dev,
430 iwl_pcie_tfd_tb_get_addr(trans, tfd, i),
431 iwl_pcie_tfd_tb_get_len(trans, tfd, i),
434 dma_unmap_single(trans->dev,
435 iwl_pcie_tfd_tb_get_addr(trans, tfd,
437 iwl_pcie_tfd_tb_get_len(trans, tfd,
442 if (trans->cfg->use_tfh) {
443 struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
447 struct iwl_tfd *tfd_fh = (void *)tfd;
455 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
456 * @trans - transport private data
458 * @dma_dir - the direction of the DMA mapping
460 * Does NOT advance any TFD circular buffer read/write indexes
461 * Does NOT free the TFD itself (which is within circular buffer)
463 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
465 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
466 * idx is bounded by n_window
468 int rd_ptr = txq->read_ptr;
469 int idx = get_cmd_index(txq, rd_ptr);
471 lockdep_assert_held(&txq->lock);
473 /* We have only q->n_window txq->entries, but we use
474 * TFD_QUEUE_SIZE_MAX tfds
476 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr);
482 skb = txq->entries[idx].skb;
484 /* Can be called from irqs-disabled context
485 * If skb is not NULL, it means that the whole queue is being
486 * freed and that the queue is not empty - free the skb
489 iwl_op_mode_free_skb(trans->op_mode, skb);
490 txq->entries[idx].skb = NULL;
495 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
496 dma_addr_t addr, u16 len, bool reset)
498 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
502 tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr;
505 memset(tfd, 0, trans_pcie->tfd_size);
507 num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
509 /* Each TFD can point to a maximum max_tbs Tx buffers */
510 if (num_tbs >= trans_pcie->max_tbs) {
511 IWL_ERR(trans, "Error can not send more than %d chunks\n",
512 trans_pcie->max_tbs);
516 if (WARN(addr & ~IWL_TX_DMA_MASK,
517 "Unaligned address = %llx\n", (unsigned long long)addr))
520 iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len);
525 static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
526 struct iwl_txq *txq, int slots_num,
529 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
530 size_t tfd_sz = trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX;
534 if (WARN_ON(txq->entries || txq->tfds))
537 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
539 txq->trans_pcie = trans_pcie;
541 txq->n_window = slots_num;
543 txq->entries = kcalloc(slots_num,
544 sizeof(struct iwl_pcie_txq_entry),
550 if (txq_id == trans_pcie->cmd_queue)
551 for (i = 0; i < slots_num; i++) {
552 txq->entries[i].cmd =
553 kmalloc(sizeof(struct iwl_device_cmd),
555 if (!txq->entries[i].cmd)
559 /* Circular buffer of transmit frame descriptors (TFDs),
560 * shared with device */
561 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
562 &txq->dma_addr, GFP_KERNEL);
566 BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs));
568 tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num;
570 txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz,
573 if (!txq->first_tb_bufs)
580 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr);
582 if (txq->entries && txq_id == trans_pcie->cmd_queue)
583 for (i = 0; i < slots_num; i++)
584 kfree(txq->entries[i].cmd);
592 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
593 int slots_num, u32 txq_id)
597 txq->need_update = false;
599 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
600 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
601 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
603 /* Initialize queue's high/low-water marks, and head/tail indexes */
604 ret = iwl_queue_init(txq, slots_num, txq_id);
608 spin_lock_init(&txq->lock);
609 __skb_queue_head_init(&txq->overflow_q);
612 * Tell nic where to find circular buffer of Tx Frame Descriptors for
613 * given Tx queue, and enable the DMA channel used for that queue.
614 * Circular buffer (TFD queue in DRAM) physical base address */
615 if (trans->cfg->use_tfh)
616 iwl_write_direct64(trans,
617 FH_MEM_CBBC_QUEUE(trans, txq_id),
620 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),
626 static void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie,
629 struct page **page_ptr;
631 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
634 __free_page(*page_ptr);
639 static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
641 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
643 lockdep_assert_held(&trans_pcie->reg_lock);
645 if (trans_pcie->ref_cmd_in_flight) {
646 trans_pcie->ref_cmd_in_flight = false;
647 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n");
648 iwl_trans_unref(trans);
651 if (!trans->cfg->base_params->apmg_wake_up_wa)
653 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake))
656 trans_pcie->cmd_hold_nic_awake = false;
657 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
658 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
662 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
664 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
666 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
667 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
669 spin_lock_bh(&txq->lock);
670 while (txq->write_ptr != txq->read_ptr) {
671 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
672 txq_id, txq->read_ptr);
674 if (txq_id != trans_pcie->cmd_queue) {
675 struct sk_buff *skb = txq->entries[txq->read_ptr].skb;
677 if (WARN_ON_ONCE(!skb))
680 iwl_pcie_free_tso_page(trans_pcie, skb);
682 iwl_pcie_txq_free_tfd(trans, txq);
683 txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr);
685 if (txq->read_ptr == txq->write_ptr) {
688 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
689 if (txq_id != trans_pcie->cmd_queue) {
690 IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n",
692 iwl_trans_unref(trans);
694 iwl_pcie_clear_cmd_in_flight(trans);
696 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
701 while (!skb_queue_empty(&txq->overflow_q)) {
702 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
704 iwl_op_mode_free_skb(trans->op_mode, skb);
707 spin_unlock_bh(&txq->lock);
709 /* just in case - this queue may have been stopped */
710 iwl_wake_queue(trans, txq);
714 * iwl_pcie_txq_free - Deallocate DMA queue.
715 * @txq: Transmit queue to deallocate.
717 * Empty queue by removing and destroying all BD's.
719 * 0-fill, but do not free "txq" descriptor structure.
721 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
723 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
724 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
725 struct device *dev = trans->dev;
731 iwl_pcie_txq_unmap(trans, txq_id);
733 /* De-alloc array of command/tx buffers */
734 if (txq_id == trans_pcie->cmd_queue)
735 for (i = 0; i < txq->n_window; i++) {
736 kzfree(txq->entries[i].cmd);
737 kzfree(txq->entries[i].free_buf);
740 /* De-alloc circular buffer of TFDs */
742 dma_free_coherent(dev,
743 trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX,
744 txq->tfds, txq->dma_addr);
748 dma_free_coherent(dev,
749 sizeof(*txq->first_tb_bufs) * txq->n_window,
750 txq->first_tb_bufs, txq->first_tb_dma);
756 del_timer_sync(&txq->stuck_timer);
758 /* 0-fill queue descriptor structure */
759 memset(txq, 0, sizeof(*txq));
762 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
764 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
765 int nq = trans->cfg->base_params->num_of_queues;
768 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
769 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
771 /* make sure all queue are not stopped/used */
772 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
773 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
775 if (trans->cfg->use_tfh)
778 trans_pcie->scd_base_addr =
779 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
781 WARN_ON(scd_base_addr != 0 &&
782 scd_base_addr != trans_pcie->scd_base_addr);
784 /* reset context data, TX status and translation data */
785 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
786 SCD_CONTEXT_MEM_LOWER_BOUND,
789 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
790 trans_pcie->scd_bc_tbls.dma >> 10);
792 /* The chain extension of the SCD doesn't work well. This feature is
793 * enabled by default by the HW, so we need to disable it manually.
795 if (trans->cfg->base_params->scd_chain_ext_wa)
796 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
798 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
799 trans_pcie->cmd_fifo,
800 trans_pcie->cmd_q_wdg_timeout);
802 /* Activate all Tx DMA/FIFO channels */
803 iwl_scd_activate_fifos(trans);
805 /* Enable DMA channel */
806 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
807 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
808 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
809 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
811 /* Update FH chicken bits */
812 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
813 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
814 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
816 /* Enable L1-Active */
817 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
818 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
819 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
822 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
824 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
827 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
829 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
830 if (trans->cfg->use_tfh)
831 iwl_write_direct64(trans,
832 FH_MEM_CBBC_QUEUE(trans, txq_id),
835 iwl_write_direct32(trans,
836 FH_MEM_CBBC_QUEUE(trans, txq_id),
838 iwl_pcie_txq_unmap(trans, txq_id);
843 /* Tell NIC where to find the "keep warm" buffer */
844 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
845 trans_pcie->kw.dma >> 4);
848 * Send 0 as the scd_base_addr since the device may have be reset
849 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
852 iwl_pcie_tx_start(trans, 0);
855 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
857 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
862 spin_lock(&trans_pcie->irq_lock);
864 if (!iwl_trans_grab_nic_access(trans, &flags))
867 /* Stop each Tx DMA channel */
868 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
869 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
870 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
873 /* Wait for DMA channels to be idle */
874 ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
877 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
878 ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
880 iwl_trans_release_nic_access(trans, &flags);
883 spin_unlock(&trans_pcie->irq_lock);
887 * iwl_pcie_tx_stop - Stop all Tx DMA channels
889 int iwl_pcie_tx_stop(struct iwl_trans *trans)
891 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
894 /* Turn off all Tx DMA fifos */
895 iwl_scd_deactivate_fifos(trans);
897 /* Turn off all Tx DMA channels */
898 iwl_pcie_tx_stop_fh(trans);
901 * This function can be called before the op_mode disabled the
902 * queues. This happens when we have an rfkill interrupt.
903 * Since we stop Tx altogether - mark the queues as stopped.
905 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
906 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
908 /* This can happen: start_hw, stop_device */
909 if (!trans_pcie->txq)
912 /* Unmap DMA from host system and free skb's */
913 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
915 iwl_pcie_txq_unmap(trans, txq_id);
921 * iwl_trans_tx_free - Free TXQ Context
923 * Destroy all TX DMA queues and structures
925 void iwl_pcie_tx_free(struct iwl_trans *trans)
928 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
931 if (trans_pcie->txq) {
933 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
934 iwl_pcie_txq_free(trans, txq_id);
937 kfree(trans_pcie->txq);
938 trans_pcie->txq = NULL;
940 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
942 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
946 * iwl_pcie_tx_alloc - allocate TX context
947 * Allocate all Tx DMA structures and initialize them
949 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
952 int txq_id, slots_num;
953 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
955 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
956 sizeof(struct iwlagn_scd_bc_tbl);
958 /*It is not allowed to alloc twice, so warn when this happens.
959 * We cannot rely on the previous allocation, so free and fail */
960 if (WARN_ON(trans_pcie->txq)) {
965 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
968 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
972 /* Alloc keep-warm buffer */
973 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
975 IWL_ERR(trans, "Keep Warm allocation failed\n");
979 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
980 sizeof(struct iwl_txq), GFP_KERNEL);
981 if (!trans_pcie->txq) {
982 IWL_ERR(trans, "Not enough memory for txq\n");
987 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
988 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
990 slots_num = (txq_id == trans_pcie->cmd_queue) ?
991 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
992 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
995 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
1003 iwl_pcie_tx_free(trans);
1007 int iwl_pcie_tx_init(struct iwl_trans *trans)
1009 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1011 int txq_id, slots_num;
1014 if (!trans_pcie->txq) {
1015 ret = iwl_pcie_tx_alloc(trans);
1021 spin_lock(&trans_pcie->irq_lock);
1023 /* Turn off all Tx DMA fifos */
1024 iwl_scd_deactivate_fifos(trans);
1026 /* Tell NIC where to find the "keep warm" buffer */
1027 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
1028 trans_pcie->kw.dma >> 4);
1030 spin_unlock(&trans_pcie->irq_lock);
1032 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
1033 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1035 slots_num = (txq_id == trans_pcie->cmd_queue) ?
1036 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1037 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
1040 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
1045 if (trans->cfg->use_tfh) {
1046 iwl_write_direct32(trans, TFH_TRANSFER_MODE,
1047 TFH_TRANSFER_MAX_PENDING_REQ |
1048 TFH_CHUNK_SIZE_128 |
1049 TFH_CHUNK_SPLIT_MODE);
1053 iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
1054 if (trans->cfg->base_params->num_of_queues > 20)
1055 iwl_set_bits_prph(trans, SCD_GP_CTRL,
1056 SCD_GP_CTRL_ENABLE_31_QUEUES);
1060 /*Upon error, free only if we allocated something */
1062 iwl_pcie_tx_free(trans);
1066 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
1068 lockdep_assert_held(&txq->lock);
1070 if (!txq->wd_timeout)
1074 * station is asleep and we send data - that must
1075 * be uAPSD or PS-Poll. Don't rearm the timer.
1081 * if empty delete timer, otherwise move timer forward
1082 * since we're making progress on this queue
1084 if (txq->read_ptr == txq->write_ptr)
1085 del_timer(&txq->stuck_timer);
1087 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1090 /* Frees buffers until index _not_ inclusive */
1091 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1092 struct sk_buff_head *skbs)
1094 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1095 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1096 int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
1099 /* This function is not meant to release cmd queue*/
1100 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
1103 spin_lock_bh(&txq->lock);
1106 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
1111 if (txq->read_ptr == tfd_num)
1114 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1115 txq_id, txq->read_ptr, tfd_num, ssn);
1117 /*Since we free until index _not_ inclusive, the one before index is
1118 * the last we will free. This one must be used */
1119 last_to_free = iwl_queue_dec_wrap(tfd_num);
1121 if (!iwl_queue_used(txq, last_to_free)) {
1123 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
1124 __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
1125 txq->write_ptr, txq->read_ptr);
1129 if (WARN_ON(!skb_queue_empty(skbs)))
1133 txq->read_ptr != tfd_num;
1134 txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr)) {
1135 struct sk_buff *skb = txq->entries[txq->read_ptr].skb;
1137 if (WARN_ON_ONCE(!skb))
1140 iwl_pcie_free_tso_page(trans_pcie, skb);
1142 __skb_queue_tail(skbs, skb);
1144 txq->entries[txq->read_ptr].skb = NULL;
1146 if (!trans->cfg->use_tfh)
1147 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1149 iwl_pcie_txq_free_tfd(trans, txq);
1152 iwl_pcie_txq_progress(txq);
1154 if (iwl_queue_space(txq) > txq->low_mark &&
1155 test_bit(txq_id, trans_pcie->queue_stopped)) {
1156 struct sk_buff_head overflow_skbs;
1158 __skb_queue_head_init(&overflow_skbs);
1159 skb_queue_splice_init(&txq->overflow_q, &overflow_skbs);
1162 * This is tricky: we are in reclaim path which is non
1163 * re-entrant, so noone will try to take the access the
1164 * txq data from that path. We stopped tx, so we can't
1165 * have tx as well. Bottom line, we can unlock and re-lock
1168 spin_unlock_bh(&txq->lock);
1170 while (!skb_queue_empty(&overflow_skbs)) {
1171 struct sk_buff *skb = __skb_dequeue(&overflow_skbs);
1172 struct iwl_device_cmd *dev_cmd_ptr;
1174 dev_cmd_ptr = *(void **)((u8 *)skb->cb +
1175 trans_pcie->dev_cmd_offs);
1178 * Note that we can very well be overflowing again.
1179 * In that case, iwl_queue_space will be small again
1180 * and we won't wake mac80211's queue.
1182 iwl_trans_pcie_tx(trans, skb, dev_cmd_ptr, txq_id);
1184 spin_lock_bh(&txq->lock);
1186 if (iwl_queue_space(txq) > txq->low_mark)
1187 iwl_wake_queue(trans, txq);
1190 if (txq->read_ptr == txq->write_ptr) {
1191 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", txq->id);
1192 iwl_trans_unref(trans);
1196 spin_unlock_bh(&txq->lock);
1199 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1200 const struct iwl_host_cmd *cmd)
1202 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1205 lockdep_assert_held(&trans_pcie->reg_lock);
1207 if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
1208 !trans_pcie->ref_cmd_in_flight) {
1209 trans_pcie->ref_cmd_in_flight = true;
1210 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
1211 iwl_trans_ref(trans);
1215 * wake up the NIC to make sure that the firmware will see the host
1216 * command - we will let the NIC sleep once all the host commands
1217 * returned. This needs to be done only on NICs that have
1218 * apmg_wake_up_wa set.
1220 if (trans->cfg->base_params->apmg_wake_up_wa &&
1221 !trans_pcie->cmd_hold_nic_awake) {
1222 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1223 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1225 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1226 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1227 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1228 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1231 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1232 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1233 IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1236 trans_pcie->cmd_hold_nic_awake = true;
1243 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1245 * When FW advances 'R' index, all entries between old and new 'R' index
1246 * need to be reclaimed. As result, some free space forms. If there is
1247 * enough free space (> low mark), wake the stack that feeds us.
1249 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1251 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1252 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1253 unsigned long flags;
1256 lockdep_assert_held(&txq->lock);
1258 if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(txq, idx))) {
1260 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1261 __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
1262 txq->write_ptr, txq->read_ptr);
1266 for (idx = iwl_queue_inc_wrap(idx); txq->read_ptr != idx;
1267 txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr)) {
1270 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1271 idx, txq->write_ptr, txq->read_ptr);
1272 iwl_force_nmi(trans);
1276 if (txq->read_ptr == txq->write_ptr) {
1277 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1278 iwl_pcie_clear_cmd_in_flight(trans);
1279 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1282 iwl_pcie_txq_progress(txq);
1285 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1288 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1293 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1295 tbl_dw_addr = trans_pcie->scd_base_addr +
1296 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1298 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1301 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1303 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1305 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1310 /* Receiver address (actually, Rx station's index into station table),
1311 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1312 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1314 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1315 const struct iwl_trans_txq_scd_cfg *cfg,
1316 unsigned int wdg_timeout)
1318 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1319 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1322 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1323 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1325 if (cfg && trans->cfg->use_tfh)
1326 WARN_ONCE(1, "Expected no calls to SCD configuration");
1328 txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1333 /* Disable the scheduler prior configuring the cmd queue */
1334 if (txq_id == trans_pcie->cmd_queue &&
1335 trans_pcie->scd_set_active)
1336 iwl_scd_enable_set_active(trans, 0);
1338 /* Stop this Tx queue before configuring it */
1339 iwl_scd_txq_set_inactive(trans, txq_id);
1341 /* Set this queue as a chain-building queue unless it is CMD */
1342 if (txq_id != trans_pcie->cmd_queue)
1343 iwl_scd_txq_set_chain(trans, txq_id);
1345 if (cfg->aggregate) {
1346 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1348 /* Map receiver-address / traffic-ID to this queue */
1349 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1351 /* enable aggregations for the queue */
1352 iwl_scd_txq_enable_agg(trans, txq_id);
1356 * disable aggregations for the queue, this will also
1357 * make the ra_tid mapping configuration irrelevant
1358 * since it is now a non-AGG queue.
1360 iwl_scd_txq_disable_agg(trans, txq_id);
1362 ssn = txq->read_ptr;
1366 /* Place first TFD at index corresponding to start sequence number.
1367 * Assumes that ssn_idx is valid (!= 0xFFF) */
1368 txq->read_ptr = (ssn & 0xff);
1369 txq->write_ptr = (ssn & 0xff);
1370 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1371 (ssn & 0xff) | (txq_id << 8));
1374 u8 frame_limit = cfg->frame_limit;
1376 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1378 /* Set up Tx window size and frame limit for this queue */
1379 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1380 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1381 iwl_trans_write_mem32(trans,
1382 trans_pcie->scd_base_addr +
1383 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1384 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1385 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1386 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1387 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1389 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1390 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1391 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1392 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1393 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1394 SCD_QUEUE_STTS_REG_MSK);
1396 /* enable the scheduler for this queue (only) */
1397 if (txq_id == trans_pcie->cmd_queue &&
1398 trans_pcie->scd_set_active)
1399 iwl_scd_enable_set_active(trans, BIT(txq_id));
1401 IWL_DEBUG_TX_QUEUES(trans,
1402 "Activate queue %d on FIFO %d WrPtr: %d\n",
1403 txq_id, fifo, ssn & 0xff);
1405 IWL_DEBUG_TX_QUEUES(trans,
1406 "Activate queue %d WrPtr: %d\n",
1407 txq_id, ssn & 0xff);
1413 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
1416 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1417 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1419 txq->ampdu = !shared_mode;
1422 dma_addr_t iwl_trans_pcie_get_txq_byte_table(struct iwl_trans *trans, int txq)
1424 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1426 return trans_pcie->scd_bc_tbls.dma +
1427 txq * sizeof(struct iwlagn_scd_bc_tbl);
1430 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1433 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1434 u32 stts_addr = trans_pcie->scd_base_addr +
1435 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1436 static const u32 zero_val[4] = {};
1438 trans_pcie->txq[txq_id].frozen_expiry_remainder = 0;
1439 trans_pcie->txq[txq_id].frozen = false;
1442 * Upon HW Rfkill - we stop the device, and then stop the queues
1443 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1444 * allow the op_mode to call txq_disable after it already called
1447 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1448 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1449 "queue %d not used", txq_id);
1453 if (configure_scd && trans->cfg->use_tfh)
1454 WARN_ONCE(1, "Expected no calls to SCD configuration");
1456 if (configure_scd) {
1457 iwl_scd_txq_set_inactive(trans, txq_id);
1459 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1460 ARRAY_SIZE(zero_val));
1463 iwl_pcie_txq_unmap(trans, txq_id);
1464 trans_pcie->txq[txq_id].ampdu = false;
1466 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1469 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1472 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1473 * @priv: device private data point
1474 * @cmd: a pointer to the ucode command structure
1476 * The function returns < 0 values to indicate the operation
1477 * failed. On success, it returns the index (>= 0) of command in the
1480 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1481 struct iwl_host_cmd *cmd)
1483 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1484 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1485 struct iwl_device_cmd *out_cmd;
1486 struct iwl_cmd_meta *out_meta;
1487 unsigned long flags;
1488 void *dup_buf = NULL;
1489 dma_addr_t phys_addr;
1491 u16 copy_size, cmd_size, tb0_size;
1492 bool had_nocopy = false;
1493 u8 group_id = iwl_cmd_groupid(cmd->id);
1496 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1497 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1499 if (WARN(!trans->wide_cmd_header &&
1500 group_id > IWL_ALWAYS_LONG_GROUP,
1501 "unsupported wide command %#x\n", cmd->id))
1504 if (group_id != 0) {
1505 copy_size = sizeof(struct iwl_cmd_header_wide);
1506 cmd_size = sizeof(struct iwl_cmd_header_wide);
1508 copy_size = sizeof(struct iwl_cmd_header);
1509 cmd_size = sizeof(struct iwl_cmd_header);
1512 /* need one for the header if the first is NOCOPY */
1513 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1515 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1516 cmddata[i] = cmd->data[i];
1517 cmdlen[i] = cmd->len[i];
1522 /* need at least IWL_FIRST_TB_SIZE copied */
1523 if (copy_size < IWL_FIRST_TB_SIZE) {
1524 int copy = IWL_FIRST_TB_SIZE - copy_size;
1526 if (copy > cmdlen[i])
1533 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1535 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1539 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1541 * This is also a chunk that isn't copied
1542 * to the static buffer so set had_nocopy.
1546 /* only allowed once */
1547 if (WARN_ON(dup_buf)) {
1552 dup_buf = kmemdup(cmddata[i], cmdlen[i],
1557 /* NOCOPY must not be followed by normal! */
1558 if (WARN_ON(had_nocopy)) {
1562 copy_size += cmdlen[i];
1564 cmd_size += cmd->len[i];
1568 * If any of the command structures end up being larger than
1569 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1570 * allocated into separate TFDs, then we will need to
1571 * increase the size of the buffers.
1573 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1574 "Command %s (%#x) is too large (%d bytes)\n",
1575 iwl_get_cmd_string(trans, cmd->id),
1576 cmd->id, copy_size)) {
1581 spin_lock_bh(&txq->lock);
1583 if (iwl_queue_space(txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1584 spin_unlock_bh(&txq->lock);
1586 IWL_ERR(trans, "No space in command queue\n");
1587 iwl_op_mode_cmd_queue_full(trans->op_mode);
1592 idx = get_cmd_index(txq, txq->write_ptr);
1593 out_cmd = txq->entries[idx].cmd;
1594 out_meta = &txq->entries[idx].meta;
1596 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1597 if (cmd->flags & CMD_WANT_SKB)
1598 out_meta->source = cmd;
1600 /* set up the header */
1601 if (group_id != 0) {
1602 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1603 out_cmd->hdr_wide.group_id = group_id;
1604 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1605 out_cmd->hdr_wide.length =
1606 cpu_to_le16(cmd_size -
1607 sizeof(struct iwl_cmd_header_wide));
1608 out_cmd->hdr_wide.reserved = 0;
1609 out_cmd->hdr_wide.sequence =
1610 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1611 INDEX_TO_SEQ(txq->write_ptr));
1613 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1614 copy_size = sizeof(struct iwl_cmd_header_wide);
1616 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1617 out_cmd->hdr.sequence =
1618 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1619 INDEX_TO_SEQ(txq->write_ptr));
1620 out_cmd->hdr.group_id = 0;
1622 cmd_pos = sizeof(struct iwl_cmd_header);
1623 copy_size = sizeof(struct iwl_cmd_header);
1626 /* and copy the data that needs to be copied */
1627 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1633 /* copy everything if not nocopy/dup */
1634 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1635 IWL_HCMD_DFL_DUP))) {
1638 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1645 * Otherwise we need at least IWL_FIRST_TB_SIZE copied
1646 * in total (for bi-directional DMA), but copy up to what
1647 * we can fit into the payload for debug dump purposes.
1649 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1651 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1654 /* However, treat copy_size the proper way, we need it below */
1655 if (copy_size < IWL_FIRST_TB_SIZE) {
1656 copy = IWL_FIRST_TB_SIZE - copy_size;
1658 if (copy > cmd->len[i])
1665 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1666 iwl_get_cmd_string(trans, cmd->id),
1667 group_id, out_cmd->hdr.cmd,
1668 le16_to_cpu(out_cmd->hdr.sequence),
1669 cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue);
1671 /* start the TFD with the minimum copy bytes */
1672 tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
1673 memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size);
1674 iwl_pcie_txq_build_tfd(trans, txq,
1675 iwl_pcie_get_first_tb_dma(txq, idx),
1678 /* map first command fragment, if any remains */
1679 if (copy_size > tb0_size) {
1680 phys_addr = dma_map_single(trans->dev,
1681 ((u8 *)&out_cmd->hdr) + tb0_size,
1682 copy_size - tb0_size,
1684 if (dma_mapping_error(trans->dev, phys_addr)) {
1685 iwl_pcie_tfd_unmap(trans, out_meta, txq,
1691 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1692 copy_size - tb0_size, false);
1695 /* map the remaining (adjusted) nocopy/dup fragments */
1696 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1697 const void *data = cmddata[i];
1701 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1704 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1706 phys_addr = dma_map_single(trans->dev, (void *)data,
1707 cmdlen[i], DMA_TO_DEVICE);
1708 if (dma_mapping_error(trans->dev, phys_addr)) {
1709 iwl_pcie_tfd_unmap(trans, out_meta, txq,
1715 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1718 BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE);
1719 out_meta->flags = cmd->flags;
1720 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1721 kzfree(txq->entries[idx].free_buf);
1722 txq->entries[idx].free_buf = dup_buf;
1724 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1726 /* start timer if queue currently empty */
1727 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
1728 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1730 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1731 ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1734 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1738 /* Increment and update queue's write index */
1739 txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr);
1740 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1742 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1745 spin_unlock_bh(&txq->lock);
1753 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1754 * @rxb: Rx buffer to reclaim
1756 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1757 struct iwl_rx_cmd_buffer *rxb)
1759 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1760 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1761 u8 group_id = iwl_cmd_groupid(pkt->hdr.group_id);
1763 int txq_id = SEQ_TO_QUEUE(sequence);
1764 int index = SEQ_TO_INDEX(sequence);
1766 struct iwl_device_cmd *cmd;
1767 struct iwl_cmd_meta *meta;
1768 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1769 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1771 /* If a Tx command is being handled and it isn't in the actual
1772 * command queue then there a command routing bug has been introduced
1773 * in the queue management code. */
1774 if (WARN(txq_id != trans_pcie->cmd_queue,
1775 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1776 txq_id, trans_pcie->cmd_queue, sequence,
1777 trans_pcie->txq[trans_pcie->cmd_queue].read_ptr,
1778 trans_pcie->txq[trans_pcie->cmd_queue].write_ptr)) {
1779 iwl_print_hex_error(trans, pkt, 32);
1783 spin_lock_bh(&txq->lock);
1785 cmd_index = get_cmd_index(txq, index);
1786 cmd = txq->entries[cmd_index].cmd;
1787 meta = &txq->entries[cmd_index].meta;
1788 cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0);
1790 iwl_pcie_tfd_unmap(trans, meta, txq, index);
1792 /* Input error checking is done when commands are added to queue. */
1793 if (meta->flags & CMD_WANT_SKB) {
1794 struct page *p = rxb_steal_page(rxb);
1796 meta->source->resp_pkt = pkt;
1797 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1798 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1801 if (meta->flags & CMD_WANT_ASYNC_CALLBACK)
1802 iwl_op_mode_async_cb(trans->op_mode, cmd);
1804 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1806 if (!(meta->flags & CMD_ASYNC)) {
1807 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1809 "HCMD_ACTIVE already clear for command %s\n",
1810 iwl_get_cmd_string(trans, cmd_id));
1812 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1813 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1814 iwl_get_cmd_string(trans, cmd_id));
1815 wake_up(&trans_pcie->wait_command_queue);
1818 if (meta->flags & CMD_MAKE_TRANS_IDLE) {
1819 IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n",
1820 iwl_get_cmd_string(trans, cmd->hdr.cmd));
1821 set_bit(STATUS_TRANS_IDLE, &trans->status);
1822 wake_up(&trans_pcie->d0i3_waitq);
1825 if (meta->flags & CMD_WAKE_UP_TRANS) {
1826 IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n",
1827 iwl_get_cmd_string(trans, cmd->hdr.cmd));
1828 clear_bit(STATUS_TRANS_IDLE, &trans->status);
1829 wake_up(&trans_pcie->d0i3_waitq);
1834 spin_unlock_bh(&txq->lock);
1837 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1839 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1840 struct iwl_host_cmd *cmd)
1844 /* An asynchronous command can not expect an SKB to be set. */
1845 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1848 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1851 "Error sending %s: enqueue_hcmd failed: %d\n",
1852 iwl_get_cmd_string(trans, cmd->id), ret);
1858 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1859 struct iwl_host_cmd *cmd)
1861 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1865 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1866 iwl_get_cmd_string(trans, cmd->id));
1868 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1870 "Command %s: a command is already active!\n",
1871 iwl_get_cmd_string(trans, cmd->id)))
1874 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1875 iwl_get_cmd_string(trans, cmd->id));
1877 if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) {
1878 ret = wait_event_timeout(trans_pcie->d0i3_waitq,
1879 pm_runtime_active(&trans_pcie->pci_dev->dev),
1880 msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT));
1882 IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n");
1887 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1890 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1892 "Error sending %s: enqueue_hcmd failed: %d\n",
1893 iwl_get_cmd_string(trans, cmd->id), ret);
1897 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1898 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1900 HOST_COMPLETE_TIMEOUT);
1902 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1904 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1905 iwl_get_cmd_string(trans, cmd->id),
1906 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1908 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1909 txq->read_ptr, txq->write_ptr);
1911 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1912 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1913 iwl_get_cmd_string(trans, cmd->id));
1916 iwl_force_nmi(trans);
1917 iwl_trans_fw_error(trans);
1922 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1923 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1924 iwl_get_cmd_string(trans, cmd->id));
1930 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1931 test_bit(STATUS_RFKILL, &trans->status)) {
1932 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1937 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1938 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1939 iwl_get_cmd_string(trans, cmd->id));
1947 if (cmd->flags & CMD_WANT_SKB) {
1949 * Cancel the CMD_WANT_SKB flag for the cmd in the
1950 * TX cmd queue. Otherwise in case the cmd comes
1951 * in later, it will possibly set an invalid
1952 * address (cmd->meta.source).
1954 trans_pcie->txq[trans_pcie->cmd_queue].
1955 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1958 if (cmd->resp_pkt) {
1960 cmd->resp_pkt = NULL;
1966 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1968 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1969 test_bit(STATUS_RFKILL, &trans->status)) {
1970 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1975 if (cmd->flags & CMD_ASYNC)
1976 return iwl_pcie_send_hcmd_async(trans, cmd);
1978 /* We still can fail on RFKILL that can be asserted while we wait */
1979 return iwl_pcie_send_hcmd_sync(trans, cmd);
1982 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
1983 struct iwl_txq *txq, u8 hdr_len,
1984 struct iwl_cmd_meta *out_meta,
1985 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
1987 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1992 * Set up TFD's third entry to point directly to remainder
1993 * of skb's head, if any
1995 tb2_len = skb_headlen(skb) - hdr_len;
1998 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1999 skb->data + hdr_len,
2000 tb2_len, DMA_TO_DEVICE);
2001 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
2002 iwl_pcie_tfd_unmap(trans, out_meta, txq,
2006 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
2009 /* set up the remaining entries to point to the data */
2010 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2011 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2015 if (!skb_frag_size(frag))
2018 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
2019 skb_frag_size(frag), DMA_TO_DEVICE);
2021 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
2022 iwl_pcie_tfd_unmap(trans, out_meta, txq,
2026 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2027 skb_frag_size(frag), false);
2029 out_meta->tbs |= BIT(tb_idx);
2032 trace_iwlwifi_dev_tx(trans->dev, skb,
2033 iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr),
2034 trans_pcie->tfd_size,
2035 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
2036 skb->data + hdr_len, tb2_len);
2037 trace_iwlwifi_dev_tx_data(trans->dev, skb,
2038 hdr_len, skb->len - hdr_len);
2043 static struct iwl_tso_hdr_page *
2044 get_page_hdr(struct iwl_trans *trans, size_t len)
2046 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2047 struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page);
2052 /* enough room on this page */
2053 if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE)
2056 /* We don't have enough room on this page, get a new one. */
2057 __free_page(p->page);
2060 p->page = alloc_page(GFP_ATOMIC);
2063 p->pos = page_address(p->page);
2067 static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph,
2068 bool ipv6, unsigned int len)
2071 struct ipv6hdr *iphv6 = iph;
2073 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr,
2074 len + tcph->doff * 4,
2077 struct iphdr *iphv4 = iph;
2079 ip_send_check(iphv4);
2080 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr,
2081 len + tcph->doff * 4,
2086 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2087 struct iwl_txq *txq, u8 hdr_len,
2088 struct iwl_cmd_meta *out_meta,
2089 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2091 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
2092 struct ieee80211_hdr *hdr = (void *)skb->data;
2093 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
2094 unsigned int mss = skb_shinfo(skb)->gso_size;
2095 u16 length, iv_len, amsdu_pad;
2097 struct iwl_tso_hdr_page *hdr_page;
2098 struct page **page_ptr;
2102 /* if the packet is protected, then it must be CCMP or GCMP */
2103 BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN);
2104 iv_len = ieee80211_has_protected(hdr->frame_control) ?
2105 IEEE80211_CCMP_HDR_LEN : 0;
2107 trace_iwlwifi_dev_tx(trans->dev, skb,
2108 iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr),
2109 trans_pcie->tfd_size,
2110 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
2113 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
2114 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
2115 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len;
2118 /* total amount of header we may need for this A-MSDU */
2119 hdr_room = DIV_ROUND_UP(total_len, mss) *
2120 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len;
2122 /* Our device supports 9 segments at most, it will fit in 1 page */
2123 hdr_page = get_page_hdr(trans, hdr_room);
2127 get_page(hdr_page->page);
2128 start_hdr = hdr_page->pos;
2129 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
2130 *page_ptr = hdr_page->page;
2131 memcpy(hdr_page->pos, skb->data + hdr_len, iv_len);
2132 hdr_page->pos += iv_len;
2135 * Pull the ieee80211 header + IV to be able to use TSO core,
2136 * we will restore it for the tx_status flow.
2138 skb_pull(skb, hdr_len + iv_len);
2140 tso_start(skb, &tso);
2143 /* this is the data left for this subframe */
2144 unsigned int data_left =
2145 min_t(unsigned int, mss, total_len);
2146 struct sk_buff *csum_skb = NULL;
2147 unsigned int hdr_tb_len;
2148 dma_addr_t hdr_tb_phys;
2149 struct tcphdr *tcph;
2152 total_len -= data_left;
2154 memset(hdr_page->pos, 0, amsdu_pad);
2155 hdr_page->pos += amsdu_pad;
2156 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
2158 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
2159 hdr_page->pos += ETH_ALEN;
2160 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
2161 hdr_page->pos += ETH_ALEN;
2163 length = snap_ip_tcp_hdrlen + data_left;
2164 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
2165 hdr_page->pos += sizeof(length);
2168 * This will copy the SNAP as well which will be considered
2171 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
2172 iph = hdr_page->pos + 8;
2173 tcph = (void *)(iph + ip_hdrlen);
2175 /* For testing on current hardware only */
2176 if (trans_pcie->sw_csum_tx) {
2177 csum_skb = alloc_skb(data_left + tcp_hdrlen(skb),
2184 iwl_compute_pseudo_hdr_csum(iph, tcph,
2189 memcpy(skb_put(csum_skb, tcp_hdrlen(skb)),
2190 tcph, tcp_hdrlen(skb));
2191 skb_set_transport_header(csum_skb, 0);
2192 csum_skb->csum_start =
2193 (unsigned char *)tcp_hdr(csum_skb) -
2197 hdr_page->pos += snap_ip_tcp_hdrlen;
2199 hdr_tb_len = hdr_page->pos - start_hdr;
2200 hdr_tb_phys = dma_map_single(trans->dev, start_hdr,
2201 hdr_tb_len, DMA_TO_DEVICE);
2202 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) {
2203 dev_kfree_skb(csum_skb);
2207 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys,
2209 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr,
2212 /* prepare the start_hdr for the next subframe */
2213 start_hdr = hdr_page->pos;
2215 /* put the payload */
2217 unsigned int size = min_t(unsigned int, tso.size,
2221 if (trans_pcie->sw_csum_tx)
2222 memcpy(skb_put(csum_skb, size), tso.data, size);
2224 tb_phys = dma_map_single(trans->dev, tso.data,
2225 size, DMA_TO_DEVICE);
2226 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
2227 dev_kfree_skb(csum_skb);
2232 iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2234 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data,
2238 tso_build_data(skb, &tso, size);
2241 /* For testing on early hardware only */
2242 if (trans_pcie->sw_csum_tx) {
2245 csum = skb_checksum(csum_skb,
2246 skb_checksum_start_offset(csum_skb),
2248 skb_checksum_start_offset(csum_skb),
2250 dev_kfree_skb(csum_skb);
2251 dma_sync_single_for_cpu(trans->dev, hdr_tb_phys,
2252 hdr_tb_len, DMA_TO_DEVICE);
2253 tcph->check = csum_fold(csum);
2254 dma_sync_single_for_device(trans->dev, hdr_tb_phys,
2255 hdr_tb_len, DMA_TO_DEVICE);
2259 /* re -add the WiFi header and IV */
2260 skb_push(skb, hdr_len + iv_len);
2265 iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr);
2268 #else /* CONFIG_INET */
2269 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2270 struct iwl_txq *txq, u8 hdr_len,
2271 struct iwl_cmd_meta *out_meta,
2272 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2274 /* No A-MSDU without CONFIG_INET */
2279 #endif /* CONFIG_INET */
2281 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
2282 struct iwl_device_cmd *dev_cmd, int txq_id)
2284 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2285 struct ieee80211_hdr *hdr;
2286 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
2287 struct iwl_cmd_meta *out_meta;
2288 struct iwl_txq *txq;
2289 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
2293 bool wait_write_ptr;
2299 txq = &trans_pcie->txq[txq_id];
2301 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
2302 "TX on unused queue %d\n", txq_id))
2305 if (unlikely(trans_pcie->sw_csum_tx &&
2306 skb->ip_summed == CHECKSUM_PARTIAL)) {
2307 int offs = skb_checksum_start_offset(skb);
2308 int csum_offs = offs + skb->csum_offset;
2311 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16)))
2314 csum = skb_checksum(skb, offs, skb->len - offs, 0);
2315 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum);
2317 skb->ip_summed = CHECKSUM_UNNECESSARY;
2320 if (skb_is_nonlinear(skb) &&
2321 skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) &&
2322 __skb_linearize(skb))
2325 /* mac80211 always puts the full header into the SKB's head,
2326 * so there's no need to check if it's readable there
2328 hdr = (struct ieee80211_hdr *)skb->data;
2329 fc = hdr->frame_control;
2330 hdr_len = ieee80211_hdrlen(fc);
2332 spin_lock(&txq->lock);
2334 if (iwl_queue_space(txq) < txq->high_mark) {
2335 iwl_stop_queue(trans, txq);
2337 /* don't put the packet on the ring, if there is no room */
2338 if (unlikely(iwl_queue_space(txq) < 3)) {
2339 struct iwl_device_cmd **dev_cmd_ptr;
2341 dev_cmd_ptr = (void *)((u8 *)skb->cb +
2342 trans_pcie->dev_cmd_offs);
2344 *dev_cmd_ptr = dev_cmd;
2345 __skb_queue_tail(&txq->overflow_q, skb);
2347 spin_unlock(&txq->lock);
2352 /* In AGG mode, the index in the ring must correspond to the WiFi
2353 * sequence number. This is a HW requirements to help the SCD to parse
2355 * Check here that the packets are in the right place on the ring.
2357 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
2358 WARN_ONCE(txq->ampdu &&
2359 (wifi_seq & 0xff) != txq->write_ptr,
2360 "Q: %d WiFi Seq %d tfdNum %d",
2361 txq_id, wifi_seq, txq->write_ptr);
2363 /* Set up driver data for this TFD */
2364 txq->entries[txq->write_ptr].skb = skb;
2365 txq->entries[txq->write_ptr].cmd = dev_cmd;
2367 dev_cmd->hdr.sequence =
2368 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2369 INDEX_TO_SEQ(txq->write_ptr)));
2371 tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr);
2372 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
2373 offsetof(struct iwl_tx_cmd, scratch);
2375 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
2376 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
2378 /* Set up first empty entry in queue's array of Tx/cmd buffers */
2379 out_meta = &txq->entries[txq->write_ptr].meta;
2380 out_meta->flags = 0;
2383 * The second TB (tb1) points to the remainder of the TX command
2384 * and the 802.11 header - dword aligned size
2385 * (This calculation modifies the TX command, so do it before the
2386 * setup of the first TB)
2388 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
2389 hdr_len - IWL_FIRST_TB_SIZE;
2390 /* do not align A-MSDU to dword as the subframe header aligns it */
2391 amsdu = ieee80211_is_data_qos(fc) &&
2392 (*ieee80211_get_qos_ctl(hdr) &
2393 IEEE80211_QOS_CTL_A_MSDU_PRESENT);
2394 if (trans_pcie->sw_csum_tx || !amsdu) {
2395 tb1_len = ALIGN(len, 4);
2396 /* Tell NIC about any 2-byte padding after MAC header */
2398 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
2403 /* The first TB points to bi-directional DMA data */
2404 memcpy(&txq->first_tb_bufs[txq->write_ptr], &dev_cmd->hdr,
2406 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
2407 IWL_FIRST_TB_SIZE, true);
2409 /* there must be data left over for TB1 or this code must be changed */
2410 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE);
2412 /* map the data for TB1 */
2413 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
2414 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
2415 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
2417 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
2420 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
2424 } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
2425 out_meta, dev_cmd, tb1_len))) {
2429 tfd = iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr);
2430 /* Set up entry for this TFD in Tx byte-count array */
2431 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len),
2432 iwl_pcie_tfd_get_num_tbs(trans, tfd));
2434 wait_write_ptr = ieee80211_has_morefrags(fc);
2436 /* start timer if queue currently empty */
2437 if (txq->read_ptr == txq->write_ptr) {
2438 if (txq->wd_timeout) {
2440 * If the TXQ is active, then set the timer, if not,
2441 * set the timer in remainder so that the timer will
2442 * be armed with the right value when the station will
2446 mod_timer(&txq->stuck_timer,
2447 jiffies + txq->wd_timeout);
2449 txq->frozen_expiry_remainder = txq->wd_timeout;
2451 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", txq->id);
2452 iwl_trans_ref(trans);
2455 /* Tell device the write index *just past* this latest filled TFD */
2456 txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr);
2457 if (!wait_write_ptr)
2458 iwl_pcie_txq_inc_wr_ptr(trans, txq);
2461 * At this point the frame is "transmitted" successfully
2462 * and we will get a TX status notification eventually.
2464 spin_unlock(&txq->lock);
2467 spin_unlock(&txq->lock);