drivers/net/wireless/iwlwifi/iwl-agn-lib.c

   1 /******************************************************************************
   2  *
   3  * GPL LICENSE SUMMARY
   4  *
   5  * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19  * USA
  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/etherdevice.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/init.h>
  33 #include <linux/sched.h>
  34
  35 #include "iwl-dev.h"
  36 #include "iwl-core.h"
  37 #include "iwl-io.h"
  38 #include "iwl-helpers.h"
  39 #include "iwl-agn-hw.h"
  40 #include "iwl-agn.h"
  41 #include "iwl-sta.h"
  42
  43 static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
  44 {
  45         return le32_to_cpup((__le32 *)&tx_resp->status +
  46                             tx_resp->frame_count) & MAX_SN;
  47 }
  48
  49 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
  50 {
  51         status &= TX_STATUS_MSK;
  52
  53         switch (status) {
  54         case TX_STATUS_POSTPONE_DELAY:
  55                 priv->_agn.reply_tx_stats.pp_delay++;
  56                 break;
  57         case TX_STATUS_POSTPONE_FEW_BYTES:
  58                 priv->_agn.reply_tx_stats.pp_few_bytes++;
  59                 break;
  60         case TX_STATUS_POSTPONE_BT_PRIO:
  61                 priv->_agn.reply_tx_stats.pp_bt_prio++;
  62                 break;
  63         case TX_STATUS_POSTPONE_QUIET_PERIOD:
  64                 priv->_agn.reply_tx_stats.pp_quiet_period++;
  65                 break;
  66         case TX_STATUS_POSTPONE_CALC_TTAK:
  67                 priv->_agn.reply_tx_stats.pp_calc_ttak++;
  68                 break;
  69         case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
  70                 priv->_agn.reply_tx_stats.int_crossed_retry++;
  71                 break;
  72         case TX_STATUS_FAIL_SHORT_LIMIT:
  73                 priv->_agn.reply_tx_stats.short_limit++;
  74                 break;
  75         case TX_STATUS_FAIL_LONG_LIMIT:
  76                 priv->_agn.reply_tx_stats.long_limit++;
  77                 break;
  78         case TX_STATUS_FAIL_FIFO_UNDERRUN:
  79                 priv->_agn.reply_tx_stats.fifo_underrun++;
  80                 break;
  81         case TX_STATUS_FAIL_DRAIN_FLOW:
  82                 priv->_agn.reply_tx_stats.drain_flow++;
  83                 break;
  84         case TX_STATUS_FAIL_RFKILL_FLUSH:
  85                 priv->_agn.reply_tx_stats.rfkill_flush++;
  86                 break;
  87         case TX_STATUS_FAIL_LIFE_EXPIRE:
  88                 priv->_agn.reply_tx_stats.life_expire++;
  89                 break;
  90         case TX_STATUS_FAIL_DEST_PS:
  91                 priv->_agn.reply_tx_stats.dest_ps++;
  92                 break;
  93         case TX_STATUS_FAIL_HOST_ABORTED:
  94                 priv->_agn.reply_tx_stats.host_abort++;
  95                 break;
  96         case TX_STATUS_FAIL_BT_RETRY:
  97                 priv->_agn.reply_tx_stats.bt_retry++;
  98                 break;
  99         case TX_STATUS_FAIL_STA_INVALID:
 100                 priv->_agn.reply_tx_stats.sta_invalid++;
 101                 break;
 102         case TX_STATUS_FAIL_FRAG_DROPPED:
 103                 priv->_agn.reply_tx_stats.frag_drop++;
 104                 break;
 105         case TX_STATUS_FAIL_TID_DISABLE:
 106                 priv->_agn.reply_tx_stats.tid_disable++;
 107                 break;
 108         case TX_STATUS_FAIL_FIFO_FLUSHED:
 109                 priv->_agn.reply_tx_stats.fifo_flush++;
 110                 break;
 111         case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
 112                 priv->_agn.reply_tx_stats.insuff_cf_poll++;
 113                 break;
 114         case TX_STATUS_FAIL_PASSIVE_NO_RX:
 115                 priv->_agn.reply_tx_stats.fail_hw_drop++;
 116                 break;
 117         case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
 118                 priv->_agn.reply_tx_stats.sta_color_mismatch++;
 119                 break;
 120         default:
 121                 priv->_agn.reply_tx_stats.unknown++;
 122                 break;
 123         }
 124 }
 125
 126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
 127 {
 128         status &= AGG_TX_STATUS_MSK;
 129
 130         switch (status) {
 131         case AGG_TX_STATE_UNDERRUN_MSK:
 132                 priv->_agn.reply_agg_tx_stats.underrun++;
 133                 break;
 134         case AGG_TX_STATE_BT_PRIO_MSK:
 135                 priv->_agn.reply_agg_tx_stats.bt_prio++;
 136                 break;
 137         case AGG_TX_STATE_FEW_BYTES_MSK:
 138                 priv->_agn.reply_agg_tx_stats.few_bytes++;
 139                 break;
 140         case AGG_TX_STATE_ABORT_MSK:
 141                 priv->_agn.reply_agg_tx_stats.abort++;
 142                 break;
 143         case AGG_TX_STATE_LAST_SENT_TTL_MSK:
 144                 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
 145                 break;
 146         case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
 147                 priv->_agn.reply_agg_tx_stats.last_sent_try++;
 148                 break;
 149         case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
 150                 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
 151                 break;
 152         case AGG_TX_STATE_SCD_QUERY_MSK:
 153                 priv->_agn.reply_agg_tx_stats.scd_query++;
 154                 break;
 155         case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
 156                 priv->_agn.reply_agg_tx_stats.bad_crc32++;
 157                 break;
 158         case AGG_TX_STATE_RESPONSE_MSK:
 159                 priv->_agn.reply_agg_tx_stats.response++;
 160                 break;
 161         case AGG_TX_STATE_DUMP_TX_MSK:
 162                 priv->_agn.reply_agg_tx_stats.dump_tx++;
 163                 break;
 164         case AGG_TX_STATE_DELAY_TX_MSK:
 165                 priv->_agn.reply_agg_tx_stats.delay_tx++;
 166                 break;
 167         default:
 168                 priv->_agn.reply_agg_tx_stats.unknown++;
 169                 break;
 170         }
 171 }
 172
 173 static void iwlagn_set_tx_status(struct iwl_priv *priv,
 174                                  struct ieee80211_tx_info *info,
 175                                  struct iwlagn_tx_resp *tx_resp,
 176                                  int txq_id, bool is_agg)
 177 {
 178         u16  status = le16_to_cpu(tx_resp->status.status);
 179
 180         info->status.rates[0].count = tx_resp->failure_frame + 1;
 181         if (is_agg)
 182                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
 183         info->flags |= iwl_tx_status_to_mac80211(status);
 184         iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
 185                                     info);
 186         if (!iwl_is_tx_success(status))
 187                 iwlagn_count_tx_err_status(priv, status);
 188
 189         IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
 190                            "0x%x retries %d\n",
 191                            txq_id,
 192                            iwl_get_tx_fail_reason(status), status,
 193                            le32_to_cpu(tx_resp->rate_n_flags),
 194                            tx_resp->failure_frame);
 195 }
 196
 197 #ifdef CONFIG_IWLWIFI_DEBUG
 198 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
 199
 200 const char *iwl_get_agg_tx_fail_reason(u16 status)
 201 {
 202         status &= AGG_TX_STATUS_MSK;
 203         switch (status) {
 204         case AGG_TX_STATE_TRANSMITTED:
 205                 return "SUCCESS";
 206                 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
 207                 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
 208                 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
 209                 AGG_TX_STATE_FAIL(ABORT_MSK);
 210                 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
 211                 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
 212                 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
 213                 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
 214                 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
 215                 AGG_TX_STATE_FAIL(RESPONSE_MSK);
 216                 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
 217                 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
 218         }
 219
 220         return "UNKNOWN";
 221 }
 222 #endif /* CONFIG_IWLWIFI_DEBUG */
 223
 224 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
 225                                       struct iwl_ht_agg *agg,
 226                                       struct iwlagn_tx_resp *tx_resp,
 227                                       int txq_id, u16 start_idx)
 228 {
 229         u16 status;
 230         struct agg_tx_status *frame_status = &tx_resp->status;
 231         struct ieee80211_hdr *hdr = NULL;
 232         int i, sh, idx;
 233         u16 seq;
 234
 235         if (agg->wait_for_ba)
 236                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
 237
 238         agg->frame_count = tx_resp->frame_count;
 239         agg->start_idx = start_idx;
 240         agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
 241         agg->bitmap = 0;
 242
 243         /* # frames attempted by Tx command */
 244         if (agg->frame_count == 1) {
 245                 /* Only one frame was attempted; no block-ack will arrive */
 246                 idx = start_idx;
 247
 248                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
 249                                    agg->frame_count, agg->start_idx, idx);
 250                 iwlagn_set_tx_status(priv,
 251                                      IEEE80211_SKB_CB(
 252                                         priv->txq[txq_id].txb[idx].skb),
 253                                      tx_resp, txq_id, true);
 254                 agg->wait_for_ba = 0;
 255         } else {
 256                 /* Two or more frames were attempted; expect block-ack */
 257                 u64 bitmap = 0;
 258
 259                 /*
 260                  * Start is the lowest frame sent. It may not be the first
 261                  * frame in the batch; we figure this out dynamically during
 262                  * the following loop.
 263                  */
 264                 int start = agg->start_idx;
 265
 266                 /* Construct bit-map of pending frames within Tx window */
 267                 for (i = 0; i < agg->frame_count; i++) {
 268                         u16 sc;
 269                         status = le16_to_cpu(frame_status[i].status);
 270                         seq  = le16_to_cpu(frame_status[i].sequence);
 271                         idx = SEQ_TO_INDEX(seq);
 272                         txq_id = SEQ_TO_QUEUE(seq);
 273
 274                         if (status & AGG_TX_STATUS_MSK)
 275                                 iwlagn_count_agg_tx_err_status(priv, status);
 276
 277                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
 278                                       AGG_TX_STATE_ABORT_MSK))
 279                                 continue;
 280
 281                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
 282                                            agg->frame_count, txq_id, idx);
 283                         IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
 284                                            "try-count (0x%08x)\n",
 285                                            iwl_get_agg_tx_fail_reason(status),
 286                                            status & AGG_TX_STATUS_MSK,
 287                                            status & AGG_TX_TRY_MSK);
 288
 289                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
 290                         if (!hdr) {
 291                                 IWL_ERR(priv,
 292                                         "BUG_ON idx doesn't point to valid skb"
 293                                         " idx=%d, txq_id=%d\n", idx, txq_id);
 294                                 return -1;
 295                         }
 296
 297                         sc = le16_to_cpu(hdr->seq_ctrl);
 298                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
 299                                 IWL_ERR(priv,
 300                                         "BUG_ON idx doesn't match seq control"
 301                                         " idx=%d, seq_idx=%d, seq=%d\n",
 302                                           idx, SEQ_TO_SN(sc),
 303                                           hdr->seq_ctrl);
 304                                 return -1;
 305                         }
 306
 307                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
 308                                            i, idx, SEQ_TO_SN(sc));
 309
 310                         /*
 311                          * sh -> how many frames ahead of the starting frame is
 312                          * the current one?
 313                          *
 314                          * Note that all frames sent in the batch must be in a
 315                          * 64-frame window, so this number should be in [0,63].
 316                          * If outside of this window, then we've found a new
 317                          * "first" frame in the batch and need to change start.
 318                          */
 319                         sh = idx - start;
 320
 321                         /*
 322                          * If >= 64, out of window. start must be at the front
 323                          * of the circular buffer, idx must be near the end of
 324                          * the buffer, and idx is the new "first" frame. Shift
 325                          * the indices around.
 326                          */
 327                         if (sh >= 64) {
 328                                 /* Shift bitmap by start - idx, wrapped */
 329                                 sh = 0x100 - idx + start;
 330                                 bitmap = bitmap << sh;
 331                                 /* Now idx is the new start so sh = 0 */
 332                                 sh = 0;
 333                                 start = idx;
 334                         /*
 335                          * If <= -64 then wraps the 256-pkt circular buffer
 336                          * (e.g., start = 255 and idx = 0, sh should be 1)
 337                          */
 338                         } else if (sh <= -64) {
 339                                 sh  = 0x100 - start + idx;
 340                         /*
 341                          * If < 0 but > -64, out of window. idx is before start
 342                          * but not wrapped. Shift the indices around.
 343                          */
 344                         } else if (sh < 0) {
 345                                 /* Shift by how far start is ahead of idx */
 346                                 sh = start - idx;
 347                                 bitmap = bitmap << sh;
 348                                 /* Now idx is the new start so sh = 0 */
 349                                 start = idx;
 350                                 sh = 0;
 351                         }
 352                         /* Sequence number start + sh was sent in this batch */
 353                         bitmap |= 1ULL << sh;
 354                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
 355                                            start, (unsigned long long)bitmap);
 356                 }
 357
 358                 /*
 359                  * Store the bitmap and possibly the new start, if we wrapped
 360                  * the buffer above
 361                  */
 362                 agg->bitmap = bitmap;
 363                 agg->start_idx = start;
 364                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
 365                                    agg->frame_count, agg->start_idx,
 366                                    (unsigned long long)agg->bitmap);
 367
 368                 if (bitmap)
 369                         agg->wait_for_ba = 1;
 370         }
 371         return 0;
 372 }
 373
 374 void iwl_check_abort_status(struct iwl_priv *priv,
 375                             u8 frame_count, u32 status)
 376 {
 377         if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
 378                 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
 379                 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 380                         queue_work(priv->workqueue, &priv->tx_flush);
 381         }
 382 }
 383
 384 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
 385                                 struct iwl_rx_mem_buffer *rxb)
 386 {
 387         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 388         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 389         int txq_id = SEQ_TO_QUEUE(sequence);
 390         int index = SEQ_TO_INDEX(sequence);
 391         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 392         struct ieee80211_tx_info *info;
 393         struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 394         u32  status = le16_to_cpu(tx_resp->status.status);
 395         int tid;
 396         int sta_id;
 397         int freed;
 398         unsigned long flags;
 399
 400         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 401                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 402                           "is out of range [0-%d] %d %d\n", txq_id,
 403                           index, txq->q.n_bd, txq->q.write_ptr,
 404                           txq->q.read_ptr);
 405                 return;
 406         }
 407
 408         txq->time_stamp = jiffies;
 409         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
 410         memset(&info->status, 0, sizeof(info->status));
 411
 412         tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
 413                 IWLAGN_TX_RES_TID_POS;
 414         sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
 415                 IWLAGN_TX_RES_RA_POS;
 416
 417         spin_lock_irqsave(&priv->sta_lock, flags);
 418         if (txq->sched_retry) {
 419                 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
 420                 struct iwl_ht_agg *agg;
 421
 422                 agg = &priv->stations[sta_id].tid[tid].agg;
 423                 /*
 424                  * If the BT kill count is non-zero, we'll get this
 425                  * notification again.
 426                  */
 427                 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
 428                     priv->cfg->bt_params &&
 429                     priv->cfg->bt_params->advanced_bt_coexist) {
 430                         IWL_WARN(priv, "receive reply tx with bt_kill\n");
 431                 }
 432                 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
 433
 434                 /* check if BAR is needed */
 435                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
 436                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
 437
 438                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
 439                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
 440                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
 441                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
 442                                         scd_ssn , index, txq_id, txq->swq_id);
 443
 444                         freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
 445                         iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
 446
 447                         if (priv->mac80211_registered &&
 448                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
 449                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
 450                                 iwl_wake_queue(priv, txq);
 451                 }
 452         } else {
 453                 iwlagn_set_tx_status(priv, info, tx_resp, txq_id, false);
 454                 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
 455                 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
 456
 457                 if (priv->mac80211_registered &&
 458                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
 459                         iwl_wake_queue(priv, txq);
 460         }
 461
 462         iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
 463
 464         iwl_check_abort_status(priv, tx_resp->frame_count, status);
 465         spin_unlock_irqrestore(&priv->sta_lock, flags);
 466 }
 467
 468 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
 469 {
 470         /* init calibration handlers */
 471         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
 472                                         iwlagn_rx_calib_result;
 473         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
 474                                         iwlagn_rx_calib_complete;
 475         priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
 476 }
 477
 478 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
 479 {
 480         /* in agn, the tx power calibration is done in uCode */
 481         priv->disable_tx_power_cal = 1;
 482 }
 483
 484 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
 485 {
 486         return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
 487                 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
 488 }
 489
 490 int iwlagn_send_tx_power(struct iwl_priv *priv)
 491 {
 492         struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
 493         u8 tx_ant_cfg_cmd;
 494
 495         if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
 496                       "TX Power requested while scanning!\n"))
 497                 return -EAGAIN;
 498
 499         /* half dBm need to multiply */
 500         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
 501
 502         if (priv->tx_power_lmt_in_half_dbm &&
 503             priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
 504                 /*
 505                  * For the newer devices which using enhanced/extend tx power
 506                  * table in EEPROM, the format is in half dBm. driver need to
 507                  * convert to dBm format before report to mac80211.
 508                  * By doing so, there is a possibility of 1/2 dBm resolution
 509                  * lost. driver will perform "round-up" operation before
 510                  * reporting, but it will cause 1/2 dBm tx power over the
 511                  * regulatory limit. Perform the checking here, if the
 512                  * "tx_power_user_lmt" is higher than EEPROM value (in
 513                  * half-dBm format), lower the tx power based on EEPROM
 514                  */
 515                 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
 516         }
 517         tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
 518         tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
 519
 520         if (IWL_UCODE_API(priv->ucode_ver) == 1)
 521                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
 522         else
 523                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
 524
 525         return iwl_send_cmd_pdu(priv, tx_ant_cfg_cmd, sizeof(tx_power_cmd),
 526                                 &tx_power_cmd);
 527 }
 528
 529 void iwlagn_temperature(struct iwl_priv *priv)
 530 {
 531         /* store temperature from statistics (in Celsius) */
 532         priv->temperature =
 533                 le32_to_cpu(priv->_agn.statistics.general.common.temperature);
 534         iwl_tt_handler(priv);
 535 }
 536
 537 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
 538 {
 539         struct iwl_eeprom_calib_hdr {
 540                 u8 version;
 541                 u8 pa_type;
 542                 u16 voltage;
 543         } *hdr;
 544
 545         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 546                                                         EEPROM_CALIB_ALL);
 547         return hdr->version;
 548
 549 }
 550
 551 /*
 552  * EEPROM
 553  */
 554 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 555 {
 556         u16 offset = 0;
 557
 558         if ((address & INDIRECT_ADDRESS) == 0)
 559                 return address;
 560
 561         switch (address & INDIRECT_TYPE_MSK) {
 562         case INDIRECT_HOST:
 563                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
 564                 break;
 565         case INDIRECT_GENERAL:
 566                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
 567                 break;
 568         case INDIRECT_REGULATORY:
 569                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
 570                 break;
 571         case INDIRECT_CALIBRATION:
 572                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
 573                 break;
 574         case INDIRECT_PROCESS_ADJST:
 575                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
 576                 break;
 577         case INDIRECT_OTHERS:
 578                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
 579                 break;
 580         default:
 581                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
 582                 address & INDIRECT_TYPE_MSK);
 583                 break;
 584         }
 585
 586         /* translate the offset from words to byte */
 587         return (address & ADDRESS_MSK) + (offset << 1);
 588 }
 589
 590 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
 591                                            size_t offset)
 592 {
 593         u32 address = eeprom_indirect_address(priv, offset);
 594         BUG_ON(address >= priv->cfg->base_params->eeprom_size);
 595         return &priv->eeprom[address];
 596 }
 597
 598 struct iwl_mod_params iwlagn_mod_params = {
 599         .amsdu_size_8K = 1,
 600         .restart_fw = 1,
 601         /* the rest are 0 by default */
 602 };
 603
 604 void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 605 {
 606         unsigned long flags;
 607         int i;
 608         spin_lock_irqsave(&rxq->lock, flags);
 609         INIT_LIST_HEAD(&rxq->rx_free);
 610         INIT_LIST_HEAD(&rxq->rx_used);
 611         /* Fill the rx_used queue with _all_ of the Rx buffers */
 612         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 613                 /* In the reset function, these buffers may have been allocated
 614                  * to an SKB, so we need to unmap and free potential storage */
 615                 if (rxq->pool[i].page != NULL) {
 616                         pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
 617                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 618                                 PCI_DMA_FROMDEVICE);
 619                         __iwl_free_pages(priv, rxq->pool[i].page);
 620                         rxq->pool[i].page = NULL;
 621                 }
 622                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 623         }
 624
 625         for (i = 0; i < RX_QUEUE_SIZE; i++)
 626                 rxq->queue[i] = NULL;
 627
 628         /* Set us so that we have processed and used all buffers, but have
 629          * not restocked the Rx queue with fresh buffers */
 630         rxq->read = rxq->write = 0;
 631         rxq->write_actual = 0;
 632         rxq->free_count = 0;
 633         spin_unlock_irqrestore(&rxq->lock, flags);
 634 }
 635
 636 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 637 {
 638         u32 rb_size;
 639         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 640         u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
 641
 642         if (!priv->cfg->base_params->use_isr_legacy)
 643                 rb_timeout = RX_RB_TIMEOUT;
 644
 645         if (priv->cfg->mod_params->amsdu_size_8K)
 646                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 647         else
 648                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 649
 650         /* Stop Rx DMA */
 651         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 652
 653         /* Reset driver's Rx queue write index */
 654         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 655
 656         /* Tell device where to find RBD circular buffer in DRAM */
 657         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 658                            (u32)(rxq->bd_dma >> 8));
 659
 660         /* Tell device where in DRAM to update its Rx status */
 661         iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 662                            rxq->rb_stts_dma >> 4);
 663
 664         /* Enable Rx DMA
 665          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 666          *      the credit mechanism in 5000 HW RX FIFO
 667          * Direct rx interrupts to hosts
 668          * Rx buffer size 4 or 8k
 669          * RB timeout 0x10
 670          * 256 RBDs
 671          */
 672         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 673                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 674                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 675                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 676                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 677                            rb_size|
 678                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 679                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 680
 681         /* Set interrupt coalescing timer to default (2048 usecs) */
 682         iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 683
 684         return 0;
 685 }
 686
 687 static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
 688 {
 689 /*
 690  * (for documentation purposes)
 691  * to set power to V_AUX, do:
 692
 693                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 694                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 695                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 696                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 697  */
 698
 699         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 700                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 701                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 702 }
 703
 704 int iwlagn_hw_nic_init(struct iwl_priv *priv)
 705 {
 706         unsigned long flags;
 707         struct iwl_rx_queue *rxq = &priv->rxq;
 708         int ret;
 709
 710         /* nic_init */
 711         spin_lock_irqsave(&priv->lock, flags);
 712         priv->cfg->ops->lib->apm_ops.init(priv);
 713
 714         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 715         iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 716
 717         spin_unlock_irqrestore(&priv->lock, flags);
 718
 719         iwlagn_set_pwr_vmain(priv);
 720
 721         priv->cfg->ops->lib->apm_ops.config(priv);
 722
 723         /* Allocate the RX queue, or reset if it is already allocated */
 724         if (!rxq->bd) {
 725                 ret = iwl_rx_queue_alloc(priv);
 726                 if (ret) {
 727                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
 728                         return -ENOMEM;
 729                 }
 730         } else
 731                 iwlagn_rx_queue_reset(priv, rxq);
 732
 733         iwlagn_rx_replenish(priv);
 734
 735         iwlagn_rx_init(priv, rxq);
 736
 737         spin_lock_irqsave(&priv->lock, flags);
 738
 739         rxq->need_update = 1;
 740         iwl_rx_queue_update_write_ptr(priv, rxq);
 741
 742         spin_unlock_irqrestore(&priv->lock, flags);
 743
 744         /* Allocate or reset and init all Tx and Command queues */
 745         if (!priv->txq) {
 746                 ret = iwlagn_txq_ctx_alloc(priv);
 747                 if (ret)
 748                         return ret;
 749         } else
 750                 iwlagn_txq_ctx_reset(priv);
 751
 752         if (priv->cfg->base_params->shadow_reg_enable) {
 753                 /* enable shadow regs in HW */
 754                 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
 755                         0x800FFFFF);
 756         }
 757
 758         set_bit(STATUS_INIT, &priv->status);
 759
 760         return 0;
 761 }
 762
 763 /**
 764  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 765  */
 766 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
 767                                           dma_addr_t dma_addr)
 768 {
 769         return cpu_to_le32((u32)(dma_addr >> 8));
 770 }
 771
 772 /**
 773  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 774  *
 775  * If there are slots in the RX queue that need to be restocked,
 776  * and we have free pre-allocated buffers, fill the ranks as much
 777  * as we can, pulling from rx_free.
 778  *
 779  * This moves the 'write' index forward to catch up with 'processed', and
 780  * also updates the memory address in the firmware to reference the new
 781  * target buffer.
 782  */
 783 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
 784 {
 785         struct iwl_rx_queue *rxq = &priv->rxq;
 786         struct list_head *element;
 787         struct iwl_rx_mem_buffer *rxb;
 788         unsigned long flags;
 789
 790         spin_lock_irqsave(&rxq->lock, flags);
 791         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 792                 /* The overwritten rxb must be a used one */
 793                 rxb = rxq->queue[rxq->write];
 794                 BUG_ON(rxb && rxb->page);
 795
 796                 /* Get next free Rx buffer, remove from free list */
 797                 element = rxq->rx_free.next;
 798                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 799                 list_del(element);
 800
 801                 /* Point to Rx buffer via next RBD in circular buffer */
 802                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
 803                                                               rxb->page_dma);
 804                 rxq->queue[rxq->write] = rxb;
 805                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 806                 rxq->free_count--;
 807         }
 808         spin_unlock_irqrestore(&rxq->lock, flags);
 809         /* If the pre-allocated buffer pool is dropping low, schedule to
 810          * refill it */
 811         if (rxq->free_count <= RX_LOW_WATERMARK)
 812                 queue_work(priv->workqueue, &priv->rx_replenish);
 813
 814
 815         /* If we've added more space for the firmware to place data, tell it.
 816          * Increment device's write pointer in multiples of 8. */
 817         if (rxq->write_actual != (rxq->write & ~0x7)) {
 818                 spin_lock_irqsave(&rxq->lock, flags);
 819                 rxq->need_update = 1;
 820                 spin_unlock_irqrestore(&rxq->lock, flags);
 821                 iwl_rx_queue_update_write_ptr(priv, rxq);
 822         }
 823 }
 824
 825 /**
 826  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 827  *
 828  * When moving to rx_free an SKB is allocated for the slot.
 829  *
 830  * Also restock the Rx queue via iwl_rx_queue_restock.
 831  * This is called as a scheduled work item (except for during initialization)
 832  */
 833 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
 834 {
 835         struct iwl_rx_queue *rxq = &priv->rxq;
 836         struct list_head *element;
 837         struct iwl_rx_mem_buffer *rxb;
 838         struct page *page;
 839         unsigned long flags;
 840         gfp_t gfp_mask = priority;
 841
 842         while (1) {
 843                 spin_lock_irqsave(&rxq->lock, flags);
 844                 if (list_empty(&rxq->rx_used)) {
 845                         spin_unlock_irqrestore(&rxq->lock, flags);
 846                         return;
 847                 }
 848                 spin_unlock_irqrestore(&rxq->lock, flags);
 849
 850                 if (rxq->free_count > RX_LOW_WATERMARK)
 851                         gfp_mask |= __GFP_NOWARN;
 852
 853                 if (priv->hw_params.rx_page_order > 0)
 854                         gfp_mask |= __GFP_COMP;
 855
 856                 /* Alloc a new receive buffer */
 857                 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
 858                 if (!page) {
 859                         if (net_ratelimit())
 860                                 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
 861                                                "order: %d\n",
 862                                                priv->hw_params.rx_page_order);
 863
 864                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 865                             net_ratelimit())
 866                                 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
 867                                          priority == GFP_ATOMIC ?  "GFP_ATOMIC" : "GFP_KERNEL",
 868                                          rxq->free_count);
 869                         /* We don't reschedule replenish work here -- we will
 870                          * call the restock method and if it still needs
 871                          * more buffers it will schedule replenish */
 872                         return;
 873                 }
 874
 875                 spin_lock_irqsave(&rxq->lock, flags);
 876
 877                 if (list_empty(&rxq->rx_used)) {
 878                         spin_unlock_irqrestore(&rxq->lock, flags);
 879                         __free_pages(page, priv->hw_params.rx_page_order);
 880                         return;
 881                 }
 882                 element = rxq->rx_used.next;
 883                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 884                 list_del(element);
 885
 886                 spin_unlock_irqrestore(&rxq->lock, flags);
 887
 888                 BUG_ON(rxb->page);
 889                 rxb->page = page;
 890                 /* Get physical address of the RB */
 891                 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
 892                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 893                                 PCI_DMA_FROMDEVICE);
 894                 /* dma address must be no more than 36 bits */
 895                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 896                 /* and also 256 byte aligned! */
 897                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 898
 899                 spin_lock_irqsave(&rxq->lock, flags);
 900
 901                 list_add_tail(&rxb->list, &rxq->rx_free);
 902                 rxq->free_count++;
 903                 priv->alloc_rxb_page++;
 904
 905                 spin_unlock_irqrestore(&rxq->lock, flags);
 906         }
 907 }
 908
 909 void iwlagn_rx_replenish(struct iwl_priv *priv)
 910 {
 911         unsigned long flags;
 912
 913         iwlagn_rx_allocate(priv, GFP_KERNEL);
 914
 915         spin_lock_irqsave(&priv->lock, flags);
 916         iwlagn_rx_queue_restock(priv);
 917         spin_unlock_irqrestore(&priv->lock, flags);
 918 }
 919
 920 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
 921 {
 922         iwlagn_rx_allocate(priv, GFP_ATOMIC);
 923
 924         iwlagn_rx_queue_restock(priv);
 925 }
 926
 927 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
 928  * If an SKB has been detached, the POOL needs to have its SKB set to NULL
 929  * This free routine walks the list of POOL entries and if SKB is set to
 930  * non NULL it is unmapped and freed
 931  */
 932 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 933 {
 934         int i;
 935         for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
 936                 if (rxq->pool[i].page != NULL) {
 937                         pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
 938                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 939                                 PCI_DMA_FROMDEVICE);
 940                         __iwl_free_pages(priv, rxq->pool[i].page);
 941                         rxq->pool[i].page = NULL;
 942                 }
 943         }
 944
 945         dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
 946                           rxq->bd_dma);
 947         dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
 948                           rxq->rb_stts, rxq->rb_stts_dma);
 949         rxq->bd = NULL;
 950         rxq->rb_stts  = NULL;
 951 }
 952
 953 int iwlagn_rxq_stop(struct iwl_priv *priv)
 954 {
 955
 956         /* stop Rx DMA */
 957         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 958         iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
 959                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 960
 961         return 0;
 962 }
 963
 964 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
 965 {
 966         int idx = 0;
 967         int band_offset = 0;
 968
 969         /* HT rate format: mac80211 wants an MCS number, which is just LSB */
 970         if (rate_n_flags & RATE_MCS_HT_MSK) {
 971                 idx = (rate_n_flags & 0xff);
 972                 return idx;
 973         /* Legacy rate format, search for match in table */
 974         } else {
 975                 if (band == IEEE80211_BAND_5GHZ)
 976                         band_offset = IWL_FIRST_OFDM_RATE;
 977                 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
 978                         if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
 979                                 return idx - band_offset;
 980         }
 981
 982         return -1;
 983 }
 984
 985 /* Calc max signal level (dBm) among 3 possible receivers */
 986 static inline int iwlagn_calc_rssi(struct iwl_priv *priv,
 987                                 struct iwl_rx_phy_res *rx_resp)
 988 {
 989         return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
 990 }
 991
 992 static u32 iwlagn_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
 993 {
 994         u32 decrypt_out = 0;
 995
 996         if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
 997                                         RX_RES_STATUS_STATION_FOUND)
 998                 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
 999                                 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
1000
1001         decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
1002
1003         /* packet was not encrypted */
1004         if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
1005                                         RX_RES_STATUS_SEC_TYPE_NONE)
1006                 return decrypt_out;
1007
1008         /* packet was encrypted with unknown alg */
1009         if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
1010                                         RX_RES_STATUS_SEC_TYPE_ERR)
1011                 return decrypt_out;
1012
1013         /* decryption was not done in HW */
1014         if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
1015                                         RX_MPDU_RES_STATUS_DEC_DONE_MSK)
1016                 return decrypt_out;
1017
1018         switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
1019
1020         case RX_RES_STATUS_SEC_TYPE_CCMP:
1021                 /* alg is CCM: check MIC only */
1022                 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
1023                         /* Bad MIC */
1024                         decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1025                 else
1026                         decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1027
1028                 break;
1029
1030         case RX_RES_STATUS_SEC_TYPE_TKIP:
1031                 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
1032                         /* Bad TTAK */
1033                         decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
1034                         break;
1035                 }
1036                 /* fall through if TTAK OK */
1037         default:
1038                 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
1039                         decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1040                 else
1041                         decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1042                 break;
1043         }
1044
1045         IWL_DEBUG_RX(priv, "decrypt_in:0x%x  decrypt_out = 0x%x\n",
1046                                         decrypt_in, decrypt_out);
1047
1048         return decrypt_out;
1049 }
1050
1051 static void iwlagn_pass_packet_to_mac80211(struct iwl_priv *priv,
1052                                         struct ieee80211_hdr *hdr,
1053                                         u16 len,
1054                                         u32 ampdu_status,
1055                                         struct iwl_rx_mem_buffer *rxb,
1056                                         struct ieee80211_rx_status *stats)
1057 {
1058         struct sk_buff *skb;
1059         __le16 fc = hdr->frame_control;
1060
1061         /* We only process data packets if the interface is open */
1062         if (unlikely(!priv->is_open)) {
1063                 IWL_DEBUG_DROP_LIMIT(priv,
1064                     "Dropping packet while interface is not open.\n");
1065                 return;
1066         }
1067
1068         /* In case of HW accelerated crypto and bad decryption, drop */
1069         if (!priv->cfg->mod_params->sw_crypto &&
1070             iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
1071                 return;
1072
1073         skb = dev_alloc_skb(128);
1074         if (!skb) {
1075                 IWL_ERR(priv, "dev_alloc_skb failed\n");
1076                 return;
1077         }
1078
1079         skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
1080
1081         iwl_update_stats(priv, false, fc, len);
1082         memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
1083
1084         ieee80211_rx(priv->hw, skb);
1085         priv->alloc_rxb_page--;
1086         rxb->page = NULL;
1087 }
1088
1089 /* Called for REPLY_RX (legacy ABG frames), or
1090  * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
1091 void iwlagn_rx_reply_rx(struct iwl_priv *priv,
1092                                 struct iwl_rx_mem_buffer *rxb)
1093 {
1094         struct ieee80211_hdr *header;
1095         struct ieee80211_rx_status rx_status;
1096         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1097         struct iwl_rx_phy_res *phy_res;
1098         __le32 rx_pkt_status;
1099         struct iwl_rx_mpdu_res_start *amsdu;
1100         u32 len;
1101         u32 ampdu_status;
1102         u32 rate_n_flags;
1103
1104         /**
1105          * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
1106          *      REPLY_RX: physical layer info is in this buffer
1107          *      REPLY_RX_MPDU_CMD: physical layer info was sent in separate
1108          *              command and cached in priv->last_phy_res
1109          *
1110          * Here we set up local variables depending on which command is
1111          * received.
1112          */
1113         if (pkt->hdr.cmd == REPLY_RX) {
1114                 phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
1115                 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
1116                                 + phy_res->cfg_phy_cnt);
1117
1118                 len = le16_to_cpu(phy_res->byte_count);
1119                 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
1120                                 phy_res->cfg_phy_cnt + len);
1121                 ampdu_status = le32_to_cpu(rx_pkt_status);
1122         } else {
1123                 if (!priv->_agn.last_phy_res_valid) {
1124                         IWL_ERR(priv, "MPDU frame without cached PHY data\n");
1125                         return;
1126                 }
1127                 phy_res = &priv->_agn.last_phy_res;
1128                 amsdu = (struct iwl_rx_mpdu_res_start *)pkt->u.raw;
1129                 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
1130                 len = le16_to_cpu(amsdu->byte_count);
1131                 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
1132                 ampdu_status = iwlagn_translate_rx_status(priv,
1133                                 le32_to_cpu(rx_pkt_status));
1134         }
1135
1136         if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
1137                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
1138                                 phy_res->cfg_phy_cnt);
1139                 return;
1140         }
1141
1142         if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
1143             !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
1144                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
1145                                 le32_to_cpu(rx_pkt_status));
1146                 return;
1147         }
1148
1149         /* This will be used in several places later */
1150         rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
1151
1152         /* rx_status carries information about the packet to mac80211 */
1153         rx_status.mactime = le64_to_cpu(phy_res->timestamp);
1154         rx_status.freq =
1155                 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
1156         rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
1157                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
1158         rx_status.rate_idx =
1159                 iwlagn_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
1160         rx_status.flag = 0;
1161
1162         /* TSF isn't reliable. In order to allow smooth user experience,
1163          * this W/A doesn't propagate it to the mac80211 */
1164         /*rx_status.flag |= RX_FLAG_TSFT;*/
1165
1166         priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
1167
1168         /* Find max signal strength (dBm) among 3 antenna/receiver chains */
1169         rx_status.signal = iwlagn_calc_rssi(priv, phy_res);
1170
1171         iwl_dbg_log_rx_data_frame(priv, len, header);
1172         IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n",
1173                 rx_status.signal, (unsigned long long)rx_status.mactime);
1174
1175         /*
1176          * "antenna number"
1177          *
1178          * It seems that the antenna field in the phy flags value
1179          * is actually a bit field. This is undefined by radiotap,
1180          * it wants an actual antenna number but I always get "7"
1181          * for most legacy frames I receive indicating that the
1182          * same frame was received on all three RX chains.
1183          *
1184          * I think this field should be removed in favor of a
1185          * new 802.11n radiotap field "RX chains" that is defined
1186          * as a bitmask.
1187          */
1188         rx_status.antenna =
1189                 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
1190                 >> RX_RES_PHY_FLAGS_ANTENNA_POS;
1191
1192         /* set the preamble flag if appropriate */
1193         if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
1194                 rx_status.flag |= RX_FLAG_SHORTPRE;
1195
1196         /* Set up the HT phy flags */
1197         if (rate_n_flags & RATE_MCS_HT_MSK)
1198                 rx_status.flag |= RX_FLAG_HT;
1199         if (rate_n_flags & RATE_MCS_HT40_MSK)
1200                 rx_status.flag |= RX_FLAG_40MHZ;
1201         if (rate_n_flags & RATE_MCS_SGI_MSK)
1202                 rx_status.flag |= RX_FLAG_SHORT_GI;
1203
1204         iwlagn_pass_packet_to_mac80211(priv, header, len, ampdu_status,
1205                                     rxb, &rx_status);
1206 }
1207
1208 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
1209  * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
1210 void iwlagn_rx_reply_rx_phy(struct iwl_priv *priv,
1211                             struct iwl_rx_mem_buffer *rxb)
1212 {
1213         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1214         priv->_agn.last_phy_res_valid = true;
1215         memcpy(&priv->_agn.last_phy_res, pkt->u.raw,
1216                sizeof(struct iwl_rx_phy_res));
1217 }
1218
1219 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
1220                                            struct ieee80211_vif *vif,
1221                                            enum ieee80211_band band,
1222                                            struct iwl_scan_channel *scan_ch)
1223 {
1224         const struct ieee80211_supported_band *sband;
1225         u16 passive_dwell = 0;
1226         u16 active_dwell = 0;
1227         int added = 0;
1228         u16 channel = 0;
1229
1230         sband = iwl_get_hw_mode(priv, band);
1231         if (!sband) {
1232                 IWL_ERR(priv, "invalid band\n");
1233                 return added;
1234         }
1235
1236         active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1237         passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1238
1239         if (passive_dwell <= active_dwell)
1240                 passive_dwell = active_dwell + 1;
1241
1242         channel = iwl_get_single_channel_number(priv, band);
1243         if (channel) {
1244                 scan_ch->channel = cpu_to_le16(channel);
1245                 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1246                 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1247                 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1248                 /* Set txpower levels to defaults */
1249                 scan_ch->dsp_atten = 110;
1250                 if (band == IEEE80211_BAND_5GHZ)
1251                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1252                 else
1253                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1254                 added++;
1255         } else
1256                 IWL_ERR(priv, "no valid channel found\n");
1257         return added;
1258 }
1259
1260 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1261                                      struct ieee80211_vif *vif,
1262                                      enum ieee80211_band band,
1263                                      u8 is_active, u8 n_probes,
1264                                      struct iwl_scan_channel *scan_ch)
1265 {
1266         struct ieee80211_channel *chan;
1267         const struct ieee80211_supported_band *sband;
1268         const struct iwl_channel_info *ch_info;
1269         u16 passive_dwell = 0;
1270         u16 active_dwell = 0;
1271         int added, i;
1272         u16 channel;
1273
1274         sband = iwl_get_hw_mode(priv, band);
1275         if (!sband)
1276                 return 0;
1277
1278         active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1279         passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1280
1281         if (passive_dwell <= active_dwell)
1282                 passive_dwell = active_dwell + 1;
1283
1284         for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1285                 chan = priv->scan_request->channels[i];
1286
1287                 if (chan->band != band)
1288                         continue;
1289
1290                 channel = chan->hw_value;
1291                 scan_ch->channel = cpu_to_le16(channel);
1292
1293                 ch_info = iwl_get_channel_info(priv, band, channel);
1294                 if (!is_channel_valid(ch_info)) {
1295                         IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1296                                         channel);
1297                         continue;
1298                 }
1299
1300                 if (!is_active || is_channel_passive(ch_info) ||
1301                     (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1302                         scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1303                 else
1304                         scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1305
1306                 if (n_probes)
1307                         scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1308
1309                 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1310                 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1311
1312                 /* Set txpower levels to defaults */
1313                 scan_ch->dsp_atten = 110;
1314
1315                 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1316                  * power level:
1317                  * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1318                  */
1319                 if (band == IEEE80211_BAND_5GHZ)
1320                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1321                 else
1322                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1323
1324                 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1325                                channel, le32_to_cpu(scan_ch->type),
1326                                (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1327                                 "ACTIVE" : "PASSIVE",
1328                                (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1329                                active_dwell : passive_dwell);
1330
1331                 scan_ch++;
1332                 added++;
1333         }
1334
1335         IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1336         return added;
1337 }
1338
1339 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1340 {
1341         struct iwl_host_cmd cmd = {
1342                 .id = REPLY_SCAN_CMD,
1343                 .len = sizeof(struct iwl_scan_cmd),
1344                 .flags = CMD_SIZE_HUGE,
1345         };
1346         struct iwl_scan_cmd *scan;
1347         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1348         u32 rate_flags = 0;
1349         u16 cmd_len;
1350         u16 rx_chain = 0;
1351         enum ieee80211_band band;
1352         u8 n_probes = 0;
1353         u8 rx_ant = priv->hw_params.valid_rx_ant;
1354         u8 rate;
1355         bool is_active = false;
1356         int  chan_mod;
1357         u8 active_chains;
1358         u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1359         int ret;
1360
1361         lockdep_assert_held(&priv->mutex);
1362
1363         if (vif)
1364                 ctx = iwl_rxon_ctx_from_vif(vif);
1365
1366         if (!priv->scan_cmd) {
1367                 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1368                                          IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1369                 if (!priv->scan_cmd) {
1370                         IWL_DEBUG_SCAN(priv,
1371                                        "fail to allocate memory for scan\n");
1372                         return -ENOMEM;
1373                 }
1374         }
1375         scan = priv->scan_cmd;
1376         memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1377
1378         scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1379         scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1380
1381         if (iwl_is_any_associated(priv)) {
1382                 u16 interval = 0;
1383                 u32 extra;
1384                 u32 suspend_time = 100;
1385                 u32 scan_suspend_time = 100;
1386                 unsigned long flags;
1387
1388                 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1389                 spin_lock_irqsave(&priv->lock, flags);
1390                 if (priv->is_internal_short_scan)
1391                         interval = 0;
1392                 else
1393                         interval = vif->bss_conf.beacon_int;
1394                 spin_unlock_irqrestore(&priv->lock, flags);
1395
1396                 scan->suspend_time = 0;
1397                 scan->max_out_time = cpu_to_le32(200 * 1024);
1398                 if (!interval)
1399                         interval = suspend_time;
1400
1401                 extra = (suspend_time / interval) << 22;
1402                 scan_suspend_time = (extra |
1403                     ((suspend_time % interval) * 1024));
1404                 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1405                 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1406                                scan_suspend_time, interval);
1407         }
1408
1409         if (priv->is_internal_short_scan) {
1410                 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1411         } else if (priv->scan_request->n_ssids) {
1412                 int i, p = 0;
1413                 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1414                 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1415                         /* always does wildcard anyway */
1416                         if (!priv->scan_request->ssids[i].ssid_len)
1417                                 continue;
1418                         scan->direct_scan[p].id = WLAN_EID_SSID;
1419                         scan->direct_scan[p].len =
1420                                 priv->scan_request->ssids[i].ssid_len;
1421                         memcpy(scan->direct_scan[p].ssid,
1422                                priv->scan_request->ssids[i].ssid,
1423                                priv->scan_request->ssids[i].ssid_len);
1424                         n_probes++;
1425                         p++;
1426                 }
1427                 is_active = true;
1428         } else
1429                 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1430
1431         scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1432         scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1433         scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1434
1435         switch (priv->scan_band) {
1436         case IEEE80211_BAND_2GHZ:
1437                 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1438                 chan_mod = le32_to_cpu(
1439                         priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1440                                                 RXON_FLG_CHANNEL_MODE_MSK)
1441                                        >> RXON_FLG_CHANNEL_MODE_POS;
1442                 if (chan_mod == CHANNEL_MODE_PURE_40) {
1443                         rate = IWL_RATE_6M_PLCP;
1444                 } else {
1445                         rate = IWL_RATE_1M_PLCP;
1446                         rate_flags = RATE_MCS_CCK_MSK;
1447                 }
1448                 /*
1449                  * Internal scans are passive, so we can indiscriminately set
1450                  * the BT ignore flag on 2.4 GHz since it applies to TX only.
1451                  */
1452                 if (priv->cfg->bt_params &&
1453                     priv->cfg->bt_params->advanced_bt_coexist)
1454                         scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1455                 break;
1456         case IEEE80211_BAND_5GHZ:
1457                 rate = IWL_RATE_6M_PLCP;
1458                 break;
1459         default:
1460                 IWL_WARN(priv, "Invalid scan band\n");
1461                 return -EIO;
1462         }
1463
1464         /*
1465          * If active scanning is requested but a certain channel is
1466          * marked passive, we can do active scanning if we detect
1467          * transmissions.
1468          *
1469          * There is an issue with some firmware versions that triggers
1470          * a sysassert on a "good CRC threshold" of zero (== disabled),
1471          * on a radar channel even though this means that we should NOT
1472          * send probes.
1473          *
1474          * The "good CRC threshold" is the number of frames that we
1475          * need to receive during our dwell time on a channel before
1476          * sending out probes -- setting this to a huge value will
1477          * mean we never reach it, but at the same time work around
1478          * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1479          * here instead of IWL_GOOD_CRC_TH_DISABLED.
1480          */
1481         scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1482                                         IWL_GOOD_CRC_TH_NEVER;
1483
1484         band = priv->scan_band;
1485
1486         if (priv->cfg->scan_rx_antennas[band])
1487                 rx_ant = priv->cfg->scan_rx_antennas[band];
1488
1489         if (priv->cfg->scan_tx_antennas[band])
1490                 scan_tx_antennas = priv->cfg->scan_tx_antennas[band];
1491
1492         if (priv->cfg->bt_params &&
1493             priv->cfg->bt_params->advanced_bt_coexist &&
1494             priv->bt_full_concurrent) {
1495                 /* operated as 1x1 in full concurrency mode */
1496                 scan_tx_antennas = first_antenna(
1497                         priv->cfg->scan_tx_antennas[band]);
1498         }
1499
1500         priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1501                                                     scan_tx_antennas);
1502         rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1503         scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1504
1505         /* In power save mode use one chain, otherwise use all chains */
1506         if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1507                 /* rx_ant has been set to all valid chains previously */
1508                 active_chains = rx_ant &
1509                                 ((u8)(priv->chain_noise_data.active_chains));
1510                 if (!active_chains)
1511                         active_chains = rx_ant;
1512
1513                 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1514                                 priv->chain_noise_data.active_chains);
1515
1516                 rx_ant = first_antenna(active_chains);
1517         }
1518         if (priv->cfg->bt_params &&
1519             priv->cfg->bt_params->advanced_bt_coexist &&
1520             priv->bt_full_concurrent) {
1521                 /* operated as 1x1 in full concurrency mode */
1522                 rx_ant = first_antenna(rx_ant);
1523         }
1524
1525         /* MIMO is not used here, but value is required */
1526         rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1527         rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1528         rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1529         rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1530         scan->rx_chain = cpu_to_le16(rx_chain);
1531         if (!priv->is_internal_short_scan) {
1532                 cmd_len = iwl_fill_probe_req(priv,
1533                                         (struct ieee80211_mgmt *)scan->data,
1534                                         vif->addr,
1535                                         priv->scan_request->ie,
1536                                         priv->scan_request->ie_len,
1537                                         IWL_MAX_SCAN_SIZE - sizeof(*scan));
1538         } else {
1539                 /* use bcast addr, will not be transmitted but must be valid */
1540                 cmd_len = iwl_fill_probe_req(priv,
1541                                         (struct ieee80211_mgmt *)scan->data,
1542                                         iwl_bcast_addr, NULL, 0,
1543                                         IWL_MAX_SCAN_SIZE - sizeof(*scan));
1544
1545         }
1546         scan->tx_cmd.len = cpu_to_le16(cmd_len);
1547
1548         scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1549                                RXON_FILTER_BCON_AWARE_MSK);
1550
1551         if (priv->is_internal_short_scan) {
1552                 scan->channel_count =
1553                         iwl_get_single_channel_for_scan(priv, vif, band,
1554                                 (void *)&scan->data[le16_to_cpu(
1555                                 scan->tx_cmd.len)]);
1556         } else {
1557                 scan->channel_count =
1558                         iwl_get_channels_for_scan(priv, vif, band,
1559                                 is_active, n_probes,
1560                                 (void *)&scan->data[le16_to_cpu(
1561                                 scan->tx_cmd.len)]);
1562         }
1563         if (scan->channel_count == 0) {
1564                 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1565                 return -EIO;
1566         }
1567
1568         cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1569             scan->channel_count * sizeof(struct iwl_scan_channel);
1570         cmd.data = scan;
1571         scan->len = cpu_to_le16(cmd.len);
1572
1573         /* set scan bit here for PAN params */
1574         set_bit(STATUS_SCAN_HW, &priv->status);
1575
1576         if (priv->cfg->ops->hcmd->set_pan_params) {
1577                 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1578                 if (ret)
1579                         return ret;
1580         }
1581
1582         ret = iwl_send_cmd_sync(priv, &cmd);
1583         if (ret) {
1584                 clear_bit(STATUS_SCAN_HW, &priv->status);
1585                 if (priv->cfg->ops->hcmd->set_pan_params)
1586                         priv->cfg->ops->hcmd->set_pan_params(priv);
1587         }
1588
1589         return ret;
1590 }
1591
1592 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1593                                struct ieee80211_vif *vif, bool add)
1594 {
1595         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1596
1597         if (add)
1598                 return iwlagn_add_bssid_station(priv, vif_priv->ctx,
1599                                                 vif->bss_conf.bssid,
1600                                                 &vif_priv->ibss_bssid_sta_id);
1601         return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1602                                   vif->bss_conf.bssid);
1603 }
1604
1605 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1606                             int sta_id, int tid, int freed)
1607 {
1608         lockdep_assert_held(&priv->sta_lock);
1609
1610         if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1611                 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1612         else {
1613                 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1614                         priv->stations[sta_id].tid[tid].tfds_in_queue,
1615                         freed);
1616                 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1617         }
1618 }
1619
1620 #define IWL_FLUSH_WAIT_MS       2000
1621
1622 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1623 {
1624         struct iwl_tx_queue *txq;
1625         struct iwl_queue *q;
1626         int cnt;
1627         unsigned long now = jiffies;
1628         int ret = 0;
1629
1630         /* waiting for all the tx frames complete might take a while */
1631         for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1632                 if (cnt == priv->cmd_queue)
1633                         continue;
1634                 txq = &priv->txq[cnt];
1635                 q = &txq->q;
1636                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1637                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1638                                 msleep(1);
1639
1640                 if (q->read_ptr != q->write_ptr) {
1641                         IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1642                         ret = -ETIMEDOUT;
1643                         break;
1644                 }
1645         }
1646         return ret;
1647 }
1648
1649 #define IWL_TX_QUEUE_MSK        0xfffff
1650
1651 /**
1652  * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1653  *
1654  * pre-requirements:
1655  *  1. acquire mutex before calling
1656  *  2. make sure rf is on and not in exit state
1657  */
1658 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1659 {
1660         struct iwl_txfifo_flush_cmd flush_cmd;
1661         struct iwl_host_cmd cmd = {
1662                 .id = REPLY_TXFIFO_FLUSH,
1663                 .len = sizeof(struct iwl_txfifo_flush_cmd),
1664                 .flags = CMD_SYNC,
1665                 .data = &flush_cmd,
1666         };
1667
1668         might_sleep();
1669
1670         memset(&flush_cmd, 0, sizeof(flush_cmd));
1671         flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
1672                                  IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
1673         if (priv->cfg->sku & IWL_SKU_N)
1674                 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1675
1676         IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1677                        flush_cmd.fifo_control);
1678         flush_cmd.flush_control = cpu_to_le16(flush_control);
1679
1680         return iwl_send_cmd(priv, &cmd);
1681 }
1682
1683 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1684 {
1685         mutex_lock(&priv->mutex);
1686         ieee80211_stop_queues(priv->hw);
1687         if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
1688                 IWL_ERR(priv, "flush request fail\n");
1689                 goto done;
1690         }
1691         IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1692         iwlagn_wait_tx_queue_empty(priv);
1693 done:
1694         ieee80211_wake_queues(priv->hw);
1695         mutex_unlock(&priv->mutex);
1696 }
1697
1698 /*
1699  * BT coex
1700  */
1701 /*
1702  * Macros to access the lookup table.
1703  *
1704  * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1705 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1706  *
1707  * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1708  *
1709  * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1710  * one after another in 32-bit registers, and "registers" 0 through 7 contain
1711  * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1712  *
1713  * These macros encode that format.
1714  */
1715 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1716                   wifi_txrx, wifi_sh_ant_req) \
1717         (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1718         (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1719
1720 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1721         lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1722 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1723                                  wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1724         (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1725                                    bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1726                                    wifi_sh_ant_req))))
1727 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1728                                 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1729         LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1730                                bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1731                                wifi_sh_ant_req))
1732 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1733                                   wifi_req, wifi_prio, wifi_txrx, \
1734                                   wifi_sh_ant_req) \
1735         LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1736                                bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1737                                wifi_sh_ant_req))
1738
1739 #define LUT_WLAN_KILL_OP(lut, op, val) \
1740         lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1741 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1742                            wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1743         (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1744                              wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1745 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1746                           wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1747         LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1748                          wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1749 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1750                             wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1751         LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1752                          wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1753
1754 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1755         lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1756 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1757                             wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1758         (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1759                               wifi_req, wifi_prio, wifi_txrx, \
1760                               wifi_sh_ant_req))))
1761 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1762                            wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1763         LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1764                           wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1765 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1766                              wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1767         LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1768                           wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1769
1770 static const __le32 iwlagn_def_3w_lookup[12] = {
1771         cpu_to_le32(0xaaaaaaaa),
1772         cpu_to_le32(0xaaaaaaaa),
1773         cpu_to_le32(0xaeaaaaaa),
1774         cpu_to_le32(0xaaaaaaaa),
1775         cpu_to_le32(0xcc00ff28),
1776         cpu_to_le32(0x0000aaaa),
1777         cpu_to_le32(0xcc00aaaa),
1778         cpu_to_le32(0x0000aaaa),
1779         cpu_to_le32(0xc0004000),
1780         cpu_to_le32(0x00004000),
1781         cpu_to_le32(0xf0005000),
1782         cpu_to_le32(0xf0005000),
1783 };
1784
1785 static const __le32 iwlagn_concurrent_lookup[12] = {
1786         cpu_to_le32(0xaaaaaaaa),
1787         cpu_to_le32(0xaaaaaaaa),
1788         cpu_to_le32(0xaaaaaaaa),
1789         cpu_to_le32(0xaaaaaaaa),
1790         cpu_to_le32(0xaaaaaaaa),
1791         cpu_to_le32(0xaaaaaaaa),
1792         cpu_to_le32(0xaaaaaaaa),
1793         cpu_to_le32(0xaaaaaaaa),
1794         cpu_to_le32(0x00000000),
1795         cpu_to_le32(0x00000000),
1796         cpu_to_le32(0x00000000),
1797         cpu_to_le32(0x00000000),
1798 };
1799
1800 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1801 {
1802         struct iwlagn_bt_cmd bt_cmd = {
1803                 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1804                 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1805                 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1806                 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1807         };
1808
1809         BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1810                         sizeof(bt_cmd.bt3_lookup_table));
1811
1812         if (priv->cfg->bt_params)
1813                 bt_cmd.prio_boost = priv->cfg->bt_params->bt_prio_boost;
1814         else
1815                 bt_cmd.prio_boost = 0;
1816         bt_cmd.kill_ack_mask = priv->kill_ack_mask;
1817         bt_cmd.kill_cts_mask = priv->kill_cts_mask;
1818
1819         bt_cmd.valid = priv->bt_valid;
1820         bt_cmd.tx_prio_boost = 0;
1821         bt_cmd.rx_prio_boost = 0;
1822
1823         /*
1824          * Configure BT coex mode to "no coexistence" when the
1825          * user disabled BT coexistence, we have no interface
1826          * (might be in monitor mode), or the interface is in
1827          * IBSS mode (no proper uCode support for coex then).
1828          */
1829         if (!bt_coex_active || priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1830                 bt_cmd.flags = 0;
1831         } else {
1832                 bt_cmd.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1833                                         IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1834                 if (priv->cfg->bt_params &&
1835                     priv->cfg->bt_params->bt_sco_disable)
1836                         bt_cmd.flags |= IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE;
1837
1838                 if (priv->bt_ch_announce)
1839                         bt_cmd.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1840                 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", bt_cmd.flags);
1841         }
1842         if (priv->bt_full_concurrent)
1843                 memcpy(bt_cmd.bt3_lookup_table, iwlagn_concurrent_lookup,
1844                         sizeof(iwlagn_concurrent_lookup));
1845         else
1846                 memcpy(bt_cmd.bt3_lookup_table, iwlagn_def_3w_lookup,
1847                         sizeof(iwlagn_def_3w_lookup));
1848
1849         IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
1850                        bt_cmd.flags ? "active" : "disabled",
1851                        priv->bt_full_concurrent ?
1852                        "full concurrency" : "3-wire");
1853
1854         if (iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, sizeof(bt_cmd), &bt_cmd))
1855                 IWL_ERR(priv, "failed to send BT Coex Config\n");
1856
1857         /*
1858          * When we are doing a restart, need to also reconfigure BT
1859          * SCO to the device. If not doing a restart, bt_sco_active
1860          * will always be false, so there's no need to have an extra
1861          * variable to check for it.
1862          */
1863         if (priv->bt_sco_active) {
1864                 struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
1865
1866                 if (priv->bt_sco_active)
1867                         sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
1868                 if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_SCO,
1869                                      sizeof(sco_cmd), &sco_cmd))
1870                         IWL_ERR(priv, "failed to send BT SCO command\n");
1871         }
1872 }
1873
1874 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1875 {
1876         struct iwl_priv *priv =
1877                 container_of(work, struct iwl_priv, bt_traffic_change_work);
1878         struct iwl_rxon_context *ctx;
1879         int smps_request = -1;
1880
1881         /*
1882          * Note: bt_traffic_load can be overridden by scan complete and
1883          * coex profile notifications. Ignore that since only bad consequence
1884          * can be not matching debug print with actual state.
1885          */
1886         IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
1887                        priv->bt_traffic_load);
1888
1889         switch (priv->bt_traffic_load) {
1890         case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1891                 if (priv->bt_status)
1892                         smps_request = IEEE80211_SMPS_DYNAMIC;
1893                 else
1894                         smps_request = IEEE80211_SMPS_AUTOMATIC;
1895                 break;
1896         case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1897                 smps_request = IEEE80211_SMPS_DYNAMIC;
1898                 break;
1899         case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1900         case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1901                 smps_request = IEEE80211_SMPS_STATIC;
1902                 break;
1903         default:
1904                 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1905                         priv->bt_traffic_load);
1906                 break;
1907         }
1908
1909         mutex_lock(&priv->mutex);
1910
1911         /*
1912          * We can not send command to firmware while scanning. When the scan
1913          * complete we will schedule this work again. We do check with mutex
1914          * locked to prevent new scan request to arrive. We do not check
1915          * STATUS_SCANNING to avoid race when queue_work two times from
1916          * different notifications, but quit and not perform any work at all.
1917          */
1918         if (test_bit(STATUS_SCAN_HW, &priv->status))
1919                 goto out;
1920
1921         if (priv->cfg->ops->lib->update_chain_flags)
1922                 priv->cfg->ops->lib->update_chain_flags(priv);
1923
1924         if (smps_request != -1) {
1925                 for_each_context(priv, ctx) {
1926                         if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1927                                 ieee80211_request_smps(ctx->vif, smps_request);
1928                 }
1929         }
1930 out:
1931         mutex_unlock(&priv->mutex);
1932 }
1933
1934 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1935                                 struct iwl_bt_uart_msg *uart_msg)
1936 {
1937         IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
1938                         "Update Req = 0x%X",
1939                 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1940                         BT_UART_MSG_FRAME1MSGTYPE_POS,
1941                 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1942                         BT_UART_MSG_FRAME1SSN_POS,
1943                 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1944                         BT_UART_MSG_FRAME1UPDATEREQ_POS);
1945
1946         IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1947                         "Chl_SeqN = 0x%X, In band = 0x%X",
1948                 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1949                         BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1950                 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1951                         BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1952                 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1953                         BT_UART_MSG_FRAME2CHLSEQN_POS,
1954                 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1955                         BT_UART_MSG_FRAME2INBAND_POS);
1956
1957         IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1958                         "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1959                 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1960                         BT_UART_MSG_FRAME3SCOESCO_POS,
1961                 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1962                         BT_UART_MSG_FRAME3SNIFF_POS,
1963                 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1964                         BT_UART_MSG_FRAME3A2DP_POS,
1965                 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1966                         BT_UART_MSG_FRAME3ACL_POS,
1967                 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1968                         BT_UART_MSG_FRAME3MASTER_POS,
1969                 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1970                         BT_UART_MSG_FRAME3OBEX_POS);
1971
1972         IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
1973                 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1974                         BT_UART_MSG_FRAME4IDLEDURATION_POS);
1975
1976         IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1977                         "eSCO Retransmissions = 0x%X",
1978                 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1979                         BT_UART_MSG_FRAME5TXACTIVITY_POS,
1980                 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1981                         BT_UART_MSG_FRAME5RXACTIVITY_POS,
1982                 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1983                         BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1984
1985         IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1986                 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1987                         BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1988                 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1989                         BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1990
1991         IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Inquiry/Page SR Mode = "
1992                         "0x%X, Connectable = 0x%X",
1993                 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1994                         BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1995                 (BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_MSK & uart_msg->frame7) >>
1996                         BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_POS,
1997                 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1998                         BT_UART_MSG_FRAME7CONNECTABLE_POS);
1999 }
2000
2001 static void iwlagn_set_kill_msk(struct iwl_priv *priv,
2002                                 struct iwl_bt_uart_msg *uart_msg)
2003 {
2004         u8 kill_msk;
2005         static const __le32 bt_kill_ack_msg[2] = {
2006                 IWLAGN_BT_KILL_ACK_MASK_DEFAULT,
2007                 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
2008         static const __le32 bt_kill_cts_msg[2] = {
2009                 IWLAGN_BT_KILL_CTS_MASK_DEFAULT,
2010                 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
2011
2012         kill_msk = (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3)
2013                 ? 1 : 0;
2014         if (priv->kill_ack_mask != bt_kill_ack_msg[kill_msk] ||
2015             priv->kill_cts_mask != bt_kill_cts_msg[kill_msk]) {
2016                 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
2017                 priv->kill_ack_mask = bt_kill_ack_msg[kill_msk];
2018                 priv->bt_valid |= IWLAGN_BT_VALID_KILL_CTS_MASK;
2019                 priv->kill_cts_mask = bt_kill_cts_msg[kill_msk];
2020
2021                 /* schedule to send runtime bt_config */
2022                 queue_work(priv->workqueue, &priv->bt_runtime_config);
2023         }
2024 }
2025
2026 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
2027                                              struct iwl_rx_mem_buffer *rxb)
2028 {
2029         unsigned long flags;
2030         struct iwl_rx_packet *pkt = rxb_addr(rxb);
2031         struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
2032         struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
2033         struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
2034
2035         IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
2036         IWL_DEBUG_NOTIF(priv, "    status: %d\n", coex->bt_status);
2037         IWL_DEBUG_NOTIF(priv, "    traffic load: %d\n", coex->bt_traffic_load);
2038         IWL_DEBUG_NOTIF(priv, "    CI compliance: %d\n",
2039                         coex->bt_ci_compliance);
2040         iwlagn_print_uartmsg(priv, uart_msg);
2041
2042         priv->last_bt_traffic_load = priv->bt_traffic_load;
2043         if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2044                 if (priv->bt_status != coex->bt_status ||
2045                     priv->last_bt_traffic_load != coex->bt_traffic_load) {
2046                         if (coex->bt_status) {
2047                                 /* BT on */
2048                                 if (!priv->bt_ch_announce)
2049                                         priv->bt_traffic_load =
2050                                                 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
2051                                 else
2052                                         priv->bt_traffic_load =
2053                                                 coex->bt_traffic_load;
2054                         } else {
2055                                 /* BT off */
2056                                 priv->bt_traffic_load =
2057                                         IWL_BT_COEX_TRAFFIC_LOAD_NONE;
2058                         }
2059                         priv->bt_status = coex->bt_status;
2060                         queue_work(priv->workqueue,
2061                                    &priv->bt_traffic_change_work);
2062                 }
2063                 if (priv->bt_sco_active !=
2064                     (uart_msg->frame3 & BT_UART_MSG_FRAME3SCOESCO_MSK)) {
2065                         priv->bt_sco_active = uart_msg->frame3 &
2066                                 BT_UART_MSG_FRAME3SCOESCO_MSK;
2067                         if (priv->bt_sco_active)
2068                                 sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
2069                         iwl_send_cmd_pdu_async(priv, REPLY_BT_COEX_SCO,
2070                                        sizeof(sco_cmd), &sco_cmd, NULL);
2071                 }
2072         }
2073
2074         iwlagn_set_kill_msk(priv, uart_msg);
2075
2076         /* FIXME: based on notification, adjust the prio_boost */
2077
2078         spin_lock_irqsave(&priv->lock, flags);
2079         priv->bt_ci_compliance = coex->bt_ci_compliance;
2080         spin_unlock_irqrestore(&priv->lock, flags);
2081 }
2082
2083 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
2084 {
2085         iwlagn_rx_handler_setup(priv);
2086         priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
2087                 iwlagn_bt_coex_profile_notif;
2088 }
2089
2090 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
2091 {
2092         iwlagn_setup_deferred_work(priv);
2093
2094         INIT_WORK(&priv->bt_traffic_change_work,
2095                   iwlagn_bt_traffic_change_work);
2096 }
2097
2098 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
2099 {
2100         cancel_work_sync(&priv->bt_traffic_change_work);
2101 }
2102
2103 static bool is_single_rx_stream(struct iwl_priv *priv)
2104 {
2105         return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
2106                priv->current_ht_config.single_chain_sufficient;
2107 }
2108
2109 #define IWL_NUM_RX_CHAINS_MULTIPLE      3
2110 #define IWL_NUM_RX_CHAINS_SINGLE        2
2111 #define IWL_NUM_IDLE_CHAINS_DUAL        2
2112 #define IWL_NUM_IDLE_CHAINS_SINGLE      1
2113
2114 /*
2115  * Determine how many receiver/antenna chains to use.
2116  *
2117  * More provides better reception via diversity.  Fewer saves power
2118  * at the expense of throughput, but only when not in powersave to
2119  * start with.
2120  *
2121  * MIMO (dual stream) requires at least 2, but works better with 3.
2122  * This does not determine *which* chains to use, just how many.
2123  */
2124 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
2125 {
2126         if (priv->cfg->bt_params &&
2127             priv->cfg->bt_params->advanced_bt_coexist &&
2128             (priv->bt_full_concurrent ||
2129              priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2130                 /*
2131                  * only use chain 'A' in bt high traffic load or
2132                  * full concurrency mode
2133                  */
2134                 return IWL_NUM_RX_CHAINS_SINGLE;
2135         }
2136         /* # of Rx chains to use when expecting MIMO. */
2137         if (is_single_rx_stream(priv))
2138                 return IWL_NUM_RX_CHAINS_SINGLE;
2139         else
2140                 return IWL_NUM_RX_CHAINS_MULTIPLE;
2141 }
2142
2143 /*
2144  * When we are in power saving mode, unless device support spatial
2145  * multiplexing power save, use the active count for rx chain count.
2146  */
2147 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
2148 {
2149         /* # Rx chains when idling, depending on SMPS mode */
2150         switch (priv->current_ht_config.smps) {
2151         case IEEE80211_SMPS_STATIC:
2152         case IEEE80211_SMPS_DYNAMIC:
2153                 return IWL_NUM_IDLE_CHAINS_SINGLE;
2154         case IEEE80211_SMPS_OFF:
2155                 return active_cnt;
2156         default:
2157                 WARN(1, "invalid SMPS mode %d",
2158                      priv->current_ht_config.smps);
2159                 return active_cnt;
2160         }
2161 }
2162
2163 /* up to 4 chains */
2164 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
2165 {
2166         u8 res;
2167         res = (chain_bitmap & BIT(0)) >> 0;
2168         res += (chain_bitmap & BIT(1)) >> 1;
2169         res += (chain_bitmap & BIT(2)) >> 2;
2170         res += (chain_bitmap & BIT(3)) >> 3;
2171         return res;
2172 }
2173
2174 /**
2175  * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2176  *
2177  * Selects how many and which Rx receivers/antennas/chains to use.
2178  * This should not be used for scan command ... it puts data in wrong place.
2179  */
2180 void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
2181 {
2182         bool is_single = is_single_rx_stream(priv);
2183         bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
2184         u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
2185         u32 active_chains;
2186         u16 rx_chain;
2187
2188         /* Tell uCode which antennas are actually connected.
2189          * Before first association, we assume all antennas are connected.
2190          * Just after first association, iwl_chain_noise_calibration()
2191          *    checks which antennas actually *are* connected. */
2192         if (priv->chain_noise_data.active_chains)
2193                 active_chains = priv->chain_noise_data.active_chains;
2194         else
2195                 active_chains = priv->hw_params.valid_rx_ant;
2196
2197         if (priv->cfg->bt_params &&
2198             priv->cfg->bt_params->advanced_bt_coexist &&
2199             (priv->bt_full_concurrent ||
2200              priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2201                 /*
2202                  * only use chain 'A' in bt high traffic load or
2203                  * full concurrency mode
2204                  */
2205                 active_chains = first_antenna(active_chains);
2206         }
2207
2208         rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
2209
2210         /* How many receivers should we use? */
2211         active_rx_cnt = iwl_get_active_rx_chain_count(priv);
2212         idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
2213
2214
2215         /* correct rx chain count according hw settings
2216          * and chain noise calibration
2217          */
2218         valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
2219         if (valid_rx_cnt < active_rx_cnt)
2220                 active_rx_cnt = valid_rx_cnt;
2221
2222         if (valid_rx_cnt < idle_rx_cnt)
2223                 idle_rx_cnt = valid_rx_cnt;
2224
2225         rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
2226         rx_chain |= idle_rx_cnt  << RXON_RX_CHAIN_CNT_POS;
2227
2228         ctx->staging.rx_chain = cpu_to_le16(rx_chain);
2229
2230         if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
2231                 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2232         else
2233                 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2234
2235         IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
2236                         ctx->staging.rx_chain,
2237                         active_rx_cnt, idle_rx_cnt);
2238
2239         WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
2240                 active_rx_cnt < idle_rx_cnt);
2241 }
2242
2243 u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
2244 {
2245         int i;
2246         u8 ind = ant;
2247
2248         if (priv->band == IEEE80211_BAND_2GHZ &&
2249             priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
2250                 return 0;
2251
2252         for (i = 0; i < RATE_ANT_NUM - 1; i++) {
2253                 ind = (ind + 1) < RATE_ANT_NUM ?  ind + 1 : 0;
2254                 if (valid & BIT(ind))
2255                         return ind;
2256         }
2257         return ant;
2258 }
2259
2260 static const char *get_csr_string(int cmd)
2261 {
2262         switch (cmd) {
2263         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2264         IWL_CMD(CSR_INT_COALESCING);
2265         IWL_CMD(CSR_INT);
2266         IWL_CMD(CSR_INT_MASK);
2267         IWL_CMD(CSR_FH_INT_STATUS);
2268         IWL_CMD(CSR_GPIO_IN);
2269         IWL_CMD(CSR_RESET);
2270         IWL_CMD(CSR_GP_CNTRL);
2271         IWL_CMD(CSR_HW_REV);
2272         IWL_CMD(CSR_EEPROM_REG);
2273         IWL_CMD(CSR_EEPROM_GP);
2274         IWL_CMD(CSR_OTP_GP_REG);
2275         IWL_CMD(CSR_GIO_REG);
2276         IWL_CMD(CSR_GP_UCODE_REG);
2277         IWL_CMD(CSR_GP_DRIVER_REG);
2278         IWL_CMD(CSR_UCODE_DRV_GP1);
2279         IWL_CMD(CSR_UCODE_DRV_GP2);
2280         IWL_CMD(CSR_LED_REG);
2281         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2282         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2283         IWL_CMD(CSR_ANA_PLL_CFG);
2284         IWL_CMD(CSR_HW_REV_WA_REG);
2285         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2286         default:
2287                 return "UNKNOWN";
2288         }
2289 }
2290
2291 void iwl_dump_csr(struct iwl_priv *priv)
2292 {
2293         int i;
2294         static const u32 csr_tbl[] = {
2295                 CSR_HW_IF_CONFIG_REG,
2296                 CSR_INT_COALESCING,
2297                 CSR_INT,
2298                 CSR_INT_MASK,
2299                 CSR_FH_INT_STATUS,
2300                 CSR_GPIO_IN,
2301                 CSR_RESET,
2302                 CSR_GP_CNTRL,
2303                 CSR_HW_REV,
2304                 CSR_EEPROM_REG,
2305                 CSR_EEPROM_GP,
2306                 CSR_OTP_GP_REG,
2307                 CSR_GIO_REG,
2308                 CSR_GP_UCODE_REG,
2309                 CSR_GP_DRIVER_REG,
2310                 CSR_UCODE_DRV_GP1,
2311                 CSR_UCODE_DRV_GP2,
2312                 CSR_LED_REG,
2313                 CSR_DRAM_INT_TBL_REG,
2314                 CSR_GIO_CHICKEN_BITS,
2315                 CSR_ANA_PLL_CFG,
2316                 CSR_HW_REV_WA_REG,
2317                 CSR_DBG_HPET_MEM_REG
2318         };
2319         IWL_ERR(priv, "CSR values:\n");
2320         IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
2321                 "CSR_INT_PERIODIC_REG)\n");
2322         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2323                 IWL_ERR(priv, "  %25s: 0X%08x\n",
2324                         get_csr_string(csr_tbl[i]),
2325                         iwl_read32(priv, csr_tbl[i]));
2326         }
2327 }
2328
2329 static const char *get_fh_string(int cmd)
2330 {
2331         switch (cmd) {
2332         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
2333         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
2334         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
2335         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
2336         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
2337         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
2338         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
2339         IWL_CMD(FH_TSSR_TX_STATUS_REG);
2340         IWL_CMD(FH_TSSR_TX_ERROR_REG);
2341         default:
2342                 return "UNKNOWN";
2343         }
2344 }
2345
2346 int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
2347 {
2348         int i;
2349 #ifdef CONFIG_IWLWIFI_DEBUG
2350         int pos = 0;
2351         size_t bufsz = 0;
2352 #endif
2353         static const u32 fh_tbl[] = {
2354                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
2355                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
2356                 FH_RSCSR_CHNL0_WPTR,
2357                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
2358                 FH_MEM_RSSR_SHARED_CTRL_REG,
2359                 FH_MEM_RSSR_RX_STATUS_REG,
2360                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
2361                 FH_TSSR_TX_STATUS_REG,
2362                 FH_TSSR_TX_ERROR_REG
2363         };
2364 #ifdef CONFIG_IWLWIFI_DEBUG
2365         if (display) {
2366                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
2367                 *buf = kmalloc(bufsz, GFP_KERNEL);
2368                 if (!*buf)
2369                         return -ENOMEM;
2370                 pos += scnprintf(*buf + pos, bufsz - pos,
2371                                 "FH register values:\n");
2372                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2373                         pos += scnprintf(*buf + pos, bufsz - pos,
2374                                 "  %34s: 0X%08x\n",
2375                                 get_fh_string(fh_tbl[i]),
2376                                 iwl_read_direct32(priv, fh_tbl[i]));
2377                 }
2378                 return pos;
2379         }
2380 #endif
2381         IWL_ERR(priv, "FH register values:\n");
2382         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
2383                 IWL_ERR(priv, "  %34s: 0X%08x\n",
2384                         get_fh_string(fh_tbl[i]),
2385                         iwl_read_direct32(priv, fh_tbl[i]));
2386         }
2387         return 0;
2388 }