2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
21 #define DMA_DUMMY_TXWI ((void *) ~0)
24 mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q)
29 spin_lock_init(&q->lock);
30 INIT_LIST_HEAD(&q->swq);
32 size = q->ndesc * sizeof(struct mt76_desc);
33 q->desc = dmam_alloc_coherent(dev->dev, size, &q->desc_dma, GFP_KERNEL);
37 size = q->ndesc * sizeof(*q->entry);
38 q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL);
42 /* clear descriptors */
43 for (i = 0; i < q->ndesc; i++)
44 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE);
46 iowrite32(q->desc_dma, &q->regs->desc_base);
47 iowrite32(0, &q->regs->cpu_idx);
48 iowrite32(0, &q->regs->dma_idx);
49 iowrite32(q->ndesc, &q->regs->ring_size);
55 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
56 struct mt76_queue_buf *buf, int nbufs, u32 info,
57 struct sk_buff *skb, void *txwi)
59 struct mt76_desc *desc;
64 q->entry[q->head].txwi = DMA_DUMMY_TXWI;
66 for (i = 0; i < nbufs; i += 2, buf += 2) {
67 u32 buf0 = buf[0].addr, buf1 = 0;
69 ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
72 ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
76 ctrl |= MT_DMA_CTL_LAST_SEC0;
77 else if (i == nbufs - 2)
78 ctrl |= MT_DMA_CTL_LAST_SEC1;
81 q->head = (q->head + 1) % q->ndesc;
85 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0));
86 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1));
87 WRITE_ONCE(desc->info, cpu_to_le32(info));
88 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl));
93 q->entry[idx].txwi = txwi;
94 q->entry[idx].skb = skb;
100 mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx,
101 struct mt76_queue_entry *prev_e)
103 struct mt76_queue_entry *e = &q->entry[idx];
104 __le32 __ctrl = READ_ONCE(q->desc[idx].ctrl);
105 u32 ctrl = le32_to_cpu(__ctrl);
107 if (!e->txwi || !e->skb) {
108 __le32 addr = READ_ONCE(q->desc[idx].buf0);
109 u32 len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctrl);
111 dma_unmap_single(dev->dev, le32_to_cpu(addr), len,
115 if (!(ctrl & MT_DMA_CTL_LAST_SEC0)) {
116 __le32 addr = READ_ONCE(q->desc[idx].buf1);
117 u32 len = FIELD_GET(MT_DMA_CTL_SD_LEN1, ctrl);
119 dma_unmap_single(dev->dev, le32_to_cpu(addr), len,
123 if (e->txwi == DMA_DUMMY_TXWI)
127 memset(e, 0, sizeof(*e));
131 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q)
133 q->head = ioread32(&q->regs->dma_idx);
135 iowrite32(q->head, &q->regs->cpu_idx);
139 mt76_dma_tx_cleanup(struct mt76_dev *dev, enum mt76_txq_id qid, bool flush)
141 struct mt76_queue *q = &dev->q_tx[qid];
142 struct mt76_queue_entry entry;
149 spin_lock_bh(&q->lock);
153 last = ioread32(&q->regs->dma_idx);
155 while (q->queued && q->tail != last) {
156 mt76_dma_tx_cleanup_idx(dev, q, q->tail, &entry);
160 q->tail = (q->tail + 1) % q->ndesc;
164 spin_unlock_bh(&q->lock);
165 dev->drv->tx_complete_skb(dev, q, &entry, flush);
166 spin_lock_bh(&q->lock);
170 mt76_put_txwi(dev, entry.txwi);
174 if (!flush && q->tail == last)
175 last = ioread32(&q->regs->dma_idx);
179 mt76_txq_schedule(dev, q);
181 mt76_dma_sync_idx(dev, q);
183 wake = wake && qid < IEEE80211_NUM_ACS && q->queued < q->ndesc - 8;
186 wake_up(&dev->tx_wait);
188 spin_unlock_bh(&q->lock);
191 ieee80211_wake_queue(dev->hw, qid);
195 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
196 int *len, u32 *info, bool *more)
198 struct mt76_queue_entry *e = &q->entry[idx];
199 struct mt76_desc *desc = &q->desc[idx];
202 int buf_len = SKB_WITH_OVERHEAD(q->buf_size);
204 buf_addr = le32_to_cpu(READ_ONCE(desc->buf0));
206 u32 ctl = le32_to_cpu(READ_ONCE(desc->ctrl));
207 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl);
208 *more = !(ctl & MT_DMA_CTL_LAST_SEC0);
212 *info = le32_to_cpu(desc->info);
214 dma_unmap_single(dev->dev, buf_addr, buf_len, DMA_FROM_DEVICE);
221 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
222 int *len, u32 *info, bool *more)
230 if (!flush && !(q->desc[idx].ctrl & cpu_to_le32(MT_DMA_CTL_DMA_DONE)))
233 q->tail = (q->tail + 1) % q->ndesc;
236 return mt76_dma_get_buf(dev, q, idx, len, info, more);
240 mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q)
242 iowrite32(q->head, &q->regs->cpu_idx);
246 mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, enum mt76_txq_id qid,
247 struct sk_buff *skb, u32 tx_info)
249 struct mt76_queue *q = &dev->q_tx[qid];
250 struct mt76_queue_buf buf;
253 addr = dma_map_single(dev->dev, skb->data, skb->len,
255 if (dma_mapping_error(dev->dev, addr))
261 spin_lock_bh(&q->lock);
262 mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL);
263 mt76_dma_kick_queue(dev, q);
264 spin_unlock_bh(&q->lock);
269 int mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
270 struct sk_buff *skb, struct mt76_wcid *wcid,
271 struct ieee80211_sta *sta)
273 struct mt76_queue_entry e;
274 struct mt76_txwi_cache *t;
275 struct mt76_queue_buf buf[32];
276 struct sk_buff *iter;
282 t = mt76_get_txwi(dev);
284 ieee80211_free_txskb(dev->hw, skb);
288 skb->prev = skb->next = NULL;
289 dma_sync_single_for_cpu(dev->dev, t->dma_addr, sizeof(t->txwi),
291 ret = dev->drv->tx_prepare_skb(dev, &t->txwi, skb, q, wcid, sta,
293 dma_sync_single_for_device(dev->dev, t->dma_addr, sizeof(t->txwi),
298 len = skb->len - skb->data_len;
299 addr = dma_map_single(dev->dev, skb->data, len, DMA_TO_DEVICE);
300 if (dma_mapping_error(dev->dev, addr)) {
306 buf[n].addr = t->dma_addr;
307 buf[n++].len = dev->drv->txwi_size;
311 skb_walk_frags(skb, iter) {
312 if (n == ARRAY_SIZE(buf))
315 addr = dma_map_single(dev->dev, iter->data, iter->len,
317 if (dma_mapping_error(dev->dev, addr))
321 buf[n++].len = iter->len;
324 if (q->queued + (n + 1) / 2 >= q->ndesc - 1)
327 return mt76_dma_add_buf(dev, q, buf, n, tx_info, skb, t);
331 for (n--; n > 0; n--)
332 dma_unmap_single(dev->dev, buf[n].addr, buf[n].len,
338 dev->drv->tx_complete_skb(dev, q, &e, true);
339 mt76_put_txwi(dev, t);
342 EXPORT_SYMBOL_GPL(mt76_dma_tx_queue_skb);
345 mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
350 int len = SKB_WITH_OVERHEAD(q->buf_size);
351 int offset = q->buf_offset;
354 spin_lock_bh(&q->lock);
356 while (q->queued < q->ndesc - 1) {
357 struct mt76_queue_buf qbuf;
359 buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
363 addr = dma_map_single(dev->dev, buf, len, DMA_FROM_DEVICE);
364 if (dma_mapping_error(dev->dev, addr)) {
369 qbuf.addr = addr + offset;
370 qbuf.len = len - offset;
371 idx = mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL);
376 mt76_dma_kick_queue(dev, q);
378 spin_unlock_bh(&q->lock);
384 mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
390 spin_lock_bh(&q->lock);
392 buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more);
398 spin_unlock_bh(&q->lock);
403 page = virt_to_page(q->rx_page.va);
404 __page_frag_cache_drain(page, q->rx_page.pagecnt_bias);
405 memset(&q->rx_page, 0, sizeof(q->rx_page));
409 mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
411 struct mt76_queue *q = &dev->q_rx[qid];
414 for (i = 0; i < q->ndesc; i++)
415 q->desc[i].ctrl &= ~cpu_to_le32(MT_DMA_CTL_DMA_DONE);
417 mt76_dma_rx_cleanup(dev, q);
418 mt76_dma_sync_idx(dev, q);
419 mt76_dma_rx_fill(dev, q);
423 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
426 struct page *page = virt_to_head_page(data);
427 int offset = data - page_address(page);
428 struct sk_buff *skb = q->rx_head;
430 offset += q->buf_offset;
431 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, offset, len,
438 dev->drv->rx_skb(dev, q - dev->q_rx, skb);
442 mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
444 int len, data_len, done = 0;
449 while (done < budget) {
452 data = mt76_dma_dequeue(dev, q, false, &len, &info, &more);
457 data_len = q->buf_size;
459 data_len = SKB_WITH_OVERHEAD(q->buf_size);
461 if (data_len < len + q->buf_offset) {
462 dev_kfree_skb(q->rx_head);
470 mt76_add_fragment(dev, q, data, len, more);
474 skb = build_skb(data, q->buf_size);
479 skb_reserve(skb, q->buf_offset);
481 if (q == &dev->q_rx[MT_RXQ_MCU]) {
482 u32 *rxfce = (u32 *) skb->cb;
494 dev->drv->rx_skb(dev, q - dev->q_rx, skb);
497 mt76_dma_rx_fill(dev, q);
502 mt76_dma_rx_poll(struct napi_struct *napi, int budget)
504 struct mt76_dev *dev;
505 int qid, done = 0, cur;
507 dev = container_of(napi->dev, struct mt76_dev, napi_dev);
508 qid = napi - dev->napi;
513 cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done);
514 mt76_rx_poll_complete(dev, qid, napi);
516 } while (cur && done < budget);
522 dev->drv->rx_poll_complete(dev, qid);
529 mt76_dma_init(struct mt76_dev *dev)
533 init_dummy_netdev(&dev->napi_dev);
535 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) {
536 netif_napi_add(&dev->napi_dev, &dev->napi[i], mt76_dma_rx_poll,
538 mt76_dma_rx_fill(dev, &dev->q_rx[i]);
539 skb_queue_head_init(&dev->rx_skb[i]);
540 napi_enable(&dev->napi[i]);
546 static const struct mt76_queue_ops mt76_dma_ops = {
547 .init = mt76_dma_init,
548 .alloc = mt76_dma_alloc_queue,
549 .tx_queue_skb_raw = mt76_dma_tx_queue_skb_raw,
550 .tx_queue_skb = mt76_dma_tx_queue_skb,
551 .tx_cleanup = mt76_dma_tx_cleanup,
552 .rx_reset = mt76_dma_rx_reset,
553 .kick = mt76_dma_kick_queue,
556 void mt76_dma_attach(struct mt76_dev *dev)
558 dev->queue_ops = &mt76_dma_ops;
560 EXPORT_SYMBOL_GPL(mt76_dma_attach);
562 void mt76_dma_cleanup(struct mt76_dev *dev)
566 for (i = 0; i < ARRAY_SIZE(dev->q_tx); i++)
567 mt76_dma_tx_cleanup(dev, i, true);
569 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) {
570 netif_napi_del(&dev->napi[i]);
571 mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
574 EXPORT_SYMBOL_GPL(mt76_dma_cleanup);