1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2019 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * Roy Luo <royluo@google.com>
6 * Felix Fietkau <nbd@nbd.name>
7 * Lorenzo Bianconi <lorenzo@kernel.org>
10 #include <linux/etherdevice.h>
11 #include <linux/timekeeping.h>
16 static inline s8 to_rssi(u32 field, u32 rxv)
18 return (FIELD_GET(field, rxv) - 220) / 2;
21 static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev,
24 struct mt7615_sta *sta;
25 struct mt76_wcid *wcid;
27 if (idx >= ARRAY_SIZE(dev->mt76.wcid))
30 wcid = rcu_dereference(dev->mt76.wcid[idx]);
37 sta = container_of(wcid, struct mt7615_sta, wcid);
41 return &sta->vif->sta.wcid;
44 int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb)
46 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
47 struct ieee80211_supported_band *sband;
48 struct ieee80211_hdr *hdr;
49 __le32 *rxd = (__le32 *)skb->data;
50 u32 rxd0 = le32_to_cpu(rxd[0]);
51 u32 rxd1 = le32_to_cpu(rxd[1]);
52 u32 rxd2 = le32_to_cpu(rxd[2]);
53 bool unicast, remove_pad, insert_ccmp_hdr = false;
56 if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state))
59 memset(status, 0, sizeof(*status));
61 unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M;
62 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
63 status->wcid = mt7615_rx_get_wcid(dev, idx, unicast);
65 /* TODO: properly support DBDC */
66 status->freq = dev->mt76.chandef.chan->center_freq;
67 status->band = dev->mt76.chandef.chan->band;
68 if (status->band == NL80211_BAND_5GHZ)
69 sband = &dev->mt76.sband_5g.sband;
71 sband = &dev->mt76.sband_2g.sband;
73 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
74 status->flag |= RX_FLAG_FAILED_FCS_CRC;
76 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
77 status->flag |= RX_FLAG_MMIC_ERROR;
79 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
80 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
81 status->flag |= RX_FLAG_DECRYPTED;
82 status->flag |= RX_FLAG_IV_STRIPPED;
83 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
86 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
88 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
95 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
97 if ((u8 *)rxd - skb->data >= skb->len)
101 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
102 u8 *data = (u8 *)rxd;
104 if (status->flag & RX_FLAG_DECRYPTED) {
105 status->iv[0] = data[5];
106 status->iv[1] = data[4];
107 status->iv[2] = data[3];
108 status->iv[3] = data[2];
109 status->iv[4] = data[1];
110 status->iv[5] = data[0];
112 insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
115 if ((u8 *)rxd - skb->data >= skb->len)
119 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
121 if ((u8 *)rxd - skb->data >= skb->len)
125 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
126 u32 rxdg0 = le32_to_cpu(rxd[0]);
127 u32 rxdg1 = le32_to_cpu(rxd[1]);
128 u32 rxdg3 = le32_to_cpu(rxd[3]);
129 u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
132 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
133 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
134 case MT_PHY_TYPE_CCK:
137 case MT_PHY_TYPE_OFDM:
138 i = mt76_get_rate(&dev->mt76, sband, i, cck);
140 case MT_PHY_TYPE_HT_GF:
142 status->encoding = RX_ENC_HT;
146 case MT_PHY_TYPE_VHT:
147 status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1;
148 status->encoding = RX_ENC_VHT;
153 status->rate_idx = i;
155 switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) {
159 status->bw = RATE_INFO_BW_40;
162 status->bw = RATE_INFO_BW_80;
165 status->bw = RATE_INFO_BW_160;
171 if (rxdg0 & MT_RXV1_HT_SHORT_GI)
172 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
173 if (rxdg0 & MT_RXV1_HT_AD_CODE)
174 status->enc_flags |= RX_ENC_FLAG_LDPC;
176 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
178 status->chains = dev->mt76.antenna_mask;
179 status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3);
180 status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3);
181 status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3);
182 status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3);
183 status->signal = status->chain_signal[0];
185 for (i = 1; i < hweight8(dev->mt76.antenna_mask); i++) {
186 if (!(status->chains & BIT(i)))
189 status->signal = max(status->signal,
190 status->chain_signal[i]);
194 if ((u8 *)rxd - skb->data >= skb->len)
198 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
200 if (insert_ccmp_hdr) {
201 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
203 mt76_insert_ccmp_hdr(skb, key_id);
206 hdr = (struct ieee80211_hdr *)skb->data;
207 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
210 status->aggr = unicast &&
211 !ieee80211_is_qos_nullfunc(hdr->frame_control);
212 status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK;
213 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
218 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
222 void mt7615_tx_complete_skb(struct mt76_dev *mdev, enum mt76_txq_id qid,
223 struct mt76_queue_entry *e)
226 dev_kfree_skb_any(e->skb);
231 if (e->skb == DMA_DUMMY_DATA) {
232 struct mt76_txwi_cache *t;
233 struct mt7615_dev *dev;
234 struct mt7615_txp *txp;
237 txwi_ptr = mt76_get_txwi_ptr(mdev, e->txwi);
238 txp = (struct mt7615_txp *)(txwi_ptr + MT_TXD_SIZE);
239 dev = container_of(mdev, struct mt7615_dev, mt76);
241 spin_lock_bh(&dev->token_lock);
242 t = idr_remove(&dev->token, le16_to_cpu(txp->token));
243 spin_unlock_bh(&dev->token_lock);
244 e->skb = t ? t->skb : NULL;
248 mt76_tx_complete_skb(mdev, e->skb);
252 mt7615_mac_tx_rate_val(struct mt7615_dev *dev,
253 const struct ieee80211_tx_rate *rate,
256 u8 phy, nss, rate_idx;
261 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
262 rate_idx = ieee80211_rate_get_vht_mcs(rate);
263 nss = ieee80211_rate_get_vht_nss(rate);
264 phy = MT_PHY_TYPE_VHT;
265 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
267 else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
269 else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
271 } else if (rate->flags & IEEE80211_TX_RC_MCS) {
272 rate_idx = rate->idx;
273 nss = 1 + (rate->idx >> 3);
274 phy = MT_PHY_TYPE_HT;
275 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
276 phy = MT_PHY_TYPE_HT_GF;
277 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
280 const struct ieee80211_rate *r;
281 int band = dev->mt76.chandef.chan->band;
285 r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx];
286 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
287 val = r->hw_value_short;
292 rate_idx = val & 0xff;
295 rateval = (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
296 FIELD_PREP(MT_TX_RATE_MODE, phy) |
297 FIELD_PREP(MT_TX_RATE_NSS, nss - 1));
299 if (stbc && nss == 1)
300 rateval |= MT_TX_RATE_STBC;
305 int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi,
306 struct sk_buff *skb, struct mt76_wcid *wcid,
307 struct ieee80211_sta *sta, int pid,
308 struct ieee80211_key_conf *key)
310 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
311 struct ieee80211_tx_rate *rate = &info->control.rates[0];
312 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
313 struct ieee80211_vif *vif = info->control.vif;
315 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0;
316 __le16 fc = hdr->frame_control;
321 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
323 omac_idx = mvif->omac_idx;
327 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
329 tx_count = msta->rate_count;
332 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
333 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
335 if (ieee80211_is_data(fc)) {
336 q_idx = skb_get_queue_mapping(skb);
337 p_fmt = MT_TX_TYPE_CT;
338 } else if (ieee80211_is_beacon(fc)) {
339 q_idx = MT_LMAC_BCN0;
340 p_fmt = MT_TX_TYPE_FW;
342 q_idx = MT_LMAC_ALTX0;
343 p_fmt = MT_TX_TYPE_CT;
346 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
347 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) |
348 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
349 txwi[0] = cpu_to_le32(val);
351 val = MT_TXD1_LONG_FORMAT |
352 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
353 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
354 FIELD_PREP(MT_TXD1_HDR_INFO,
355 ieee80211_get_hdrlen_from_skb(skb) / 2) |
356 FIELD_PREP(MT_TXD1_TID,
357 skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
358 FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) |
359 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
360 txwi[1] = cpu_to_le32(val);
362 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
363 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
364 FIELD_PREP(MT_TXD2_MULTICAST,
365 is_multicast_ether_addr(hdr->addr1));
366 txwi[2] = cpu_to_le32(val);
368 if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
369 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
374 if (rate->idx >= 0 && rate->count &&
375 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
376 bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
378 u16 rateval = mt7615_mac_tx_rate_val(dev, rate, stbc, &bw);
380 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
382 val = MT_TXD6_FIXED_BW |
383 FIELD_PREP(MT_TXD6_BW, bw) |
384 FIELD_PREP(MT_TXD6_TX_RATE, rateval);
385 txwi[6] |= cpu_to_le32(val);
387 if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
388 txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
390 if (info->flags & IEEE80211_TX_CTL_LDPC)
391 txwi[6] |= cpu_to_le32(MT_TXD6_LDPC);
393 if (!(rate->flags & (IEEE80211_TX_RC_MCS |
394 IEEE80211_TX_RC_VHT_MCS)))
395 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
397 tx_count = rate->count;
400 if (!ieee80211_is_beacon(fc)) {
401 val = MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT |
402 FIELD_PREP(MT_TXD5_PID, pid);
403 txwi[5] = cpu_to_le32(val);
406 /* use maximum tx count for beacons */
410 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count);
411 if (ieee80211_is_data_qos(hdr->frame_control)) {
412 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
413 val |= MT_TXD3_SN_VALID;
414 } else if (ieee80211_is_back_req(hdr->frame_control)) {
415 struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data;
417 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(bar->start_seq_num));
418 val |= MT_TXD3_SN_VALID;
420 val |= FIELD_PREP(MT_TXD3_SEQ, seqno);
422 txwi[3] = cpu_to_le32(val);
424 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
425 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK);
428 txwi[3] |= cpu_to_le32(MT_TXD3_PROTECT_FRAME);
430 txwi[7] = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
431 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype);
436 void mt7615_txp_skb_unmap(struct mt76_dev *dev,
437 struct mt76_txwi_cache *t)
439 struct mt7615_txp *txp;
443 txwi = mt76_get_txwi_ptr(dev, t);
444 txp = (struct mt7615_txp *)(txwi + MT_TXD_SIZE);
445 for (i = 1; i < txp->nbuf; i++)
446 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]),
447 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE);
450 void mt7615_mac_set_rates(struct mt7615_dev *dev, struct mt7615_sta *sta,
451 struct ieee80211_tx_rate *probe_rate,
452 struct ieee80211_tx_rate *rates)
454 int wcid = sta->wcid.idx;
455 u32 addr = MT_WTBL_BASE + wcid * MT_WTBL_ENTRY_SIZE;
457 int n_rates = sta->n_rates;
458 u8 bw, bw_prev, bw_idx = 0;
464 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
467 for (i = n_rates; i < 4; i++)
468 rates[i] = rates[n_rates - 1];
470 val[0] = mt7615_mac_tx_rate_val(dev, &rates[0], stbc, &bw);
474 probe_val = mt7615_mac_tx_rate_val(dev, probe_rate, stbc, &bw);
483 val[1] = mt7615_mac_tx_rate_val(dev, &rates[1], stbc, &bw);
489 val[2] = mt7615_mac_tx_rate_val(dev, &rates[2], stbc, &bw);
495 val[3] = mt7615_mac_tx_rate_val(dev, &rates[3], stbc, &bw);
499 w27 = mt76_rr(dev, addr + 27 * 4);
500 w27 &= ~MT_WTBL_W27_CC_BW_SEL;
501 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, bw);
503 w5 = mt76_rr(dev, addr + 5 * 4);
504 w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE);
505 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, bw) |
506 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE, bw_idx ? bw_idx - 1 : 7);
508 mt76_wr(dev, MT_WTBL_RIUCR0, w5);
510 mt76_wr(dev, MT_WTBL_RIUCR1,
511 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, probe_val) |
512 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) |
513 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[0]));
515 mt76_wr(dev, MT_WTBL_RIUCR2,
516 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[0] >> 8) |
517 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) |
518 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[1]) |
519 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2]));
521 mt76_wr(dev, MT_WTBL_RIUCR3,
522 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) |
523 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[2]) |
524 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3]));
526 mt76_wr(dev, MT_WTBL_UPDATE,
527 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
528 MT_WTBL_UPDATE_RATE_UPDATE |
529 MT_WTBL_UPDATE_TX_COUNT_CLEAR);
531 mt76_wr(dev, addr + 27 * 4, w27);
533 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
534 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
536 sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates;
537 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
539 int mt7615_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
540 enum mt76_txq_id qid, struct mt76_wcid *wcid,
541 struct ieee80211_sta *sta,
542 struct mt76_tx_info *tx_info)
544 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data;
545 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
546 struct mt7615_sta *msta = container_of(wcid, struct mt7615_sta, wcid);
547 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
548 struct ieee80211_key_conf *key = info->control.hw_key;
549 struct ieee80211_vif *vif = info->control.vif;
550 int i, pid, id, nbuf = tx_info->nbuf - 1;
551 u8 *txwi = (u8 *)txwi_ptr;
552 struct mt76_txwi_cache *t;
553 struct mt7615_txp *txp;
556 wcid = &dev->mt76.global_wcid;
558 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
560 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) {
561 spin_lock_bh(&dev->mt76.lock);
562 msta->rate_probe = true;
563 mt7615_mac_set_rates(dev, msta, &info->control.rates[0],
565 spin_unlock_bh(&dev->mt76.lock);
568 mt7615_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, sta,
571 txp = (struct mt7615_txp *)(txwi + MT_TXD_SIZE);
572 for (i = 0; i < nbuf; i++) {
573 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr);
574 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len);
578 /* pass partial skb header to fw */
579 tx_info->buf[1].len = MT_CT_PARSE_LEN;
580 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
582 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD);
585 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME);
587 if (ieee80211_is_mgmt(hdr->frame_control))
588 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME);
591 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
593 txp->bss_idx = mvif->idx;
596 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size);
597 t->skb = tx_info->skb;
599 spin_lock_bh(&dev->token_lock);
600 id = idr_alloc(&dev->token, t, 0, MT7615_TOKEN_SIZE, GFP_ATOMIC);
601 spin_unlock_bh(&dev->token_lock);
605 txp->token = cpu_to_le16(id);
606 txp->rept_wds_wcid = 0xff;
607 tx_info->skb = DMA_DUMMY_DATA;
612 static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta,
613 struct ieee80211_tx_info *info, __le32 *txs_data)
615 struct ieee80211_supported_band *sband;
616 int i, idx, count, final_idx = 0;
617 bool fixed_rate, ack_timeout;
618 bool probe, ampdu, cck = false;
619 u32 final_rate, final_rate_flags, final_nss, txs;
621 fixed_rate = info->status.rates[0].count;
622 probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
624 txs = le32_to_cpu(txs_data[1]);
625 ampdu = !fixed_rate && (txs & MT_TXS1_AMPDU);
627 txs = le32_to_cpu(txs_data[3]);
628 count = FIELD_GET(MT_TXS3_TX_COUNT, txs);
630 txs = le32_to_cpu(txs_data[0]);
631 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
632 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
634 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
637 if (txs & MT_TXS0_QUEUE_TIMEOUT)
641 info->flags |= IEEE80211_TX_STAT_ACK;
643 info->status.ampdu_len = 1;
644 info->status.ampdu_ack_len = !!(info->flags &
645 IEEE80211_TX_STAT_ACK);
647 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
648 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
650 if (fixed_rate && !probe) {
651 info->status.rates[0].count = count;
655 for (i = 0, idx = 0; i < ARRAY_SIZE(info->status.rates); i++) {
656 int cur_count = min_t(int, count, 2 * MT7615_RATE_RETRY);
661 info->status.rates[i] = sta->rates[idx];
665 if (i && info->status.rates[i].idx < 0) {
666 info->status.rates[i - 1].count += count;
671 info->status.rates[i].idx = -1;
675 info->status.rates[i].count = cur_count;
681 final_rate_flags = info->status.rates[final_idx].flags;
683 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
684 case MT_PHY_TYPE_CCK:
687 case MT_PHY_TYPE_OFDM:
688 if (dev->mt76.chandef.chan->band == NL80211_BAND_5GHZ)
689 sband = &dev->mt76.sband_5g.sband;
691 sband = &dev->mt76.sband_2g.sband;
692 final_rate &= MT_TX_RATE_IDX;
693 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate,
695 final_rate_flags = 0;
697 case MT_PHY_TYPE_HT_GF:
699 final_rate_flags |= IEEE80211_TX_RC_MCS;
700 final_rate &= MT_TX_RATE_IDX;
704 case MT_PHY_TYPE_VHT:
705 final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate);
706 final_rate_flags |= IEEE80211_TX_RC_VHT_MCS;
707 final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4);
713 info->status.rates[final_idx].idx = final_rate;
714 info->status.rates[final_idx].flags = final_rate_flags;
719 static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev,
720 struct mt7615_sta *sta, int pid,
723 struct mt76_dev *mdev = &dev->mt76;
724 struct sk_buff_head list;
727 if (pid < MT_PACKET_ID_FIRST)
730 mt76_tx_status_lock(mdev, &list);
731 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
733 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
735 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) {
736 spin_lock_bh(&dev->mt76.lock);
737 if (sta->rate_probe) {
738 mt7615_mac_set_rates(dev, sta, NULL,
740 sta->rate_probe = false;
742 spin_unlock_bh(&dev->mt76.lock);
745 if (!mt7615_fill_txs(dev, sta, info, txs_data)) {
746 ieee80211_tx_info_clear_status(info);
747 info->status.rates[0].idx = -1;
750 mt76_tx_status_skb_done(mdev, skb, &list);
752 mt76_tx_status_unlock(mdev, &list);
757 void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data)
759 struct ieee80211_tx_info info = {};
760 struct ieee80211_sta *sta = NULL;
761 struct mt7615_sta *msta = NULL;
762 struct mt76_wcid *wcid;
763 __le32 *txs_data = data;
768 txs = le32_to_cpu(txs_data[0]);
769 pid = FIELD_GET(MT_TXS0_PID, txs);
770 txs = le32_to_cpu(txs_data[2]);
771 wcidx = FIELD_GET(MT_TXS2_WCID, txs);
773 if (pid == MT_PACKET_ID_NO_ACK)
776 if (wcidx >= ARRAY_SIZE(dev->mt76.wcid))
781 wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
785 msta = container_of(wcid, struct mt7615_sta, wcid);
786 sta = wcid_to_sta(wcid);
788 if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data))
791 if (wcidx >= MT7615_WTBL_STA || !sta)
794 if (mt7615_fill_txs(dev, msta, &info, txs_data))
795 ieee80211_tx_status_noskb(mt76_hw(dev), sta, &info);
801 void mt7615_mac_tx_free(struct mt7615_dev *dev, struct sk_buff *skb)
803 struct mt7615_tx_free *free = (struct mt7615_tx_free *)skb->data;
804 struct mt76_dev *mdev = &dev->mt76;
805 struct mt76_txwi_cache *txwi;
808 count = FIELD_GET(MT_TX_FREE_MSDU_ID_CNT, le16_to_cpu(free->ctrl));
809 for (i = 0; i < count; i++) {
810 spin_lock_bh(&dev->token_lock);
811 txwi = idr_remove(&dev->token, le16_to_cpu(free->token[i]));
812 spin_unlock_bh(&dev->token_lock);
817 mt7615_txp_skb_unmap(mdev, txwi);
819 mt76_tx_complete_skb(mdev, txwi->skb);
823 mt76_put_txwi(mdev, txwi);
828 void mt7615_mac_work(struct work_struct *work)
830 struct mt7615_dev *dev;
832 dev = (struct mt7615_dev *)container_of(work, struct mt76_dev,
835 mt76_tx_status_check(&dev->mt76, NULL, false);
836 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mt76.mac_work,
837 MT7615_WATCHDOG_TIME);
840 int mt7615_dfs_stop_radar_detector(struct mt7615_dev *dev)
842 struct cfg80211_chan_def *chandef = &dev->mt76.chandef;
845 err = mt7615_mcu_rdd_cmd(dev, RDD_STOP, MT_HW_RDD0,
850 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
851 chandef->width == NL80211_CHAN_WIDTH_80P80)
852 err = mt7615_mcu_rdd_cmd(dev, RDD_STOP, MT_HW_RDD1,
857 static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain)
861 err = mt7615_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0);
865 return mt7615_mcu_rdd_cmd(dev, RDD_DET_MODE, chain,
869 int mt7615_dfs_start_radar_detector(struct mt7615_dev *dev)
871 struct cfg80211_chan_def *chandef = &dev->mt76.chandef;
875 err = mt7615_mcu_rdd_cmd(dev, RDD_CAC_START, MT_HW_RDD0,
880 /* TODO: DBDC support */
882 err = mt7615_dfs_start_rdd(dev, MT_HW_RDD0);
886 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
887 chandef->width == NL80211_CHAN_WIDTH_80P80) {
888 err = mt7615_dfs_start_rdd(dev, MT_HW_RDD1);
896 int mt7615_dfs_init_radar_detector(struct mt7615_dev *dev)
898 struct cfg80211_chan_def *chandef = &dev->mt76.chandef;
901 if (dev->mt76.region == NL80211_DFS_UNSET)
904 if (test_bit(MT76_SCANNING, &dev->mt76.state))
907 if (dev->dfs_state == chandef->chan->dfs_state)
910 dev->dfs_state = chandef->chan->dfs_state;
912 if (chandef->chan->flags & IEEE80211_CHAN_RADAR) {
913 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE)
914 return mt7615_dfs_start_radar_detector(dev);
916 return mt7615_mcu_rdd_cmd(dev, RDD_CAC_END, MT_HW_RDD0,
919 err = mt7615_mcu_rdd_cmd(dev, RDD_NORMAL_START,
920 MT_HW_RDD0, MT_RX_SEL0, 0);
924 return mt7615_dfs_stop_radar_detector(dev);