1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2019 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * Roy Luo <royluo@google.com>
6 * Felix Fietkau <nbd@nbd.name>
7 * Lorenzo Bianconi <lorenzo@kernel.org>
10 #include <linux/etherdevice.h>
11 #include <linux/timekeeping.h>
16 static inline s8 to_rssi(u32 field, u32 rxv)
18 return (FIELD_GET(field, rxv) - 220) / 2;
21 static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev,
24 struct mt7615_sta *sta;
25 struct mt76_wcid *wcid;
27 if (idx >= ARRAY_SIZE(dev->mt76.wcid))
30 wcid = rcu_dereference(dev->mt76.wcid[idx]);
37 sta = container_of(wcid, struct mt7615_sta, wcid);
41 return &sta->vif->sta.wcid;
44 int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb)
46 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
47 struct ieee80211_supported_band *sband;
48 struct ieee80211_hdr *hdr;
49 __le32 *rxd = (__le32 *)skb->data;
50 u32 rxd0 = le32_to_cpu(rxd[0]);
51 u32 rxd1 = le32_to_cpu(rxd[1]);
52 u32 rxd2 = le32_to_cpu(rxd[2]);
53 bool unicast, remove_pad, insert_ccmp_hdr = false;
56 if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state))
59 memset(status, 0, sizeof(*status));
61 unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M;
62 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
63 status->wcid = mt7615_rx_get_wcid(dev, idx, unicast);
65 /* TODO: properly support DBDC */
66 status->freq = dev->mt76.chandef.chan->center_freq;
67 status->band = dev->mt76.chandef.chan->band;
68 if (status->band == NL80211_BAND_5GHZ)
69 sband = &dev->mt76.sband_5g.sband;
71 sband = &dev->mt76.sband_2g.sband;
73 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
74 status->flag |= RX_FLAG_FAILED_FCS_CRC;
76 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
77 status->flag |= RX_FLAG_MMIC_ERROR;
79 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
80 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
81 status->flag |= RX_FLAG_DECRYPTED;
82 status->flag |= RX_FLAG_IV_STRIPPED;
83 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
86 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
88 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
95 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
97 if ((u8 *)rxd - skb->data >= skb->len)
101 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
102 u8 *data = (u8 *)rxd;
104 if (status->flag & RX_FLAG_DECRYPTED) {
105 status->iv[0] = data[5];
106 status->iv[1] = data[4];
107 status->iv[2] = data[3];
108 status->iv[3] = data[2];
109 status->iv[4] = data[1];
110 status->iv[5] = data[0];
112 insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
115 if ((u8 *)rxd - skb->data >= skb->len)
119 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
121 if ((u8 *)rxd - skb->data >= skb->len)
125 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
126 u32 rxdg0 = le32_to_cpu(rxd[0]);
127 u32 rxdg1 = le32_to_cpu(rxd[1]);
128 u32 rxdg3 = le32_to_cpu(rxd[3]);
129 u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
132 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
133 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
134 case MT_PHY_TYPE_CCK:
137 case MT_PHY_TYPE_OFDM:
138 i = mt76_get_rate(&dev->mt76, sband, i, cck);
140 case MT_PHY_TYPE_HT_GF:
142 status->encoding = RX_ENC_HT;
146 case MT_PHY_TYPE_VHT:
147 status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1;
148 status->encoding = RX_ENC_VHT;
153 status->rate_idx = i;
155 switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) {
159 status->bw = RATE_INFO_BW_40;
162 status->bw = RATE_INFO_BW_80;
165 status->bw = RATE_INFO_BW_160;
171 if (rxdg0 & MT_RXV1_HT_SHORT_GI)
172 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
173 if (rxdg0 & MT_RXV1_HT_AD_CODE)
174 status->enc_flags |= RX_ENC_FLAG_LDPC;
176 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
178 status->chains = dev->mt76.antenna_mask;
179 status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3);
180 status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3);
181 status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3);
182 status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3);
183 status->signal = status->chain_signal[0];
185 for (i = 1; i < hweight8(dev->mt76.antenna_mask); i++) {
186 if (!(status->chains & BIT(i)))
189 status->signal = max(status->signal,
190 status->chain_signal[i]);
194 if ((u8 *)rxd - skb->data >= skb->len)
198 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
200 if (insert_ccmp_hdr) {
201 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
203 mt76_insert_ccmp_hdr(skb, key_id);
206 hdr = (struct ieee80211_hdr *)skb->data;
207 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
210 status->aggr = unicast &&
211 !ieee80211_is_qos_nullfunc(hdr->frame_control);
212 status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK;
213 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
218 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
222 void mt7615_tx_complete_skb(struct mt76_dev *mdev, enum mt76_txq_id qid,
223 struct mt76_queue_entry *e)
226 dev_kfree_skb_any(e->skb);
231 if (e->skb == DMA_DUMMY_DATA) {
232 struct mt76_txwi_cache *t;
233 struct mt7615_dev *dev;
234 struct mt7615_txp *txp;
237 txwi_ptr = mt76_get_txwi_ptr(mdev, e->txwi);
238 txp = (struct mt7615_txp *)(txwi_ptr + MT_TXD_SIZE);
239 dev = container_of(mdev, struct mt7615_dev, mt76);
241 spin_lock_bh(&dev->token_lock);
242 t = idr_remove(&dev->token, le16_to_cpu(txp->token));
243 spin_unlock_bh(&dev->token_lock);
244 e->skb = t ? t->skb : NULL;
248 mt76_tx_complete_skb(mdev, e->skb);
252 mt7615_mac_tx_rate_val(struct mt7615_dev *dev,
253 const struct ieee80211_tx_rate *rate,
256 u8 phy, nss, rate_idx;
261 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
262 rate_idx = ieee80211_rate_get_vht_mcs(rate);
263 nss = ieee80211_rate_get_vht_nss(rate);
264 phy = MT_PHY_TYPE_VHT;
265 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
267 else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
269 else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
271 } else if (rate->flags & IEEE80211_TX_RC_MCS) {
272 rate_idx = rate->idx;
273 nss = 1 + (rate->idx >> 3);
274 phy = MT_PHY_TYPE_HT;
275 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
276 phy = MT_PHY_TYPE_HT_GF;
277 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
280 const struct ieee80211_rate *r;
281 int band = dev->mt76.chandef.chan->band;
285 r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx];
286 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
287 val = r->hw_value_short;
292 rate_idx = val & 0xff;
295 if (stbc && nss == 1) {
297 rateval |= MT_TX_RATE_STBC;
300 rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
301 FIELD_PREP(MT_TX_RATE_MODE, phy) |
302 FIELD_PREP(MT_TX_RATE_NSS, nss - 1));
307 int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi,
308 struct sk_buff *skb, struct mt76_wcid *wcid,
309 struct ieee80211_sta *sta, int pid,
310 struct ieee80211_key_conf *key)
312 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
313 struct ieee80211_tx_rate *rate = &info->control.rates[0];
314 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
315 struct ieee80211_vif *vif = info->control.vif;
317 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0;
318 __le16 fc = hdr->frame_control;
323 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
325 omac_idx = mvif->omac_idx;
329 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
331 tx_count = msta->rate_count;
334 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
335 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
337 if (ieee80211_is_data(fc) || ieee80211_is_bufferable_mmpdu(fc)) {
338 q_idx = skb_get_queue_mapping(skb);
339 p_fmt = MT_TX_TYPE_CT;
340 } else if (ieee80211_is_beacon(fc)) {
341 q_idx = MT_LMAC_BCN0;
342 p_fmt = MT_TX_TYPE_FW;
344 q_idx = MT_LMAC_ALTX0;
345 p_fmt = MT_TX_TYPE_CT;
348 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
349 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) |
350 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
351 txwi[0] = cpu_to_le32(val);
353 val = MT_TXD1_LONG_FORMAT |
354 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
355 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
356 FIELD_PREP(MT_TXD1_HDR_INFO,
357 ieee80211_get_hdrlen_from_skb(skb) / 2) |
358 FIELD_PREP(MT_TXD1_TID,
359 skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
360 FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) |
361 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
362 txwi[1] = cpu_to_le32(val);
364 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
365 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
366 FIELD_PREP(MT_TXD2_MULTICAST,
367 is_multicast_ether_addr(hdr->addr1));
368 txwi[2] = cpu_to_le32(val);
370 if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
371 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
376 if (rate->idx >= 0 && rate->count &&
377 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
378 bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
380 u16 rateval = mt7615_mac_tx_rate_val(dev, rate, stbc, &bw);
382 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
384 val = MT_TXD6_FIXED_BW |
385 FIELD_PREP(MT_TXD6_BW, bw) |
386 FIELD_PREP(MT_TXD6_TX_RATE, rateval);
387 txwi[6] |= cpu_to_le32(val);
389 if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
390 txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
392 if (info->flags & IEEE80211_TX_CTL_LDPC)
393 txwi[6] |= cpu_to_le32(MT_TXD6_LDPC);
395 if (!(rate->flags & (IEEE80211_TX_RC_MCS |
396 IEEE80211_TX_RC_VHT_MCS)))
397 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
399 tx_count = rate->count;
402 if (!ieee80211_is_beacon(fc)) {
403 val = MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT |
404 FIELD_PREP(MT_TXD5_PID, pid);
405 txwi[5] = cpu_to_le32(val);
408 /* use maximum tx count for beacons */
412 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count);
413 if (ieee80211_is_data_qos(hdr->frame_control)) {
414 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
415 val |= MT_TXD3_SN_VALID;
416 } else if (ieee80211_is_back_req(hdr->frame_control)) {
417 struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data;
419 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(bar->start_seq_num));
420 val |= MT_TXD3_SN_VALID;
422 val |= FIELD_PREP(MT_TXD3_SEQ, seqno);
424 txwi[3] = cpu_to_le32(val);
426 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
427 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK);
430 txwi[3] |= cpu_to_le32(MT_TXD3_PROTECT_FRAME);
432 txwi[7] = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
433 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype);
438 void mt7615_txp_skb_unmap(struct mt76_dev *dev,
439 struct mt76_txwi_cache *t)
441 struct mt7615_txp *txp;
445 txwi = mt76_get_txwi_ptr(dev, t);
446 txp = (struct mt7615_txp *)(txwi + MT_TXD_SIZE);
447 for (i = 1; i < txp->nbuf; i++)
448 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]),
449 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE);
452 void mt7615_mac_set_rates(struct mt7615_dev *dev, struct mt7615_sta *sta,
453 struct ieee80211_tx_rate *probe_rate,
454 struct ieee80211_tx_rate *rates)
456 struct ieee80211_tx_rate *ref;
457 int wcid = sta->wcid.idx;
458 u32 addr = MT_WTBL_BASE + wcid * MT_WTBL_ENTRY_SIZE;
460 int n_rates = sta->n_rates;
461 u8 bw, bw_prev, bw_idx = 0;
468 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
471 for (i = n_rates; i < 4; i++)
472 rates[i] = rates[n_rates - 1];
474 rateset = !(sta->rate_set_tsf & BIT(0));
475 memcpy(sta->rateset[rateset].rates, rates,
476 sizeof(sta->rateset[rateset].rates));
478 sta->rateset[rateset].probe_rate = *probe_rate;
479 ref = &sta->rateset[rateset].probe_rate;
481 sta->rateset[rateset].probe_rate.idx = -1;
482 ref = &sta->rateset[rateset].rates[0];
485 rates = sta->rateset[rateset].rates;
486 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) {
488 * We don't support switching between short and long GI
489 * within the rate set. For accurate tx status reporting, we
490 * need to make sure that flags match.
491 * For improved performance, avoid duplicate entries by
492 * decrementing the MCS index if necessary
494 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI)
495 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI;
497 for (k = 0; k < i; k++) {
498 if (rates[i].idx != rates[k].idx)
500 if ((rates[i].flags ^ rates[k].flags) &
501 (IEEE80211_TX_RC_40_MHZ_WIDTH |
502 IEEE80211_TX_RC_80_MHZ_WIDTH |
503 IEEE80211_TX_RC_160_MHZ_WIDTH))
511 val[0] = mt7615_mac_tx_rate_val(dev, &rates[0], stbc, &bw);
515 probe_val = mt7615_mac_tx_rate_val(dev, probe_rate, stbc, &bw);
524 val[1] = mt7615_mac_tx_rate_val(dev, &rates[1], stbc, &bw);
530 val[2] = mt7615_mac_tx_rate_val(dev, &rates[2], stbc, &bw);
536 val[3] = mt7615_mac_tx_rate_val(dev, &rates[3], stbc, &bw);
540 w27 = mt76_rr(dev, addr + 27 * 4);
541 w27 &= ~MT_WTBL_W27_CC_BW_SEL;
542 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, bw);
544 w5 = mt76_rr(dev, addr + 5 * 4);
545 w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE |
546 MT_WTBL_W5_MPDU_OK_COUNT |
547 MT_WTBL_W5_MPDU_FAIL_COUNT |
548 MT_WTBL_W5_RATE_IDX);
549 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, bw) |
550 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE, bw_idx ? bw_idx - 1 : 7);
552 mt76_wr(dev, MT_WTBL_RIUCR0, w5);
554 mt76_wr(dev, MT_WTBL_RIUCR1,
555 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, probe_val) |
556 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) |
557 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[1]));
559 mt76_wr(dev, MT_WTBL_RIUCR2,
560 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[1] >> 8) |
561 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) |
562 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[2]) |
563 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2]));
565 mt76_wr(dev, MT_WTBL_RIUCR3,
566 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) |
567 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[3]) |
568 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3]));
570 mt76_wr(dev, MT_WTBL_UPDATE,
571 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
572 MT_WTBL_UPDATE_RATE_UPDATE |
573 MT_WTBL_UPDATE_TX_COUNT_CLEAR);
575 mt76_wr(dev, addr + 27 * 4, w27);
577 mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */
578 sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset;
580 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
581 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
583 sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates;
584 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
586 int mt7615_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
587 enum mt76_txq_id qid, struct mt76_wcid *wcid,
588 struct ieee80211_sta *sta,
589 struct mt76_tx_info *tx_info)
591 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data;
592 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
593 struct mt7615_sta *msta = container_of(wcid, struct mt7615_sta, wcid);
594 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
595 struct ieee80211_key_conf *key = info->control.hw_key;
596 struct ieee80211_vif *vif = info->control.vif;
597 int i, pid, id, nbuf = tx_info->nbuf - 1;
598 u8 *txwi = (u8 *)txwi_ptr;
599 struct mt76_txwi_cache *t;
600 struct mt7615_txp *txp;
603 wcid = &dev->mt76.global_wcid;
605 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
607 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) {
608 spin_lock_bh(&dev->mt76.lock);
609 mt7615_mac_set_rates(dev, msta, &info->control.rates[0],
611 msta->rate_probe = true;
612 spin_unlock_bh(&dev->mt76.lock);
615 mt7615_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, sta,
618 txp = (struct mt7615_txp *)(txwi + MT_TXD_SIZE);
619 for (i = 0; i < nbuf; i++) {
620 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr);
621 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len);
625 /* pass partial skb header to fw */
626 tx_info->buf[1].len = MT_CT_PARSE_LEN;
627 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
629 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD);
632 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME);
634 if (ieee80211_is_mgmt(hdr->frame_control))
635 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME);
638 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
640 txp->bss_idx = mvif->idx;
643 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size);
644 t->skb = tx_info->skb;
646 spin_lock_bh(&dev->token_lock);
647 id = idr_alloc(&dev->token, t, 0, MT7615_TOKEN_SIZE, GFP_ATOMIC);
648 spin_unlock_bh(&dev->token_lock);
652 txp->token = cpu_to_le16(id);
653 txp->rept_wds_wcid = 0xff;
654 tx_info->skb = DMA_DUMMY_DATA;
659 static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta,
660 struct ieee80211_tx_info *info, __le32 *txs_data)
662 struct ieee80211_supported_band *sband;
663 struct mt7615_rate_set *rs;
664 int first_idx = 0, last_idx;
666 bool fixed_rate, ack_timeout;
667 bool probe, ampdu, cck = false;
670 u32 final_rate, final_rate_flags, final_nss, txs;
672 fixed_rate = info->status.rates[0].count;
673 probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
675 txs = le32_to_cpu(txs_data[1]);
676 ampdu = !fixed_rate && (txs & MT_TXS1_AMPDU);
678 txs = le32_to_cpu(txs_data[3]);
679 count = FIELD_GET(MT_TXS3_TX_COUNT, txs);
680 last_idx = FIELD_GET(MT_TXS3_LAST_TX_RATE, txs);
682 txs = le32_to_cpu(txs_data[0]);
683 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
684 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
686 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
689 if (txs & MT_TXS0_QUEUE_TIMEOUT)
693 info->flags |= IEEE80211_TX_STAT_ACK;
695 info->status.ampdu_len = 1;
696 info->status.ampdu_ack_len = !!(info->flags &
697 IEEE80211_TX_STAT_ACK);
699 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
700 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
702 first_idx = max_t(int, 0, last_idx - (count + 1) / MT7615_RATE_RETRY);
704 if (fixed_rate && !probe) {
705 info->status.rates[0].count = count;
710 rate_set_tsf = READ_ONCE(sta->rate_set_tsf);
711 rs_idx = !((u32)(FIELD_GET(MT_TXS4_F0_TIMESTAMP, le32_to_cpu(txs_data[4])) -
712 rate_set_tsf) < 1000000);
713 rs_idx ^= rate_set_tsf & BIT(0);
714 rs = &sta->rateset[rs_idx];
716 if (!first_idx && rs->probe_rate.idx >= 0) {
717 info->status.rates[0] = rs->probe_rate;
719 spin_lock_bh(&dev->mt76.lock);
720 if (sta->rate_probe) {
721 mt7615_mac_set_rates(dev, sta, NULL, sta->rates);
722 sta->rate_probe = false;
724 spin_unlock_bh(&dev->mt76.lock);
726 info->status.rates[0] = rs->rates[first_idx / 2];
727 info->status.rates[0].count = 0;
729 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) {
730 struct ieee80211_tx_rate *cur_rate;
733 cur_rate = &rs->rates[idx / 2];
734 cur_count = min_t(int, MT7615_RATE_RETRY, count);
737 if (idx && (cur_rate->idx != info->status.rates[i].idx ||
738 cur_rate->flags != info->status.rates[i].flags)) {
740 if (i == ARRAY_SIZE(info->status.rates))
743 info->status.rates[i] = *cur_rate;
744 info->status.rates[i].count = 0;
747 info->status.rates[i].count += cur_count;
751 final_rate_flags = info->status.rates[i].flags;
753 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
754 case MT_PHY_TYPE_CCK:
757 case MT_PHY_TYPE_OFDM:
758 if (dev->mt76.chandef.chan->band == NL80211_BAND_5GHZ)
759 sband = &dev->mt76.sband_5g.sband;
761 sband = &dev->mt76.sband_2g.sband;
762 final_rate &= MT_TX_RATE_IDX;
763 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate,
765 final_rate_flags = 0;
767 case MT_PHY_TYPE_HT_GF:
769 final_rate_flags |= IEEE80211_TX_RC_MCS;
770 final_rate &= MT_TX_RATE_IDX;
774 case MT_PHY_TYPE_VHT:
775 final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate);
777 if ((final_rate & MT_TX_RATE_STBC) && final_nss)
780 final_rate_flags |= IEEE80211_TX_RC_VHT_MCS;
781 final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4);
787 info->status.rates[i].idx = final_rate;
788 info->status.rates[i].flags = final_rate_flags;
793 static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev,
794 struct mt7615_sta *sta, int pid,
797 struct mt76_dev *mdev = &dev->mt76;
798 struct sk_buff_head list;
801 if (pid < MT_PACKET_ID_FIRST)
804 mt76_tx_status_lock(mdev, &list);
805 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
807 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
809 if (!mt7615_fill_txs(dev, sta, info, txs_data)) {
810 ieee80211_tx_info_clear_status(info);
811 info->status.rates[0].idx = -1;
814 mt76_tx_status_skb_done(mdev, skb, &list);
816 mt76_tx_status_unlock(mdev, &list);
821 void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data)
823 struct ieee80211_tx_info info = {};
824 struct ieee80211_sta *sta = NULL;
825 struct mt7615_sta *msta = NULL;
826 struct mt76_wcid *wcid;
827 __le32 *txs_data = data;
832 txs = le32_to_cpu(txs_data[0]);
833 pid = FIELD_GET(MT_TXS0_PID, txs);
834 txs = le32_to_cpu(txs_data[2]);
835 wcidx = FIELD_GET(MT_TXS2_WCID, txs);
837 if (pid == MT_PACKET_ID_NO_ACK)
840 if (wcidx >= ARRAY_SIZE(dev->mt76.wcid))
845 wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
849 msta = container_of(wcid, struct mt7615_sta, wcid);
850 sta = wcid_to_sta(wcid);
852 if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data))
855 if (wcidx >= MT7615_WTBL_STA || !sta)
858 if (mt7615_fill_txs(dev, msta, &info, txs_data))
859 ieee80211_tx_status_noskb(mt76_hw(dev), sta, &info);
865 void mt7615_mac_tx_free(struct mt7615_dev *dev, struct sk_buff *skb)
867 struct mt7615_tx_free *free = (struct mt7615_tx_free *)skb->data;
868 struct mt76_dev *mdev = &dev->mt76;
869 struct mt76_txwi_cache *txwi;
872 count = FIELD_GET(MT_TX_FREE_MSDU_ID_CNT, le16_to_cpu(free->ctrl));
873 for (i = 0; i < count; i++) {
874 spin_lock_bh(&dev->token_lock);
875 txwi = idr_remove(&dev->token, le16_to_cpu(free->token[i]));
876 spin_unlock_bh(&dev->token_lock);
881 mt7615_txp_skb_unmap(mdev, txwi);
883 mt76_tx_complete_skb(mdev, txwi->skb);
887 mt76_put_txwi(mdev, txwi);
892 void mt7615_mac_work(struct work_struct *work)
894 struct mt7615_dev *dev;
896 dev = (struct mt7615_dev *)container_of(work, struct mt76_dev,
899 mt76_tx_status_check(&dev->mt76, NULL, false);
900 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mt76.mac_work,
901 MT7615_WATCHDOG_TIME);
904 int mt7615_dfs_stop_radar_detector(struct mt7615_dev *dev)
906 struct cfg80211_chan_def *chandef = &dev->mt76.chandef;
909 err = mt7615_mcu_rdd_cmd(dev, RDD_STOP, MT_HW_RDD0,
914 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
915 chandef->width == NL80211_CHAN_WIDTH_80P80)
916 err = mt7615_mcu_rdd_cmd(dev, RDD_STOP, MT_HW_RDD1,
921 static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain)
925 err = mt7615_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0);
929 return mt7615_mcu_rdd_cmd(dev, RDD_DET_MODE, chain,
933 int mt7615_dfs_start_radar_detector(struct mt7615_dev *dev)
935 struct cfg80211_chan_def *chandef = &dev->mt76.chandef;
939 err = mt7615_mcu_rdd_cmd(dev, RDD_CAC_START, MT_HW_RDD0,
944 /* TODO: DBDC support */
946 err = mt7615_dfs_start_rdd(dev, MT_HW_RDD0);
950 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
951 chandef->width == NL80211_CHAN_WIDTH_80P80) {
952 err = mt7615_dfs_start_rdd(dev, MT_HW_RDD1);
960 int mt7615_dfs_init_radar_detector(struct mt7615_dev *dev)
962 struct cfg80211_chan_def *chandef = &dev->mt76.chandef;
965 if (dev->mt76.region == NL80211_DFS_UNSET)
968 if (test_bit(MT76_SCANNING, &dev->mt76.state))
971 if (dev->dfs_state == chandef->chan->dfs_state)
974 dev->dfs_state = chandef->chan->dfs_state;
976 if (chandef->chan->flags & IEEE80211_CHAN_RADAR) {
977 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE)
978 return mt7615_dfs_start_radar_detector(dev);
980 return mt7615_mcu_rdd_cmd(dev, RDD_CAC_END, MT_HW_RDD0,
983 err = mt7615_mcu_rdd_cmd(dev, RDD_NORMAL_START,
984 MT_HW_RDD0, MT_RX_SEL0, 0);
988 return mt7615_dfs_stop_radar_detector(dev);