2 * (c) Copyright 2002-2010, Ralink Technology, Inc.
3 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
4 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
5 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2
9 * as published by the Free Software Foundation
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
21 #include "../mt76x02_util.h"
22 #include "../mt76x02_dma.h"
26 static void mt76x0_vht_cap_mask(struct ieee80211_supported_band *sband)
28 struct ieee80211_sta_vht_cap *vht_cap = &sband->vht_cap;
32 vht_cap->cap &= ~IEEE80211_VHT_CAP_RXLDPC;
33 for (i = 0; i < 8; i++) {
35 mcs_map |= (IEEE80211_VHT_MCS_SUPPORT_0_7 << (i * 2));
38 (IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2));
40 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
41 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
45 mt76x0_set_wlan_state(struct mt76x0_dev *dev, u32 val, bool enable)
47 u32 mask = MT_CMB_CTRL_XTAL_RDY | MT_CMB_CTRL_PLL_LD;
49 /* Note: we don't turn off WLAN_CLK because that makes the device
50 * not respond properly on the probe path.
51 * In case anyone (PSM?) wants to use this function we can
52 * bring the clock stuff back and fixup the probe path.
56 val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
57 MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
59 val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN);
61 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
64 /* Note: vendor driver tries to disable/enable wlan here and retry
65 * but the code which does it is so buggy it must have never
66 * triggered, so don't bother.
68 if (enable && !mt76_poll(dev, MT_CMB_CTRL, mask, mask, 2000))
69 dev_err(dev->mt76.dev, "PLL and XTAL check failed\n");
72 void mt76x0_chip_onoff(struct mt76x0_dev *dev, bool enable, bool reset)
76 val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
79 val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN;
80 val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
82 if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
83 val |= (MT_WLAN_FUN_CTRL_WLAN_RESET |
84 MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
85 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
88 val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET |
89 MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
93 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
96 mt76x0_set_wlan_state(dev, val, enable);
98 EXPORT_SYMBOL_GPL(mt76x0_chip_onoff);
100 static void mt76x0_reset_csr_bbp(struct mt76x0_dev *dev)
102 mt76_wr(dev, MT_MAC_SYS_CTRL,
103 MT_MAC_SYS_CTRL_RESET_CSR |
104 MT_MAC_SYS_CTRL_RESET_BBP);
106 mt76_clear(dev, MT_MAC_SYS_CTRL,
107 MT_MAC_SYS_CTRL_RESET_CSR |
108 MT_MAC_SYS_CTRL_RESET_BBP);
111 #define RANDOM_WRITE(dev, tab) \
112 mt76_wr_rp(dev, MT_MCU_MEMMAP_WLAN, \
113 tab, ARRAY_SIZE(tab))
115 static int mt76x0_init_bbp(struct mt76x0_dev *dev)
119 ret = mt76x0_wait_bbp_ready(dev);
123 RANDOM_WRITE(dev, mt76x0_bbp_init_tab);
125 for (i = 0; i < ARRAY_SIZE(mt76x0_bbp_switch_tab); i++) {
126 const struct mt76x0_bbp_switch_item *item = &mt76x0_bbp_switch_tab[i];
127 const struct mt76_reg_pair *pair = &item->reg_pair;
129 if (((RF_G_BAND | RF_BW_20) & item->bw_band) == (RF_G_BAND | RF_BW_20))
130 mt76_wr(dev, pair->reg, pair->value);
133 RANDOM_WRITE(dev, mt76x0_dcoc_tab);
138 static void mt76x0_init_mac_registers(struct mt76x0_dev *dev)
142 RANDOM_WRITE(dev, common_mac_reg_table);
144 mt76x02_set_beacon_offsets(&dev->mt76);
146 /* Enable PBF and MAC clock SYS_CTRL[11:10] = 0x3 */
147 RANDOM_WRITE(dev, mt76x0_mac_reg_table);
149 /* Release BBP and MAC reset MAC_SYS_CTRL[1:0] = 0x0 */
150 reg = mt76_rr(dev, MT_MAC_SYS_CTRL);
152 mt76_wr(dev, MT_MAC_SYS_CTRL, reg);
154 /* Set 0x141C[15:12]=0xF */
155 reg = mt76_rr(dev, MT_EXT_CCA_CFG);
157 mt76_wr(dev, MT_EXT_CCA_CFG, reg);
159 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
162 TxRing 9 is for Mgmt frame.
163 TxRing 8 is for In-band command frame.
164 WMM_RG0_TXQMA: This register setting is for FCE to define the rule of TxRing 9.
165 WMM_RG1_TXQMA: This register setting is for FCE to define the rule of TxRing 8.
167 reg = mt76_rr(dev, MT_WMM_CTRL);
170 mt76_wr(dev, MT_WMM_CTRL, reg);
173 static int mt76x0_init_wcid_mem(struct mt76x0_dev *dev)
178 vals = kmalloc(sizeof(*vals) * MT76_N_WCIDS * 2, GFP_KERNEL);
182 for (i = 0; i < MT76_N_WCIDS; i++) {
183 vals[i * 2] = 0xffffffff;
184 vals[i * 2 + 1] = 0x00ffffff;
187 mt76_wr_copy(dev, MT_WCID_ADDR_BASE, vals, MT76_N_WCIDS * 2);
192 static void mt76x0_init_key_mem(struct mt76x0_dev *dev)
196 mt76_wr_copy(dev, MT_SKEY_MODE_BASE_0, vals, ARRAY_SIZE(vals));
199 static int mt76x0_init_wcid_attr_mem(struct mt76x0_dev *dev)
204 vals = kmalloc(sizeof(*vals) * MT76_N_WCIDS * 2, GFP_KERNEL);
208 for (i = 0; i < MT76_N_WCIDS * 2; i++)
211 mt76_wr_copy(dev, MT_WCID_ATTR_BASE, vals, MT76_N_WCIDS * 2);
216 static void mt76x0_reset_counters(struct mt76x0_dev *dev)
218 mt76_rr(dev, MT_RX_STAT_0);
219 mt76_rr(dev, MT_RX_STAT_1);
220 mt76_rr(dev, MT_RX_STAT_2);
221 mt76_rr(dev, MT_TX_STA_0);
222 mt76_rr(dev, MT_TX_STA_1);
223 mt76_rr(dev, MT_TX_STA_2);
226 int mt76x0_mac_start(struct mt76x0_dev *dev)
228 mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
230 if (!mt76x02_wait_for_wpdma(&dev->mt76, 200000))
233 mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter);
234 mt76_wr(dev, MT_MAC_SYS_CTRL,
235 MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX);
237 return !mt76x02_wait_for_wpdma(&dev->mt76, 50) ? -ETIMEDOUT : 0;
239 EXPORT_SYMBOL_GPL(mt76x0_mac_start);
241 void mt76x0_mac_stop(struct mt76x0_dev *dev)
245 /* Page count on TxQ */
246 while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) ||
247 (mt76_rr(dev, 0x0a30) & 0x000000ff) ||
248 (mt76_rr(dev, 0x0a34) & 0x00ff00ff)))
251 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000))
252 dev_warn(dev->mt76.dev, "Warning: MAC TX did not stop!\n");
254 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX |
255 MT_MAC_SYS_CTRL_ENABLE_TX);
257 /* Page count on RxQ */
258 for (i = 0; i < 200; i++) {
259 if (!(mt76_rr(dev, MT_RXQ_STA) & 0x00ff0000) &&
260 !mt76_rr(dev, 0x0a30) &&
261 !mt76_rr(dev, 0x0a34)) {
269 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000))
270 dev_warn(dev->mt76.dev, "Warning: MAC RX did not stop!\n");
272 EXPORT_SYMBOL_GPL(mt76x0_mac_stop);
274 int mt76x0_init_hardware(struct mt76x0_dev *dev)
278 if (!mt76x02_wait_for_wpdma(&dev->mt76, 1000))
281 /* Wait for ASIC ready after FW load. */
282 if (!mt76x02_wait_for_mac(&dev->mt76))
285 mt76x0_reset_csr_bbp(dev);
286 ret = mt76x02_mcu_function_select(&dev->mt76, Q_SELECT, 1, false);
290 mt76x0_init_mac_registers(dev);
292 if (!mt76x02_wait_for_txrx_idle(&dev->mt76))
295 ret = mt76x0_init_bbp(dev);
299 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
301 ret = mt76x0_init_wcid_mem(dev);
305 mt76x0_init_key_mem(dev);
307 ret = mt76x0_init_wcid_attr_mem(dev);
311 mt76_clear(dev, MT_BEACON_TIME_CFG, (MT_BEACON_TIME_CFG_TIMER_EN |
312 MT_BEACON_TIME_CFG_SYNC_MODE |
313 MT_BEACON_TIME_CFG_TBTT_EN |
314 MT_BEACON_TIME_CFG_BEACON_TX));
316 mt76x0_reset_counters(dev);
318 ret = mt76x0_eeprom_init(dev);
322 mt76x0_phy_init(dev);
326 EXPORT_SYMBOL_GPL(mt76x0_init_hardware);
329 mt76x0_alloc_device(struct device *pdev,
330 const struct mt76_driver_ops *drv_ops,
331 const struct ieee80211_ops *ops)
333 struct mt76x0_dev *dev;
334 struct mt76_dev *mdev;
336 mdev = mt76_alloc_device(sizeof(*dev), ops);
343 dev = container_of(mdev, struct mt76x0_dev, mt76);
344 mutex_init(&dev->reg_atomic_mutex);
345 atomic_set(&dev->avg_ampdu_len, 1);
349 EXPORT_SYMBOL_GPL(mt76x0_alloc_device);
351 int mt76x0_register_device(struct mt76x0_dev *dev)
353 struct mt76_dev *mdev = &dev->mt76;
354 struct ieee80211_hw *hw = mdev->hw;
355 struct wiphy *wiphy = hw->wiphy;
358 /* Reserve WCID 0 for mcast - thanks to this APs WCID will go to
359 * entry no. 1 like it does in the vendor driver.
361 mdev->wcid_mask[0] |= 1;
363 /* init fake wcid for monitor interfaces */
364 mdev->global_wcid.idx = 0xff;
365 mdev->global_wcid.hw_key_idx = -1;
367 /* init antenna configuration */
368 mdev->antenna_mask = 1;
372 hw->max_report_rates = 7;
373 hw->max_rate_tries = 1;
374 hw->extra_tx_headroom = sizeof(struct mt76x02_txwi) + 4 + 2;
376 hw->sta_data_size = sizeof(struct mt76x02_sta);
377 hw->vif_data_size = sizeof(struct mt76x02_vif);
379 wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
381 INIT_DELAYED_WORK(&dev->mac_work, mt76x0_mac_work);
383 ret = mt76_register_device(mdev, true, mt76x02_rates,
384 ARRAY_SIZE(mt76x02_rates));
388 /* overwrite unsupported features */
389 if (mdev->cap.has_5ghz)
390 mt76x0_vht_cap_mask(&dev->mt76.sband_5g.sband);
392 mt76x0_init_debugfs(dev);
396 EXPORT_SYMBOL_GPL(mt76x0_register_device);