2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <asm/unaligned.h>
19 #include "mt76x2_eeprom.h"
21 #define EE_FIELD(_name, _value) [MT_EE_##_name] = (_value) | 1
24 mt76x2_eeprom_copy(struct mt76x2_dev *dev, enum mt76x02_eeprom_field field,
27 if (field + len > dev->mt76.eeprom.size)
30 memcpy(dest, dev->mt76.eeprom.data + field, len);
35 mt76x2_eeprom_get_macaddr(struct mt76x2_dev *dev)
37 void *src = dev->mt76.eeprom.data + MT_EE_MAC_ADDR;
39 memcpy(dev->mt76.macaddr, src, ETH_ALEN);
44 mt76x2_has_cal_free_data(struct mt76x2_dev *dev, u8 *efuse)
46 u16 *efuse_w = (u16 *) efuse;
48 if (efuse_w[MT_EE_NIC_CONF_0] != 0)
51 if (efuse_w[MT_EE_XTAL_TRIM_1] == 0xffff)
54 if (efuse_w[MT_EE_TX_POWER_DELTA_BW40] != 0)
57 if (efuse_w[MT_EE_TX_POWER_0_START_2G] == 0xffff)
60 if (efuse_w[MT_EE_TX_POWER_0_GRP3_TX_POWER_DELTA] != 0)
63 if (efuse_w[MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE] == 0xffff)
70 mt76x2_apply_cal_free_data(struct mt76x2_dev *dev, u8 *efuse)
72 #define GROUP_5G(_id) \
73 MT_EE_TX_POWER_0_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id), \
74 MT_EE_TX_POWER_0_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id) + 1, \
75 MT_EE_TX_POWER_1_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id), \
76 MT_EE_TX_POWER_1_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id) + 1
78 static const u8 cal_free_bytes[] = {
80 MT_EE_TX_POWER_EXT_PA_5G + 1,
81 MT_EE_TX_POWER_0_START_2G,
82 MT_EE_TX_POWER_0_START_2G + 1,
83 MT_EE_TX_POWER_1_START_2G,
84 MT_EE_TX_POWER_1_START_2G + 1,
91 MT_EE_RF_2G_TSSI_OFF_TXPOWER,
92 MT_EE_RF_2G_RX_HIGH_GAIN + 1,
93 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN,
94 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN + 1,
95 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN,
96 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN + 1,
97 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN,
98 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN + 1,
100 u8 *eeprom = dev->mt76.eeprom.data;
102 eeprom[MT_EE_TX_POWER_0_START_5G],
103 eeprom[MT_EE_TX_POWER_0_START_5G + 1],
104 eeprom[MT_EE_TX_POWER_1_START_5G],
105 eeprom[MT_EE_TX_POWER_1_START_5G + 1]
110 if (!mt76x2_has_cal_free_data(dev, efuse))
113 for (i = 0; i < ARRAY_SIZE(cal_free_bytes); i++) {
114 int offset = cal_free_bytes[i];
116 eeprom[offset] = efuse[offset];
119 if (!(efuse[MT_EE_TX_POWER_0_START_5G] |
120 efuse[MT_EE_TX_POWER_0_START_5G + 1]))
121 memcpy(eeprom + MT_EE_TX_POWER_0_START_5G, prev_grp0, 2);
122 if (!(efuse[MT_EE_TX_POWER_1_START_5G] |
123 efuse[MT_EE_TX_POWER_1_START_5G + 1]))
124 memcpy(eeprom + MT_EE_TX_POWER_1_START_5G, prev_grp0 + 2, 2);
126 val = get_unaligned_le16(efuse + MT_EE_BT_RCAL_RESULT);
128 eeprom[MT_EE_BT_RCAL_RESULT] = val & 0xff;
130 val = get_unaligned_le16(efuse + MT_EE_BT_VCDL_CALIBRATION);
132 eeprom[MT_EE_BT_VCDL_CALIBRATION + 1] = val >> 8;
134 val = get_unaligned_le16(efuse + MT_EE_BT_PMUCFG);
136 eeprom[MT_EE_BT_PMUCFG] = val & 0xff;
139 static int mt76x2_check_eeprom(struct mt76x2_dev *dev)
141 u16 val = get_unaligned_le16(dev->mt76.eeprom.data);
144 val = get_unaligned_le16(dev->mt76.eeprom.data + MT_EE_PCI_ID);
151 dev_err(dev->mt76.dev, "EEPROM data check failed: %04x\n", val);
157 mt76x2_eeprom_load(struct mt76x2_dev *dev)
163 ret = mt76_eeprom_init(&dev->mt76, MT7662_EEPROM_SIZE);
169 found = !mt76x2_check_eeprom(dev);
171 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, MT7662_EEPROM_SIZE,
173 dev->mt76.otp.size = MT7662_EEPROM_SIZE;
174 if (!dev->mt76.otp.data)
177 efuse = dev->mt76.otp.data;
179 if (mt76x02_get_efuse_data(&dev->mt76, 0, efuse,
180 MT7662_EEPROM_SIZE, MT_EE_READ))
184 mt76x2_apply_cal_free_data(dev, efuse);
186 /* FIXME: check if efuse data is complete */
188 memcpy(dev->mt76.eeprom.data, efuse, MT7662_EEPROM_SIZE);
199 mt76x2_sign_extend_optional(u32 val, unsigned int size)
201 bool enable = val & BIT(size);
203 return enable ? mt76x02_sign_extend(val, size) : 0;
207 mt76x2_set_rx_gain_group(struct mt76x2_dev *dev, u8 val)
209 s8 *dest = dev->cal.rx.high_gain;
211 if (!mt76x02_field_valid(val)) {
217 dest[0] = mt76x02_sign_extend(val, 4);
218 dest[1] = mt76x02_sign_extend(val >> 4, 4);
222 mt76x2_set_rssi_offset(struct mt76x2_dev *dev, int chain, u8 val)
224 s8 *dest = dev->cal.rx.rssi_offset;
226 if (!mt76x02_field_valid(val)) {
231 dest[chain] = mt76x2_sign_extend_optional(val, 7);
234 static enum mt76x2_cal_channel_group
235 mt76x2_get_cal_channel_group(int channel)
237 if (channel >= 184 && channel <= 196)
238 return MT_CH_5G_JAPAN;
240 return MT_CH_5G_UNII_1;
242 return MT_CH_5G_UNII_2;
244 return MT_CH_5G_UNII_2E_1;
246 return MT_CH_5G_UNII_2E_2;
247 return MT_CH_5G_UNII_3;
251 mt76x2_get_5g_rx_gain(struct mt76x2_dev *dev, u8 channel)
253 enum mt76x2_cal_channel_group group;
255 group = mt76x2_get_cal_channel_group(channel);
258 return mt76x02_eeprom_get(&dev->mt76,
259 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN);
260 case MT_CH_5G_UNII_1:
261 return mt76x02_eeprom_get(&dev->mt76,
262 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN) >> 8;
263 case MT_CH_5G_UNII_2:
264 return mt76x02_eeprom_get(&dev->mt76,
265 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN);
266 case MT_CH_5G_UNII_2E_1:
267 return mt76x02_eeprom_get(&dev->mt76,
268 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN) >> 8;
269 case MT_CH_5G_UNII_2E_2:
270 return mt76x02_eeprom_get(&dev->mt76,
271 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN);
273 return mt76x02_eeprom_get(&dev->mt76,
274 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN) >> 8;
278 void mt76x2_read_rx_gain(struct mt76x2_dev *dev)
280 struct ieee80211_channel *chan = dev->mt76.chandef.chan;
281 int channel = chan->hw_value;
282 s8 lna_5g[3], lna_2g;
286 if (chan->band == NL80211_BAND_2GHZ)
287 val = mt76x02_eeprom_get(&dev->mt76,
288 MT_EE_RF_2G_RX_HIGH_GAIN) >> 8;
290 val = mt76x2_get_5g_rx_gain(dev, channel);
292 mt76x2_set_rx_gain_group(dev, val);
294 mt76x02_get_rx_gain(&dev->mt76, chan->band, &val, &lna_2g, lna_5g);
295 mt76x2_set_rssi_offset(dev, 0, val);
296 mt76x2_set_rssi_offset(dev, 1, val >> 8);
298 dev->cal.rx.mcu_gain = (lna_2g & 0xff);
299 dev->cal.rx.mcu_gain |= (lna_5g[0] & 0xff) << 8;
300 dev->cal.rx.mcu_gain |= (lna_5g[1] & 0xff) << 16;
301 dev->cal.rx.mcu_gain |= (lna_5g[2] & 0xff) << 24;
303 lna = mt76x02_get_lna_gain(&dev->mt76, &lna_2g, lna_5g, chan);
304 dev->cal.rx.lna_gain = mt76x02_sign_extend(lna, 8);
306 EXPORT_SYMBOL_GPL(mt76x2_read_rx_gain);
309 mt76x2_rate_power_val(u8 val)
311 if (!mt76x02_field_valid(val))
314 return mt76x2_sign_extend_optional(val, 7);
317 void mt76x2_get_rate_power(struct mt76x2_dev *dev, struct mt76_rate_power *t,
318 struct ieee80211_channel *chan)
323 is_5ghz = chan->band == NL80211_BAND_5GHZ;
325 memset(t, 0, sizeof(*t));
327 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_CCK);
328 t->cck[0] = t->cck[1] = mt76x2_rate_power_val(val);
329 t->cck[2] = t->cck[3] = mt76x2_rate_power_val(val >> 8);
332 val = mt76x02_eeprom_get(&dev->mt76,
333 MT_EE_TX_POWER_OFDM_5G_6M);
335 val = mt76x02_eeprom_get(&dev->mt76,
336 MT_EE_TX_POWER_OFDM_2G_6M);
337 t->ofdm[0] = t->ofdm[1] = mt76x2_rate_power_val(val);
338 t->ofdm[2] = t->ofdm[3] = mt76x2_rate_power_val(val >> 8);
341 val = mt76x02_eeprom_get(&dev->mt76,
342 MT_EE_TX_POWER_OFDM_5G_24M);
344 val = mt76x02_eeprom_get(&dev->mt76,
345 MT_EE_TX_POWER_OFDM_2G_24M);
346 t->ofdm[4] = t->ofdm[5] = mt76x2_rate_power_val(val);
347 t->ofdm[6] = t->ofdm[7] = mt76x2_rate_power_val(val >> 8);
349 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_HT_MCS0);
350 t->ht[0] = t->ht[1] = mt76x2_rate_power_val(val);
351 t->ht[2] = t->ht[3] = mt76x2_rate_power_val(val >> 8);
353 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_HT_MCS4);
354 t->ht[4] = t->ht[5] = mt76x2_rate_power_val(val);
355 t->ht[6] = t->ht[7] = mt76x2_rate_power_val(val >> 8);
357 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_HT_MCS8);
358 t->ht[8] = t->ht[9] = mt76x2_rate_power_val(val);
359 t->ht[10] = t->ht[11] = mt76x2_rate_power_val(val >> 8);
361 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_HT_MCS12);
362 t->ht[12] = t->ht[13] = mt76x2_rate_power_val(val);
363 t->ht[14] = t->ht[15] = mt76x2_rate_power_val(val >> 8);
365 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_VHT_MCS0);
366 t->vht[0] = t->vht[1] = mt76x2_rate_power_val(val);
367 t->vht[2] = t->vht[3] = mt76x2_rate_power_val(val >> 8);
369 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_VHT_MCS4);
370 t->vht[4] = t->vht[5] = mt76x2_rate_power_val(val);
371 t->vht[6] = t->vht[7] = mt76x2_rate_power_val(val >> 8);
373 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_VHT_MCS8);
376 t->vht[8] = t->vht[9] = mt76x2_rate_power_val(val >> 8);
378 memcpy(t->stbc, t->ht, sizeof(t->stbc[0]) * 8);
379 t->stbc[8] = t->vht[8];
380 t->stbc[9] = t->vht[9];
382 EXPORT_SYMBOL_GPL(mt76x2_get_rate_power);
384 int mt76x2_get_max_rate_power(struct mt76_rate_power *r)
389 for (i = 0; i < sizeof(r->all); i++)
390 ret = max(ret, r->all[i]);
394 EXPORT_SYMBOL_GPL(mt76x2_get_max_rate_power);
397 mt76x2_get_power_info_2g(struct mt76x2_dev *dev, struct mt76x2_tx_power_info *t,
398 struct ieee80211_channel *chan, int chain, int offset)
400 int channel = chan->hw_value;
407 else if (channel < 11)
412 mt76x2_eeprom_copy(dev, offset, data, sizeof(data));
414 t->chain[chain].tssi_slope = data[0];
415 t->chain[chain].tssi_offset = data[1];
416 t->chain[chain].target_power = data[2];
417 t->chain[chain].delta = mt76x2_sign_extend_optional(data[delta_idx], 7);
419 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_RF_2G_TSSI_OFF_TXPOWER);
420 t->target_power = val >> 8;
424 mt76x2_get_power_info_5g(struct mt76x2_dev *dev, struct mt76x2_tx_power_info *t,
425 struct ieee80211_channel *chan, int chain, int offset)
427 int channel = chan->hw_value;
428 enum mt76x2_cal_channel_group group;
433 group = mt76x2_get_cal_channel_group(channel);
434 offset += group * MT_TX_POWER_GROUP_SIZE_5G;
438 else if (channel >= 184)
440 else if (channel < 44)
442 else if (channel < 52)
444 else if (channel < 58)
446 else if (channel < 98)
448 else if (channel < 106)
450 else if (channel < 116)
452 else if (channel < 130)
454 else if (channel < 149)
456 else if (channel < 157)
461 mt76x2_eeprom_copy(dev, offset, data, sizeof(data));
463 t->chain[chain].tssi_slope = data[0];
464 t->chain[chain].tssi_offset = data[1];
465 t->chain[chain].target_power = data[2];
466 t->chain[chain].delta = mt76x2_sign_extend_optional(data[delta_idx], 7);
468 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_RF_2G_RX_HIGH_GAIN);
469 t->target_power = val & 0xff;
472 void mt76x2_get_power_info(struct mt76x2_dev *dev,
473 struct mt76x2_tx_power_info *t,
474 struct ieee80211_channel *chan)
478 memset(t, 0, sizeof(*t));
480 bw40 = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_DELTA_BW40);
481 bw80 = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_DELTA_BW80);
483 if (chan->band == NL80211_BAND_5GHZ) {
485 mt76x2_get_power_info_5g(dev, t, chan, 0,
486 MT_EE_TX_POWER_0_START_5G);
487 mt76x2_get_power_info_5g(dev, t, chan, 1,
488 MT_EE_TX_POWER_1_START_5G);
490 mt76x2_get_power_info_2g(dev, t, chan, 0,
491 MT_EE_TX_POWER_0_START_2G);
492 mt76x2_get_power_info_2g(dev, t, chan, 1,
493 MT_EE_TX_POWER_1_START_2G);
496 if (mt76x2_tssi_enabled(dev) ||
497 !mt76x02_field_valid(t->target_power))
498 t->target_power = t->chain[0].target_power;
500 t->delta_bw40 = mt76x2_rate_power_val(bw40);
501 t->delta_bw80 = mt76x2_rate_power_val(bw80);
503 EXPORT_SYMBOL_GPL(mt76x2_get_power_info);
505 int mt76x2_get_temp_comp(struct mt76x2_dev *dev, struct mt76x2_temp_comp *t)
507 enum nl80211_band band = dev->mt76.chandef.chan->band;
511 memset(t, 0, sizeof(*t));
513 if (!mt76x2_temp_tx_alc_enabled(dev))
516 if (!mt76x02_ext_pa_enabled(&dev->mt76, band))
519 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_EXT_PA_5G) >> 8;
520 t->temp_25_ref = val & 0x7f;
521 if (band == NL80211_BAND_5GHZ) {
522 slope = mt76x02_eeprom_get(&dev->mt76,
523 MT_EE_RF_TEMP_COMP_SLOPE_5G);
524 bounds = mt76x02_eeprom_get(&dev->mt76,
525 MT_EE_TX_POWER_EXT_PA_5G);
527 slope = mt76x02_eeprom_get(&dev->mt76,
528 MT_EE_RF_TEMP_COMP_SLOPE_2G);
529 bounds = mt76x02_eeprom_get(&dev->mt76,
530 MT_EE_TX_POWER_DELTA_BW80) >> 8;
533 t->high_slope = slope & 0xff;
534 t->low_slope = slope >> 8;
535 t->lower_bound = 0 - (bounds & 0xf);
536 t->upper_bound = (bounds >> 4) & 0xf;
540 EXPORT_SYMBOL_GPL(mt76x2_get_temp_comp);
542 int mt76x2_eeprom_init(struct mt76x2_dev *dev)
546 ret = mt76x2_eeprom_load(dev);
550 mt76x02_eeprom_parse_hw_cap(&dev->mt76);
551 mt76x2_eeprom_get_macaddr(dev);
552 mt76_eeprom_override(&dev->mt76);
553 dev->mt76.macaddr[0] &= ~BIT(1);
557 EXPORT_SYMBOL_GPL(mt76x2_eeprom_init);
559 MODULE_LICENSE("Dual BSD/GPL");