drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c

   1 /*
   2  * RTL8XXXU mac80211 USB driver - 8192e specific subdriver
   3  *
   4  * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
   5  *
   6  * Portions, notably calibration code:
   7  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   8  *
   9  * This driver was written as a replacement for the vendor provided
  10  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  11  * their programming interface, I have started adding support for
  12  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of version 2 of the GNU General Public License as
  16  * published by the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  21  * more details.
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/errno.h>
  28 #include <linux/slab.h>
  29 #include <linux/module.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/list.h>
  32 #include <linux/usb.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/wireless.h>
  37 #include <linux/firmware.h>
  38 #include <linux/moduleparam.h>
  39 #include <net/mac80211.h>
  40 #include "rtl8xxxu.h"
  41 #include "rtl8xxxu_regs.h"
  42
  43 static struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = {
  44         {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7},
  45         {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00},
  46         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
  47         {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
  48         {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
  49         {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
  50         {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
  51         {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
  52         {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
  53         {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
  54         {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff},
  55         {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f},
  56         {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e},
  57         {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e},
  58         {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00},
  59         {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a},
  60         {0x525, 0x4f}, {0x540, 0x12}, {0x541, 0x64}, {0x550, 0x10},
  61         {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, {0x55d, 0xff},
  62         {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, {0x620, 0xff},
  63         {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff},
  64         {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50},
  65         {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e},
  66         {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8},
  67         {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65},
  68         {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65},
  69         {0x70b, 0x87},
  70         {0xffff, 0xff},
  71 };
  72
  73 static struct rtl8xxxu_reg32val rtl8192eu_phy_init_table[] = {
  74         {0x800, 0x80040000}, {0x804, 0x00000003},
  75         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
  76         {0x810, 0x10001331}, {0x814, 0x020c3d10},
  77         {0x818, 0x02220385}, {0x81c, 0x00000000},
  78         {0x820, 0x01000100}, {0x824, 0x00390204},
  79         {0x828, 0x01000100}, {0x82c, 0x00390204},
  80         {0x830, 0x32323232}, {0x834, 0x30303030},
  81         {0x838, 0x30303030}, {0x83c, 0x30303030},
  82         {0x840, 0x00010000}, {0x844, 0x00010000},
  83         {0x848, 0x28282828}, {0x84c, 0x28282828},
  84         {0x850, 0x00000000}, {0x854, 0x00000000},
  85         {0x858, 0x009a009a}, {0x85c, 0x01000014},
  86         {0x860, 0x66f60000}, {0x864, 0x061f0000},
  87         {0x868, 0x30303030}, {0x86c, 0x30303030},
  88         {0x870, 0x00000000}, {0x874, 0x55004200},
  89         {0x878, 0x08080808}, {0x87c, 0x00000000},
  90         {0x880, 0xb0000c1c}, {0x884, 0x00000001},
  91         {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
  92         {0x890, 0x00000800}, {0x894, 0xfffffffe},
  93         {0x898, 0x40302010}, {0x900, 0x00000000},
  94         {0x904, 0x00000023}, {0x908, 0x00000000},
  95         {0x90c, 0x81121313}, {0x910, 0x806c0001},
  96         {0x914, 0x00000001}, {0x918, 0x00000000},
  97         {0x91c, 0x00010000}, {0x924, 0x00000001},
  98         {0x928, 0x00000000}, {0x92c, 0x00000000},
  99         {0x930, 0x00000000}, {0x934, 0x00000000},
 100         {0x938, 0x00000000}, {0x93c, 0x00000000},
 101         {0x940, 0x00000000}, {0x944, 0x00000000},
 102         {0x94c, 0x00000008}, {0xa00, 0x00d0c7c8},
 103         {0xa04, 0x81ff000c}, {0xa08, 0x8c838300},
 104         {0xa0c, 0x2e68120f}, {0xa10, 0x95009b78},
 105         {0xa14, 0x1114d028}, {0xa18, 0x00881117},
 106         {0xa1c, 0x89140f00}, {0xa20, 0x1a1b0000},
 107         {0xa24, 0x090e1317}, {0xa28, 0x00000204},
 108         {0xa2c, 0x00d30000}, {0xa70, 0x101fff00},
 109         {0xa74, 0x00000007}, {0xa78, 0x00000900},
 110         {0xa7c, 0x225b0606}, {0xa80, 0x218075b1},
 111         {0xb38, 0x00000000}, {0xc00, 0x48071d40},
 112         {0xc04, 0x03a05633}, {0xc08, 0x000000e4},
 113         {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
 114         {0xc14, 0x40000100}, {0xc18, 0x08800000},
 115         {0xc1c, 0x40000100}, {0xc20, 0x00000000},
 116         {0xc24, 0x00000000}, {0xc28, 0x00000000},
 117         {0xc2c, 0x00000000}, {0xc30, 0x69e9ac47},
 118         {0xc34, 0x469652af}, {0xc38, 0x49795994},
 119         {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
 120         {0xc44, 0x000100b7}, {0xc48, 0xec020107},
 121         {0xc4c, 0x007f037f},
 122 #ifdef EXT_PA_8192EU
 123         /* External PA or external LNA */
 124         {0xc50, 0x00340220},
 125 #else
 126         {0xc50, 0x00340020},
 127 #endif
 128         {0xc54, 0x0080801f},
 129 #ifdef EXT_PA_8192EU
 130         /* External PA or external LNA */
 131         {0xc58, 0x00000220},
 132 #else
 133         {0xc58, 0x00000020},
 134 #endif
 135         {0xc5c, 0x00248492}, {0xc60, 0x00000000},
 136         {0xc64, 0x7112848b}, {0xc68, 0x47c00bff},
 137         {0xc6c, 0x00000036}, {0xc70, 0x00000600},
 138         {0xc74, 0x02013169}, {0xc78, 0x0000001f},
 139         {0xc7c, 0x00b91612},
 140 #ifdef EXT_PA_8192EU
 141         /* External PA or external LNA */
 142         {0xc80, 0x2d4000b5},
 143 #else
 144         {0xc80, 0x40000100},
 145 #endif
 146         {0xc84, 0x21f60000},
 147 #ifdef EXT_PA_8192EU
 148         /* External PA or external LNA */
 149         {0xc88, 0x2d4000b5},
 150 #else
 151         {0xc88, 0x40000100},
 152 #endif
 153         {0xc8c, 0xa0e40000}, {0xc90, 0x00121820},
 154         {0xc94, 0x00000000}, {0xc98, 0x00121820},
 155         {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
 156         {0xca4, 0x000300a0}, {0xca8, 0x00000000},
 157         {0xcac, 0x00000000}, {0xcb0, 0x00000000},
 158         {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
 159         {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
 160         {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
 161         {0xccc, 0x00000000}, {0xcd0, 0x00000000},
 162         {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
 163         {0xcdc, 0x00766932}, {0xce0, 0x00222222},
 164         {0xce4, 0x00040000}, {0xce8, 0x77644302},
 165         {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
 166         {0xd04, 0x00020403}, {0xd08, 0x0000907f},
 167         {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
 168         {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
 169         {0xd1c, 0x0000007f}, {0xd2c, 0xcc979975},
 170         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 171         {0xd38, 0x00000000}, {0xd3c, 0x00127353},
 172         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 173         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 174         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 175         {0xd58, 0x00000282}, {0xd5c, 0x30032064},
 176         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 177         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 178         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 179         {0xd78, 0x000e3c24}, {0xd80, 0x01081008},
 180         {0xd84, 0x00000800}, {0xd88, 0xf0b50000},
 181         {0xe00, 0x30303030}, {0xe04, 0x30303030},
 182         {0xe08, 0x03903030}, {0xe10, 0x30303030},
 183         {0xe14, 0x30303030}, {0xe18, 0x30303030},
 184         {0xe1c, 0x30303030}, {0xe28, 0x00000000},
 185         {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
 186         {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
 187         {0xe40, 0x01007c00}, {0xe44, 0x01004800},
 188         {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
 189         {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
 190         {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
 191         {0xe60, 0x00000008}, {0xe68, 0x0fc05656},
 192         {0xe6c, 0x03c09696}, {0xe70, 0x03c09696},
 193         {0xe74, 0x0c005656}, {0xe78, 0x0c005656},
 194         {0xe7c, 0x0c005656}, {0xe80, 0x0c005656},
 195         {0xe84, 0x03c09696}, {0xe88, 0x0c005656},
 196         {0xe8c, 0x03c09696}, {0xed0, 0x03c09696},
 197         {0xed4, 0x03c09696}, {0xed8, 0x03c09696},
 198         {0xedc, 0x0000d6d6}, {0xee0, 0x0000d6d6},
 199         {0xeec, 0x0fc01616}, {0xee4, 0xb0000c1c},
 200         {0xee8, 0x00000001}, {0xf14, 0x00000003},
 201         {0xf4c, 0x00000000}, {0xf00, 0x00000300},
 202         {0xffff, 0xffffffff},
 203 };
 204
 205 static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table[] = {
 206         {0xc78, 0xfb000001}, {0xc78, 0xfb010001},
 207         {0xc78, 0xfb020001}, {0xc78, 0xfb030001},
 208         {0xc78, 0xfb040001}, {0xc78, 0xfb050001},
 209         {0xc78, 0xfa060001}, {0xc78, 0xf9070001},
 210         {0xc78, 0xf8080001}, {0xc78, 0xf7090001},
 211         {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001},
 212         {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001},
 213         {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001},
 214         {0xc78, 0xf0100001}, {0xc78, 0xef110001},
 215         {0xc78, 0xee120001}, {0xc78, 0xed130001},
 216         {0xc78, 0xec140001}, {0xc78, 0xeb150001},
 217         {0xc78, 0xea160001}, {0xc78, 0xe9170001},
 218         {0xc78, 0xe8180001}, {0xc78, 0xe7190001},
 219         {0xc78, 0xc81a0001}, {0xc78, 0xc71b0001},
 220         {0xc78, 0xc61c0001}, {0xc78, 0x071d0001},
 221         {0xc78, 0x061e0001}, {0xc78, 0x051f0001},
 222         {0xc78, 0x04200001}, {0xc78, 0x03210001},
 223         {0xc78, 0xaa220001}, {0xc78, 0xa9230001},
 224         {0xc78, 0xa8240001}, {0xc78, 0xa7250001},
 225         {0xc78, 0xa6260001}, {0xc78, 0x85270001},
 226         {0xc78, 0x84280001}, {0xc78, 0x83290001},
 227         {0xc78, 0x252a0001}, {0xc78, 0x242b0001},
 228         {0xc78, 0x232c0001}, {0xc78, 0x222d0001},
 229         {0xc78, 0x672e0001}, {0xc78, 0x662f0001},
 230         {0xc78, 0x65300001}, {0xc78, 0x64310001},
 231         {0xc78, 0x63320001}, {0xc78, 0x62330001},
 232         {0xc78, 0x61340001}, {0xc78, 0x45350001},
 233         {0xc78, 0x44360001}, {0xc78, 0x43370001},
 234         {0xc78, 0x42380001}, {0xc78, 0x41390001},
 235         {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
 236         {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
 237         {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
 238         {0xc78, 0xfb400001}, {0xc78, 0xfb410001},
 239         {0xc78, 0xfb420001}, {0xc78, 0xfb430001},
 240         {0xc78, 0xfb440001}, {0xc78, 0xfb450001},
 241         {0xc78, 0xfa460001}, {0xc78, 0xf9470001},
 242         {0xc78, 0xf8480001}, {0xc78, 0xf7490001},
 243         {0xc78, 0xf64a0001}, {0xc78, 0xf54b0001},
 244         {0xc78, 0xf44c0001}, {0xc78, 0xf34d0001},
 245         {0xc78, 0xf24e0001}, {0xc78, 0xf14f0001},
 246         {0xc78, 0xf0500001}, {0xc78, 0xef510001},
 247         {0xc78, 0xee520001}, {0xc78, 0xed530001},
 248         {0xc78, 0xec540001}, {0xc78, 0xeb550001},
 249         {0xc78, 0xea560001}, {0xc78, 0xe9570001},
 250         {0xc78, 0xe8580001}, {0xc78, 0xe7590001},
 251         {0xc78, 0xe65a0001}, {0xc78, 0xe55b0001},
 252         {0xc78, 0xe45c0001}, {0xc78, 0xe35d0001},
 253         {0xc78, 0xe25e0001}, {0xc78, 0xe15f0001},
 254         {0xc78, 0x8a600001}, {0xc78, 0x89610001},
 255         {0xc78, 0x88620001}, {0xc78, 0x87630001},
 256         {0xc78, 0x86640001}, {0xc78, 0x85650001},
 257         {0xc78, 0x84660001}, {0xc78, 0x83670001},
 258         {0xc78, 0x82680001}, {0xc78, 0x6b690001},
 259         {0xc78, 0x6a6a0001}, {0xc78, 0x696b0001},
 260         {0xc78, 0x686c0001}, {0xc78, 0x676d0001},
 261         {0xc78, 0x666e0001}, {0xc78, 0x656f0001},
 262         {0xc78, 0x64700001}, {0xc78, 0x63710001},
 263         {0xc78, 0x62720001}, {0xc78, 0x61730001},
 264         {0xc78, 0x49740001}, {0xc78, 0x48750001},
 265         {0xc78, 0x47760001}, {0xc78, 0x46770001},
 266         {0xc78, 0x45780001}, {0xc78, 0x44790001},
 267         {0xc78, 0x437a0001}, {0xc78, 0x427b0001},
 268         {0xc78, 0x417c0001}, {0xc78, 0x407d0001},
 269         {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
 270         {0xc50, 0x00040022}, {0xc50, 0x00040020},
 271         {0xffff, 0xffffffff}
 272 };
 273
 274 static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table[] = {
 275         {0xc78, 0xfa000001}, {0xc78, 0xf9010001},
 276         {0xc78, 0xf8020001}, {0xc78, 0xf7030001},
 277         {0xc78, 0xf6040001}, {0xc78, 0xf5050001},
 278         {0xc78, 0xf4060001}, {0xc78, 0xf3070001},
 279         {0xc78, 0xf2080001}, {0xc78, 0xf1090001},
 280         {0xc78, 0xf00a0001}, {0xc78, 0xef0b0001},
 281         {0xc78, 0xee0c0001}, {0xc78, 0xed0d0001},
 282         {0xc78, 0xec0e0001}, {0xc78, 0xeb0f0001},
 283         {0xc78, 0xea100001}, {0xc78, 0xe9110001},
 284         {0xc78, 0xe8120001}, {0xc78, 0xe7130001},
 285         {0xc78, 0xe6140001}, {0xc78, 0xe5150001},
 286         {0xc78, 0xe4160001}, {0xc78, 0xe3170001},
 287         {0xc78, 0xe2180001}, {0xc78, 0xe1190001},
 288         {0xc78, 0x8a1a0001}, {0xc78, 0x891b0001},
 289         {0xc78, 0x881c0001}, {0xc78, 0x871d0001},
 290         {0xc78, 0x861e0001}, {0xc78, 0x851f0001},
 291         {0xc78, 0x84200001}, {0xc78, 0x83210001},
 292         {0xc78, 0x82220001}, {0xc78, 0x6a230001},
 293         {0xc78, 0x69240001}, {0xc78, 0x68250001},
 294         {0xc78, 0x67260001}, {0xc78, 0x66270001},
 295         {0xc78, 0x65280001}, {0xc78, 0x64290001},
 296         {0xc78, 0x632a0001}, {0xc78, 0x622b0001},
 297         {0xc78, 0x612c0001}, {0xc78, 0x602d0001},
 298         {0xc78, 0x472e0001}, {0xc78, 0x462f0001},
 299         {0xc78, 0x45300001}, {0xc78, 0x44310001},
 300         {0xc78, 0x43320001}, {0xc78, 0x42330001},
 301         {0xc78, 0x41340001}, {0xc78, 0x40350001},
 302         {0xc78, 0x40360001}, {0xc78, 0x40370001},
 303         {0xc78, 0x40380001}, {0xc78, 0x40390001},
 304         {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
 305         {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
 306         {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
 307         {0xc78, 0xfa400001}, {0xc78, 0xf9410001},
 308         {0xc78, 0xf8420001}, {0xc78, 0xf7430001},
 309         {0xc78, 0xf6440001}, {0xc78, 0xf5450001},
 310         {0xc78, 0xf4460001}, {0xc78, 0xf3470001},
 311         {0xc78, 0xf2480001}, {0xc78, 0xf1490001},
 312         {0xc78, 0xf04a0001}, {0xc78, 0xef4b0001},
 313         {0xc78, 0xee4c0001}, {0xc78, 0xed4d0001},
 314         {0xc78, 0xec4e0001}, {0xc78, 0xeb4f0001},
 315         {0xc78, 0xea500001}, {0xc78, 0xe9510001},
 316         {0xc78, 0xe8520001}, {0xc78, 0xe7530001},
 317         {0xc78, 0xe6540001}, {0xc78, 0xe5550001},
 318         {0xc78, 0xe4560001}, {0xc78, 0xe3570001},
 319         {0xc78, 0xe2580001}, {0xc78, 0xe1590001},
 320         {0xc78, 0x8a5a0001}, {0xc78, 0x895b0001},
 321         {0xc78, 0x885c0001}, {0xc78, 0x875d0001},
 322         {0xc78, 0x865e0001}, {0xc78, 0x855f0001},
 323         {0xc78, 0x84600001}, {0xc78, 0x83610001},
 324         {0xc78, 0x82620001}, {0xc78, 0x6a630001},
 325         {0xc78, 0x69640001}, {0xc78, 0x68650001},
 326         {0xc78, 0x67660001}, {0xc78, 0x66670001},
 327         {0xc78, 0x65680001}, {0xc78, 0x64690001},
 328         {0xc78, 0x636a0001}, {0xc78, 0x626b0001},
 329         {0xc78, 0x616c0001}, {0xc78, 0x606d0001},
 330         {0xc78, 0x476e0001}, {0xc78, 0x466f0001},
 331         {0xc78, 0x45700001}, {0xc78, 0x44710001},
 332         {0xc78, 0x43720001}, {0xc78, 0x42730001},
 333         {0xc78, 0x41740001}, {0xc78, 0x40750001},
 334         {0xc78, 0x40760001}, {0xc78, 0x40770001},
 335         {0xc78, 0x40780001}, {0xc78, 0x40790001},
 336         {0xc78, 0x407a0001}, {0xc78, 0x407b0001},
 337         {0xc78, 0x407c0001}, {0xc78, 0x407d0001},
 338         {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
 339         {0xc50, 0x00040222}, {0xc50, 0x00040220},
 340         {0xffff, 0xffffffff}
 341 };
 342
 343 static struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = {
 344         {0x7f, 0x00000082}, {0x81, 0x0003fc00},
 345         {0x00, 0x00030000}, {0x08, 0x00008400},
 346         {0x18, 0x00000407}, {0x19, 0x00000012},
 347         {0x1b, 0x00000064}, {0x1e, 0x00080009},
 348         {0x1f, 0x00000880}, {0x2f, 0x0001a060},
 349         {0x3f, 0x00000000}, {0x42, 0x000060c0},
 350         {0x57, 0x000d0000}, {0x58, 0x000be180},
 351         {0x67, 0x00001552}, {0x83, 0x00000000},
 352         {0xb0, 0x000ff9f1}, {0xb1, 0x00055418},
 353         {0xb2, 0x0008cc00}, {0xb4, 0x00043083},
 354         {0xb5, 0x00008166}, {0xb6, 0x0000803e},
 355         {0xb7, 0x0001c69f}, {0xb8, 0x0000407f},
 356         {0xb9, 0x00080001}, {0xba, 0x00040001},
 357         {0xbb, 0x00000400}, {0xbf, 0x000c0000},
 358         {0xc2, 0x00002400}, {0xc3, 0x00000009},
 359         {0xc4, 0x00040c91}, {0xc5, 0x00099999},
 360         {0xc6, 0x000000a3}, {0xc7, 0x00088820},
 361         {0xc8, 0x00076c06}, {0xc9, 0x00000000},
 362         {0xca, 0x00080000}, {0xdf, 0x00000180},
 363         {0xef, 0x000001a0}, {0x51, 0x00069545},
 364         {0x52, 0x0007e45e}, {0x53, 0x00000071},
 365         {0x56, 0x00051ff3}, {0x35, 0x000000a8},
 366         {0x35, 0x000001e2}, {0x35, 0x000002a8},
 367         {0x36, 0x00001c24}, {0x36, 0x00009c24},
 368         {0x36, 0x00011c24}, {0x36, 0x00019c24},
 369         {0x18, 0x00000c07}, {0x5a, 0x00048000},
 370         {0x19, 0x000739d0},
 371 #ifdef EXT_PA_8192EU
 372         /* External PA or external LNA */
 373         {0x34, 0x0000a093}, {0x34, 0x0000908f},
 374         {0x34, 0x0000808c}, {0x34, 0x0000704d},
 375         {0x34, 0x0000604a}, {0x34, 0x00005047},
 376         {0x34, 0x0000400a}, {0x34, 0x00003007},
 377         {0x34, 0x00002004}, {0x34, 0x00001001},
 378         {0x34, 0x00000000},
 379 #else
 380         /* Regular */
 381         {0x34, 0x0000add7}, {0x34, 0x00009dd4},
 382         {0x34, 0x00008dd1}, {0x34, 0x00007dce},
 383         {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
 384         {0x34, 0x00004dc5}, {0x34, 0x000034cc},
 385         {0x34, 0x0000244f}, {0x34, 0x0000144c},
 386         {0x34, 0x00000014},
 387 #endif
 388         {0x00, 0x00030159},
 389         {0x84, 0x00068180},
 390         {0x86, 0x0000014e},
 391         {0x87, 0x00048e00},
 392         {0x8e, 0x00065540},
 393         {0x8f, 0x00088000},
 394         {0xef, 0x000020a0},
 395 #ifdef EXT_PA_8192EU
 396         /* External PA or external LNA */
 397         {0x3b, 0x000f07b0},
 398 #else
 399         {0x3b, 0x000f02b0},
 400 #endif
 401         {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
 402         {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
 403         {0x3b, 0x000a0080}, {0x3b, 0x00090080},
 404         {0x3b, 0x0008f780},
 405 #ifdef EXT_PA_8192EU
 406         /* External PA or external LNA */
 407         {0x3b, 0x000787b0},
 408 #else
 409         {0x3b, 0x00078730},
 410 #endif
 411         {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
 412         {0x3b, 0x00040620}, {0x3b, 0x00037090},
 413         {0x3b, 0x00020080}, {0x3b, 0x0001f060},
 414         {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
 415         {0xfe, 0x00000000}, {0x18, 0x0000fc07},
 416         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 417         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 418         {0x1e, 0x00000001}, {0x1f, 0x00080000},
 419         {0x00, 0x00033e70},
 420         {0xff, 0xffffffff}
 421 };
 422
 423 static struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table[] = {
 424         {0x7f, 0x00000082}, {0x81, 0x0003fc00},
 425         {0x00, 0x00030000}, {0x08, 0x00008400},
 426         {0x18, 0x00000407}, {0x19, 0x00000012},
 427         {0x1b, 0x00000064}, {0x1e, 0x00080009},
 428         {0x1f, 0x00000880}, {0x2f, 0x0001a060},
 429         {0x3f, 0x00000000}, {0x42, 0x000060c0},
 430         {0x57, 0x000d0000}, {0x58, 0x000be180},
 431         {0x67, 0x00001552}, {0x7f, 0x00000082},
 432         {0x81, 0x0003f000}, {0x83, 0x00000000},
 433         {0xdf, 0x00000180}, {0xef, 0x000001a0},
 434         {0x51, 0x00069545}, {0x52, 0x0007e42e},
 435         {0x53, 0x00000071}, {0x56, 0x00051ff3},
 436         {0x35, 0x000000a8}, {0x35, 0x000001e0},
 437         {0x35, 0x000002a8}, {0x36, 0x00001ca8},
 438         {0x36, 0x00009c24}, {0x36, 0x00011c24},
 439         {0x36, 0x00019c24}, {0x18, 0x00000c07},
 440         {0x5a, 0x00048000}, {0x19, 0x000739d0},
 441 #ifdef EXT_PA_8192EU
 442         /* External PA or external LNA */
 443         {0x34, 0x0000a093}, {0x34, 0x0000908f},
 444         {0x34, 0x0000808c}, {0x34, 0x0000704d},
 445         {0x34, 0x0000604a}, {0x34, 0x00005047},
 446         {0x34, 0x0000400a}, {0x34, 0x00003007},
 447         {0x34, 0x00002004}, {0x34, 0x00001001},
 448         {0x34, 0x00000000},
 449 #else
 450         {0x34, 0x0000add7}, {0x34, 0x00009dd4},
 451         {0x34, 0x00008dd1}, {0x34, 0x00007dce},
 452         {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
 453         {0x34, 0x00004dc5}, {0x34, 0x000034cc},
 454         {0x34, 0x0000244f}, {0x34, 0x0000144c},
 455         {0x34, 0x00000014},
 456 #endif
 457         {0x00, 0x00030159}, {0x84, 0x00068180},
 458         {0x86, 0x000000ce}, {0x87, 0x00048a00},
 459         {0x8e, 0x00065540}, {0x8f, 0x00088000},
 460         {0xef, 0x000020a0},
 461 #ifdef EXT_PA_8192EU
 462         /* External PA or external LNA */
 463         {0x3b, 0x000f07b0},
 464 #else
 465         {0x3b, 0x000f02b0},
 466 #endif
 467
 468         {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
 469         {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
 470         {0x3b, 0x000a0080}, {0x3b, 0x00090080},
 471         {0x3b, 0x0008f780},
 472 #ifdef EXT_PA_8192EU
 473         /* External PA or external LNA */
 474         {0x3b, 0x000787b0},
 475 #else
 476         {0x3b, 0x00078730},
 477 #endif
 478         {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
 479         {0x3b, 0x00040620}, {0x3b, 0x00037090},
 480         {0x3b, 0x00020080}, {0x3b, 0x0001f060},
 481         {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
 482         {0x00, 0x00010159}, {0xfe, 0x00000000},
 483         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 484         {0xfe, 0x00000000}, {0x1e, 0x00000001},
 485         {0x1f, 0x00080000}, {0x00, 0x00033e70},
 486         {0xff, 0xffffffff}
 487 };
 488
 489 static void
 490 rtl8192e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
 491 {
 492         u32 val32, ofdm, mcs;
 493         u8 cck, ofdmbase, mcsbase;
 494         int group, tx_idx;
 495
 496         tx_idx = 0;
 497         group = rtl8xxxu_gen2_channel_to_group(channel);
 498
 499         cck = priv->cck_tx_power_index_A[group];
 500
 501         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
 502         val32 &= 0xffff00ff;
 503         val32 |= (cck << 8);
 504         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
 505
 506         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
 507         val32 &= 0xff;
 508         val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
 509         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
 510
 511         ofdmbase = priv->ht40_1s_tx_power_index_A[group];
 512         ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a;
 513         ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
 514
 515         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
 516         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
 517
 518         mcsbase = priv->ht40_1s_tx_power_index_A[group];
 519         if (ht40)
 520                 mcsbase += priv->ht40_tx_power_diff[tx_idx++].a;
 521         else
 522                 mcsbase += priv->ht20_tx_power_diff[tx_idx++].a;
 523         mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
 524
 525         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
 526         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
 527         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs);
 528         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs);
 529
 530         if (priv->tx_paths > 1) {
 531                 cck = priv->cck_tx_power_index_B[group];
 532
 533                 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
 534                 val32 &= 0xff;
 535                 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
 536                 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
 537
 538                 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
 539                 val32 &= 0xffffff00;
 540                 val32 |= cck;
 541                 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
 542
 543                 ofdmbase = priv->ht40_1s_tx_power_index_B[group];
 544                 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
 545                 ofdm = ofdmbase | ofdmbase << 8 |
 546                         ofdmbase << 16 | ofdmbase << 24;
 547
 548                 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm);
 549                 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm);
 550
 551                 mcsbase = priv->ht40_1s_tx_power_index_B[group];
 552                 if (ht40)
 553                         mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
 554                 else
 555                         mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
 556                 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
 557
 558                 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs);
 559                 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs);
 560                 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs);
 561                 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs);
 562         }
 563 }
 564
 565 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
 566 {
 567         struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
 568         int i;
 569
 570         if (efuse->rtl_id != cpu_to_le16(0x8129))
 571                 return -EINVAL;
 572
 573         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
 574
 575         memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
 576                sizeof(efuse->tx_power_index_A.cck_base));
 577         memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
 578                sizeof(efuse->tx_power_index_B.cck_base));
 579
 580         memcpy(priv->ht40_1s_tx_power_index_A,
 581                efuse->tx_power_index_A.ht40_base,
 582                sizeof(efuse->tx_power_index_A.ht40_base));
 583         memcpy(priv->ht40_1s_tx_power_index_B,
 584                efuse->tx_power_index_B.ht40_base,
 585                sizeof(efuse->tx_power_index_B.ht40_base));
 586
 587         priv->ht20_tx_power_diff[0].a =
 588                 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
 589         priv->ht20_tx_power_diff[0].b =
 590                 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
 591
 592         priv->ht40_tx_power_diff[0].a = 0;
 593         priv->ht40_tx_power_diff[0].b = 0;
 594
 595         for (i = 1; i < RTL8723B_TX_COUNT; i++) {
 596                 priv->ofdm_tx_power_diff[i].a =
 597                         efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
 598                 priv->ofdm_tx_power_diff[i].b =
 599                         efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
 600
 601                 priv->ht20_tx_power_diff[i].a =
 602                         efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
 603                 priv->ht20_tx_power_diff[i].b =
 604                         efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
 605
 606                 priv->ht40_tx_power_diff[i].a =
 607                         efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
 608                 priv->ht40_tx_power_diff[i].b =
 609                         efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
 610         }
 611
 612         priv->has_xtalk = 1;
 613         priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f;
 614
 615         dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
 616         dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name);
 617         if (memchr_inv(efuse->serial, 0xff, 11))
 618                 dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial);
 619         else
 620                 dev_info(&priv->udev->dev, "Serial not available.\n");
 621
 622         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
 623                 unsigned char *raw = priv->efuse_wifi.raw;
 624
 625                 dev_info(&priv->udev->dev,
 626                          "%s: dumping efuse (0x%02zx bytes):\n",
 627                          __func__, sizeof(struct rtl8192eu_efuse));
 628                 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8)
 629                         dev_info(&priv->udev->dev, "%02x: %8ph\n", i, &raw[i]);
 630         }
 631         return 0;
 632 }
 633
 634 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
 635 {
 636         char *fw_name;
 637         int ret;
 638
 639         fw_name = "rtlwifi/rtl8192eu_nic.bin";
 640
 641         ret = rtl8xxxu_load_firmware(priv, fw_name);
 642
 643         return ret;
 644 }
 645
 646 static void rtl8192eu_init_phy_bb(struct rtl8xxxu_priv *priv)
 647 {
 648         u8 val8;
 649         u16 val16;
 650
 651         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
 652         val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF;
 653         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
 654
 655         /* 6. 0x1f[7:0] = 0x07 */
 656         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
 657         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
 658
 659         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
 660         val16 |= (SYS_FUNC_USBA | SYS_FUNC_USBD | SYS_FUNC_DIO_RF |
 661                   SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB);
 662         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
 663         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
 664         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
 665         rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table);
 666
 667         if (priv->hi_pa)
 668                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_highpa_table);
 669         else
 670                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_std_table);
 671 }
 672
 673 static int rtl8192eu_init_phy_rf(struct rtl8xxxu_priv *priv)
 674 {
 675         int ret;
 676
 677         ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radioa_init_table, RF_A);
 678         if (ret)
 679                 goto exit;
 680
 681         ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radiob_init_table, RF_B);
 682
 683 exit:
 684         return ret;
 685 }
 686
 687 static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv)
 688 {
 689         u32 reg_eac, reg_e94, reg_e9c;
 690         int result = 0;
 691
 692         /*
 693          * TX IQK
 694          * PA/PAD controlled by 0x0
 695          */
 696         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 697         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00180);
 698         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 699
 700         /* Path A IQK setting */
 701         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
 702         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
 703         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
 704         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 705
 706         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140303);
 707         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160000);
 708
 709         /* LO calibration setting */
 710         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
 711
 712         /* One shot, path A LOK & IQK */
 713         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
 714         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 715
 716         mdelay(10);
 717
 718         /* Check failed */
 719         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 720         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
 721         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
 722
 723         if (!(reg_eac & BIT(28)) &&
 724             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
 725             ((reg_e9c & 0x03ff0000) != 0x00420000))
 726                 result |= 0x01;
 727
 728         return result;
 729 }
 730
 731 static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
 732 {
 733         u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32;
 734         int result = 0;
 735
 736         /* Leave IQK mode */
 737         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00);
 738
 739         /* Enable path A PA in TX IQK mode */
 740         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
 741         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
 742         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
 743         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf117b);
 744
 745         /* PA/PAD control by 0x56, and set = 0x0 */
 746         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980);
 747         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000);
 748
 749         /* Enter IQK mode */
 750         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 751
 752         /* TX IQK setting */
 753         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
 754         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
 755
 756         /* path-A IQK setting */
 757         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
 758         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
 759         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
 760         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 761
 762         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
 763         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160c1f);
 764
 765         /* LO calibration setting */
 766         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
 767
 768         /* One shot, path A LOK & IQK */
 769         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
 770         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 771
 772         mdelay(10);
 773
 774         /* Check failed */
 775         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 776         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
 777         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
 778
 779         if (!(reg_eac & BIT(28)) &&
 780             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
 781             ((reg_e9c & 0x03ff0000) != 0x00420000)) {
 782                 result |= 0x01;
 783         } else {
 784                 /* PA/PAD controlled by 0x0 */
 785                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 786                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
 787                 goto out;
 788         }
 789
 790         val32 = 0x80007c00 |
 791                 (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff);
 792         rtl8xxxu_write32(priv, REG_TX_IQK, val32);
 793
 794         /* Modify RX IQK mode table */
 795         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 796
 797         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
 798         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
 799         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
 800         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ffa);
 801
 802         /* PA/PAD control by 0x56, and set = 0x0 */
 803         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980);
 804         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000);
 805
 806         /* Enter IQK mode */
 807         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 808
 809         /* IQK setting */
 810         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
 811
 812         /* Path A IQK setting */
 813         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
 814         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
 815         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
 816         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 817
 818         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
 819         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f);
 820
 821         /* LO calibration setting */
 822         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);
 823
 824         /* One shot, path A LOK & IQK */
 825         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
 826         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 827
 828         mdelay(10);
 829
 830         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 831         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
 832
 833         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 834         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
 835
 836         if (!(reg_eac & BIT(27)) &&
 837             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
 838             ((reg_eac & 0x03ff0000) != 0x00360000))
 839                 result |= 0x02;
 840         else
 841                 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
 842                          __func__);
 843
 844 out:
 845         return result;
 846 }
 847
 848 static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv)
 849 {
 850         u32 reg_eac, reg_eb4, reg_ebc;
 851         int result = 0;
 852
 853         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 854         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00180);
 855         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 856
 857         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 858         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 859
 860         /* Path B IQK setting */
 861         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
 862         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
 863         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);
 864         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 865
 866         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x821403e2);
 867         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000);
 868
 869         /* LO calibration setting */
 870         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00492911);
 871
 872         /* One shot, path A LOK & IQK */
 873         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
 874         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 875
 876         mdelay(1);
 877
 878         /* Check failed */
 879         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 880         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
 881         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
 882
 883         if (!(reg_eac & BIT(31)) &&
 884             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
 885             ((reg_ebc & 0x03ff0000) != 0x00420000))
 886                 result |= 0x01;
 887         else
 888                 dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n",
 889                          __func__);
 890
 891         return result;
 892 }
 893
 894 static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv)
 895 {
 896         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32;
 897         int result = 0;
 898
 899         /* Leave IQK mode */
 900         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 901
 902         /* Enable path A PA in TX IQK mode */
 903         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
 904         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);
 905         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);
 906         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf117b);
 907
 908         /* PA/PAD control by 0x56, and set = 0x0 */
 909         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980);
 910         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000);
 911
 912         /* Enter IQK mode */
 913         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 914
 915         /* TX IQK setting */
 916         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
 917         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
 918
 919         /* path-A IQK setting */
 920         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
 921         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
 922         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);
 923         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 924
 925         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160c1f);
 926         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160c1f);
 927
 928         /* LO calibration setting */
 929         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
 930
 931         /* One shot, path A LOK & IQK */
 932         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
 933         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 934
 935         mdelay(10);
 936
 937         /* Check failed */
 938         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 939         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
 940         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
 941
 942         if (!(reg_eac & BIT(31)) &&
 943             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
 944             ((reg_ebc & 0x03ff0000) != 0x00420000)) {
 945                 result |= 0x01;
 946         } else {
 947                 /*
 948                  * PA/PAD controlled by 0x0
 949                  * Vendor driver restores RF_A here which I believe is a bug
 950                  */
 951                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 952                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180);
 953                 goto out;
 954         }
 955
 956         val32 = 0x80007c00 |
 957                 (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff);
 958         rtl8xxxu_write32(priv, REG_TX_IQK, val32);
 959
 960         /* Modify RX IQK mode table */
 961         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 962
 963         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
 964         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);
 965         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);
 966         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ffa);
 967
 968         /* PA/PAD control by 0x56, and set = 0x0 */
 969         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980);
 970         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000);
 971
 972         /* Enter IQK mode */
 973         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 974
 975         /* IQK setting */
 976         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
 977
 978         /* Path A IQK setting */
 979         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
 980         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
 981         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
 982         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c);
 983
 984         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
 985         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f);
 986
 987         /* LO calibration setting */
 988         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);
 989
 990         /* One shot, path A LOK & IQK */
 991         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
 992         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 993
 994         mdelay(10);
 995
 996         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 997         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
 998         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
 999
1000         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1001         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180);
1002
1003         if (!(reg_eac & BIT(30)) &&
1004             ((reg_ec4 & 0x03ff0000) != 0x01320000) &&
1005             ((reg_ecc & 0x03ff0000) != 0x00360000))
1006                 result |= 0x02;
1007         else
1008                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
1009                          __func__);
1010
1011 out:
1012         return result;
1013 }
1014
1015 static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
1016                                       int result[][8], int t)
1017 {
1018         struct device *dev = &priv->udev->dev;
1019         u32 i, val32;
1020         int path_a_ok, path_b_ok;
1021         int retry = 2;
1022         const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
1023                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
1024                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
1025                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
1026                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
1027                 REG_TX_TO_TX, REG_RX_CCK,
1028                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
1029                 REG_RX_TO_RX, REG_STANDBY,
1030                 REG_SLEEP, REG_PMPD_ANAEN
1031         };
1032         const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
1033                 REG_TXPAUSE, REG_BEACON_CTRL,
1034                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
1035         };
1036         const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
1037                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
1038                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
1039                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
1040                 REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING
1041         };
1042         u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
1043         u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
1044
1045         /*
1046          * Note: IQ calibration must be performed after loading
1047          *       PHY_REG.txt , and radio_a, radio_b.txt
1048          */
1049
1050         if (t == 0) {
1051                 /* Save ADDA parameters, turn Path A ADDA on */
1052                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
1053                                    RTL8XXXU_ADDA_REGS);
1054                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
1055                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
1056                                    priv->bb_backup, RTL8XXXU_BB_REGS);
1057         }
1058
1059         rtl8xxxu_path_adda_on(priv, adda_regs, true);
1060
1061         /* MAC settings */
1062         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
1063
1064         val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
1065         val32 |= 0x0f000000;
1066         rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
1067
1068         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
1069         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
1070         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200);
1071
1072         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
1073         val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
1074         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
1075
1076         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
1077         val32 |= BIT(10);
1078         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
1079         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
1080         val32 |= BIT(10);
1081         rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
1082
1083         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1084         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
1085         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
1086
1087         for (i = 0; i < retry; i++) {
1088                 path_a_ok = rtl8192eu_iqk_path_a(priv);
1089                 if (path_a_ok == 0x01) {
1090                         val32 = rtl8xxxu_read32(priv,
1091                                                 REG_TX_POWER_BEFORE_IQK_A);
1092                         result[t][0] = (val32 >> 16) & 0x3ff;
1093                         val32 = rtl8xxxu_read32(priv,
1094                                                 REG_TX_POWER_AFTER_IQK_A);
1095                         result[t][1] = (val32 >> 16) & 0x3ff;
1096
1097                         break;
1098                 }
1099         }
1100
1101         if (!path_a_ok)
1102                 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
1103
1104         for (i = 0; i < retry; i++) {
1105                 path_a_ok = rtl8192eu_rx_iqk_path_a(priv);
1106                 if (path_a_ok == 0x03) {
1107                         val32 = rtl8xxxu_read32(priv,
1108                                                 REG_RX_POWER_BEFORE_IQK_A_2);
1109                         result[t][2] = (val32 >> 16) & 0x3ff;
1110                         val32 = rtl8xxxu_read32(priv,
1111                                                 REG_RX_POWER_AFTER_IQK_A_2);
1112                         result[t][3] = (val32 >> 16) & 0x3ff;
1113
1114                         break;
1115                 }
1116         }
1117
1118         if (!path_a_ok)
1119                 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
1120
1121         if (priv->rf_paths > 1) {
1122                 /* Path A into standby */
1123                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1124                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
1125                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1126
1127                 /* Turn Path B ADDA on */
1128                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
1129
1130                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1131                 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
1132                 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
1133
1134                 for (i = 0; i < retry; i++) {
1135                         path_b_ok = rtl8192eu_iqk_path_b(priv);
1136                         if (path_b_ok == 0x01) {
1137                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
1138                                 result[t][4] = (val32 >> 16) & 0x3ff;
1139                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
1140                                 result[t][5] = (val32 >> 16) & 0x3ff;
1141                                 break;
1142                         }
1143                 }
1144
1145                 if (!path_b_ok)
1146                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
1147
1148                 for (i = 0; i < retry; i++) {
1149                         path_b_ok = rtl8192eu_rx_iqk_path_b(priv);
1150                         if (path_b_ok == 0x03) {
1151                                 val32 = rtl8xxxu_read32(priv,
1152                                                         REG_RX_POWER_BEFORE_IQK_B_2);
1153                                 result[t][6] = (val32 >> 16) & 0x3ff;
1154                                 val32 = rtl8xxxu_read32(priv,
1155                                                         REG_RX_POWER_AFTER_IQK_B_2);
1156                                 result[t][7] = (val32 >> 16) & 0x3ff;
1157                                 break;
1158                         }
1159                 }
1160
1161                 if (!path_b_ok)
1162                         dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
1163         }
1164
1165         /* Back to BB mode, load original value */
1166         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1167
1168         if (t) {
1169                 /* Reload ADDA power saving parameters */
1170                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
1171                                       RTL8XXXU_ADDA_REGS);
1172
1173                 /* Reload MAC parameters */
1174                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
1175
1176                 /* Reload BB parameters */
1177                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
1178                                       priv->bb_backup, RTL8XXXU_BB_REGS);
1179
1180                 /* Restore RX initial gain */
1181                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1182                 val32 &= 0xffffff00;
1183                 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
1184                 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
1185
1186                 if (priv->rf_paths > 1) {
1187                         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
1188                         val32 &= 0xffffff00;
1189                         rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1190                                          val32 | 0x50);
1191                         rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1192                                          val32 | xb_agc);
1193                 }
1194
1195                 /* Load 0xe30 IQC default value */
1196                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
1197                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
1198         }
1199 }
1200
1201 static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
1202 {
1203         struct device *dev = &priv->udev->dev;
1204         int result[4][8];       /* last is final result */
1205         int i, candidate;
1206         bool path_a_ok, path_b_ok;
1207         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
1208         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1209         bool simu;
1210
1211         memset(result, 0, sizeof(result));
1212         candidate = -1;
1213
1214         path_a_ok = false;
1215         path_b_ok = false;
1216
1217         for (i = 0; i < 3; i++) {
1218                 rtl8192eu_phy_iqcalibrate(priv, result, i);
1219
1220                 if (i == 1) {
1221                         simu = rtl8xxxu_gen2_simularity_compare(priv,
1222                                                                 result, 0, 1);
1223                         if (simu) {
1224                                 candidate = 0;
1225                                 break;
1226                         }
1227                 }
1228
1229                 if (i == 2) {
1230                         simu = rtl8xxxu_gen2_simularity_compare(priv,
1231                                                                 result, 0, 2);
1232                         if (simu) {
1233                                 candidate = 0;
1234                                 break;
1235                         }
1236
1237                         simu = rtl8xxxu_gen2_simularity_compare(priv,
1238                                                                 result, 1, 2);
1239                         if (simu)
1240                                 candidate = 1;
1241                         else
1242                                 candidate = 3;
1243                 }
1244         }
1245
1246         for (i = 0; i < 4; i++) {
1247                 reg_e94 = result[i][0];
1248                 reg_e9c = result[i][1];
1249                 reg_ea4 = result[i][2];
1250                 reg_eb4 = result[i][4];
1251                 reg_ebc = result[i][5];
1252                 reg_ec4 = result[i][6];
1253         }
1254
1255         if (candidate >= 0) {
1256                 reg_e94 = result[candidate][0];
1257                 priv->rege94 =  reg_e94;
1258                 reg_e9c = result[candidate][1];
1259                 priv->rege9c = reg_e9c;
1260                 reg_ea4 = result[candidate][2];
1261                 reg_eac = result[candidate][3];
1262                 reg_eb4 = result[candidate][4];
1263                 priv->regeb4 = reg_eb4;
1264                 reg_ebc = result[candidate][5];
1265                 priv->regebc = reg_ebc;
1266                 reg_ec4 = result[candidate][6];
1267                 reg_ecc = result[candidate][7];
1268                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
1269                 dev_dbg(dev,
1270                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",
1271                         __func__, reg_e94, reg_e9c,
1272                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
1273                 path_a_ok = true;
1274                 path_b_ok = true;
1275         } else {
1276                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
1277                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
1278         }
1279
1280         if (reg_e94 && candidate >= 0)
1281                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
1282                                            candidate, (reg_ea4 == 0));
1283
1284         if (priv->rf_paths > 1)
1285                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
1286                                            candidate, (reg_ec4 == 0));
1287
1288         rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
1289                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
1290 }
1291
1292 /*
1293  * This is needed for 8723bu as well, presumable
1294  */
1295 static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv)
1296 {
1297         u8 val8;
1298         u32 val32;
1299
1300         /*
1301          * 40Mhz crystal source, MAC 0x28[2]=0
1302          */
1303         val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
1304         val8 &= 0xfb;
1305         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
1306
1307         val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);
1308         val32 &= 0xfffffc7f;
1309         rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);
1310
1311         /*
1312          * 92e AFE parameter
1313          * AFE PLL KVCO selection, MAC 0x28[6]=1
1314          */
1315         val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
1316         val8 &= 0xbf;
1317         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
1318
1319         /*
1320          * AFE PLL KVCO selection, MAC 0x78[21]=0
1321          */
1322         val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);
1323         val32 &= 0xffdfffff;
1324         rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);
1325 }
1326
1327 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
1328 {
1329         u8 val8;
1330
1331         /* Clear suspend enable and power down enable*/
1332         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1333         val8 &= ~(BIT(3) | BIT(4));
1334         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1335 }
1336
1337 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
1338 {
1339         u8 val8;
1340         u32 val32;
1341         int count, ret = 0;
1342
1343         /* disable HWPDN 0x04[15]=0*/
1344         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1345         val8 &= ~BIT(7);
1346         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1347
1348         /* disable SW LPS 0x04[10]= 0 */
1349         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1350         val8 &= ~BIT(2);
1351         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1352
1353         /* disable WL suspend*/
1354         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1355         val8 &= ~(BIT(3) | BIT(4));
1356         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1357
1358         /* wait till 0x04[17] = 1 power ready*/
1359         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1360                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1361                 if (val32 & BIT(17))
1362                         break;
1363
1364                 udelay(10);
1365         }
1366
1367         if (!count) {
1368                 ret = -EBUSY;
1369                 goto exit;
1370         }
1371
1372         /* We should be able to optimize the following three entries into one */
1373
1374         /* release WLON reset 0x04[16]= 1*/
1375         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
1376         val8 |= BIT(0);
1377         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
1378
1379         /* set, then poll until 0 */
1380         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1381         val32 |= APS_FSMCO_MAC_ENABLE;
1382         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1383
1384         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1385                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1386                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
1387                         ret = 0;
1388                         break;
1389                 }
1390                 udelay(10);
1391         }
1392
1393         if (!count) {
1394                 ret = -EBUSY;
1395                 goto exit;
1396         }
1397
1398 exit:
1399         return ret;
1400 }
1401
1402 static int rtl8192eu_active_to_lps(struct rtl8xxxu_priv *priv)
1403 {
1404         struct device *dev = &priv->udev->dev;
1405         u8 val8;
1406         u16 val16;
1407         u32 val32;
1408         int retry, retval;
1409
1410         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1411
1412         retry = 100;
1413         retval = -EBUSY;
1414         /*
1415          * Poll 32 bit wide 0x05f8 for 0x00000000 to ensure no TX is pending.
1416          */
1417         do {
1418                 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD);
1419                 if (!val32) {
1420                         retval = 0;
1421                         break;
1422                 }
1423         } while (retry--);
1424
1425         if (!retry) {
1426                 dev_warn(dev, "Failed to flush TX queue\n");
1427                 retval = -EBUSY;
1428                 goto out;
1429         }
1430
1431         /* Disable CCK and OFDM, clock gated */
1432         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
1433         val8 &= ~SYS_FUNC_BBRSTB;
1434         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
1435
1436         udelay(2);
1437
1438         /* Reset whole BB */
1439         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
1440         val8 &= ~SYS_FUNC_BB_GLB_RSTN;
1441         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
1442
1443         /* Reset MAC TRX */
1444         val16 = rtl8xxxu_read16(priv, REG_CR);
1445         val16 &= 0xff00;
1446         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE);
1447         rtl8xxxu_write16(priv, REG_CR, val16);
1448
1449         val16 = rtl8xxxu_read16(priv, REG_CR);
1450         val16 &= ~CR_SECURITY_ENABLE;
1451         rtl8xxxu_write16(priv, REG_CR, val16);
1452
1453         val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
1454         val8 |= DUAL_TSF_TX_OK;
1455         rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
1456
1457 out:
1458         return retval;
1459 }
1460
1461 static int rtl8192eu_active_to_emu(struct rtl8xxxu_priv *priv)
1462 {
1463         u8 val8;
1464         int count, ret = 0;
1465
1466         /* Turn off RF */
1467         val8 = rtl8xxxu_read8(priv, REG_RF_CTRL);
1468         val8 &= ~RF_ENABLE;
1469         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
1470
1471         /* Switch DPDT_SEL_P output from register 0x65[2] */
1472         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
1473         val8 &= ~LEDCFG2_DPDT_SELECT;
1474         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
1475
1476         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
1477         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1478         val8 |= BIT(1);
1479         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1480
1481         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1482                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1483                 if ((val8 & BIT(1)) == 0)
1484                         break;
1485                 udelay(10);
1486         }
1487
1488         if (!count) {
1489                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
1490                          __func__);
1491                 ret = -EBUSY;
1492                 goto exit;
1493         }
1494
1495 exit:
1496         return ret;
1497 }
1498
1499 static int rtl8192eu_emu_to_disabled(struct rtl8xxxu_priv *priv)
1500 {
1501         u8 val8;
1502
1503         /* 0x04[12:11] = 01 enable WL suspend */
1504         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1505         val8 &= ~(BIT(3) | BIT(4));
1506         val8 |= BIT(3);
1507         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1508
1509         return 0;
1510 }
1511
1512 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
1513 {
1514         u16 val16;
1515         u32 val32;
1516         int ret;
1517
1518         ret = 0;
1519
1520         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1521         if (val32 & SYS_CFG_SPS_LDO_SEL) {
1522                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
1523         } else {
1524                 /*
1525                  * Raise 1.2V voltage
1526                  */
1527                 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
1528                 val32 &= 0xff0fffff;
1529                 val32 |= 0x00500000;
1530                 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
1531                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
1532         }
1533
1534         /*
1535          * Adjust AFE before enabling PLL
1536          */
1537         rtl8192e_crystal_afe_adjust(priv);
1538         rtl8192e_disabled_to_emu(priv);
1539
1540         ret = rtl8192e_emu_to_active(priv);
1541         if (ret)
1542                 goto exit;
1543
1544         rtl8xxxu_write16(priv, REG_CR, 0x0000);
1545
1546         /*
1547          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
1548          * Set CR bit10 to enable 32k calibration.
1549          */
1550         val16 = rtl8xxxu_read16(priv, REG_CR);
1551         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
1552                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
1553                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
1554                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
1555                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
1556         rtl8xxxu_write16(priv, REG_CR, val16);
1557
1558 exit:
1559         return ret;
1560 }
1561
1562 static void rtl8192eu_power_off(struct rtl8xxxu_priv *priv)
1563 {
1564         u8 val8;
1565         u16 val16;
1566
1567         rtl8xxxu_flush_fifo(priv);
1568
1569         val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
1570         val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
1571         rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
1572
1573         /* Turn off RF */
1574         rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
1575
1576         rtl8192eu_active_to_lps(priv);
1577
1578         /* Reset Firmware if running in RAM */
1579         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
1580                 rtl8xxxu_firmware_self_reset(priv);
1581
1582         /* Reset MCU */
1583         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1584         val16 &= ~SYS_FUNC_CPU_ENABLE;
1585         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1586
1587         /* Reset MCU ready status */
1588         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
1589
1590         rtl8xxxu_reset_8051(priv);
1591
1592         rtl8192eu_active_to_emu(priv);
1593         rtl8192eu_emu_to_disabled(priv);
1594 }
1595
1596 static void rtl8192e_enable_rf(struct rtl8xxxu_priv *priv)
1597 {
1598         u32 val32;
1599         u8 val8;
1600
1601         val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
1602         val32 |= (BIT(22) | BIT(23));
1603         rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
1604
1605         val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
1606         val8 |= BIT(5);
1607         rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
1608
1609         /*
1610          * WLAN action by PTA
1611          */
1612         rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
1613
1614         val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
1615         val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
1616         rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
1617
1618         val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
1619         val32 |= (BIT(0) | BIT(1));
1620         rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
1621
1622         rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
1623
1624         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
1625         val32 &= ~BIT(24);
1626         val32 |= BIT(23);
1627         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
1628
1629         /*
1630          * Fix external switch Main->S1, Aux->S0
1631          */
1632         val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
1633         val8 &= ~BIT(0);
1634         rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
1635 }
1636
1637 struct rtl8xxxu_fileops rtl8192eu_fops = {
1638         .parse_efuse = rtl8192eu_parse_efuse,
1639         .load_firmware = rtl8192eu_load_firmware,
1640         .power_on = rtl8192eu_power_on,
1641         .power_off = rtl8192eu_power_off,
1642         .reset_8051 = rtl8xxxu_reset_8051,
1643         .llt_init = rtl8xxxu_auto_llt_table,
1644         .init_phy_bb = rtl8192eu_init_phy_bb,
1645         .init_phy_rf = rtl8192eu_init_phy_rf,
1646         .phy_iq_calibrate = rtl8192eu_phy_iq_calibrate,
1647         .config_channel = rtl8xxxu_gen2_config_channel,
1648         .parse_rx_desc = rtl8xxxu_parse_rxdesc24,
1649         .enable_rf = rtl8192e_enable_rf,
1650         .disable_rf = rtl8xxxu_gen2_disable_rf,
1651         .usb_quirks = rtl8xxxu_gen2_usb_quirks,
1652         .set_tx_power = rtl8192e_set_tx_power,
1653         .update_rate_mask = rtl8xxxu_gen2_update_rate_mask,
1654         .report_connect = rtl8xxxu_gen2_report_connect,
1655         .fill_txdesc = rtl8xxxu_fill_txdesc_v2,
1656         .writeN_block_size = 128,
1657         .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
1658         .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),
1659         .has_s0s1 = 0,
1660         .gen2_thermal_meter = 1,
1661         .adda_1t_init = 0x0fc01616,
1662         .adda_1t_path_on = 0x0fc01616,
1663         .adda_2t_path_on_a = 0x0fc01616,
1664         .adda_2t_path_on_b = 0x0fc01616,
1665         .trxff_boundary = 0x3cff,
1666         .mactable = rtl8192e_mac_init_table,
1667         .total_page_num = TX_TOTAL_PAGE_NUM_8192E,
1668         .page_num_hi = TX_PAGE_NUM_HI_PQ_8192E,
1669         .page_num_lo = TX_PAGE_NUM_LO_PQ_8192E,
1670         .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192E,
1671 };