drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2009-2014  Realtek Corporation.*/
   3
   4 #include "../wifi.h"
   5 #include "../pci.h"
   6 #include "../base.h"
   7 #include "../stats.h"
   8 #include "reg.h"
   9 #include "def.h"
  10 #include "phy.h"
  11 #include "trx.h"
  12 #include "led.h"
  13 #include "dm.h"
  14 #include "fw.h"
  15
  16 static u8 _rtl92ee_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
  17 {
  18         __le16 fc = rtl_get_fc(skb);
  19
  20         if (unlikely(ieee80211_is_beacon(fc)))
  21                 return QSLT_BEACON;
  22         if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
  23                 return QSLT_MGNT;
  24
  25         return skb->priority;
  26 }
  27
  28 static void _rtl92ee_query_rxphystatus(struct ieee80211_hw *hw,
  29                                        struct rtl_stats *pstatus, u8 *pdesc,
  30                                        struct rx_fwinfo *p_drvinfo,
  31                                        bool bpacket_match_bssid,
  32                                        bool bpacket_toself,
  33                                        bool packet_beacon)
  34 {
  35         struct rtl_priv *rtlpriv = rtl_priv(hw);
  36         struct phy_status_rpt *p_phystrpt = (struct phy_status_rpt *)p_drvinfo;
  37         s8 rx_pwr_all = 0, rx_pwr[4];
  38         u8 rf_rx_num = 0, evm, pwdb_all;
  39         u8 i, max_spatial_stream;
  40         u32 rssi, total_rssi = 0;
  41         bool is_cck = pstatus->is_cck;
  42         u8 lan_idx, vga_idx;
  43
  44         /* Record it for next packet processing */
  45         pstatus->packet_matchbssid = bpacket_match_bssid;
  46         pstatus->packet_toself = bpacket_toself;
  47         pstatus->packet_beacon = packet_beacon;
  48         pstatus->rx_mimo_signalquality[0] = -1;
  49         pstatus->rx_mimo_signalquality[1] = -1;
  50
  51         if (is_cck) {
  52                 u8 cck_highpwr;
  53                 u8 cck_agc_rpt;
  54                 /* CCK Driver info Structure is not the same as OFDM packet. */
  55                 cck_agc_rpt = p_phystrpt->cck_agc_rpt_ofdm_cfosho_a;
  56
  57                 /* (1)Hardware does not provide RSSI for CCK
  58                  * (2)PWDB, Average PWDB cacluated by
  59                  * hardware (for rate adaptive)
  60                  */
  61                 cck_highpwr = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2,
  62                                                  BIT(9));
  63
  64                 lan_idx = ((cck_agc_rpt & 0xE0) >> 5);
  65                 vga_idx = (cck_agc_rpt & 0x1f);
  66                 switch (lan_idx) {
  67                 case 7: /*VGA_idx = 27~2*/
  68                                 if (vga_idx <= 27)
  69                                         rx_pwr_all = -100 + 2 * (27 - vga_idx);
  70                                 else
  71                                         rx_pwr_all = -100;
  72                                 break;
  73                 case 6: /*VGA_idx = 2~0*/
  74                                 rx_pwr_all = -48 + 2 * (2 - vga_idx);
  75                                 break;
  76                 case 5: /*VGA_idx = 7~5*/
  77                                 rx_pwr_all = -42 + 2 * (7 - vga_idx);
  78                                 break;
  79                 case 4: /*VGA_idx = 7~4*/
  80                                 rx_pwr_all = -36 + 2 * (7 - vga_idx);
  81                                 break;
  82                 case 3: /*VGA_idx = 7~0*/
  83                                 rx_pwr_all = -24 + 2 * (7 - vga_idx);
  84                                 break;
  85                 case 2: /*VGA_idx = 5~0*/
  86                                 if (cck_highpwr)
  87                                         rx_pwr_all = -12 + 2 * (5 - vga_idx);
  88                                 else
  89                                         rx_pwr_all = -6 + 2 * (5 - vga_idx);
  90                                 break;
  91                 case 1:
  92                                 rx_pwr_all = 8 - 2 * vga_idx;
  93                                 break;
  94                 case 0:
  95                                 rx_pwr_all = 14 - 2 * vga_idx;
  96                                 break;
  97                 default:
  98                                 break;
  99                 }
 100                 rx_pwr_all += 16;
 101                 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
 102
 103                 if (!cck_highpwr) {
 104                         if (pwdb_all >= 80)
 105                                 pwdb_all = ((pwdb_all - 80) << 1) +
 106                                            ((pwdb_all - 80) >> 1) + 80;
 107                         else if ((pwdb_all <= 78) && (pwdb_all >= 20))
 108                                 pwdb_all += 3;
 109                         if (pwdb_all > 100)
 110                                 pwdb_all = 100;
 111                 }
 112
 113                 pstatus->rx_pwdb_all = pwdb_all;
 114                 pstatus->bt_rx_rssi_percentage = pwdb_all;
 115                 pstatus->recvsignalpower = rx_pwr_all;
 116
 117                 /* (3) Get Signal Quality (EVM) */
 118                 if (bpacket_match_bssid) {
 119                         u8 sq, sq_rpt;
 120
 121                         if (pstatus->rx_pwdb_all > 40) {
 122                                 sq = 100;
 123                         } else {
 124                                 sq_rpt = p_phystrpt->cck_sig_qual_ofdm_pwdb_all;
 125                                 if (sq_rpt > 64)
 126                                         sq = 0;
 127                                 else if (sq_rpt < 20)
 128                                         sq = 100;
 129                                 else
 130                                         sq = ((64 - sq_rpt) * 100) / 44;
 131                         }
 132
 133                         pstatus->signalquality = sq;
 134                         pstatus->rx_mimo_signalquality[0] = sq;
 135                         pstatus->rx_mimo_signalquality[1] = -1;
 136                 }
 137         } else {
 138                 /* (1)Get RSSI for HT rate */
 139                 for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) {
 140                         /* we will judge RF RX path now. */
 141                         if (rtlpriv->dm.rfpath_rxenable[i])
 142                                 rf_rx_num++;
 143
 144                         rx_pwr[i] = ((p_phystrpt->path_agc[i].gain & 0x3f) * 2)
 145                                     - 110;
 146
 147                         pstatus->rx_pwr[i] = rx_pwr[i];
 148                         /* Translate DBM to percentage. */
 149                         rssi = rtl_query_rxpwrpercentage(rx_pwr[i]);
 150                         total_rssi += rssi;
 151
 152                         pstatus->rx_mimo_signalstrength[i] = (u8)rssi;
 153                 }
 154
 155                 /* (2)PWDB, Average PWDB cacluated by
 156                  * hardware (for rate adaptive)
 157                  */
 158                 rx_pwr_all = ((p_phystrpt->cck_sig_qual_ofdm_pwdb_all >> 1)
 159                               & 0x7f) - 110;
 160
 161                 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
 162                 pstatus->rx_pwdb_all = pwdb_all;
 163                 pstatus->bt_rx_rssi_percentage = pwdb_all;
 164                 pstatus->rxpower = rx_pwr_all;
 165                 pstatus->recvsignalpower = rx_pwr_all;
 166
 167                 /* (3)EVM of HT rate */
 168                 if (pstatus->rate >= DESC_RATEMCS8 &&
 169                     pstatus->rate <= DESC_RATEMCS15)
 170                         max_spatial_stream = 2;
 171                 else
 172                         max_spatial_stream = 1;
 173
 174                 for (i = 0; i < max_spatial_stream; i++) {
 175                         evm = rtl_evm_db_to_percentage(
 176                                                 p_phystrpt->stream_rxevm[i]);
 177
 178                         if (bpacket_match_bssid) {
 179                                 /* Fill value in RFD, Get the first
 180                                  * spatial stream only
 181                                  */
 182                                 if (i == 0)
 183                                         pstatus->signalquality = (u8)(evm &
 184                                                                        0xff);
 185                                 pstatus->rx_mimo_signalquality[i] = (u8)(evm &
 186                                                                           0xff);
 187                         }
 188                 }
 189
 190                 if (bpacket_match_bssid) {
 191                         for (i = RF90_PATH_A; i <= RF90_PATH_B; i++)
 192                                 rtl_priv(hw)->dm.cfo_tail[i] =
 193                                         (int)p_phystrpt->path_cfotail[i];
 194
 195                         if (rtl_priv(hw)->dm.packet_count == 0xffffffff)
 196                                 rtl_priv(hw)->dm.packet_count = 0;
 197                         else
 198                                 rtl_priv(hw)->dm.packet_count++;
 199                 }
 200         }
 201
 202         /* UI BSS List signal strength(in percentage),
 203          * make it good looking, from 0~100.
 204          */
 205         if (is_cck)
 206                 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
 207                                                                      pwdb_all));
 208         else if (rf_rx_num != 0)
 209                 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
 210                                                       total_rssi /= rf_rx_num));
 211 }
 212
 213 static void _rtl92ee_translate_rx_signal_stuff(struct ieee80211_hw *hw,
 214                                                struct sk_buff *skb,
 215                                                struct rtl_stats *pstatus,
 216                                                u8 *pdesc,
 217                                                struct rx_fwinfo *p_drvinfo)
 218 {
 219         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 220         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 221         struct ieee80211_hdr *hdr;
 222         u8 *tmp_buf;
 223         u8 *praddr;
 224         u8 *psaddr;
 225         __le16 fc;
 226         bool packet_matchbssid, packet_toself, packet_beacon;
 227
 228         tmp_buf = skb->data + pstatus->rx_drvinfo_size +
 229                   pstatus->rx_bufshift + 24;
 230
 231         hdr = (struct ieee80211_hdr *)tmp_buf;
 232         fc = hdr->frame_control;
 233         praddr = hdr->addr1;
 234         psaddr = ieee80211_get_SA(hdr);
 235         ether_addr_copy(pstatus->psaddr, psaddr);
 236
 237         packet_matchbssid = (!ieee80211_is_ctl(fc) &&
 238                                (ether_addr_equal(mac->bssid,
 239                                                 ieee80211_has_tods(fc) ?
 240                                                 hdr->addr1 :
 241                                                 ieee80211_has_fromds(fc) ?
 242                                                 hdr->addr2 : hdr->addr3)) &&
 243                                 (!pstatus->hwerror) && (!pstatus->crc) &&
 244                                 (!pstatus->icv));
 245
 246         packet_toself = packet_matchbssid &&
 247                          (ether_addr_equal(praddr, rtlefuse->dev_addr));
 248
 249         if (ieee80211_is_beacon(fc))
 250                 packet_beacon = true;
 251         else
 252                 packet_beacon = false;
 253
 254         if (packet_beacon && packet_matchbssid)
 255                 rtl_priv(hw)->dm.dbginfo.num_qry_beacon_pkt++;
 256
 257         if (packet_matchbssid && ieee80211_is_data_qos(hdr->frame_control) &&
 258             !is_multicast_ether_addr(ieee80211_get_DA(hdr))) {
 259                 struct ieee80211_qos_hdr *hdr_qos =
 260                                             (struct ieee80211_qos_hdr *)tmp_buf;
 261                 u16 tid = le16_to_cpu(hdr_qos->qos_ctrl) & 0xf;
 262
 263                 if (tid != 0 && tid != 3)
 264                         rtl_priv(hw)->dm.dbginfo.num_non_be_pkt++;
 265         }
 266
 267         _rtl92ee_query_rxphystatus(hw, pstatus, pdesc, p_drvinfo,
 268                                    packet_matchbssid, packet_toself,
 269                                    packet_beacon);
 270         rtl_process_phyinfo(hw, tmp_buf, pstatus);
 271 }
 272
 273 static void _rtl92ee_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
 274                                       u8 *virtualaddress)
 275 {
 276         u32 dwtmp = 0;
 277
 278         memset(virtualaddress, 0, 8);
 279
 280         SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num);
 281         if (ptcb_desc->empkt_num == 1) {
 282                 dwtmp = ptcb_desc->empkt_len[0];
 283         } else {
 284                 dwtmp = ptcb_desc->empkt_len[0];
 285                 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
 286                 dwtmp += ptcb_desc->empkt_len[1];
 287         }
 288         SET_EARLYMODE_LEN0(virtualaddress, dwtmp);
 289
 290         if (ptcb_desc->empkt_num <= 3) {
 291                 dwtmp = ptcb_desc->empkt_len[2];
 292         } else {
 293                 dwtmp = ptcb_desc->empkt_len[2];
 294                 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
 295                 dwtmp += ptcb_desc->empkt_len[3];
 296         }
 297         SET_EARLYMODE_LEN1(virtualaddress, dwtmp);
 298         if (ptcb_desc->empkt_num <= 5) {
 299                 dwtmp = ptcb_desc->empkt_len[4];
 300         } else {
 301                 dwtmp = ptcb_desc->empkt_len[4];
 302                 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
 303                 dwtmp += ptcb_desc->empkt_len[5];
 304         }
 305         SET_EARLYMODE_LEN2_1(virtualaddress, dwtmp & 0xF);
 306         SET_EARLYMODE_LEN2_2(virtualaddress, dwtmp >> 4);
 307         if (ptcb_desc->empkt_num <= 7) {
 308                 dwtmp = ptcb_desc->empkt_len[6];
 309         } else {
 310                 dwtmp = ptcb_desc->empkt_len[6];
 311                 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
 312                 dwtmp += ptcb_desc->empkt_len[7];
 313         }
 314         SET_EARLYMODE_LEN3(virtualaddress, dwtmp);
 315         if (ptcb_desc->empkt_num <= 9) {
 316                 dwtmp = ptcb_desc->empkt_len[8];
 317         } else {
 318                 dwtmp = ptcb_desc->empkt_len[8];
 319                 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
 320                 dwtmp += ptcb_desc->empkt_len[9];
 321         }
 322         SET_EARLYMODE_LEN4(virtualaddress, dwtmp);
 323 }
 324
 325 bool rtl92ee_rx_query_desc(struct ieee80211_hw *hw,
 326                            struct rtl_stats *status,
 327                            struct ieee80211_rx_status *rx_status,
 328                            u8 *pdesc, struct sk_buff *skb)
 329 {
 330         struct rtl_priv *rtlpriv = rtl_priv(hw);
 331         struct rx_fwinfo *p_drvinfo;
 332         struct ieee80211_hdr *hdr;
 333         u32 phystatus = GET_RX_DESC_PHYST(pdesc);
 334
 335         if (GET_RX_STATUS_DESC_RPT_SEL(pdesc) == 0)
 336                 status->packet_report_type = NORMAL_RX;
 337         else
 338                 status->packet_report_type = C2H_PACKET;
 339         status->length = (u16)GET_RX_DESC_PKT_LEN(pdesc);
 340         status->rx_drvinfo_size = (u8)GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
 341                                   RX_DRV_INFO_SIZE_UNIT;
 342         status->rx_bufshift = (u8)(GET_RX_DESC_SHIFT(pdesc) & 0x03);
 343         status->icv = (u16)GET_RX_DESC_ICV(pdesc);
 344         status->crc = (u16)GET_RX_DESC_CRC32(pdesc);
 345         status->hwerror = (status->crc | status->icv);
 346         status->decrypted = !GET_RX_DESC_SWDEC(pdesc);
 347         status->rate = (u8)GET_RX_DESC_RXMCS(pdesc);
 348         status->isampdu = (bool)(GET_RX_DESC_PAGGR(pdesc) == 1);
 349         status->timestamp_low = GET_RX_DESC_TSFL(pdesc);
 350         status->is_cck = RTL92EE_RX_HAL_IS_CCK_RATE(status->rate);
 351
 352         status->macid = GET_RX_DESC_MACID(pdesc);
 353         if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
 354                 status->wake_match = BIT(2);
 355         else if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
 356                 status->wake_match = BIT(1);
 357         else if (GET_RX_STATUS_DESC_UNICAST_MATCH(pdesc))
 358                 status->wake_match = BIT(0);
 359         else
 360                 status->wake_match = 0;
 361         if (status->wake_match)
 362                 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD,
 363                          "GGGGGGGGGGGGGet Wakeup Packet!! WakeMatch=%d\n",
 364                          status->wake_match);
 365         rx_status->freq = hw->conf.chandef.chan->center_freq;
 366         rx_status->band = hw->conf.chandef.chan->band;
 367
 368         hdr = (struct ieee80211_hdr *)(skb->data + status->rx_drvinfo_size +
 369                                        status->rx_bufshift + 24);
 370
 371         if (status->crc)
 372                 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
 373
 374         if (status->rx_is40mhzpacket)
 375                 rx_status->bw = RATE_INFO_BW_40;
 376
 377         if (status->is_ht)
 378                 rx_status->encoding = RX_ENC_HT;
 379
 380         rx_status->flag |= RX_FLAG_MACTIME_START;
 381
 382         /* hw will set status->decrypted true, if it finds the
 383          * frame is open data frame or mgmt frame.
 384          * So hw will not decryption robust managment frame
 385          * for IEEE80211w but still set status->decrypted
 386          * true, so here we should set it back to undecrypted
 387          * for IEEE80211w frame, and mac80211 sw will help
 388          * to decrypt it
 389          */
 390         if (status->decrypted) {
 391                 if ((!_ieee80211_is_robust_mgmt_frame(hdr)) &&
 392                     (ieee80211_has_protected(hdr->frame_control)))
 393                         rx_status->flag |= RX_FLAG_DECRYPTED;
 394                 else
 395                         rx_status->flag &= ~RX_FLAG_DECRYPTED;
 396         }
 397
 398         /* rate_idx: index of data rate into band's
 399          * supported rates or MCS index if HT rates
 400          * are use (RX_FLAG_HT)
 401          * Notice: this is diff with windows define
 402          */
 403         rx_status->rate_idx = rtlwifi_rate_mapping(hw, status->is_ht,
 404                                                    false, status->rate);
 405
 406         rx_status->mactime = status->timestamp_low;
 407         if (phystatus) {
 408                 p_drvinfo = (struct rx_fwinfo *)(skb->data +
 409                                                  status->rx_bufshift + 24);
 410
 411                 _rtl92ee_translate_rx_signal_stuff(hw, skb, status, pdesc,
 412                                                    p_drvinfo);
 413         }
 414         rx_status->signal = status->recvsignalpower + 10;
 415         if (status->packet_report_type == TX_REPORT2) {
 416                 status->macid_valid_entry[0] =
 417                         GET_RX_RPT2_DESC_MACID_VALID_1(pdesc);
 418                 status->macid_valid_entry[1] =
 419                         GET_RX_RPT2_DESC_MACID_VALID_2(pdesc);
 420         }
 421         return true;
 422 }
 423
 424 /*in Windows, this == Rx_92EE_Interrupt*/
 425 void rtl92ee_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc,
 426                              u8 queue_index)
 427 {
 428         u8 first_seg = 0;
 429         u8 last_seg = 0;
 430         u16 total_len = 0;
 431         u16 read_cnt = 0;
 432
 433         if (header_desc == NULL)
 434                 return;
 435
 436         total_len = (u16)GET_RX_BUFFER_DESC_TOTAL_LENGTH(header_desc);
 437
 438         first_seg = (u8)GET_RX_BUFFER_DESC_FS(header_desc);
 439
 440         last_seg = (u8)GET_RX_BUFFER_DESC_LS(header_desc);
 441
 442         while (total_len == 0 && first_seg == 0 && last_seg == 0) {
 443                 read_cnt++;
 444                 total_len = (u16)GET_RX_BUFFER_DESC_TOTAL_LENGTH(header_desc);
 445                 first_seg = (u8)GET_RX_BUFFER_DESC_FS(header_desc);
 446                 last_seg = (u8)GET_RX_BUFFER_DESC_LS(header_desc);
 447
 448                 if (read_cnt > 20)
 449                         break;
 450         }
 451 }
 452
 453 u16 rtl92ee_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw, u8 queue_index)
 454 {
 455         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 456         struct rtl_priv *rtlpriv = rtl_priv(hw);
 457         u16 read_point = 0, write_point = 0, remind_cnt = 0;
 458         u32 tmp_4byte = 0;
 459         static bool start_rx;
 460
 461         tmp_4byte = rtl_read_dword(rtlpriv, REG_RXQ_TXBD_IDX);
 462         read_point = (u16)((tmp_4byte>>16) & 0x7ff);
 463         write_point = (u16)(tmp_4byte & 0x7ff);
 464
 465         if (write_point != rtlpci->rx_ring[queue_index].next_rx_rp) {
 466                 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_DMESG,
 467                          "!!!write point is 0x%x, reg 0x3B4 value is 0x%x\n",
 468                           write_point, tmp_4byte);
 469                 tmp_4byte = rtl_read_dword(rtlpriv, REG_RXQ_TXBD_IDX);
 470                 read_point = (u16)((tmp_4byte>>16) & 0x7ff);
 471                 write_point = (u16)(tmp_4byte & 0x7ff);
 472         }
 473
 474         if (read_point > 0)
 475                 start_rx = true;
 476         if (!start_rx)
 477                 return 0;
 478
 479         remind_cnt = calc_fifo_space(read_point, write_point,
 480                                      RTL_PCI_MAX_RX_COUNT);
 481
 482         if (remind_cnt == 0)
 483                 return 0;
 484
 485         rtlpci->rx_ring[queue_index].next_rx_rp = write_point;
 486
 487         return remind_cnt;
 488 }
 489
 490 static u16 get_desc_addr_fr_q_idx(u16 queue_index)
 491 {
 492         u16 desc_address = REG_BEQ_TXBD_IDX;
 493
 494         switch (queue_index) {
 495         case BK_QUEUE:
 496                 desc_address = REG_BKQ_TXBD_IDX;
 497                 break;
 498         case BE_QUEUE:
 499                 desc_address = REG_BEQ_TXBD_IDX;
 500                 break;
 501         case VI_QUEUE:
 502                 desc_address = REG_VIQ_TXBD_IDX;
 503                 break;
 504         case VO_QUEUE:
 505                 desc_address = REG_VOQ_TXBD_IDX;
 506                 break;
 507         case BEACON_QUEUE:
 508                 desc_address = REG_BEQ_TXBD_IDX;
 509                 break;
 510         case TXCMD_QUEUE:
 511                 desc_address = REG_BEQ_TXBD_IDX;
 512                 break;
 513         case MGNT_QUEUE:
 514                 desc_address = REG_MGQ_TXBD_IDX;
 515                 break;
 516         case HIGH_QUEUE:
 517                 desc_address = REG_HI0Q_TXBD_IDX;
 518                 break;
 519         case HCCA_QUEUE:
 520                 desc_address = REG_BEQ_TXBD_IDX;
 521                 break;
 522         default:
 523                 break;
 524         }
 525         return desc_address;
 526 }
 527
 528 u16 rtl92ee_get_available_desc(struct ieee80211_hw *hw, u8 q_idx)
 529 {
 530         struct rtl_priv *rtlpriv = rtl_priv(hw);
 531         u16 point_diff = 0;
 532         u16 current_tx_read_point = 0, current_tx_write_point = 0;
 533         u32 tmp_4byte;
 534
 535         tmp_4byte = rtl_read_dword(rtlpriv,
 536                                    get_desc_addr_fr_q_idx(q_idx));
 537         current_tx_read_point = (u16)((tmp_4byte >> 16) & 0x0fff);
 538         current_tx_write_point = (u16)((tmp_4byte) & 0x0fff);
 539
 540         point_diff = calc_fifo_space(current_tx_read_point,
 541                                      current_tx_write_point,
 542                                      TX_DESC_NUM_92E);
 543
 544         return point_diff;
 545 }
 546
 547 void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw,
 548                                  u8 *tx_bd_desc, u8 *desc, u8 queue_index,
 549                                  struct sk_buff *skb, dma_addr_t addr)
 550 {
 551         struct rtl_priv *rtlpriv = rtl_priv(hw);
 552         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 553         u32 pkt_len = skb->len;
 554         u16 desc_size = 40; /*tx desc size*/
 555         u32 psblen = 0;
 556         u16 tx_page_size = 0;
 557         u32 total_packet_size = 0;
 558         u16 current_bd_desc;
 559         u8 i = 0;
 560         u16 real_desc_size = 0x28;
 561         u16     append_early_mode_size = 0;
 562         u8 segmentnum = 1 << (RTL8192EE_SEG_NUM + 1);
 563         dma_addr_t desc_dma_addr;
 564         bool dma64 = rtlpriv->cfg->mod_params->dma64;
 565
 566         tx_page_size = 2;
 567         current_bd_desc = rtlpci->tx_ring[queue_index].cur_tx_wp;
 568
 569         total_packet_size = desc_size+pkt_len;
 570
 571         if (rtlpriv->rtlhal.earlymode_enable)   {
 572                 if (queue_index < BEACON_QUEUE) {
 573                         append_early_mode_size = 8;
 574                         total_packet_size += append_early_mode_size;
 575                 }
 576         }
 577
 578         if (tx_page_size > 0) {
 579                 psblen = (pkt_len + real_desc_size + append_early_mode_size) /
 580                          (tx_page_size * 128);
 581
 582                 if (psblen * (tx_page_size * 128) < total_packet_size)
 583                         psblen += 1;
 584         }
 585
 586         /* tx desc addr */
 587         desc_dma_addr = rtlpci->tx_ring[queue_index].dma +
 588                         (current_bd_desc * TX_DESC_SIZE);
 589
 590         /* Reset */
 591         SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, 0);
 592         SET_TX_BUFF_DESC_PSB(tx_bd_desc, 0);
 593         SET_TX_BUFF_DESC_OWN(tx_bd_desc, 0);
 594
 595         for (i = 1; i < segmentnum; i++) {
 596                 SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, i, 0);
 597                 SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, i, 0);
 598                 SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, i, 0);
 599                 SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(tx_bd_desc, i, 0, dma64);
 600         }
 601
 602         /* Clear all status */
 603         CLEAR_PCI_TX_DESC_CONTENT(desc, TX_DESC_SIZE);
 604
 605         if (rtlpriv->rtlhal.earlymode_enable) {
 606                 if (queue_index < BEACON_QUEUE) {
 607                         /* This if needs braces */
 608                         SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size + 8);
 609                 } else {
 610                         SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size);
 611                 }
 612         } else {
 613                 SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size);
 614         }
 615         SET_TX_BUFF_DESC_PSB(tx_bd_desc, psblen);
 616         SET_TX_BUFF_DESC_ADDR_LOW_0(tx_bd_desc, desc_dma_addr);
 617         SET_TX_BUFF_DESC_ADDR_HIGH_0(tx_bd_desc, ((u64)desc_dma_addr >> 32),
 618                                      dma64);
 619
 620         SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, 1, pkt_len);
 621         /* don't using extendsion mode. */
 622         SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, 1, 0);
 623         SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, 1, addr);
 624         SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(tx_bd_desc, 1,
 625                                                ((u64)addr >> 32), dma64);
 626
 627         SET_TX_DESC_PKT_SIZE(desc, (u16)(pkt_len));
 628         SET_TX_DESC_TX_BUFFER_SIZE(desc, (u16)(pkt_len));
 629 }
 630
 631 void rtl92ee_tx_fill_desc(struct ieee80211_hw *hw,
 632                           struct ieee80211_hdr *hdr, u8 *pdesc_tx,
 633                           u8 *pbd_desc_tx,
 634                           struct ieee80211_tx_info *info,
 635                           struct ieee80211_sta *sta,
 636                           struct sk_buff *skb,
 637                           u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
 638 {
 639         struct rtl_priv *rtlpriv = rtl_priv(hw);
 640         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 641         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 642         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 643         struct rtlwifi_tx_info *tx_info = rtl_tx_skb_cb_info(skb);
 644         u8 *pdesc = (u8 *)pdesc_tx;
 645         u16 seq_number;
 646         __le16 fc = hdr->frame_control;
 647         unsigned int buf_len = 0;
 648         u8 fw_qsel = _rtl92ee_map_hwqueue_to_fwqueue(skb, hw_queue);
 649         bool firstseg = ((hdr->seq_ctrl &
 650                             cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
 651         bool lastseg = ((hdr->frame_control &
 652                            cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
 653         dma_addr_t mapping;
 654         u8 bw_40 = 0;
 655         u8 short_gi = 0;
 656
 657         if (mac->opmode == NL80211_IFTYPE_STATION) {
 658                 bw_40 = mac->bw_40;
 659         } else if (mac->opmode == NL80211_IFTYPE_AP ||
 660                    mac->opmode == NL80211_IFTYPE_ADHOC) {
 661                 if (sta)
 662                         bw_40 = sta->ht_cap.cap &
 663                                 IEEE80211_HT_CAP_SUP_WIDTH_20_40;
 664         }
 665         seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
 666         rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc);
 667         /* reserve 8 byte for AMPDU early mode */
 668         if (rtlhal->earlymode_enable) {
 669                 skb_push(skb, EM_HDR_LEN);
 670                 memset(skb->data, 0, EM_HDR_LEN);
 671         }
 672         buf_len = skb->len;
 673         mapping = pci_map_single(rtlpci->pdev, skb->data, skb->len,
 674                                  PCI_DMA_TODEVICE);
 675         if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
 676                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 677                          "DMA mapping error\n");
 678                 return;
 679         }
 680
 681         if (pbd_desc_tx != NULL)
 682                 rtl92ee_pre_fill_tx_bd_desc(hw, pbd_desc_tx, pdesc, hw_queue,
 683                                             skb, mapping);
 684
 685         if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
 686                 firstseg = true;
 687                 lastseg = true;
 688         }
 689         if (firstseg) {
 690                 if (rtlhal->earlymode_enable) {
 691                         SET_TX_DESC_PKT_OFFSET(pdesc, 1);
 692                         SET_TX_DESC_OFFSET(pdesc,
 693                                            USB_HWDESC_HEADER_LEN + EM_HDR_LEN);
 694                         if (ptcb_desc->empkt_num) {
 695                                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 696                                          "Insert 8 byte.pTcb->EMPktNum:%d\n",
 697                                           ptcb_desc->empkt_num);
 698                                 _rtl92ee_insert_emcontent(ptcb_desc,
 699                                                           (u8 *)(skb->data));
 700                         }
 701                 } else {
 702                         SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
 703                 }
 704
 705
 706                 SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate);
 707
 708                 if (ieee80211_is_mgmt(fc)) {
 709                         ptcb_desc->use_driver_rate = true;
 710                 } else {
 711                         if (rtlpriv->ra.is_special_data) {
 712                                 ptcb_desc->use_driver_rate = true;
 713                                 SET_TX_DESC_TX_RATE(pdesc, DESC_RATE11M);
 714                         } else {
 715                                 ptcb_desc->use_driver_rate = false;
 716                         }
 717                 }
 718
 719                 if (ptcb_desc->hw_rate > DESC_RATEMCS0)
 720                         short_gi = (ptcb_desc->use_shortgi) ? 1 : 0;
 721                 else
 722                         short_gi = (ptcb_desc->use_shortpreamble) ? 1 : 0;
 723
 724                 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
 725                         SET_TX_DESC_AGG_ENABLE(pdesc, 1);
 726                         SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14);
 727                 }
 728                 SET_TX_DESC_SEQ(pdesc, seq_number);
 729                 SET_TX_DESC_RTS_ENABLE(pdesc,
 730                                        ((ptcb_desc->rts_enable &&
 731                                          !ptcb_desc->cts_enable) ? 1 : 0));
 732                 SET_TX_DESC_HW_RTS_ENABLE(pdesc, 0);
 733                 SET_TX_DESC_CTS2SELF(pdesc,
 734                                      ((ptcb_desc->cts_enable) ? 1 : 0));
 735
 736                 SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate);
 737                 SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc);
 738                 SET_TX_DESC_RTS_SHORT(pdesc,
 739                                 ((ptcb_desc->rts_rate <= DESC_RATE54M) ?
 740                                  (ptcb_desc->rts_use_shortpreamble ? 1 : 0) :
 741                                  (ptcb_desc->rts_use_shortgi ? 1 : 0)));
 742
 743                 if (ptcb_desc->tx_enable_sw_calc_duration)
 744                         SET_TX_DESC_NAV_USE_HDR(pdesc, 1);
 745
 746                 if (bw_40) {
 747                         if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) {
 748                                 SET_TX_DESC_DATA_BW(pdesc, 1);
 749                                 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
 750                         } else {
 751                                 SET_TX_DESC_DATA_BW(pdesc, 0);
 752                                 SET_TX_DESC_TX_SUB_CARRIER(pdesc,
 753                                                            mac->cur_40_prime_sc);
 754                         }
 755                 } else {
 756                         SET_TX_DESC_DATA_BW(pdesc, 0);
 757                         SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
 758                 }
 759
 760                 SET_TX_DESC_LINIP(pdesc, 0);
 761                 if (sta) {
 762                         u8 ampdu_density = sta->ht_cap.ampdu_density;
 763
 764                         SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
 765                 }
 766                 if (info->control.hw_key) {
 767                         struct ieee80211_key_conf *key = info->control.hw_key;
 768
 769                         switch (key->cipher) {
 770                         case WLAN_CIPHER_SUITE_WEP40:
 771                         case WLAN_CIPHER_SUITE_WEP104:
 772                         case WLAN_CIPHER_SUITE_TKIP:
 773                                 SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
 774                                 break;
 775                         case WLAN_CIPHER_SUITE_CCMP:
 776                                 SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
 777                                 break;
 778                         default:
 779                                 SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
 780                                 break;
 781                         }
 782                 }
 783
 784                 SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
 785                 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
 786                 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
 787                 SET_TX_DESC_DISABLE_FB(pdesc,
 788                                        ptcb_desc->disable_ratefallback ? 1 : 0);
 789                 SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
 790
 791                 /*SET_TX_DESC_PWR_STATUS(pdesc, pwr_status);*/
 792                 /* Set TxRate and RTSRate in TxDesc  */
 793                 /* This prevent Tx initial rate of new-coming packets */
 794                 /* from being overwritten by retried  packet rate.*/
 795                 if (!ptcb_desc->use_driver_rate) {
 796                         /*SET_TX_DESC_RTS_RATE(pdesc, 0x08); */
 797                         /* SET_TX_DESC_TX_RATE(pdesc, 0x0b); */
 798                 }
 799                 if (ieee80211_is_data_qos(fc)) {
 800                         if (mac->rdg_en) {
 801                                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 802                                          "Enable RDG function.\n");
 803                                 SET_TX_DESC_RDG_ENABLE(pdesc, 1);
 804                                 SET_TX_DESC_HTC(pdesc, 1);
 805                         }
 806                 }
 807                 /* tx report */
 808                 rtl_set_tx_report(ptcb_desc, pdesc, hw, tx_info);
 809         }
 810
 811         SET_TX_DESC_FIRST_SEG(pdesc, (firstseg ? 1 : 0));
 812         SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0));
 813         SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
 814         if (rtlpriv->dm.useramask) {
 815                 SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
 816                 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
 817         } else {
 818                 SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
 819                 SET_TX_DESC_MACID(pdesc, ptcb_desc->ratr_index);
 820         }
 821
 822         SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
 823         if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
 824             is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
 825                 SET_TX_DESC_BMC(pdesc, 1);
 826         }
 827         RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n");
 828 }
 829
 830 void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw,
 831                              u8 *pdesc, bool firstseg,
 832                              bool lastseg, struct sk_buff *skb)
 833 {
 834         struct rtl_priv *rtlpriv = rtl_priv(hw);
 835         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 836         u8 fw_queue = QSLT_BEACON;
 837         dma_addr_t mapping = pci_map_single(rtlpci->pdev,
 838                                             skb->data, skb->len,
 839                                             PCI_DMA_TODEVICE);
 840         u8 txdesc_len = 40;
 841
 842         if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
 843                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 844                          "DMA mapping error\n");
 845                 return;
 846         }
 847         CLEAR_PCI_TX_DESC_CONTENT(pdesc, txdesc_len);
 848
 849         if (firstseg)
 850                 SET_TX_DESC_OFFSET(pdesc, txdesc_len);
 851
 852         SET_TX_DESC_TX_RATE(pdesc, DESC_RATE1M);
 853
 854         SET_TX_DESC_SEQ(pdesc, 0);
 855
 856         SET_TX_DESC_LINIP(pdesc, 0);
 857
 858         SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
 859
 860         SET_TX_DESC_FIRST_SEG(pdesc, 1);
 861         SET_TX_DESC_LAST_SEG(pdesc, 1);
 862
 863         SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len));
 864
 865         SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
 866
 867         SET_TX_DESC_RATE_ID(pdesc, 7);
 868         SET_TX_DESC_MACID(pdesc, 0);
 869
 870         SET_TX_DESC_OWN(pdesc, 1);
 871
 872         SET_TX_DESC_PKT_SIZE((u8 *)pdesc, (u16)(skb->len));
 873
 874         SET_TX_DESC_FIRST_SEG(pdesc, 1);
 875         SET_TX_DESC_LAST_SEG(pdesc, 1);
 876
 877         SET_TX_DESC_OFFSET(pdesc, 40);
 878
 879         SET_TX_DESC_USE_RATE(pdesc, 1);
 880
 881         RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
 882                       "H2C Tx Cmd Content\n", pdesc, txdesc_len);
 883 }
 884
 885 void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
 886                       u8 desc_name, u8 *val)
 887 {
 888         struct rtl_priv *rtlpriv = rtl_priv(hw);
 889         u8 q_idx = *val;
 890         bool dma64 = rtlpriv->cfg->mod_params->dma64;
 891
 892         if (istx) {
 893                 switch (desc_name) {
 894                 case HW_DESC_TX_NEXTDESC_ADDR:
 895                         SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *)val);
 896                         break;
 897                 case HW_DESC_OWN:{
 898                         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 899                         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[q_idx];
 900                         u16 max_tx_desc = ring->entries;
 901
 902                         if (q_idx == BEACON_QUEUE) {
 903                                 ring->cur_tx_wp = 0;
 904                                 ring->cur_tx_rp = 0;
 905                                 SET_TX_BUFF_DESC_OWN(pdesc, 1);
 906                                 return;
 907                         }
 908
 909                         /* make sure tx desc is available by caller */
 910                         ring->cur_tx_wp = ((ring->cur_tx_wp + 1) % max_tx_desc);
 911
 912                         rtl_write_word(rtlpriv,
 913                                        get_desc_addr_fr_q_idx(q_idx),
 914                                        ring->cur_tx_wp);
 915                 }
 916                 break;
 917                 }
 918         } else {
 919                 switch (desc_name) {
 920                 case HW_DESC_RX_PREPARE:
 921                         SET_RX_BUFFER_DESC_LS(pdesc, 0);
 922                         SET_RX_BUFFER_DESC_FS(pdesc, 0);
 923                         SET_RX_BUFFER_DESC_TOTAL_LENGTH(pdesc, 0);
 924
 925                         SET_RX_BUFFER_DESC_DATA_LENGTH(pdesc,
 926                                                        MAX_RECEIVE_BUFFER_SIZE +
 927                                                        RX_DESC_SIZE);
 928
 929                         SET_RX_BUFFER_PHYSICAL_LOW(pdesc, (*(dma_addr_t *)val) &
 930                                                    DMA_BIT_MASK(32));
 931                         SET_RX_BUFFER_PHYSICAL_HIGH(pdesc,
 932                                                     ((u64)(*(dma_addr_t *)val)
 933                                                     >> 32),
 934                                                     dma64);
 935                         break;
 936                 case HW_DESC_RXERO:
 937                         SET_RX_DESC_EOR(pdesc, 1);
 938                         break;
 939                 default:
 940                         WARN_ONCE(true,
 941                                   "rtl8192ee: ERR rxdesc :%d not processed\n",
 942                                   desc_name);
 943                         break;
 944                 }
 945         }
 946 }
 947
 948 u64 rtl92ee_get_desc(struct ieee80211_hw *hw,
 949                      u8 *pdesc, bool istx, u8 desc_name)
 950 {
 951         struct rtl_priv *rtlpriv = rtl_priv(hw);
 952         u64 ret = 0;
 953         bool dma64 = rtlpriv->cfg->mod_params->dma64;
 954
 955         if (istx) {
 956                 switch (desc_name) {
 957                 case HW_DESC_OWN:
 958                         ret = GET_TX_DESC_OWN(pdesc);
 959                         break;
 960                 case HW_DESC_TXBUFF_ADDR:
 961                         ret = GET_TXBUFFER_DESC_ADDR_LOW(pdesc, 1);
 962                         ret |= (u64)GET_TXBUFFER_DESC_ADDR_HIGH(pdesc, 1,
 963                                                                 dma64) << 32;
 964                         break;
 965                 default:
 966                         WARN_ONCE(true,
 967                                   "rtl8192ee: ERR txdesc :%d not processed\n",
 968                                   desc_name);
 969                         break;
 970                 }
 971         } else {
 972                 switch (desc_name) {
 973                 case HW_DESC_OWN:
 974                         ret = GET_RX_DESC_OWN(pdesc);
 975                         break;
 976                 case HW_DESC_RXPKT_LEN:
 977                         ret = GET_RX_DESC_PKT_LEN(pdesc);
 978                         break;
 979                 case HW_DESC_RXBUFF_ADDR:
 980                         ret = GET_RX_DESC_BUFF_ADDR(pdesc);
 981                         break;
 982                 default:
 983                         WARN_ONCE(true,
 984                                   "rtl8192ee: ERR rxdesc :%d not processed\n",
 985                                   desc_name);
 986                         break;
 987                 }
 988         }
 989         return ret;
 990 }
 991
 992 bool rtl92ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index)
 993 {
 994         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 995         struct rtl_priv *rtlpriv = rtl_priv(hw);
 996         u16 read_point, write_point;
 997         bool ret = false;
 998         static u8 stop_report_cnt;
 999         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
1000
1001         {
1002                 u16 cur_tx_rp, cur_tx_wp;
1003                 u32 tmpu32 = 0;
1004
1005                 tmpu32 =
1006                   rtl_read_dword(rtlpriv,
1007                                  get_desc_addr_fr_q_idx(hw_queue));
1008                 cur_tx_rp = (u16)((tmpu32 >> 16) & 0x0fff);
1009                 cur_tx_wp = (u16)(tmpu32 & 0x0fff);
1010
1011                 /* don't need to update ring->cur_tx_wp */
1012                 ring->cur_tx_rp = cur_tx_rp;
1013         }
1014
1015         read_point = ring->cur_tx_rp;
1016         write_point = ring->cur_tx_wp;
1017
1018         if (write_point > read_point) {
1019                 if (index < write_point && index >= read_point)
1020                         ret = false;
1021                 else
1022                         ret = true;
1023         } else if (write_point < read_point) {
1024                 if (index > write_point && index < read_point)
1025                         ret = true;
1026                 else
1027                         ret = false;
1028         } else {
1029                 if (index != read_point)
1030                         ret = true;
1031         }
1032
1033         if (hw_queue == BEACON_QUEUE)
1034                 ret = true;
1035
1036         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1037             rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS)
1038                 ret = true;
1039
1040         if (hw_queue < BEACON_QUEUE) {
1041                 if (!ret)
1042                         stop_report_cnt++;
1043                 else
1044                         stop_report_cnt = 0;
1045         }
1046
1047         return ret;
1048 }
1049
1050 void rtl92ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
1051 {
1052 }