drivers/net/wireless/realtek/rtw88/main.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2 /* Copyright(c) 2018-2019  Realtek Corporation
   3  */
   4
   5 #ifndef __RTK_MAIN_H_
   6 #define __RTK_MAIN_H_
   7
   8 #include <net/mac80211.h>
   9 #include <linux/vmalloc.h>
  10 #include <linux/firmware.h>
  11 #include <linux/average.h>
  12 #include <linux/bitops.h>
  13 #include <linux/bitfield.h>
  14
  15 #include "util.h"
  16
  17 #define RTW_MAX_MAC_ID_NUM              32
  18 #define RTW_MAX_SEC_CAM_NUM             32
  19
  20 #define RTW_WATCH_DOG_DELAY_TIME        round_jiffies_relative(HZ * 2)
  21
  22 #define RFREG_MASK                      0xfffff
  23 #define INV_RF_DATA                     0xffffffff
  24 #define TX_PAGE_SIZE_SHIFT              7
  25
  26 #define RTW_CHANNEL_WIDTH_MAX           3
  27 #define RTW_RF_PATH_MAX                 4
  28 #define HW_FEATURE_LEN                  13
  29
  30 extern unsigned int rtw_debug_mask;
  31 extern const struct ieee80211_ops rtw_ops;
  32 extern struct rtw_chip_info rtw8822b_hw_spec;
  33 extern struct rtw_chip_info rtw8822c_hw_spec;
  34
  35 #define RTW_MAX_CHANNEL_NUM_2G 14
  36 #define RTW_MAX_CHANNEL_NUM_5G 49
  37
  38 struct rtw_dev;
  39
  40 enum rtw_hci_type {
  41         RTW_HCI_TYPE_PCIE,
  42         RTW_HCI_TYPE_USB,
  43         RTW_HCI_TYPE_SDIO,
  44
  45         RTW_HCI_TYPE_UNDEFINE,
  46 };
  47
  48 struct rtw_hci {
  49         struct rtw_hci_ops *ops;
  50         enum rtw_hci_type type;
  51
  52         u32 rpwm_addr;
  53
  54         u8 bulkout_num;
  55 };
  56
  57 enum rtw_supported_band {
  58         RTW_BAND_2G = 1 << 0,
  59         RTW_BAND_5G = 1 << 1,
  60         RTW_BAND_60G = 1 << 2,
  61
  62         RTW_BAND_MAX,
  63 };
  64
  65 /* now, support upto 80M bw */
  66 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80
  67
  68 enum rtw_bandwidth {
  69         RTW_CHANNEL_WIDTH_20    = 0,
  70         RTW_CHANNEL_WIDTH_40    = 1,
  71         RTW_CHANNEL_WIDTH_80    = 2,
  72         RTW_CHANNEL_WIDTH_160   = 3,
  73         RTW_CHANNEL_WIDTH_80_80 = 4,
  74         RTW_CHANNEL_WIDTH_5     = 5,
  75         RTW_CHANNEL_WIDTH_10    = 6,
  76 };
  77
  78 enum rtw_net_type {
  79         RTW_NET_NO_LINK         = 0,
  80         RTW_NET_AD_HOC          = 1,
  81         RTW_NET_MGD_LINKED      = 2,
  82         RTW_NET_AP_MODE         = 3,
  83 };
  84
  85 enum rtw_rf_type {
  86         RF_1T1R                 = 0,
  87         RF_1T2R                 = 1,
  88         RF_2T2R                 = 2,
  89         RF_2T3R                 = 3,
  90         RF_2T4R                 = 4,
  91         RF_3T3R                 = 5,
  92         RF_3T4R                 = 6,
  93         RF_4T4R                 = 7,
  94         RF_TYPE_MAX,
  95 };
  96
  97 enum rtw_rf_path {
  98         RF_PATH_A = 0,
  99         RF_PATH_B = 1,
 100         RF_PATH_C = 2,
 101         RF_PATH_D = 3,
 102 };
 103
 104 enum rtw_bb_path {
 105         BB_PATH_A = BIT(0),
 106         BB_PATH_B = BIT(1),
 107         BB_PATH_C = BIT(2),
 108         BB_PATH_D = BIT(3),
 109
 110         BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
 111         BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
 112         BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
 113         BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
 114         BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
 115         BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
 116
 117         BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
 118         BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
 119         BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
 120         BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
 121
 122         BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
 123 };
 124
 125 enum rtw_rate_section {
 126         RTW_RATE_SECTION_CCK = 0,
 127         RTW_RATE_SECTION_OFDM,
 128         RTW_RATE_SECTION_HT_1S,
 129         RTW_RATE_SECTION_HT_2S,
 130         RTW_RATE_SECTION_VHT_1S,
 131         RTW_RATE_SECTION_VHT_2S,
 132
 133         /* keep last */
 134         RTW_RATE_SECTION_MAX,
 135 };
 136
 137 enum rtw_wireless_set {
 138         WIRELESS_CCK    = 0x00000001,
 139         WIRELESS_OFDM   = 0x00000002,
 140         WIRELESS_HT     = 0x00000004,
 141         WIRELESS_VHT    = 0x00000008,
 142 };
 143
 144 #define HT_STBC_EN      BIT(0)
 145 #define VHT_STBC_EN     BIT(1)
 146 #define HT_LDPC_EN      BIT(0)
 147 #define VHT_LDPC_EN     BIT(1)
 148
 149 enum rtw_chip_type {
 150         RTW_CHIP_TYPE_8822B,
 151         RTW_CHIP_TYPE_8822C,
 152 };
 153
 154 enum rtw_tx_queue_type {
 155         /* the order of AC queues matters */
 156         RTW_TX_QUEUE_BK = 0x0,
 157         RTW_TX_QUEUE_BE = 0x1,
 158         RTW_TX_QUEUE_VI = 0x2,
 159         RTW_TX_QUEUE_VO = 0x3,
 160
 161         RTW_TX_QUEUE_BCN = 0x4,
 162         RTW_TX_QUEUE_MGMT = 0x5,
 163         RTW_TX_QUEUE_HI0 = 0x6,
 164         RTW_TX_QUEUE_H2C = 0x7,
 165         /* keep it last */
 166         RTK_MAX_TX_QUEUE_NUM
 167 };
 168
 169 enum rtw_rx_queue_type {
 170         RTW_RX_QUEUE_MPDU = 0x0,
 171         RTW_RX_QUEUE_C2H = 0x1,
 172         /* keep it last */
 173         RTK_MAX_RX_QUEUE_NUM
 174 };
 175
 176 enum rtw_rate_index {
 177         RTW_RATEID_BGN_40M_2SS  = 0,
 178         RTW_RATEID_BGN_40M_1SS  = 1,
 179         RTW_RATEID_BGN_20M_2SS  = 2,
 180         RTW_RATEID_BGN_20M_1SS  = 3,
 181         RTW_RATEID_GN_N2SS      = 4,
 182         RTW_RATEID_GN_N1SS      = 5,
 183         RTW_RATEID_BG           = 6,
 184         RTW_RATEID_G            = 7,
 185         RTW_RATEID_B_20M        = 8,
 186         RTW_RATEID_ARFR0_AC_2SS = 9,
 187         RTW_RATEID_ARFR1_AC_1SS = 10,
 188         RTW_RATEID_ARFR2_AC_2G_1SS = 11,
 189         RTW_RATEID_ARFR3_AC_2G_2SS = 12,
 190         RTW_RATEID_ARFR4_AC_3SS = 13,
 191         RTW_RATEID_ARFR5_N_3SS  = 14,
 192         RTW_RATEID_ARFR7_N_4SS  = 15,
 193         RTW_RATEID_ARFR6_AC_4SS = 16
 194 };
 195
 196 enum rtw_trx_desc_rate {
 197         DESC_RATE1M     = 0x00,
 198         DESC_RATE2M     = 0x01,
 199         DESC_RATE5_5M   = 0x02,
 200         DESC_RATE11M    = 0x03,
 201
 202         DESC_RATE6M     = 0x04,
 203         DESC_RATE9M     = 0x05,
 204         DESC_RATE12M    = 0x06,
 205         DESC_RATE18M    = 0x07,
 206         DESC_RATE24M    = 0x08,
 207         DESC_RATE36M    = 0x09,
 208         DESC_RATE48M    = 0x0a,
 209         DESC_RATE54M    = 0x0b,
 210
 211         DESC_RATEMCS0   = 0x0c,
 212         DESC_RATEMCS1   = 0x0d,
 213         DESC_RATEMCS2   = 0x0e,
 214         DESC_RATEMCS3   = 0x0f,
 215         DESC_RATEMCS4   = 0x10,
 216         DESC_RATEMCS5   = 0x11,
 217         DESC_RATEMCS6   = 0x12,
 218         DESC_RATEMCS7   = 0x13,
 219         DESC_RATEMCS8   = 0x14,
 220         DESC_RATEMCS9   = 0x15,
 221         DESC_RATEMCS10  = 0x16,
 222         DESC_RATEMCS11  = 0x17,
 223         DESC_RATEMCS12  = 0x18,
 224         DESC_RATEMCS13  = 0x19,
 225         DESC_RATEMCS14  = 0x1a,
 226         DESC_RATEMCS15  = 0x1b,
 227         DESC_RATEMCS16  = 0x1c,
 228         DESC_RATEMCS17  = 0x1d,
 229         DESC_RATEMCS18  = 0x1e,
 230         DESC_RATEMCS19  = 0x1f,
 231         DESC_RATEMCS20  = 0x20,
 232         DESC_RATEMCS21  = 0x21,
 233         DESC_RATEMCS22  = 0x22,
 234         DESC_RATEMCS23  = 0x23,
 235         DESC_RATEMCS24  = 0x24,
 236         DESC_RATEMCS25  = 0x25,
 237         DESC_RATEMCS26  = 0x26,
 238         DESC_RATEMCS27  = 0x27,
 239         DESC_RATEMCS28  = 0x28,
 240         DESC_RATEMCS29  = 0x29,
 241         DESC_RATEMCS30  = 0x2a,
 242         DESC_RATEMCS31  = 0x2b,
 243
 244         DESC_RATEVHT1SS_MCS0    = 0x2c,
 245         DESC_RATEVHT1SS_MCS1    = 0x2d,
 246         DESC_RATEVHT1SS_MCS2    = 0x2e,
 247         DESC_RATEVHT1SS_MCS3    = 0x2f,
 248         DESC_RATEVHT1SS_MCS4    = 0x30,
 249         DESC_RATEVHT1SS_MCS5    = 0x31,
 250         DESC_RATEVHT1SS_MCS6    = 0x32,
 251         DESC_RATEVHT1SS_MCS7    = 0x33,
 252         DESC_RATEVHT1SS_MCS8    = 0x34,
 253         DESC_RATEVHT1SS_MCS9    = 0x35,
 254
 255         DESC_RATEVHT2SS_MCS0    = 0x36,
 256         DESC_RATEVHT2SS_MCS1    = 0x37,
 257         DESC_RATEVHT2SS_MCS2    = 0x38,
 258         DESC_RATEVHT2SS_MCS3    = 0x39,
 259         DESC_RATEVHT2SS_MCS4    = 0x3a,
 260         DESC_RATEVHT2SS_MCS5    = 0x3b,
 261         DESC_RATEVHT2SS_MCS6    = 0x3c,
 262         DESC_RATEVHT2SS_MCS7    = 0x3d,
 263         DESC_RATEVHT2SS_MCS8    = 0x3e,
 264         DESC_RATEVHT2SS_MCS9    = 0x3f,
 265
 266         DESC_RATEVHT3SS_MCS0    = 0x40,
 267         DESC_RATEVHT3SS_MCS1    = 0x41,
 268         DESC_RATEVHT3SS_MCS2    = 0x42,
 269         DESC_RATEVHT3SS_MCS3    = 0x43,
 270         DESC_RATEVHT3SS_MCS4    = 0x44,
 271         DESC_RATEVHT3SS_MCS5    = 0x45,
 272         DESC_RATEVHT3SS_MCS6    = 0x46,
 273         DESC_RATEVHT3SS_MCS7    = 0x47,
 274         DESC_RATEVHT3SS_MCS8    = 0x48,
 275         DESC_RATEVHT3SS_MCS9    = 0x49,
 276
 277         DESC_RATEVHT4SS_MCS0    = 0x4a,
 278         DESC_RATEVHT4SS_MCS1    = 0x4b,
 279         DESC_RATEVHT4SS_MCS2    = 0x4c,
 280         DESC_RATEVHT4SS_MCS3    = 0x4d,
 281         DESC_RATEVHT4SS_MCS4    = 0x4e,
 282         DESC_RATEVHT4SS_MCS5    = 0x4f,
 283         DESC_RATEVHT4SS_MCS6    = 0x50,
 284         DESC_RATEVHT4SS_MCS7    = 0x51,
 285         DESC_RATEVHT4SS_MCS8    = 0x52,
 286         DESC_RATEVHT4SS_MCS9    = 0x53,
 287
 288         DESC_RATE_MAX,
 289 };
 290
 291 enum rtw_regulatory_domains {
 292         RTW_REGD_FCC            = 0,
 293         RTW_REGD_MKK            = 1,
 294         RTW_REGD_ETSI           = 2,
 295         RTW_REGD_IC             = 3,
 296         RTW_REGD_KCC            = 4,
 297         RTW_REGD_ACMA           = 5,
 298         RTW_REGD_CHILE          = 6,
 299         RTW_REGD_UKRAINE        = 7,
 300         RTW_REGD_MEXICO         = 8,
 301         RTW_REGD_WW,
 302
 303         RTW_REGD_MAX
 304 };
 305
 306 enum rtw_flags {
 307         RTW_FLAG_RUNNING,
 308         RTW_FLAG_FW_RUNNING,
 309         RTW_FLAG_SCANNING,
 310         RTW_FLAG_INACTIVE_PS,
 311         RTW_FLAG_LEISURE_PS,
 312         RTW_FLAG_DIG_DISABLE,
 313         RTW_FLAG_BUSY_TRAFFIC,
 314
 315         NUM_OF_RTW_FLAGS,
 316 };
 317
 318 /* the power index is represented by differences, which cck-1s & ht40-1s are
 319  * the base values, so for 1s's differences, there are only ht20 & ofdm
 320  */
 321 struct rtw_2g_1s_pwr_idx_diff {
 322 #ifdef __LITTLE_ENDIAN
 323         s8 ofdm:4;
 324         s8 bw20:4;
 325 #else
 326         s8 bw20:4;
 327         s8 ofdm:4;
 328 #endif
 329 } __packed;
 330
 331 struct rtw_2g_ns_pwr_idx_diff {
 332 #ifdef __LITTLE_ENDIAN
 333         s8 bw20:4;
 334         s8 bw40:4;
 335         s8 cck:4;
 336         s8 ofdm:4;
 337 #else
 338         s8 ofdm:4;
 339         s8 cck:4;
 340         s8 bw40:4;
 341         s8 bw20:4;
 342 #endif
 343 } __packed;
 344
 345 struct rtw_2g_txpwr_idx {
 346         u8 cck_base[6];
 347         u8 bw40_base[5];
 348         struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
 349         struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
 350         struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
 351         struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
 352 };
 353
 354 struct rtw_5g_ht_1s_pwr_idx_diff {
 355 #ifdef __LITTLE_ENDIAN
 356         s8 ofdm:4;
 357         s8 bw20:4;
 358 #else
 359         s8 bw20:4;
 360         s8 ofdm:4;
 361 #endif
 362 } __packed;
 363
 364 struct rtw_5g_ht_ns_pwr_idx_diff {
 365 #ifdef __LITTLE_ENDIAN
 366         s8 bw20:4;
 367         s8 bw40:4;
 368 #else
 369         s8 bw40:4;
 370         s8 bw20:4;
 371 #endif
 372 } __packed;
 373
 374 struct rtw_5g_ofdm_ns_pwr_idx_diff {
 375 #ifdef __LITTLE_ENDIAN
 376         s8 ofdm_3s:4;
 377         s8 ofdm_2s:4;
 378         s8 ofdm_4s:4;
 379         s8 res:4;
 380 #else
 381         s8 res:4;
 382         s8 ofdm_4s:4;
 383         s8 ofdm_2s:4;
 384         s8 ofdm_3s:4;
 385 #endif
 386 } __packed;
 387
 388 struct rtw_5g_vht_ns_pwr_idx_diff {
 389 #ifdef __LITTLE_ENDIAN
 390         s8 bw160:4;
 391         s8 bw80:4;
 392 #else
 393         s8 bw80:4;
 394         s8 bw160:4;
 395 #endif
 396 } __packed;
 397
 398 struct rtw_5g_txpwr_idx {
 399         u8 bw40_base[14];
 400         struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
 401         struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
 402         struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
 403         struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
 404         struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
 405         struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
 406         struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
 407         struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
 408         struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
 409 };
 410
 411 struct rtw_txpwr_idx {
 412         struct rtw_2g_txpwr_idx pwr_idx_2g;
 413         struct rtw_5g_txpwr_idx pwr_idx_5g;
 414 };
 415
 416 struct rtw_timer_list {
 417         struct timer_list timer;
 418         void (*function)(void *data);
 419         void *args;
 420 };
 421
 422 struct rtw_channel_params {
 423         u8 center_chan;
 424         u8 bandwidth;
 425         u8 primary_chan_idx;
 426         /* center channel by different available bandwidth,
 427          * val of (bw > current bandwidth) is invalid
 428          */
 429         u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
 430 };
 431
 432 struct rtw_hw_reg {
 433         u32 addr;
 434         u32 mask;
 435 };
 436
 437 struct rtw_backup_info {
 438         u8 len;
 439         u32 reg;
 440         u32 val;
 441 };
 442
 443 enum rtw_vif_port_set {
 444         PORT_SET_MAC_ADDR       = BIT(0),
 445         PORT_SET_BSSID          = BIT(1),
 446         PORT_SET_NET_TYPE       = BIT(2),
 447         PORT_SET_AID            = BIT(3),
 448         PORT_SET_BCN_CTRL       = BIT(4),
 449 };
 450
 451 struct rtw_vif_port {
 452         struct rtw_hw_reg mac_addr;
 453         struct rtw_hw_reg bssid;
 454         struct rtw_hw_reg net_type;
 455         struct rtw_hw_reg aid;
 456         struct rtw_hw_reg bcn_ctrl;
 457 };
 458
 459 struct rtw_tx_pkt_info {
 460         u32 tx_pkt_size;
 461         u8 offset;
 462         u8 pkt_offset;
 463         u8 mac_id;
 464         u8 rate_id;
 465         u8 rate;
 466         u8 qsel;
 467         u8 bw;
 468         u8 sec_type;
 469         u8 sn;
 470         bool ampdu_en;
 471         u8 ampdu_factor;
 472         u8 ampdu_density;
 473         u16 seq;
 474         bool stbc;
 475         bool ldpc;
 476         bool dis_rate_fallback;
 477         bool bmc;
 478         bool use_rate;
 479         bool ls;
 480         bool fs;
 481         bool short_gi;
 482         bool report;
 483 };
 484
 485 struct rtw_rx_pkt_stat {
 486         bool phy_status;
 487         bool icv_err;
 488         bool crc_err;
 489         bool decrypted;
 490         bool is_c2h;
 491
 492         s32 signal_power;
 493         u16 pkt_len;
 494         u8 bw;
 495         u8 drv_info_sz;
 496         u8 shift;
 497         u8 rate;
 498         u8 mac_id;
 499         u8 cam_id;
 500         u8 ppdu_cnt;
 501         u32 tsf_low;
 502         s8 rx_power[RTW_RF_PATH_MAX];
 503         u8 rssi;
 504         u8 rxsc;
 505         struct rtw_sta_info *si;
 506         struct ieee80211_vif *vif;
 507 };
 508
 509 struct rtw_traffic_stats {
 510         /* units in bytes */
 511         u64 tx_unicast;
 512         u64 rx_unicast;
 513
 514         /* count for packets */
 515         u64 tx_cnt;
 516         u64 rx_cnt;
 517
 518         /* units in Mbps */
 519         u32 tx_throughput;
 520         u32 rx_throughput;
 521 };
 522
 523 enum rtw_lps_mode {
 524         RTW_MODE_ACTIVE = 0,
 525         RTW_MODE_LPS    = 1,
 526         RTW_MODE_WMM_PS = 2,
 527 };
 528
 529 enum rtw_pwr_state {
 530         RTW_RF_OFF      = 0x0,
 531         RTW_RF_ON       = 0x4,
 532         RTW_ALL_ON      = 0xc,
 533 };
 534
 535 struct rtw_lps_conf {
 536         /* the interface to enter lps */
 537         struct rtw_vif *rtwvif;
 538         enum rtw_lps_mode mode;
 539         enum rtw_pwr_state state;
 540         u8 awake_interval;
 541         u8 rlbm;
 542         u8 smart_ps;
 543         u8 port_id;
 544 };
 545
 546 enum rtw_hw_key_type {
 547         RTW_CAM_NONE    = 0,
 548         RTW_CAM_WEP40   = 1,
 549         RTW_CAM_TKIP    = 2,
 550         RTW_CAM_AES     = 4,
 551         RTW_CAM_WEP104  = 5,
 552 };
 553
 554 struct rtw_cam_entry {
 555         bool valid;
 556         bool group;
 557         u8 addr[ETH_ALEN];
 558         u8 hw_key_type;
 559         struct ieee80211_key_conf *key;
 560 };
 561
 562 struct rtw_sec_desc {
 563         /* search strategy */
 564         bool default_key_search;
 565
 566         u32 total_cam_num;
 567         struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
 568         DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
 569 };
 570
 571 struct rtw_tx_report {
 572         /* protect the tx report queue */
 573         spinlock_t q_lock;
 574         struct sk_buff_head queue;
 575         atomic_t sn;
 576         struct timer_list purge_timer;
 577 };
 578
 579 #define RTW_BC_MC_MACID 1
 580 DECLARE_EWMA(rssi, 10, 16);
 581
 582 struct rtw_sta_info {
 583         struct ieee80211_sta *sta;
 584         struct ieee80211_vif *vif;
 585
 586         struct ewma_rssi avg_rssi;
 587         u8 rssi_level;
 588
 589         u8 mac_id;
 590         u8 rate_id;
 591         enum rtw_bandwidth bw_mode;
 592         enum rtw_rf_type rf_type;
 593         enum rtw_wireless_set wireless_set;
 594         u8 stbc_en:2;
 595         u8 ldpc_en:2;
 596         bool sgi_enable;
 597         bool vht_enable;
 598         bool updated;
 599         u8 init_ra_lv;
 600         u64 ra_mask;
 601 };
 602
 603 struct rtw_vif {
 604         struct ieee80211_vif *vif;
 605         enum rtw_net_type net_type;
 606         u16 aid;
 607         u8 mac_addr[ETH_ALEN];
 608         u8 bssid[ETH_ALEN];
 609         u8 port;
 610         u8 bcn_ctrl;
 611         const struct rtw_vif_port *conf;
 612
 613         struct rtw_traffic_stats stats;
 614         bool in_lps;
 615 };
 616
 617 struct rtw_regulatory {
 618         char alpha2[2];
 619         u8 chplan;
 620         u8 txpwr_regd;
 621 };
 622
 623 struct rtw_chip_ops {
 624         int (*mac_init)(struct rtw_dev *rtwdev);
 625         int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
 626         void (*phy_set_param)(struct rtw_dev *rtwdev);
 627         void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
 628                             u8 bandwidth, u8 primary_chan_idx);
 629         void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc,
 630                               struct rtw_rx_pkt_stat *pkt_stat,
 631                               struct ieee80211_rx_status *rx_status);
 632         u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
 633                        u32 addr, u32 mask);
 634         bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
 635                          u32 addr, u32 mask, u32 data);
 636         void (*set_tx_power_index)(struct rtw_dev *rtwdev);
 637         int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
 638                               u32 size);
 639         void (*set_antenna)(struct rtw_dev *rtwdev, u8 antenna_tx,
 640                             u8 antenna_rx);
 641         void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
 642         void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
 643         void (*phy_calibration)(struct rtw_dev *rtwdev);
 644         void (*dpk_track)(struct rtw_dev *rtwdev);
 645         void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
 646
 647         /* for coex */
 648         void (*coex_set_init)(struct rtw_dev *rtwdev);
 649         void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
 650                                     u8 ctrl_type, u8 pos_type);
 651         void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
 652         void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
 653         void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
 654         void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
 655         void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
 656 };
 657
 658 #define RTW_PWR_POLLING_CNT     20000
 659
 660 #define RTW_PWR_CMD_READ        0x00
 661 #define RTW_PWR_CMD_WRITE       0x01
 662 #define RTW_PWR_CMD_POLLING     0x02
 663 #define RTW_PWR_CMD_DELAY       0x03
 664 #define RTW_PWR_CMD_END         0x04
 665
 666 /* define the base address of each block */
 667 #define RTW_PWR_ADDR_MAC        0x00
 668 #define RTW_PWR_ADDR_USB        0x01
 669 #define RTW_PWR_ADDR_PCIE       0x02
 670 #define RTW_PWR_ADDR_SDIO       0x03
 671
 672 #define RTW_PWR_INTF_SDIO_MSK   BIT(0)
 673 #define RTW_PWR_INTF_USB_MSK    BIT(1)
 674 #define RTW_PWR_INTF_PCI_MSK    BIT(2)
 675 #define RTW_PWR_INTF_ALL_MSK    (BIT(0) | BIT(1) | BIT(2) | BIT(3))
 676
 677 #define RTW_PWR_CUT_A_MSK       BIT(1)
 678 #define RTW_PWR_CUT_B_MSK       BIT(2)
 679 #define RTW_PWR_CUT_C_MSK       BIT(3)
 680 #define RTW_PWR_CUT_D_MSK       BIT(4)
 681 #define RTW_PWR_CUT_E_MSK       BIT(5)
 682 #define RTW_PWR_CUT_F_MSK       BIT(6)
 683 #define RTW_PWR_CUT_G_MSK       BIT(7)
 684 #define RTW_PWR_CUT_ALL_MSK     0xFF
 685
 686 enum rtw_pwr_seq_cmd_delay_unit {
 687         RTW_PWR_DELAY_US,
 688         RTW_PWR_DELAY_MS,
 689 };
 690
 691 struct rtw_pwr_seq_cmd {
 692         u16 offset;
 693         u8 cut_mask;
 694         u8 intf_mask;
 695         u8 base:4;
 696         u8 cmd:4;
 697         u8 mask;
 698         u8 value;
 699 };
 700
 701 enum rtw_chip_ver {
 702         RTW_CHIP_VER_CUT_A = 0x00,
 703         RTW_CHIP_VER_CUT_B = 0x01,
 704         RTW_CHIP_VER_CUT_C = 0x02,
 705         RTW_CHIP_VER_CUT_D = 0x03,
 706         RTW_CHIP_VER_CUT_E = 0x04,
 707         RTW_CHIP_VER_CUT_F = 0x05,
 708         RTW_CHIP_VER_CUT_G = 0x06,
 709 };
 710
 711 #define RTW_INTF_PHY_PLATFORM_ALL 0
 712
 713 enum rtw_intf_phy_cut {
 714         RTW_INTF_PHY_CUT_A = BIT(0),
 715         RTW_INTF_PHY_CUT_B = BIT(1),
 716         RTW_INTF_PHY_CUT_C = BIT(2),
 717         RTW_INTF_PHY_CUT_D = BIT(3),
 718         RTW_INTF_PHY_CUT_E = BIT(4),
 719         RTW_INTF_PHY_CUT_F = BIT(5),
 720         RTW_INTF_PHY_CUT_G = BIT(6),
 721         RTW_INTF_PHY_CUT_ALL = 0xFFFF,
 722 };
 723
 724 enum rtw_ip_sel {
 725         RTW_IP_SEL_PHY = 0,
 726         RTW_IP_SEL_MAC = 1,
 727         RTW_IP_SEL_DBI = 2,
 728
 729         RTW_IP_SEL_UNDEF = 0xFFFF
 730 };
 731
 732 enum rtw_pq_map_id {
 733         RTW_PQ_MAP_VO = 0x0,
 734         RTW_PQ_MAP_VI = 0x1,
 735         RTW_PQ_MAP_BE = 0x2,
 736         RTW_PQ_MAP_BK = 0x3,
 737         RTW_PQ_MAP_MG = 0x4,
 738         RTW_PQ_MAP_HI = 0x5,
 739         RTW_PQ_MAP_NUM = 0x6,
 740
 741         RTW_PQ_MAP_UNDEF,
 742 };
 743
 744 enum rtw_dma_mapping {
 745         RTW_DMA_MAPPING_EXTRA   = 0,
 746         RTW_DMA_MAPPING_LOW     = 1,
 747         RTW_DMA_MAPPING_NORMAL  = 2,
 748         RTW_DMA_MAPPING_HIGH    = 3,
 749
 750         RTW_DMA_MAPPING_UNDEF,
 751 };
 752
 753 struct rtw_rqpn {
 754         enum rtw_dma_mapping dma_map_vo;
 755         enum rtw_dma_mapping dma_map_vi;
 756         enum rtw_dma_mapping dma_map_be;
 757         enum rtw_dma_mapping dma_map_bk;
 758         enum rtw_dma_mapping dma_map_mg;
 759         enum rtw_dma_mapping dma_map_hi;
 760 };
 761
 762 struct rtw_page_table {
 763         u16 hq_num;
 764         u16 nq_num;
 765         u16 lq_num;
 766         u16 exq_num;
 767         u16 gapq_num;
 768 };
 769
 770 struct rtw_intf_phy_para {
 771         u16 offset;
 772         u16 value;
 773         u16 ip_sel;
 774         u16 cut_mask;
 775         u16 platform;
 776 };
 777
 778 struct rtw_intf_phy_para_table {
 779         struct rtw_intf_phy_para *usb2_para;
 780         struct rtw_intf_phy_para *usb3_para;
 781         struct rtw_intf_phy_para *gen1_para;
 782         struct rtw_intf_phy_para *gen2_para;
 783         u8 n_usb2_para;
 784         u8 n_usb3_para;
 785         u8 n_gen1_para;
 786         u8 n_gen2_para;
 787 };
 788
 789 struct rtw_table {
 790         const void *data;
 791         const u32 size;
 792         void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
 793         void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
 794                        u32 addr, u32 data);
 795         enum rtw_rf_path rf_path;
 796 };
 797
 798 static inline void rtw_load_table(struct rtw_dev *rtwdev,
 799                                   const struct rtw_table *tbl)
 800 {
 801         (*tbl->parse)(rtwdev, tbl);
 802 }
 803
 804 enum rtw_rfe_fem {
 805         RTW_RFE_IFEM,
 806         RTW_RFE_EFEM,
 807         RTW_RFE_IFEM2G_EFEM5G,
 808         RTW_RFE_NUM,
 809 };
 810
 811 struct rtw_rfe_def {
 812         const struct rtw_table *phy_pg_tbl;
 813         const struct rtw_table *txpwr_lmt_tbl;
 814 };
 815
 816 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) {                                \
 817         .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl,       \
 818         .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
 819         }
 820
 821 /* hardware configuration for each IC */
 822 struct rtw_chip_info {
 823         struct rtw_chip_ops *ops;
 824         u8 id;
 825
 826         const char *fw_name;
 827         u8 tx_pkt_desc_sz;
 828         u8 tx_buf_desc_sz;
 829         u8 rx_pkt_desc_sz;
 830         u8 rx_buf_desc_sz;
 831         u32 phy_efuse_size;
 832         u32 log_efuse_size;
 833         u32 ptct_efuse_size;
 834         u32 txff_size;
 835         u32 rxff_size;
 836         u8 band;
 837         u8 page_size;
 838         u8 csi_buf_pg_num;
 839         u8 dig_max;
 840         u8 dig_min;
 841         u8 txgi_factor;
 842         bool is_pwr_by_rate_dec;
 843         u8 max_power_index;
 844
 845         bool ht_supported;
 846         bool vht_supported;
 847
 848         /* init values */
 849         u8 sys_func_en;
 850         struct rtw_pwr_seq_cmd **pwr_on_seq;
 851         struct rtw_pwr_seq_cmd **pwr_off_seq;
 852         struct rtw_rqpn *rqpn_table;
 853         struct rtw_page_table *page_table;
 854         struct rtw_intf_phy_para_table *intf_table;
 855
 856         struct rtw_hw_reg *dig;
 857         u32 rf_base_addr[2];
 858         u32 rf_sipi_addr[2];
 859
 860         const struct rtw_table *mac_tbl;
 861         const struct rtw_table *agc_tbl;
 862         const struct rtw_table *bb_tbl;
 863         const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
 864         const struct rtw_table *rfk_init_tbl;
 865
 866         const struct rtw_rfe_def *rfe_defs;
 867         u32 rfe_defs_size;
 868
 869         bool en_dis_dpd;
 870         u16 dpd_ratemask;
 871
 872         /* coex paras */
 873         u32 coex_para_ver;
 874         u8 bt_desired_ver;
 875         bool scbd_support;
 876         bool new_scbd10_def; /* true: fix 2M(8822c) */
 877         u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
 878         u8 bt_rssi_type;
 879         u8 ant_isolation;
 880         u8 rssi_tolerance;
 881         u8 table_sant_num;
 882         u8 table_nsant_num;
 883         u8 tdma_sant_num;
 884         u8 tdma_nsant_num;
 885         u8 bt_afh_span_bw20;
 886         u8 bt_afh_span_bw40;
 887         u8 afh_5g_num;
 888         u8 wl_rf_para_num;
 889         const u8 *bt_rssi_step;
 890         const u8 *wl_rssi_step;
 891         const struct coex_table_para *table_nsant;
 892         const struct coex_table_para *table_sant;
 893         const struct coex_tdma_para *tdma_sant;
 894         const struct coex_tdma_para *tdma_nsant;
 895         const struct coex_rf_para *wl_rf_para_tx;
 896         const struct coex_rf_para *wl_rf_para_rx;
 897         const struct coex_5g_afh_map *afh_5g;
 898 };
 899
 900 enum rtw_coex_bt_state_cnt {
 901         COEX_CNT_BT_RETRY,
 902         COEX_CNT_BT_REINIT,
 903         COEX_CNT_BT_REENABLE,
 904         COEX_CNT_BT_POPEVENT,
 905         COEX_CNT_BT_SETUPLINK,
 906         COEX_CNT_BT_IGNWLANACT,
 907         COEX_CNT_BT_INQ,
 908         COEX_CNT_BT_PAGE,
 909         COEX_CNT_BT_ROLESWITCH,
 910         COEX_CNT_BT_AFHUPDATE,
 911         COEX_CNT_BT_INFOUPDATE,
 912         COEX_CNT_BT_IQK,
 913         COEX_CNT_BT_IQKFAIL,
 914
 915         COEX_CNT_BT_MAX
 916 };
 917
 918 enum rtw_coex_wl_state_cnt {
 919         COEX_CNT_WL_CONNPKT,
 920         COEX_CNT_WL_COEXRUN,
 921         COEX_CNT_WL_NOISY0,
 922         COEX_CNT_WL_NOISY1,
 923         COEX_CNT_WL_NOISY2,
 924         COEX_CNT_WL_5MS_NOEXTEND,
 925         COEX_CNT_WL_FW_NOTIFY,
 926
 927         COEX_CNT_WL_MAX
 928 };
 929
 930 struct rtw_coex_rfe {
 931         bool ant_switch_exist;
 932         bool ant_switch_diversity;
 933         bool ant_switch_with_bt;
 934         u8 rfe_module_type;
 935         u8 ant_switch_polarity;
 936
 937         /* true if WLG at BTG, else at WLAG */
 938         bool wlg_at_btg;
 939 };
 940
 941 struct rtw_coex_dm {
 942         bool cur_ps_tdma_on;
 943         bool cur_wl_rx_low_gain_en;
 944
 945         u8 reason;
 946         u8 bt_rssi_state[4];
 947         u8 wl_rssi_state[4];
 948         u8 wl_ch_info[3];
 949         u8 cur_ps_tdma;
 950         u8 cur_table;
 951         u8 ps_tdma_para[5];
 952         u8 cur_bt_pwr_lvl;
 953         u8 cur_bt_lna_lvl;
 954         u8 cur_wl_pwr_lvl;
 955         u8 bt_status;
 956         u32 cur_ant_pos_type;
 957         u32 cur_switch_status;
 958         u32 setting_tdma;
 959 };
 960
 961 #define COEX_BTINFO_SRC_WL_FW   0x0
 962 #define COEX_BTINFO_SRC_BT_RSP  0x1
 963 #define COEX_BTINFO_SRC_BT_ACT  0x2
 964 #define COEX_BTINFO_SRC_BT_IQK  0x3
 965 #define COEX_BTINFO_SRC_BT_SCBD 0x4
 966 #define COEX_BTINFO_SRC_MAX     0x5
 967
 968 #define COEX_INFO_FTP           BIT(7)
 969 #define COEX_INFO_A2DP          BIT(6)
 970 #define COEX_INFO_HID           BIT(5)
 971 #define COEX_INFO_SCO_BUSY      BIT(4)
 972 #define COEX_INFO_ACL_BUSY      BIT(3)
 973 #define COEX_INFO_INQ_PAGE      BIT(2)
 974 #define COEX_INFO_SCO_ESCO      BIT(1)
 975 #define COEX_INFO_CONNECTION    BIT(0)
 976 #define COEX_BTINFO_LENGTH_MAX  10
 977
 978 struct rtw_coex_stat {
 979         bool bt_disabled;
 980         bool bt_disabled_pre;
 981         bool bt_link_exist;
 982         bool bt_whck_test;
 983         bool bt_inq_page;
 984         bool bt_inq;
 985         bool bt_page;
 986         bool bt_ble_voice;
 987         bool bt_ble_exist;
 988         bool bt_hfp_exist;
 989         bool bt_a2dp_exist;
 990         bool bt_hid_exist;
 991         bool bt_pan_exist; /* PAN or OPP */
 992         bool bt_opp_exist; /* OPP only */
 993         bool bt_acl_busy;
 994         bool bt_fix_2M;
 995         bool bt_setup_link;
 996         bool bt_multi_link;
 997         bool bt_a2dp_sink;
 998         bool bt_a2dp_active;
 999         bool bt_reenable;
1000         bool bt_ble_scan_en;
1001         bool bt_init_scan;
1002         bool bt_slave;
1003         bool bt_418_hid_exist;
1004         bool bt_mailbox_reply;
1005
1006         bool wl_under_lps;
1007         bool wl_under_ips;
1008         bool wl_hi_pri_task1;
1009         bool wl_hi_pri_task2;
1010         bool wl_force_lps_ctrl;
1011         bool wl_gl_busy;
1012         bool wl_linkscan_proc;
1013         bool wl_ps_state_fail;
1014         bool wl_tx_limit_en;
1015         bool wl_ampdu_limit_en;
1016         bool wl_connected;
1017         bool wl_slot_extend;
1018         bool wl_cck_lock;
1019         bool wl_cck_lock_pre;
1020         bool wl_cck_lock_ever;
1021
1022         u32 bt_supported_version;
1023         u32 bt_supported_feature;
1024         s8 bt_rssi;
1025         u8 kt_ver;
1026         u8 gnt_workaround_state;
1027         u8 tdma_timer_base;
1028         u8 bt_profile_num;
1029         u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
1030         u8 bt_info_lb2;
1031         u8 bt_info_lb3;
1032         u8 bt_info_hb0;
1033         u8 bt_info_hb1;
1034         u8 bt_info_hb2;
1035         u8 bt_info_hb3;
1036         u8 bt_ble_scan_type;
1037         u8 bt_hid_pair_num;
1038         u8 bt_hid_slot;
1039         u8 bt_a2dp_bitpool;
1040         u8 bt_iqk_state;
1041
1042         u8 wl_noisy_level;
1043         u8 wl_fw_dbg_info[10];
1044         u8 wl_fw_dbg_info_pre[10];
1045         u8 wl_coex_mode;
1046         u8 ampdu_max_time;
1047         u8 wl_tput_dir;
1048
1049         u16 score_board;
1050         u16 retry_limit;
1051
1052         /* counters to record bt states */
1053         u32 cnt_bt[COEX_CNT_BT_MAX];
1054
1055         /* counters to record wifi states */
1056         u32 cnt_wl[COEX_CNT_WL_MAX];
1057
1058         u32 darfrc;
1059         u32 darfrch;
1060 };
1061
1062 struct rtw_coex {
1063         /* protects coex info request section */
1064         struct mutex mutex;
1065         struct sk_buff_head queue;
1066         wait_queue_head_t wait;
1067
1068         bool under_5g;
1069         bool stop_dm;
1070         bool freeze;
1071         bool freerun;
1072         bool wl_rf_off;
1073
1074         struct rtw_coex_stat stat;
1075         struct rtw_coex_dm dm;
1076         struct rtw_coex_rfe rfe;
1077
1078         struct delayed_work bt_relink_work;
1079         struct delayed_work bt_reenable_work;
1080         struct delayed_work defreeze_work;
1081 };
1082
1083 #define DPK_RF_REG_NUM 7
1084 #define DPK_RF_PATH_NUM 2
1085 #define DPK_BB_REG_NUM 18
1086 #define DPK_CHANNEL_WIDTH_80 1
1087
1088 DECLARE_EWMA(thermal, 10, 4);
1089
1090 struct rtw_dpk_info {
1091         bool is_dpk_pwr_on;
1092         bool is_reload;
1093
1094         DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM);
1095
1096         u8 thermal_dpk[DPK_RF_PATH_NUM];
1097         struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM];
1098
1099         u32 gnt_control;
1100         u32 gnt_value;
1101
1102         u8 result[RTW_RF_PATH_MAX];
1103         u8 dpk_txagc[RTW_RF_PATH_MAX];
1104         u32 coef[RTW_RF_PATH_MAX][20];
1105         u16 dpk_gs[RTW_RF_PATH_MAX];
1106         u8 thermal_dpk_delta[RTW_RF_PATH_MAX];
1107         u8 pre_pwsf[RTW_RF_PATH_MAX];
1108
1109         u8 dpk_band;
1110         u8 dpk_ch;
1111         u8 dpk_bw;
1112 };
1113
1114 struct rtw_phy_cck_pd_reg {
1115         u32 reg_pd;
1116         u32 mask_pd;
1117         u32 reg_cs;
1118         u32 mask_cs;
1119 };
1120
1121 #define DACK_MSBK_BACKUP_NUM    0xf
1122 #define DACK_DCK_BACKUP_NUM     0x2
1123
1124 struct rtw_dm_info {
1125         u32 cck_fa_cnt;
1126         u32 ofdm_fa_cnt;
1127         u32 total_fa_cnt;
1128
1129         u32 cck_ok_cnt;
1130         u32 cck_err_cnt;
1131         u32 ofdm_ok_cnt;
1132         u32 ofdm_err_cnt;
1133         u32 ht_ok_cnt;
1134         u32 ht_err_cnt;
1135         u32 vht_ok_cnt;
1136         u32 vht_err_cnt;
1137
1138         u8 min_rssi;
1139         u8 pre_min_rssi;
1140         u16 fa_history[4];
1141         u8 igi_history[4];
1142         u8 igi_bitmap;
1143         bool damping;
1144         u8 damping_cnt;
1145         u8 damping_rssi;
1146
1147         u8 cck_gi_u_bnd;
1148         u8 cck_gi_l_bnd;
1149
1150         /* backup dack results for each path and I/Q */
1151         u32 dack_adck[RTW_RF_PATH_MAX];
1152         u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM];
1153         u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM];
1154
1155         struct rtw_dpk_info dpk_info;
1156
1157         /* [bandwidth 0:20M/1:40M][number of path] */
1158         u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
1159         u32 cck_fa_avg;
1160 };
1161
1162 struct rtw_efuse {
1163         u32 size;
1164         u32 physical_size;
1165         u32 logical_size;
1166         u32 protect_size;
1167
1168         u8 addr[ETH_ALEN];
1169         u8 channel_plan;
1170         u8 country_code[2];
1171         u8 rf_board_option;
1172         u8 rfe_option;
1173         u8 thermal_meter;
1174         u8 crystal_cap;
1175         u8 ant_div_cfg;
1176         u8 ant_div_type;
1177         u8 regd;
1178
1179         u8 lna_type_2g;
1180         u8 lna_type_5g;
1181         u8 glna_type;
1182         u8 alna_type;
1183         bool ext_lna_2g;
1184         bool ext_lna_5g;
1185         u8 pa_type_2g;
1186         u8 pa_type_5g;
1187         u8 gpa_type;
1188         u8 apa_type;
1189         bool ext_pa_2g;
1190         bool ext_pa_5g;
1191
1192         bool btcoex;
1193         /* bt share antenna with wifi */
1194         bool share_ant;
1195         u8 bt_setting;
1196
1197         struct {
1198                 u8 hci;
1199                 u8 bw;
1200                 u8 ptcl;
1201                 u8 nss;
1202                 u8 ant_num;
1203         } hw_cap;
1204
1205         struct rtw_txpwr_idx txpwr_idx_table[4];
1206 };
1207
1208 struct rtw_phy_cond {
1209 #ifdef __LITTLE_ENDIAN
1210         u32 rfe:8;
1211         u32 intf:4;
1212         u32 pkg:4;
1213         u32 plat:4;
1214         u32 intf_rsvd:4;
1215         u32 cut:4;
1216         u32 branch:2;
1217         u32 neg:1;
1218         u32 pos:1;
1219 #else
1220         u32 pos:1;
1221         u32 neg:1;
1222         u32 branch:2;
1223         u32 cut:4;
1224         u32 intf_rsvd:4;
1225         u32 plat:4;
1226         u32 pkg:4;
1227         u32 intf:4;
1228         u32 rfe:8;
1229 #endif
1230         /* for intf:4 */
1231         #define INTF_PCIE       BIT(0)
1232         #define INTF_USB        BIT(1)
1233         #define INTF_SDIO       BIT(2)
1234         /* for branch:2 */
1235         #define BRANCH_IF       0
1236         #define BRANCH_ELIF     1
1237         #define BRANCH_ELSE     2
1238         #define BRANCH_ENDIF    3
1239 };
1240
1241 struct rtw_fifo_conf {
1242         /* tx fifo information */
1243         u16 rsvd_boundary;
1244         u16 rsvd_pg_num;
1245         u16 rsvd_drv_pg_num;
1246         u16 txff_pg_num;
1247         u16 acq_pg_num;
1248         u16 rsvd_drv_addr;
1249         u16 rsvd_h2c_info_addr;
1250         u16 rsvd_h2c_sta_info_addr;
1251         u16 rsvd_h2cq_addr;
1252         u16 rsvd_cpu_instr_addr;
1253         u16 rsvd_fw_txbuf_addr;
1254         u16 rsvd_csibuf_addr;
1255         enum rtw_dma_mapping pq_map[RTW_PQ_MAP_NUM];
1256 };
1257
1258 struct rtw_fw_state {
1259         const struct firmware *firmware;
1260         struct completion completion;
1261         u16 version;
1262         u8 sub_version;
1263         u8 sub_index;
1264         u16 h2c_version;
1265 };
1266
1267 struct rtw_hal {
1268         u32 rcr;
1269
1270         u32 chip_version;
1271         u8 fab_version;
1272         u8 cut_version;
1273         u8 mp_chip;
1274         u8 oem_id;
1275         struct rtw_phy_cond phy_cond;
1276
1277         u8 ps_mode;
1278         u8 current_channel;
1279         u8 current_band_width;
1280         u8 current_band_type;
1281
1282         /* center channel for different available bandwidth,
1283          * val of (bw > current_band_width) is invalid
1284          */
1285         u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
1286
1287         u8 sec_ch_offset;
1288         u8 rf_type;
1289         u8 rf_path_num;
1290         u8 antenna_tx;
1291         u8 antenna_rx;
1292
1293         /* protect tx power section */
1294         struct mutex tx_power_mutex;
1295         s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
1296                                    [DESC_RATE_MAX];
1297         s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
1298                                    [DESC_RATE_MAX];
1299         s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
1300                                  [RTW_RATE_SECTION_MAX];
1301         s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
1302                                  [RTW_RATE_SECTION_MAX];
1303         s8 tx_pwr_limit_2g[RTW_REGD_MAX]
1304                           [RTW_CHANNEL_WIDTH_MAX]
1305                           [RTW_RATE_SECTION_MAX]
1306                           [RTW_MAX_CHANNEL_NUM_2G];
1307         s8 tx_pwr_limit_5g[RTW_REGD_MAX]
1308                           [RTW_CHANNEL_WIDTH_MAX]
1309                           [RTW_RATE_SECTION_MAX]
1310                           [RTW_MAX_CHANNEL_NUM_5G];
1311         s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
1312                      [DESC_RATE_MAX];
1313 };
1314
1315 struct rtw_dev {
1316         struct ieee80211_hw *hw;
1317         struct device *dev;
1318
1319         struct rtw_hci hci;
1320
1321         struct rtw_chip_info *chip;
1322         struct rtw_hal hal;
1323         struct rtw_fifo_conf fifo;
1324         struct rtw_fw_state fw;
1325         struct rtw_efuse efuse;
1326         struct rtw_sec_desc sec;
1327         struct rtw_traffic_stats stats;
1328         struct rtw_regulatory regd;
1329
1330         struct rtw_dm_info dm_info;
1331         struct rtw_coex coex;
1332
1333         /* ensures exclusive access from mac80211 callbacks */
1334         struct mutex mutex;
1335
1336         /* lock for dm to use */
1337         spinlock_t dm_lock;
1338
1339         /* read/write rf register */
1340         spinlock_t rf_lock;
1341
1342         /* watch dog every 2 sec */
1343         struct delayed_work watch_dog_work;
1344         u32 watch_dog_cnt;
1345
1346         struct list_head rsvd_page_list;
1347
1348         /* c2h cmd queue & handler work */
1349         struct sk_buff_head c2h_queue;
1350         struct work_struct c2h_work;
1351
1352         struct rtw_tx_report tx_report;
1353
1354         struct {
1355                 /* incicate the mail box to use with fw */
1356                 u8 last_box_num;
1357                 /* protect to send h2c to fw */
1358                 spinlock_t lock;
1359                 u32 seq;
1360         } h2c;
1361
1362         /* lps power state & handler work */
1363         struct rtw_lps_conf lps_conf;
1364
1365         struct dentry *debugfs;
1366
1367         u8 sta_cnt;
1368
1369         DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
1370         DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
1371
1372         u8 mp_mode;
1373
1374         /* hci related data, must be last */
1375         u8 priv[0] __aligned(sizeof(void *));
1376 };
1377
1378 #include "hci.h"
1379
1380 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev)
1381 {
1382         return !!rtwdev->sta_cnt;
1383 }
1384
1385 void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
1386                             struct rtw_channel_params *ch_param);
1387 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
1388 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
1389 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
1390 void rtw_restore_reg(struct rtw_dev *rtwdev,
1391                      struct rtw_backup_info *bckp, u32 num);
1392 void rtw_set_channel(struct rtw_dev *rtwdev);
1393 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
1394                          u32 config);
1395 void rtw_tx_report_purge_timer(struct timer_list *t);
1396 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
1397 int rtw_core_start(struct rtw_dev *rtwdev);
1398 void rtw_core_stop(struct rtw_dev *rtwdev);
1399 int rtw_chip_info_setup(struct rtw_dev *rtwdev);
1400 int rtw_core_init(struct rtw_dev *rtwdev);
1401 void rtw_core_deinit(struct rtw_dev *rtwdev);
1402 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
1403 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
1404
1405 #endif