1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
8 #include <net/mac80211.h>
9 #include <linux/vmalloc.h>
10 #include <linux/firmware.h>
11 #include <linux/average.h>
12 #include <linux/bitops.h>
13 #include <linux/bitfield.h>
17 #define RTW_MAX_MAC_ID_NUM 32
18 #define RTW_MAX_SEC_CAM_NUM 32
20 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2)
22 #define RFREG_MASK 0xfffff
23 #define INV_RF_DATA 0xffffffff
24 #define TX_PAGE_SIZE_SHIFT 7
26 #define RTW_CHANNEL_WIDTH_MAX 3
27 #define RTW_RF_PATH_MAX 4
28 #define HW_FEATURE_LEN 13
30 extern unsigned int rtw_debug_mask;
31 extern const struct ieee80211_ops rtw_ops;
32 extern struct rtw_chip_info rtw8822b_hw_spec;
33 extern struct rtw_chip_info rtw8822c_hw_spec;
35 #define RTW_MAX_CHANNEL_NUM_2G 14
36 #define RTW_MAX_CHANNEL_NUM_5G 49
45 RTW_HCI_TYPE_UNDEFINE,
49 struct rtw_hci_ops *ops;
50 enum rtw_hci_type type;
57 enum rtw_supported_band {
60 RTW_BAND_60G = 1 << 2,
65 /* now, support upto 80M bw */
66 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80
69 RTW_CHANNEL_WIDTH_20 = 0,
70 RTW_CHANNEL_WIDTH_40 = 1,
71 RTW_CHANNEL_WIDTH_80 = 2,
72 RTW_CHANNEL_WIDTH_160 = 3,
73 RTW_CHANNEL_WIDTH_80_80 = 4,
74 RTW_CHANNEL_WIDTH_5 = 5,
75 RTW_CHANNEL_WIDTH_10 = 6,
81 RTW_NET_MGD_LINKED = 2,
110 BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
111 BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
112 BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
113 BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
114 BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
115 BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
117 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
118 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
119 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
120 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
122 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
125 enum rtw_rate_section {
126 RTW_RATE_SECTION_CCK = 0,
127 RTW_RATE_SECTION_OFDM,
128 RTW_RATE_SECTION_HT_1S,
129 RTW_RATE_SECTION_HT_2S,
130 RTW_RATE_SECTION_VHT_1S,
131 RTW_RATE_SECTION_VHT_2S,
134 RTW_RATE_SECTION_MAX,
137 enum rtw_wireless_set {
138 WIRELESS_CCK = 0x00000001,
139 WIRELESS_OFDM = 0x00000002,
140 WIRELESS_HT = 0x00000004,
141 WIRELESS_VHT = 0x00000008,
144 #define HT_STBC_EN BIT(0)
145 #define VHT_STBC_EN BIT(1)
146 #define HT_LDPC_EN BIT(0)
147 #define VHT_LDPC_EN BIT(1)
154 enum rtw_tx_queue_type {
155 /* the order of AC queues matters */
156 RTW_TX_QUEUE_BK = 0x0,
157 RTW_TX_QUEUE_BE = 0x1,
158 RTW_TX_QUEUE_VI = 0x2,
159 RTW_TX_QUEUE_VO = 0x3,
161 RTW_TX_QUEUE_BCN = 0x4,
162 RTW_TX_QUEUE_MGMT = 0x5,
163 RTW_TX_QUEUE_HI0 = 0x6,
164 RTW_TX_QUEUE_H2C = 0x7,
169 enum rtw_rx_queue_type {
170 RTW_RX_QUEUE_MPDU = 0x0,
171 RTW_RX_QUEUE_C2H = 0x1,
176 enum rtw_rate_index {
177 RTW_RATEID_BGN_40M_2SS = 0,
178 RTW_RATEID_BGN_40M_1SS = 1,
179 RTW_RATEID_BGN_20M_2SS = 2,
180 RTW_RATEID_BGN_20M_1SS = 3,
181 RTW_RATEID_GN_N2SS = 4,
182 RTW_RATEID_GN_N1SS = 5,
185 RTW_RATEID_B_20M = 8,
186 RTW_RATEID_ARFR0_AC_2SS = 9,
187 RTW_RATEID_ARFR1_AC_1SS = 10,
188 RTW_RATEID_ARFR2_AC_2G_1SS = 11,
189 RTW_RATEID_ARFR3_AC_2G_2SS = 12,
190 RTW_RATEID_ARFR4_AC_3SS = 13,
191 RTW_RATEID_ARFR5_N_3SS = 14,
192 RTW_RATEID_ARFR7_N_4SS = 15,
193 RTW_RATEID_ARFR6_AC_4SS = 16
196 enum rtw_trx_desc_rate {
199 DESC_RATE5_5M = 0x02,
211 DESC_RATEMCS0 = 0x0c,
212 DESC_RATEMCS1 = 0x0d,
213 DESC_RATEMCS2 = 0x0e,
214 DESC_RATEMCS3 = 0x0f,
215 DESC_RATEMCS4 = 0x10,
216 DESC_RATEMCS5 = 0x11,
217 DESC_RATEMCS6 = 0x12,
218 DESC_RATEMCS7 = 0x13,
219 DESC_RATEMCS8 = 0x14,
220 DESC_RATEMCS9 = 0x15,
221 DESC_RATEMCS10 = 0x16,
222 DESC_RATEMCS11 = 0x17,
223 DESC_RATEMCS12 = 0x18,
224 DESC_RATEMCS13 = 0x19,
225 DESC_RATEMCS14 = 0x1a,
226 DESC_RATEMCS15 = 0x1b,
227 DESC_RATEMCS16 = 0x1c,
228 DESC_RATEMCS17 = 0x1d,
229 DESC_RATEMCS18 = 0x1e,
230 DESC_RATEMCS19 = 0x1f,
231 DESC_RATEMCS20 = 0x20,
232 DESC_RATEMCS21 = 0x21,
233 DESC_RATEMCS22 = 0x22,
234 DESC_RATEMCS23 = 0x23,
235 DESC_RATEMCS24 = 0x24,
236 DESC_RATEMCS25 = 0x25,
237 DESC_RATEMCS26 = 0x26,
238 DESC_RATEMCS27 = 0x27,
239 DESC_RATEMCS28 = 0x28,
240 DESC_RATEMCS29 = 0x29,
241 DESC_RATEMCS30 = 0x2a,
242 DESC_RATEMCS31 = 0x2b,
244 DESC_RATEVHT1SS_MCS0 = 0x2c,
245 DESC_RATEVHT1SS_MCS1 = 0x2d,
246 DESC_RATEVHT1SS_MCS2 = 0x2e,
247 DESC_RATEVHT1SS_MCS3 = 0x2f,
248 DESC_RATEVHT1SS_MCS4 = 0x30,
249 DESC_RATEVHT1SS_MCS5 = 0x31,
250 DESC_RATEVHT1SS_MCS6 = 0x32,
251 DESC_RATEVHT1SS_MCS7 = 0x33,
252 DESC_RATEVHT1SS_MCS8 = 0x34,
253 DESC_RATEVHT1SS_MCS9 = 0x35,
255 DESC_RATEVHT2SS_MCS0 = 0x36,
256 DESC_RATEVHT2SS_MCS1 = 0x37,
257 DESC_RATEVHT2SS_MCS2 = 0x38,
258 DESC_RATEVHT2SS_MCS3 = 0x39,
259 DESC_RATEVHT2SS_MCS4 = 0x3a,
260 DESC_RATEVHT2SS_MCS5 = 0x3b,
261 DESC_RATEVHT2SS_MCS6 = 0x3c,
262 DESC_RATEVHT2SS_MCS7 = 0x3d,
263 DESC_RATEVHT2SS_MCS8 = 0x3e,
264 DESC_RATEVHT2SS_MCS9 = 0x3f,
266 DESC_RATEVHT3SS_MCS0 = 0x40,
267 DESC_RATEVHT3SS_MCS1 = 0x41,
268 DESC_RATEVHT3SS_MCS2 = 0x42,
269 DESC_RATEVHT3SS_MCS3 = 0x43,
270 DESC_RATEVHT3SS_MCS4 = 0x44,
271 DESC_RATEVHT3SS_MCS5 = 0x45,
272 DESC_RATEVHT3SS_MCS6 = 0x46,
273 DESC_RATEVHT3SS_MCS7 = 0x47,
274 DESC_RATEVHT3SS_MCS8 = 0x48,
275 DESC_RATEVHT3SS_MCS9 = 0x49,
277 DESC_RATEVHT4SS_MCS0 = 0x4a,
278 DESC_RATEVHT4SS_MCS1 = 0x4b,
279 DESC_RATEVHT4SS_MCS2 = 0x4c,
280 DESC_RATEVHT4SS_MCS3 = 0x4d,
281 DESC_RATEVHT4SS_MCS4 = 0x4e,
282 DESC_RATEVHT4SS_MCS5 = 0x4f,
283 DESC_RATEVHT4SS_MCS6 = 0x50,
284 DESC_RATEVHT4SS_MCS7 = 0x51,
285 DESC_RATEVHT4SS_MCS8 = 0x52,
286 DESC_RATEVHT4SS_MCS9 = 0x53,
291 enum rtw_regulatory_domains {
299 RTW_REGD_UKRAINE = 7,
310 RTW_FLAG_INACTIVE_PS,
312 RTW_FLAG_DIG_DISABLE,
313 RTW_FLAG_BUSY_TRAFFIC,
318 /* the power index is represented by differences, which cck-1s & ht40-1s are
319 * the base values, so for 1s's differences, there are only ht20 & ofdm
321 struct rtw_2g_1s_pwr_idx_diff {
322 #ifdef __LITTLE_ENDIAN
331 struct rtw_2g_ns_pwr_idx_diff {
332 #ifdef __LITTLE_ENDIAN
345 struct rtw_2g_txpwr_idx {
348 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
349 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
350 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
351 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
354 struct rtw_5g_ht_1s_pwr_idx_diff {
355 #ifdef __LITTLE_ENDIAN
364 struct rtw_5g_ht_ns_pwr_idx_diff {
365 #ifdef __LITTLE_ENDIAN
374 struct rtw_5g_ofdm_ns_pwr_idx_diff {
375 #ifdef __LITTLE_ENDIAN
388 struct rtw_5g_vht_ns_pwr_idx_diff {
389 #ifdef __LITTLE_ENDIAN
398 struct rtw_5g_txpwr_idx {
400 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
401 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
402 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
403 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
404 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
405 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
406 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
407 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
408 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
411 struct rtw_txpwr_idx {
412 struct rtw_2g_txpwr_idx pwr_idx_2g;
413 struct rtw_5g_txpwr_idx pwr_idx_5g;
416 struct rtw_timer_list {
417 struct timer_list timer;
418 void (*function)(void *data);
422 struct rtw_channel_params {
426 /* center channel by different available bandwidth,
427 * val of (bw > current bandwidth) is invalid
429 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
437 struct rtw_backup_info {
443 enum rtw_vif_port_set {
444 PORT_SET_MAC_ADDR = BIT(0),
445 PORT_SET_BSSID = BIT(1),
446 PORT_SET_NET_TYPE = BIT(2),
447 PORT_SET_AID = BIT(3),
448 PORT_SET_BCN_CTRL = BIT(4),
451 struct rtw_vif_port {
452 struct rtw_hw_reg mac_addr;
453 struct rtw_hw_reg bssid;
454 struct rtw_hw_reg net_type;
455 struct rtw_hw_reg aid;
456 struct rtw_hw_reg bcn_ctrl;
459 struct rtw_tx_pkt_info {
476 bool dis_rate_fallback;
485 struct rtw_rx_pkt_stat {
502 s8 rx_power[RTW_RF_PATH_MAX];
505 struct rtw_sta_info *si;
506 struct ieee80211_vif *vif;
509 struct rtw_traffic_stats {
514 /* count for packets */
535 struct rtw_lps_conf {
536 enum rtw_lps_mode mode;
537 enum rtw_pwr_state state;
544 enum rtw_hw_key_type {
552 struct rtw_cam_entry {
557 struct ieee80211_key_conf *key;
560 struct rtw_sec_desc {
561 /* search strategy */
562 bool default_key_search;
565 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
566 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
569 struct rtw_tx_report {
570 /* protect the tx report queue */
572 struct sk_buff_head queue;
574 struct timer_list purge_timer;
577 #define RTW_BC_MC_MACID 1
578 DECLARE_EWMA(rssi, 10, 16);
580 struct rtw_sta_info {
581 struct ieee80211_sta *sta;
582 struct ieee80211_vif *vif;
584 struct ewma_rssi avg_rssi;
589 enum rtw_bandwidth bw_mode;
590 enum rtw_rf_type rf_type;
591 enum rtw_wireless_set wireless_set;
602 struct ieee80211_vif *vif;
603 enum rtw_net_type net_type;
605 u8 mac_addr[ETH_ALEN];
609 const struct rtw_vif_port *conf;
611 struct rtw_traffic_stats stats;
615 struct rtw_regulatory {
621 struct rtw_chip_ops {
622 int (*mac_init)(struct rtw_dev *rtwdev);
623 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
624 void (*phy_set_param)(struct rtw_dev *rtwdev);
625 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
626 u8 bandwidth, u8 primary_chan_idx);
627 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc,
628 struct rtw_rx_pkt_stat *pkt_stat,
629 struct ieee80211_rx_status *rx_status);
630 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
632 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
633 u32 addr, u32 mask, u32 data);
634 void (*set_tx_power_index)(struct rtw_dev *rtwdev);
635 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
637 void (*set_antenna)(struct rtw_dev *rtwdev, u8 antenna_tx,
639 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
640 void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
641 void (*phy_calibration)(struct rtw_dev *rtwdev);
642 void (*dpk_track)(struct rtw_dev *rtwdev);
643 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
646 void (*coex_set_init)(struct rtw_dev *rtwdev);
647 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
648 u8 ctrl_type, u8 pos_type);
649 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
650 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
651 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
652 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
653 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
656 #define RTW_PWR_POLLING_CNT 20000
658 #define RTW_PWR_CMD_READ 0x00
659 #define RTW_PWR_CMD_WRITE 0x01
660 #define RTW_PWR_CMD_POLLING 0x02
661 #define RTW_PWR_CMD_DELAY 0x03
662 #define RTW_PWR_CMD_END 0x04
664 /* define the base address of each block */
665 #define RTW_PWR_ADDR_MAC 0x00
666 #define RTW_PWR_ADDR_USB 0x01
667 #define RTW_PWR_ADDR_PCIE 0x02
668 #define RTW_PWR_ADDR_SDIO 0x03
670 #define RTW_PWR_INTF_SDIO_MSK BIT(0)
671 #define RTW_PWR_INTF_USB_MSK BIT(1)
672 #define RTW_PWR_INTF_PCI_MSK BIT(2)
673 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
675 #define RTW_PWR_CUT_A_MSK BIT(1)
676 #define RTW_PWR_CUT_B_MSK BIT(2)
677 #define RTW_PWR_CUT_C_MSK BIT(3)
678 #define RTW_PWR_CUT_D_MSK BIT(4)
679 #define RTW_PWR_CUT_E_MSK BIT(5)
680 #define RTW_PWR_CUT_F_MSK BIT(6)
681 #define RTW_PWR_CUT_G_MSK BIT(7)
682 #define RTW_PWR_CUT_ALL_MSK 0xFF
684 enum rtw_pwr_seq_cmd_delay_unit {
689 struct rtw_pwr_seq_cmd {
700 RTW_CHIP_VER_CUT_A = 0x00,
701 RTW_CHIP_VER_CUT_B = 0x01,
702 RTW_CHIP_VER_CUT_C = 0x02,
703 RTW_CHIP_VER_CUT_D = 0x03,
704 RTW_CHIP_VER_CUT_E = 0x04,
705 RTW_CHIP_VER_CUT_F = 0x05,
706 RTW_CHIP_VER_CUT_G = 0x06,
709 #define RTW_INTF_PHY_PLATFORM_ALL 0
711 enum rtw_intf_phy_cut {
712 RTW_INTF_PHY_CUT_A = BIT(0),
713 RTW_INTF_PHY_CUT_B = BIT(1),
714 RTW_INTF_PHY_CUT_C = BIT(2),
715 RTW_INTF_PHY_CUT_D = BIT(3),
716 RTW_INTF_PHY_CUT_E = BIT(4),
717 RTW_INTF_PHY_CUT_F = BIT(5),
718 RTW_INTF_PHY_CUT_G = BIT(6),
719 RTW_INTF_PHY_CUT_ALL = 0xFFFF,
727 RTW_IP_SEL_UNDEF = 0xFFFF
737 RTW_PQ_MAP_NUM = 0x6,
742 enum rtw_dma_mapping {
743 RTW_DMA_MAPPING_EXTRA = 0,
744 RTW_DMA_MAPPING_LOW = 1,
745 RTW_DMA_MAPPING_NORMAL = 2,
746 RTW_DMA_MAPPING_HIGH = 3,
748 RTW_DMA_MAPPING_UNDEF,
752 enum rtw_dma_mapping dma_map_vo;
753 enum rtw_dma_mapping dma_map_vi;
754 enum rtw_dma_mapping dma_map_be;
755 enum rtw_dma_mapping dma_map_bk;
756 enum rtw_dma_mapping dma_map_mg;
757 enum rtw_dma_mapping dma_map_hi;
760 struct rtw_page_table {
768 struct rtw_intf_phy_para {
776 struct rtw_intf_phy_para_table {
777 struct rtw_intf_phy_para *usb2_para;
778 struct rtw_intf_phy_para *usb3_para;
779 struct rtw_intf_phy_para *gen1_para;
780 struct rtw_intf_phy_para *gen2_para;
790 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
791 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
793 enum rtw_rf_path rf_path;
796 static inline void rtw_load_table(struct rtw_dev *rtwdev,
797 const struct rtw_table *tbl)
799 (*tbl->parse)(rtwdev, tbl);
805 RTW_RFE_IFEM2G_EFEM5G,
810 const struct rtw_table *phy_pg_tbl;
811 const struct rtw_table *txpwr_lmt_tbl;
814 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \
815 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
816 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
819 /* hardware configuration for each IC */
820 struct rtw_chip_info {
821 struct rtw_chip_ops *ops;
840 bool is_pwr_by_rate_dec;
848 struct rtw_pwr_seq_cmd **pwr_on_seq;
849 struct rtw_pwr_seq_cmd **pwr_off_seq;
850 struct rtw_rqpn *rqpn_table;
851 struct rtw_page_table *page_table;
852 struct rtw_intf_phy_para_table *intf_table;
854 struct rtw_hw_reg *dig;
858 const struct rtw_table *mac_tbl;
859 const struct rtw_table *agc_tbl;
860 const struct rtw_table *bb_tbl;
861 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
862 const struct rtw_table *rfk_init_tbl;
864 const struct rtw_rfe_def *rfe_defs;
874 bool new_scbd10_def; /* true: fix 2M(8822c) */
875 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
887 const u8 *bt_rssi_step;
888 const u8 *wl_rssi_step;
889 const struct coex_table_para *table_nsant;
890 const struct coex_table_para *table_sant;
891 const struct coex_tdma_para *tdma_sant;
892 const struct coex_tdma_para *tdma_nsant;
893 const struct coex_rf_para *wl_rf_para_tx;
894 const struct coex_rf_para *wl_rf_para_rx;
895 const struct coex_5g_afh_map *afh_5g;
898 enum rtw_coex_bt_state_cnt {
901 COEX_CNT_BT_REENABLE,
902 COEX_CNT_BT_POPEVENT,
903 COEX_CNT_BT_SETUPLINK,
904 COEX_CNT_BT_IGNWLANACT,
907 COEX_CNT_BT_ROLESWITCH,
908 COEX_CNT_BT_AFHUPDATE,
909 COEX_CNT_BT_INFOUPDATE,
916 enum rtw_coex_wl_state_cnt {
922 COEX_CNT_WL_5MS_NOEXTEND,
923 COEX_CNT_WL_FW_NOTIFY,
928 struct rtw_coex_rfe {
929 bool ant_switch_exist;
930 bool ant_switch_diversity;
931 bool ant_switch_with_bt;
933 u8 ant_switch_polarity;
935 /* true if WLG at BTG, else at WLAG */
941 bool cur_wl_rx_low_gain_en;
954 u32 cur_ant_pos_type;
955 u32 cur_switch_status;
959 #define COEX_BTINFO_SRC_WL_FW 0x0
960 #define COEX_BTINFO_SRC_BT_RSP 0x1
961 #define COEX_BTINFO_SRC_BT_ACT 0x2
962 #define COEX_BTINFO_SRC_BT_IQK 0x3
963 #define COEX_BTINFO_SRC_BT_SCBD 0x4
964 #define COEX_BTINFO_SRC_MAX 0x5
966 #define COEX_INFO_FTP BIT(7)
967 #define COEX_INFO_A2DP BIT(6)
968 #define COEX_INFO_HID BIT(5)
969 #define COEX_INFO_SCO_BUSY BIT(4)
970 #define COEX_INFO_ACL_BUSY BIT(3)
971 #define COEX_INFO_INQ_PAGE BIT(2)
972 #define COEX_INFO_SCO_ESCO BIT(1)
973 #define COEX_INFO_CONNECTION BIT(0)
974 #define COEX_BTINFO_LENGTH_MAX 10
976 struct rtw_coex_stat {
978 bool bt_disabled_pre;
989 bool bt_pan_exist; /* PAN or OPP */
990 bool bt_opp_exist; /* OPP only */
1001 bool bt_418_hid_exist;
1002 bool bt_mailbox_reply;
1006 bool wl_hi_pri_task1;
1007 bool wl_hi_pri_task2;
1008 bool wl_force_lps_ctrl;
1010 bool wl_linkscan_proc;
1011 bool wl_ps_state_fail;
1012 bool wl_tx_limit_en;
1013 bool wl_ampdu_limit_en;
1015 bool wl_slot_extend;
1017 bool wl_cck_lock_pre;
1018 bool wl_cck_lock_ever;
1020 u32 bt_supported_version;
1021 u32 bt_supported_feature;
1024 u8 gnt_workaround_state;
1027 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
1034 u8 bt_ble_scan_type;
1041 u8 wl_fw_dbg_info[10];
1042 u8 wl_fw_dbg_info_pre[10];
1050 /* counters to record bt states */
1051 u32 cnt_bt[COEX_CNT_BT_MAX];
1053 /* counters to record wifi states */
1054 u32 cnt_wl[COEX_CNT_WL_MAX];
1061 /* protects coex info request section */
1063 struct sk_buff_head queue;
1064 wait_queue_head_t wait;
1072 struct rtw_coex_stat stat;
1073 struct rtw_coex_dm dm;
1074 struct rtw_coex_rfe rfe;
1076 struct delayed_work bt_relink_work;
1077 struct delayed_work bt_reenable_work;
1078 struct delayed_work defreeze_work;
1081 #define DPK_RF_REG_NUM 7
1082 #define DPK_RF_PATH_NUM 2
1083 #define DPK_BB_REG_NUM 18
1084 #define DPK_CHANNEL_WIDTH_80 1
1086 DECLARE_EWMA(thermal, 10, 4);
1088 struct rtw_dpk_info {
1092 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM);
1094 u8 thermal_dpk[DPK_RF_PATH_NUM];
1095 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM];
1100 u8 result[RTW_RF_PATH_MAX];
1101 u8 dpk_txagc[RTW_RF_PATH_MAX];
1102 u32 coef[RTW_RF_PATH_MAX][20];
1103 u16 dpk_gs[RTW_RF_PATH_MAX];
1104 u8 thermal_dpk_delta[RTW_RF_PATH_MAX];
1105 u8 pre_pwsf[RTW_RF_PATH_MAX];
1112 struct rtw_phy_cck_pd_reg {
1119 #define DACK_MSBK_BACKUP_NUM 0xf
1120 #define DACK_DCK_BACKUP_NUM 0x2
1122 struct rtw_dm_info {
1148 /* backup dack results for each path and I/Q */
1149 u32 dack_adck[RTW_RF_PATH_MAX];
1150 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM];
1151 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM];
1153 struct rtw_dpk_info dpk_info;
1155 /* [bandwidth 0:20M/1:40M][number of path] */
1156 u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
1191 /* bt share antenna with wifi */
1203 struct rtw_txpwr_idx txpwr_idx_table[4];
1206 struct rtw_phy_cond {
1207 #ifdef __LITTLE_ENDIAN
1229 #define INTF_PCIE BIT(0)
1230 #define INTF_USB BIT(1)
1231 #define INTF_SDIO BIT(2)
1234 #define BRANCH_ELIF 1
1235 #define BRANCH_ELSE 2
1236 #define BRANCH_ENDIF 3
1239 struct rtw_fifo_conf {
1240 /* tx fifo information */
1243 u16 rsvd_drv_pg_num;
1247 u16 rsvd_h2c_info_addr;
1248 u16 rsvd_h2c_sta_info_addr;
1250 u16 rsvd_cpu_instr_addr;
1251 u16 rsvd_fw_txbuf_addr;
1252 u16 rsvd_csibuf_addr;
1253 enum rtw_dma_mapping pq_map[RTW_PQ_MAP_NUM];
1256 struct rtw_fw_state {
1257 const struct firmware *firmware;
1258 struct completion completion;
1273 struct rtw_phy_cond phy_cond;
1277 u8 current_band_width;
1278 u8 current_band_type;
1280 /* center channel for different available bandwidth,
1281 * val of (bw > current_band_width) is invalid
1283 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
1291 /* protect tx power section */
1292 struct mutex tx_power_mutex;
1293 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
1295 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
1297 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
1298 [RTW_RATE_SECTION_MAX];
1299 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
1300 [RTW_RATE_SECTION_MAX];
1301 s8 tx_pwr_limit_2g[RTW_REGD_MAX]
1302 [RTW_CHANNEL_WIDTH_MAX]
1303 [RTW_RATE_SECTION_MAX]
1304 [RTW_MAX_CHANNEL_NUM_2G];
1305 s8 tx_pwr_limit_5g[RTW_REGD_MAX]
1306 [RTW_CHANNEL_WIDTH_MAX]
1307 [RTW_RATE_SECTION_MAX]
1308 [RTW_MAX_CHANNEL_NUM_5G];
1309 s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
1314 struct ieee80211_hw *hw;
1319 struct rtw_chip_info *chip;
1321 struct rtw_fifo_conf fifo;
1322 struct rtw_fw_state fw;
1323 struct rtw_efuse efuse;
1324 struct rtw_sec_desc sec;
1325 struct rtw_traffic_stats stats;
1326 struct rtw_regulatory regd;
1328 struct rtw_dm_info dm_info;
1329 struct rtw_coex coex;
1331 /* ensures exclusive access from mac80211 callbacks */
1334 /* lock for dm to use */
1337 /* read/write rf register */
1340 /* watch dog every 2 sec */
1341 struct delayed_work watch_dog_work;
1344 struct list_head rsvd_page_list;
1346 /* c2h cmd queue & handler work */
1347 struct sk_buff_head c2h_queue;
1348 struct work_struct c2h_work;
1350 struct rtw_tx_report tx_report;
1353 /* incicate the mail box to use with fw */
1355 /* protect to send h2c to fw */
1360 /* lps power state & handler work */
1361 struct rtw_lps_conf lps_conf;
1363 struct dentry *debugfs;
1367 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
1368 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
1372 /* hci related data, must be last */
1373 u8 priv[0] __aligned(sizeof(void *));
1378 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev)
1380 return !!rtwdev->sta_cnt;
1383 void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
1384 struct rtw_channel_params *ch_param);
1385 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
1386 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
1387 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
1388 void rtw_restore_reg(struct rtw_dev *rtwdev,
1389 struct rtw_backup_info *bckp, u32 num);
1390 void rtw_set_channel(struct rtw_dev *rtwdev);
1391 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
1393 void rtw_tx_report_purge_timer(struct timer_list *t);
1394 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
1395 int rtw_core_start(struct rtw_dev *rtwdev);
1396 void rtw_core_stop(struct rtw_dev *rtwdev);
1397 int rtw_chip_info_setup(struct rtw_dev *rtwdev);
1398 int rtw_core_init(struct rtw_dev *rtwdev);
1399 void rtw_core_deinit(struct rtw_dev *rtwdev);
1400 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
1401 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);