1 // SPDX-License-Identifier: GPL-2.0-only
3 * Firmware I/O code for mac80211 ST-Ericsson CW1200 drivers
5 * Copyright (c) 2010, ST-Ericsson
6 * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
9 * ST-Ericsson UMAC CW1200 driver which is
10 * Copyright (c) 2010, ST-Ericsson
11 * Author: Ajitpal Singh <ajitpal.singh@stericsson.com>
14 #include <linux/vmalloc.h>
15 #include <linux/sched.h>
16 #include <linux/firmware.h>
24 static int cw1200_get_hw_type(u32 config_reg_val, int *major_revision)
27 u32 silicon_type = (config_reg_val >> 24) & 0x7;
28 u32 silicon_vers = (config_reg_val >> 31) & 0x1;
30 switch (silicon_type) {
33 hw_type = HIF_9000_SILICON_VERSATILE;
36 case 0x02: /* CW1x00 */
37 case 0x04: /* CW1x60 */
38 *major_revision = silicon_type;
40 hw_type = HIF_8601_VERSATILE;
42 hw_type = HIF_8601_SILICON;
51 static int cw1200_load_firmware_cw1200(struct cw1200_common *priv)
53 int ret, block, num_blocks;
59 const struct firmware *firmware = NULL;
61 /* Macroses are local. */
62 #define APB_WRITE(reg, val) \
64 ret = cw1200_apb_write_32(priv, CW1200_APB(reg), (val)); \
68 #define APB_WRITE2(reg, val) \
70 ret = cw1200_apb_write_32(priv, CW1200_APB(reg), (val)); \
74 #define APB_READ(reg, val) \
76 ret = cw1200_apb_read_32(priv, CW1200_APB(reg), &(val)); \
80 #define REG_WRITE(reg, val) \
82 ret = cw1200_reg_write_32(priv, (reg), (val)); \
86 #define REG_READ(reg, val) \
88 ret = cw1200_reg_read_32(priv, (reg), &(val)); \
93 switch (priv->hw_revision) {
94 case CW1200_HW_REV_CUT10:
95 fw_path = FIRMWARE_CUT10;
97 priv->sdd_path = SDD_FILE_10;
99 case CW1200_HW_REV_CUT11:
100 fw_path = FIRMWARE_CUT11;
102 priv->sdd_path = SDD_FILE_11;
104 case CW1200_HW_REV_CUT20:
105 fw_path = FIRMWARE_CUT20;
107 priv->sdd_path = SDD_FILE_20;
109 case CW1200_HW_REV_CUT22:
110 fw_path = FIRMWARE_CUT22;
112 priv->sdd_path = SDD_FILE_22;
115 fw_path = FIRMWARE_CW1X60;
117 priv->sdd_path = SDD_FILE_CW1X60;
120 pr_err("Invalid silicon revision %d.\n", priv->hw_revision);
124 /* Initialize common registers */
125 APB_WRITE(DOWNLOAD_IMAGE_SIZE_REG, DOWNLOAD_ARE_YOU_HERE);
126 APB_WRITE(DOWNLOAD_PUT_REG, 0);
127 APB_WRITE(DOWNLOAD_GET_REG, 0);
128 APB_WRITE(DOWNLOAD_STATUS_REG, DOWNLOAD_PENDING);
129 APB_WRITE(DOWNLOAD_FLAGS_REG, 0);
131 /* Write the NOP Instruction */
132 REG_WRITE(ST90TDS_SRAM_BASE_ADDR_REG_ID, 0xFFF20000);
133 REG_WRITE(ST90TDS_AHB_DPORT_REG_ID, 0xEAFFFFFE);
135 /* Release CPU from RESET */
136 REG_READ(ST90TDS_CONFIG_REG_ID, val32);
137 val32 &= ~ST90TDS_CONFIG_CPU_RESET_BIT;
138 REG_WRITE(ST90TDS_CONFIG_REG_ID, val32);
141 val32 &= ~ST90TDS_CONFIG_CPU_CLK_DIS_BIT;
142 REG_WRITE(ST90TDS_CONFIG_REG_ID, val32);
144 /* Load a firmware file */
145 ret = request_firmware(&firmware, fw_path, priv->pdev);
147 pr_err("Can't load firmware file %s.\n", fw_path);
151 buf = kmalloc(DOWNLOAD_BLOCK_SIZE, GFP_KERNEL | GFP_DMA);
153 pr_err("Can't allocate firmware load buffer.\n");
155 goto firmware_release;
158 /* Check if the bootloader is ready */
159 for (i = 0; i < 100; i += 1 + i / 2) {
160 APB_READ(DOWNLOAD_IMAGE_SIZE_REG, val32);
161 if (val32 == DOWNLOAD_I_AM_HERE)
164 } /* End of for loop */
166 if (val32 != DOWNLOAD_I_AM_HERE) {
167 pr_err("Bootloader is not ready.\n");
172 /* Calculcate number of download blocks */
173 num_blocks = (firmware->size - 1) / DOWNLOAD_BLOCK_SIZE + 1;
175 /* Updating the length in Download Ctrl Area */
176 val32 = firmware->size; /* Explicit cast from size_t to u32 */
177 APB_WRITE2(DOWNLOAD_IMAGE_SIZE_REG, val32);
179 /* Firmware downloading loop */
180 for (block = 0; block < num_blocks; block++) {
184 /* check the download status */
185 APB_READ(DOWNLOAD_STATUS_REG, val32);
186 if (val32 != DOWNLOAD_PENDING) {
187 pr_err("Bootloader reported error %d.\n", val32);
192 /* loop until put - get <= 24K */
193 for (i = 0; i < 100; i++) {
194 APB_READ(DOWNLOAD_GET_REG, get);
196 (DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE))
201 if ((put - get) > (DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE)) {
202 pr_err("Timeout waiting for FIFO.\n");
207 /* calculate the block size */
208 tx_size = block_size = min_t(size_t, firmware->size - put,
209 DOWNLOAD_BLOCK_SIZE);
211 memcpy(buf, &firmware->data[put], block_size);
212 if (block_size < DOWNLOAD_BLOCK_SIZE) {
213 memset(&buf[block_size], 0,
214 DOWNLOAD_BLOCK_SIZE - block_size);
215 tx_size = DOWNLOAD_BLOCK_SIZE;
218 /* send the block to sram */
219 ret = cw1200_apb_write(priv,
220 CW1200_APB(DOWNLOAD_FIFO_OFFSET +
221 (put & (DOWNLOAD_FIFO_SIZE - 1))),
224 pr_err("Can't write firmware block @ %d!\n",
225 put & (DOWNLOAD_FIFO_SIZE - 1));
229 /* update the put register */
231 APB_WRITE2(DOWNLOAD_PUT_REG, put);
232 } /* End of firmware download loop */
234 /* Wait for the download completion */
235 for (i = 0; i < 300; i += 1 + i / 2) {
236 APB_READ(DOWNLOAD_STATUS_REG, val32);
237 if (val32 != DOWNLOAD_PENDING)
241 if (val32 != DOWNLOAD_SUCCESS) {
242 pr_err("Wait for download completion failed: 0x%.8X\n", val32);
246 pr_info("Firmware download completed.\n");
253 release_firmware(firmware);
265 static int config_reg_read(struct cw1200_common *priv, u32 *val)
267 switch (priv->hw_type) {
268 case HIF_9000_SILICON_VERSATILE: {
270 int ret = cw1200_reg_read_16(priv,
271 ST90TDS_CONFIG_REG_ID,
278 case HIF_8601_VERSATILE:
279 case HIF_8601_SILICON:
281 cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, val);
287 static int config_reg_write(struct cw1200_common *priv, u32 val)
289 switch (priv->hw_type) {
290 case HIF_9000_SILICON_VERSATILE:
291 return cw1200_reg_write_16(priv,
292 ST90TDS_CONFIG_REG_ID,
294 case HIF_8601_VERSATILE:
295 case HIF_8601_SILICON:
297 return cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID, val);
302 int cw1200_load_firmware(struct cw1200_common *priv)
308 int major_revision = -1;
310 /* Read CONFIG Register */
311 ret = cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
313 pr_err("Can't read config register.\n");
317 if (val32 == 0 || val32 == 0xffffffff) {
318 pr_err("Bad config register value (0x%08x)\n", val32);
323 priv->hw_type = cw1200_get_hw_type(val32, &major_revision);
324 if (priv->hw_type < 0) {
325 pr_err("Can't deduce hardware type.\n");
330 /* Set DPLL Reg value, and read back to confirm writes work */
331 ret = cw1200_reg_write_32(priv, ST90TDS_TSET_GEN_R_W_REG_ID,
332 cw1200_dpll_from_clk(priv->hw_refclk));
334 pr_err("Can't write DPLL register.\n");
340 ret = cw1200_reg_read_32(priv,
341 ST90TDS_TSET_GEN_R_W_REG_ID, &val32);
343 pr_err("Can't read DPLL register.\n");
347 if (val32 != cw1200_dpll_from_clk(priv->hw_refclk)) {
348 pr_err("Unable to initialise DPLL register. Wrote 0x%.8X, Read 0x%.8X.\n",
349 cw1200_dpll_from_clk(priv->hw_refclk), val32);
354 /* Set wakeup bit in device */
355 ret = cw1200_reg_read_16(priv, ST90TDS_CONTROL_REG_ID, &val16);
357 pr_err("set_wakeup: can't read control register.\n");
361 ret = cw1200_reg_write_16(priv, ST90TDS_CONTROL_REG_ID,
362 val16 | ST90TDS_CONT_WUP_BIT);
364 pr_err("set_wakeup: can't write control register.\n");
368 /* Wait for wakeup */
369 for (i = 0; i < 300; i += (1 + i / 2)) {
370 ret = cw1200_reg_read_16(priv,
371 ST90TDS_CONTROL_REG_ID, &val16);
373 pr_err("wait_for_wakeup: can't read control register.\n");
377 if (val16 & ST90TDS_CONT_RDY_BIT)
383 if ((val16 & ST90TDS_CONT_RDY_BIT) == 0) {
384 pr_err("wait_for_wakeup: device is not responding.\n");
389 switch (major_revision) {
391 /* CW1200 Hardware detection logic : Check for CUT1.1 */
392 ret = cw1200_ahb_read_32(priv, CW1200_CUT_ID_ADDR, &val32);
394 pr_err("HW detection: can't read CUT ID.\n");
399 case CW1200_CUT_11_ID_STR:
400 pr_info("CW1x00 Cut 1.1 silicon detected.\n");
401 priv->hw_revision = CW1200_HW_REV_CUT11;
404 pr_info("CW1x00 Cut 1.0 silicon detected.\n");
405 priv->hw_revision = CW1200_HW_REV_CUT10;
409 /* According to ST-E, CUT<2.0 has busted BA TID0-3.
410 Just disable it entirely...
412 priv->ba_rx_tid_mask = 0;
413 priv->ba_tx_tid_mask = 0;
417 ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR, &ar1);
419 pr_err("(1) HW detection: can't read CUT ID\n");
422 ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR + 4, &ar2);
424 pr_err("(2) HW detection: can't read CUT ID.\n");
428 ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR + 8, &ar3);
430 pr_err("(3) HW detection: can't read CUT ID.\n");
434 if (ar1 == CW1200_CUT_22_ID_STR1 &&
435 ar2 == CW1200_CUT_22_ID_STR2 &&
436 ar3 == CW1200_CUT_22_ID_STR3) {
437 pr_info("CW1x00 Cut 2.2 silicon detected.\n");
438 priv->hw_revision = CW1200_HW_REV_CUT22;
440 pr_info("CW1x00 Cut 2.0 silicon detected.\n");
441 priv->hw_revision = CW1200_HW_REV_CUT20;
446 pr_info("CW1x60 silicon detected.\n");
447 priv->hw_revision = CW1X60_HW_REV;
450 pr_err("Unsupported silicon major revision %d.\n",
456 /* Checking for access mode */
457 ret = config_reg_read(priv, &val32);
459 pr_err("Can't read config register.\n");
463 if (!(val32 & ST90TDS_CONFIG_ACCESS_MODE_BIT)) {
464 pr_err("Device is already in QUEUE mode!\n");
469 switch (priv->hw_type) {
470 case HIF_8601_SILICON:
471 if (priv->hw_revision == CW1X60_HW_REV) {
472 pr_err("Can't handle CW1160/1260 firmware load yet.\n");
476 ret = cw1200_load_firmware_cw1200(priv);
479 pr_err("Can't perform firmware load for hw type %d.\n",
485 pr_err("Firmware load error.\n");
489 /* Enable interrupt signalling */
490 priv->hwbus_ops->lock(priv->hwbus_priv);
491 ret = __cw1200_irq_enable(priv, 1);
492 priv->hwbus_ops->unlock(priv->hwbus_priv);
496 /* Configure device for MESSSAGE MODE */
497 ret = config_reg_read(priv, &val32);
499 pr_err("Can't read config register.\n");
502 ret = config_reg_write(priv, val32 & ~ST90TDS_CONFIG_ACCESS_MODE_BIT);
504 pr_err("Can't write config register.\n");
508 /* Unless we read the CONFIG Register we are
509 * not able to get an interrupt
512 config_reg_read(priv, &val32);
518 /* Disable interrupt signalling */
519 priv->hwbus_ops->lock(priv->hwbus_priv);
520 ret = __cw1200_irq_enable(priv, 0);
521 priv->hwbus_ops->unlock(priv->hwbus_priv);