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1 /*
2  * Copyright (c) 2011-2014, Intel Corporation.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  */
13
14 #ifndef _NVME_H
15 #define _NVME_H
16
17 #include <linux/nvme.h>
18 #include <linux/cdev.h>
19 #include <linux/pci.h>
20 #include <linux/kref.h>
21 #include <linux/blk-mq.h>
22 #include <linux/lightnvm.h>
23 #include <linux/sed-opal.h>
24 #include <linux/fault-inject.h>
25 #include <linux/rcupdate.h>
26
27 extern unsigned int nvme_io_timeout;
28 #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
29
30 extern unsigned int admin_timeout;
31 #define ADMIN_TIMEOUT   (admin_timeout * HZ)
32
33 #define NVME_DEFAULT_KATO       5
34 #define NVME_KATO_GRACE         10
35
36 extern struct workqueue_struct *nvme_wq;
37 extern struct workqueue_struct *nvme_reset_wq;
38 extern struct workqueue_struct *nvme_delete_wq;
39
40 enum {
41         NVME_NS_LBA             = 0,
42         NVME_NS_LIGHTNVM        = 1,
43 };
44
45 /*
46  * List of workarounds for devices that required behavior not specified in
47  * the standard.
48  */
49 enum nvme_quirks {
50         /*
51          * Prefers I/O aligned to a stripe size specified in a vendor
52          * specific Identify field.
53          */
54         NVME_QUIRK_STRIPE_SIZE                  = (1 << 0),
55
56         /*
57          * The controller doesn't handle Identify value others than 0 or 1
58          * correctly.
59          */
60         NVME_QUIRK_IDENTIFY_CNS                 = (1 << 1),
61
62         /*
63          * The controller deterministically returns O's on reads to
64          * logical blocks that deallocate was called on.
65          */
66         NVME_QUIRK_DEALLOCATE_ZEROES            = (1 << 2),
67
68         /*
69          * The controller needs a delay before starts checking the device
70          * readiness, which is done by reading the NVME_CSTS_RDY bit.
71          */
72         NVME_QUIRK_DELAY_BEFORE_CHK_RDY         = (1 << 3),
73
74         /*
75          * APST should not be used.
76          */
77         NVME_QUIRK_NO_APST                      = (1 << 4),
78
79         /*
80          * The deepest sleep state should not be used.
81          */
82         NVME_QUIRK_NO_DEEPEST_PS                = (1 << 5),
83
84         /*
85          * Supports the LighNVM command set if indicated in vs[1].
86          */
87         NVME_QUIRK_LIGHTNVM                     = (1 << 6),
88
89         /*
90          * Set MEDIUM priority on SQ creation
91          */
92         NVME_QUIRK_MEDIUM_PRIO_SQ               = (1 << 7),
93 };
94
95 /*
96  * Common request structure for NVMe passthrough.  All drivers must have
97  * this structure as the first member of their request-private data.
98  */
99 struct nvme_request {
100         struct nvme_command     *cmd;
101         union nvme_result       result;
102         u8                      retries;
103         u8                      flags;
104         u16                     status;
105         struct nvme_ctrl        *ctrl;
106 };
107
108 /*
109  * Mark a bio as coming in through the mpath node.
110  */
111 #define REQ_NVME_MPATH          REQ_DRV
112
113 enum {
114         NVME_REQ_CANCELLED              = (1 << 0),
115         NVME_REQ_USERCMD                = (1 << 1),
116 };
117
118 static inline struct nvme_request *nvme_req(struct request *req)
119 {
120         return blk_mq_rq_to_pdu(req);
121 }
122
123 static inline u16 nvme_req_qid(struct request *req)
124 {
125         if (!req->rq_disk)
126                 return 0;
127         return blk_mq_unique_tag_to_hwq(blk_mq_unique_tag(req)) + 1;
128 }
129
130 /* The below value is the specific amount of delay needed before checking
131  * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
132  * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
133  * found empirically.
134  */
135 #define NVME_QUIRK_DELAY_AMOUNT         2300
136
137 enum nvme_ctrl_state {
138         NVME_CTRL_NEW,
139         NVME_CTRL_LIVE,
140         NVME_CTRL_ADMIN_ONLY,    /* Only admin queue live */
141         NVME_CTRL_RESETTING,
142         NVME_CTRL_CONNECTING,
143         NVME_CTRL_DELETING,
144         NVME_CTRL_DEAD,
145 };
146
147 struct nvme_ctrl {
148         bool comp_seen;
149         enum nvme_ctrl_state state;
150         bool identified;
151         spinlock_t lock;
152         const struct nvme_ctrl_ops *ops;
153         struct request_queue *admin_q;
154         struct request_queue *connect_q;
155         struct device *dev;
156         int instance;
157         int numa_node;
158         struct blk_mq_tag_set *tagset;
159         struct blk_mq_tag_set *admin_tagset;
160         struct list_head namespaces;
161         struct rw_semaphore namespaces_rwsem;
162         struct device ctrl_device;
163         struct device *device;  /* char device */
164         struct cdev cdev;
165         struct work_struct reset_work;
166         struct work_struct delete_work;
167
168         struct nvme_subsystem *subsys;
169         struct list_head subsys_entry;
170
171         struct opal_dev *opal_dev;
172
173         char name[12];
174         u16 cntlid;
175
176         u32 ctrl_config;
177         u16 mtfa;
178         u32 queue_count;
179
180         u64 cap;
181         u32 page_size;
182         u32 max_hw_sectors;
183         u32 max_segments;
184         u16 oncs;
185         u16 oacs;
186         u16 nssa;
187         u16 nr_streams;
188         u32 max_namespaces;
189         atomic_t abort_limit;
190         u8 vwc;
191         u32 vs;
192         u32 sgls;
193         u16 kas;
194         u8 npss;
195         u8 apsta;
196         u32 oaes;
197         u32 aen_result;
198         u32 ctratt;
199         unsigned int shutdown_timeout;
200         unsigned int kato;
201         bool subsystem;
202         unsigned long quirks;
203         struct nvme_id_power_state psd[32];
204         struct nvme_effects_log *effects;
205         struct work_struct scan_work;
206         struct work_struct async_event_work;
207         struct delayed_work ka_work;
208         struct nvme_command ka_cmd;
209         struct work_struct fw_act_work;
210         unsigned long events;
211
212 #ifdef CONFIG_NVME_MULTIPATH
213         /* asymmetric namespace access: */
214         u8 anacap;
215         u8 anatt;
216         u32 anagrpmax;
217         u32 nanagrpid;
218         struct mutex ana_lock;
219         struct nvme_ana_rsp_hdr *ana_log_buf;
220         size_t ana_log_size;
221         struct timer_list anatt_timer;
222         struct work_struct ana_work;
223 #endif
224
225         /* Power saving configuration */
226         u64 ps_max_latency_us;
227         bool apst_enabled;
228
229         /* PCIe only: */
230         u32 hmpre;
231         u32 hmmin;
232         u32 hmminds;
233         u16 hmmaxd;
234
235         /* Fabrics only */
236         u16 sqsize;
237         u32 ioccsz;
238         u32 iorcsz;
239         u16 icdoff;
240         u16 maxcmd;
241         int nr_reconnects;
242         struct nvmf_ctrl_options *opts;
243 };
244
245 struct nvme_subsystem {
246         int                     instance;
247         struct device           dev;
248         /*
249          * Because we unregister the device on the last put we need
250          * a separate refcount.
251          */
252         struct kref             ref;
253         struct list_head        entry;
254         struct mutex            lock;
255         struct list_head        ctrls;
256         struct list_head        nsheads;
257         char                    subnqn[NVMF_NQN_SIZE];
258         char                    serial[20];
259         char                    model[40];
260         char                    firmware_rev[8];
261         u8                      cmic;
262         u16                     vendor_id;
263         struct ida              ns_ida;
264 };
265
266 /*
267  * Container structure for uniqueue namespace identifiers.
268  */
269 struct nvme_ns_ids {
270         u8      eui64[8];
271         u8      nguid[16];
272         uuid_t  uuid;
273 };
274
275 /*
276  * Anchor structure for namespaces.  There is one for each namespace in a
277  * NVMe subsystem that any of our controllers can see, and the namespace
278  * structure for each controller is chained of it.  For private namespaces
279  * there is a 1:1 relation to our namespace structures, that is ->list
280  * only ever has a single entry for private namespaces.
281  */
282 struct nvme_ns_head {
283         struct list_head        list;
284         struct srcu_struct      srcu;
285         struct nvme_subsystem   *subsys;
286         unsigned                ns_id;
287         struct nvme_ns_ids      ids;
288         struct list_head        entry;
289         struct kref             ref;
290         int                     instance;
291 #ifdef CONFIG_NVME_MULTIPATH
292         struct gendisk          *disk;
293         struct bio_list         requeue_list;
294         spinlock_t              requeue_lock;
295         struct work_struct      requeue_work;
296         struct mutex            lock;
297         struct nvme_ns __rcu    *current_path[];
298 #endif
299 };
300
301 #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
302 struct nvme_fault_inject {
303         struct fault_attr attr;
304         struct dentry *parent;
305         bool dont_retry;        /* DNR, do not retry */
306         u16 status;             /* status code */
307 };
308 #endif
309
310 struct nvme_ns {
311         struct list_head list;
312
313         struct nvme_ctrl *ctrl;
314         struct request_queue *queue;
315         struct gendisk *disk;
316 #ifdef CONFIG_NVME_MULTIPATH
317         enum nvme_ana_state ana_state;
318         u32 ana_grpid;
319 #endif
320         struct list_head siblings;
321         struct nvm_dev *ndev;
322         struct kref kref;
323         struct nvme_ns_head *head;
324
325         int lba_shift;
326         u16 ms;
327         u16 sgs;
328         u32 sws;
329         bool ext;
330         u8 pi_type;
331         unsigned long flags;
332 #define NVME_NS_REMOVING        0
333 #define NVME_NS_DEAD            1
334 #define NVME_NS_ANA_PENDING     2
335         u16 noiob;
336
337 #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
338         struct nvme_fault_inject fault_inject;
339 #endif
340
341 };
342
343 struct nvme_ctrl_ops {
344         const char *name;
345         struct module *module;
346         unsigned int flags;
347 #define NVME_F_FABRICS                  (1 << 0)
348 #define NVME_F_METADATA_SUPPORTED       (1 << 1)
349 #define NVME_F_PCI_P2PDMA               (1 << 2)
350         int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
351         int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
352         int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
353         void (*free_ctrl)(struct nvme_ctrl *ctrl);
354         void (*submit_async_event)(struct nvme_ctrl *ctrl);
355         void (*delete_ctrl)(struct nvme_ctrl *ctrl);
356         int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
357         void (*stop_ctrl)(struct nvme_ctrl *ctrl);
358 };
359
360 #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
361 void nvme_fault_inject_init(struct nvme_ns *ns);
362 void nvme_fault_inject_fini(struct nvme_ns *ns);
363 void nvme_should_fail(struct request *req);
364 #else
365 static inline void nvme_fault_inject_init(struct nvme_ns *ns) {}
366 static inline void nvme_fault_inject_fini(struct nvme_ns *ns) {}
367 static inline void nvme_should_fail(struct request *req) {}
368 #endif
369
370 static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
371 {
372         u32 val = 0;
373
374         if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
375                 return false;
376         return val & NVME_CSTS_RDY;
377 }
378
379 static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
380 {
381         if (!ctrl->subsystem)
382                 return -ENOTTY;
383         return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
384 }
385
386 static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
387 {
388         return (sector >> (ns->lba_shift - 9));
389 }
390
391 static inline void nvme_end_request(struct request *req, __le16 status,
392                 union nvme_result result)
393 {
394         struct nvme_request *rq = nvme_req(req);
395
396         rq->status = le16_to_cpu(status) >> 1;
397         rq->result = result;
398         /* inject error when permitted by fault injection framework */
399         nvme_should_fail(req);
400         blk_mq_complete_request(req);
401 }
402
403 static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl)
404 {
405         get_device(ctrl->device);
406 }
407
408 static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl)
409 {
410         put_device(ctrl->device);
411 }
412
413 void nvme_complete_rq(struct request *req);
414 bool nvme_cancel_request(struct request *req, void *data, bool reserved);
415 bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
416                 enum nvme_ctrl_state new_state);
417 int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
418 int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
419 int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
420 int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
421                 const struct nvme_ctrl_ops *ops, unsigned long quirks);
422 void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
423 void nvme_start_ctrl(struct nvme_ctrl *ctrl);
424 void nvme_stop_ctrl(struct nvme_ctrl *ctrl);
425 void nvme_put_ctrl(struct nvme_ctrl *ctrl);
426 int nvme_init_identify(struct nvme_ctrl *ctrl);
427
428 void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
429
430 int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
431                 bool send);
432
433 void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
434                 volatile union nvme_result *res);
435
436 void nvme_stop_queues(struct nvme_ctrl *ctrl);
437 void nvme_start_queues(struct nvme_ctrl *ctrl);
438 void nvme_kill_queues(struct nvme_ctrl *ctrl);
439 void nvme_unfreeze(struct nvme_ctrl *ctrl);
440 void nvme_wait_freeze(struct nvme_ctrl *ctrl);
441 void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
442 void nvme_start_freeze(struct nvme_ctrl *ctrl);
443
444 #define NVME_QID_ANY -1
445 struct request *nvme_alloc_request(struct request_queue *q,
446                 struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid);
447 void nvme_cleanup_cmd(struct request *req);
448 blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
449                 struct nvme_command *cmd);
450 int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
451                 void *buf, unsigned bufflen);
452 int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
453                 union nvme_result *result, void *buffer, unsigned bufflen,
454                 unsigned timeout, int qid, int at_head,
455                 blk_mq_req_flags_t flags);
456 int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
457 void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
458 int nvme_reset_ctrl(struct nvme_ctrl *ctrl);
459 int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl);
460 int nvme_delete_ctrl(struct nvme_ctrl *ctrl);
461 int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl);
462
463 int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp,
464                 void *log, size_t size, u64 offset);
465
466 extern const struct attribute_group *nvme_ns_id_attr_groups[];
467 extern const struct block_device_operations nvme_ns_head_ops;
468
469 #ifdef CONFIG_NVME_MULTIPATH
470 bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl);
471 void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns,
472                         struct nvme_ctrl *ctrl, int *flags);
473 void nvme_failover_req(struct request *req);
474 void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl);
475 int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head);
476 void nvme_mpath_add_disk(struct nvme_ns *ns, struct nvme_id_ns *id);
477 void nvme_mpath_remove_disk(struct nvme_ns_head *head);
478 int nvme_mpath_init(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id);
479 void nvme_mpath_uninit(struct nvme_ctrl *ctrl);
480 void nvme_mpath_stop(struct nvme_ctrl *ctrl);
481 void nvme_mpath_clear_current_path(struct nvme_ns *ns);
482 struct nvme_ns *nvme_find_path(struct nvme_ns_head *head);
483
484 static inline void nvme_mpath_check_last_path(struct nvme_ns *ns)
485 {
486         struct nvme_ns_head *head = ns->head;
487
488         if (head->disk && list_empty(&head->list))
489                 kblockd_schedule_work(&head->requeue_work);
490 }
491
492 extern struct device_attribute dev_attr_ana_grpid;
493 extern struct device_attribute dev_attr_ana_state;
494
495 #else
496 static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl)
497 {
498         return false;
499 }
500 /*
501  * Without the multipath code enabled, multiple controller per subsystems are
502  * visible as devices and thus we cannot use the subsystem instance.
503  */
504 static inline void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns,
505                                       struct nvme_ctrl *ctrl, int *flags)
506 {
507         sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->head->instance);
508 }
509
510 static inline void nvme_failover_req(struct request *req)
511 {
512 }
513 static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl)
514 {
515 }
516 static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,
517                 struct nvme_ns_head *head)
518 {
519         return 0;
520 }
521 static inline void nvme_mpath_add_disk(struct nvme_ns *ns,
522                 struct nvme_id_ns *id)
523 {
524 }
525 static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head)
526 {
527 }
528 static inline void nvme_mpath_clear_current_path(struct nvme_ns *ns)
529 {
530 }
531 static inline void nvme_mpath_check_last_path(struct nvme_ns *ns)
532 {
533 }
534 static inline int nvme_mpath_init(struct nvme_ctrl *ctrl,
535                 struct nvme_id_ctrl *id)
536 {
537         if (ctrl->subsys->cmic & (1 << 3))
538                 dev_warn(ctrl->device,
539 "Please enable CONFIG_NVME_MULTIPATH for full support of multi-port devices.\n");
540         return 0;
541 }
542 static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl)
543 {
544 }
545 static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl)
546 {
547 }
548 #endif /* CONFIG_NVME_MULTIPATH */
549
550 #ifdef CONFIG_NVM
551 void nvme_nvm_update_nvm_info(struct nvme_ns *ns);
552 int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node);
553 void nvme_nvm_unregister(struct nvme_ns *ns);
554 extern const struct attribute_group nvme_nvm_attr_group;
555 int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
556 #else
557 static inline void nvme_nvm_update_nvm_info(struct nvme_ns *ns) {};
558 static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name,
559                                     int node)
560 {
561         return 0;
562 }
563
564 static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
565 static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
566                                                         unsigned long arg)
567 {
568         return -ENOTTY;
569 }
570 #endif /* CONFIG_NVM */
571
572 static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev)
573 {
574         return dev_to_disk(dev)->private_data;
575 }
576
577 int __init nvme_core_init(void);
578 void nvme_core_exit(void);
579
580 #endif /* _NVME_H */