2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/blkdev.h>
17 #include <linux/blk-mq.h>
18 #include <linux/blk-mq-pci.h>
19 #include <linux/dmi.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/mutex.h>
26 #include <linux/once.h>
27 #include <linux/pci.h>
28 #include <linux/t10-pi.h>
29 #include <linux/types.h>
30 #include <linux/io-64-nonatomic-lo-hi.h>
31 #include <linux/sed-opal.h>
35 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
36 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
38 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
40 static int use_threaded_interrupts;
41 module_param(use_threaded_interrupts, int, 0);
43 static bool use_cmb_sqes = true;
44 module_param(use_cmb_sqes, bool, 0644);
45 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
47 static unsigned int max_host_mem_size_mb = 128;
48 module_param(max_host_mem_size_mb, uint, 0444);
49 MODULE_PARM_DESC(max_host_mem_size_mb,
50 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
52 static unsigned int sgl_threshold = SZ_32K;
53 module_param(sgl_threshold, uint, 0644);
54 MODULE_PARM_DESC(sgl_threshold,
55 "Use SGLs when average request segment size is larger or equal to "
56 "this size. Use 0 to disable SGLs.");
58 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
59 static const struct kernel_param_ops io_queue_depth_ops = {
60 .set = io_queue_depth_set,
64 static int io_queue_depth = 1024;
65 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
66 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
71 static void nvme_process_cq(struct nvme_queue *nvmeq);
72 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
75 * Represents an NVM Express device. Each nvme_dev is a PCI function.
78 struct nvme_queue *queues;
79 struct blk_mq_tag_set tagset;
80 struct blk_mq_tag_set admin_tagset;
83 struct dma_pool *prp_page_pool;
84 struct dma_pool *prp_small_pool;
85 unsigned online_queues;
87 unsigned int num_vecs;
91 unsigned long bar_mapped_size;
92 struct work_struct remove_work;
93 struct mutex shutdown_lock;
96 pci_bus_addr_t cmb_bus_addr;
100 struct nvme_ctrl ctrl;
101 struct completion ioq_wait;
103 /* shadow doorbell buffer support: */
105 dma_addr_t dbbuf_dbs_dma_addr;
107 dma_addr_t dbbuf_eis_dma_addr;
109 /* host memory buffer support: */
111 u32 nr_host_mem_descs;
112 dma_addr_t host_mem_descs_dma;
113 struct nvme_host_mem_buf_desc *host_mem_descs;
114 void **host_mem_desc_bufs;
117 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
121 ret = kstrtoint(val, 10, &n);
122 if (ret != 0 || n < 2)
125 return param_set_int(val, kp);
128 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
130 return qid * 2 * stride;
133 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
135 return (qid * 2 + 1) * stride;
138 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
140 return container_of(ctrl, struct nvme_dev, ctrl);
144 * An NVM Express queue. Each device has at least two (one for admin
145 * commands and one for I/O commands).
148 struct device *q_dmadev;
149 struct nvme_dev *dev;
151 struct nvme_command *sq_cmds;
152 struct nvme_command __iomem *sq_cmds_io;
153 volatile struct nvme_completion *cqes;
154 struct blk_mq_tags **tags;
155 dma_addr_t sq_dma_addr;
156 dma_addr_t cq_dma_addr;
172 * The nvme_iod describes the data in an I/O, including the list of PRP
173 * entries. You can't see it in this data structure because C doesn't let
174 * me express that. Use nvme_init_iod to ensure there's enough space
175 * allocated to store the PRP list.
178 struct nvme_request req;
179 struct nvme_queue *nvmeq;
182 int npages; /* In the PRP list. 0 means small pool in use */
183 int nents; /* Used in scatterlist */
184 int length; /* Of data, in bytes */
185 dma_addr_t first_dma;
186 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
187 struct scatterlist *sg;
188 struct scatterlist inline_sg[0];
192 * Check we didin't inadvertently grow the command struct
194 static inline void _nvme_check_size(void)
196 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
197 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
202 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
203 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
204 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
205 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
206 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
207 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
208 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
211 static inline unsigned int nvme_dbbuf_size(u32 stride)
213 return ((num_possible_cpus() + 1) * 8 * stride);
216 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
218 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
223 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
224 &dev->dbbuf_dbs_dma_addr,
228 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
229 &dev->dbbuf_eis_dma_addr,
231 if (!dev->dbbuf_eis) {
232 dma_free_coherent(dev->dev, mem_size,
233 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
234 dev->dbbuf_dbs = NULL;
241 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
243 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
245 if (dev->dbbuf_dbs) {
246 dma_free_coherent(dev->dev, mem_size,
247 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
248 dev->dbbuf_dbs = NULL;
250 if (dev->dbbuf_eis) {
251 dma_free_coherent(dev->dev, mem_size,
252 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
253 dev->dbbuf_eis = NULL;
257 static void nvme_dbbuf_init(struct nvme_dev *dev,
258 struct nvme_queue *nvmeq, int qid)
260 if (!dev->dbbuf_dbs || !qid)
263 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
264 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
265 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
266 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
269 static void nvme_dbbuf_set(struct nvme_dev *dev)
271 struct nvme_command c;
276 memset(&c, 0, sizeof(c));
277 c.dbbuf.opcode = nvme_admin_dbbuf;
278 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
279 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
281 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
282 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
283 /* Free memory and continue on */
284 nvme_dbbuf_dma_free(dev);
288 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
290 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
293 /* Update dbbuf and return true if an MMIO is required */
294 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
295 volatile u32 *dbbuf_ei)
301 * Ensure that the queue is written before updating
302 * the doorbell in memory
306 old_value = *dbbuf_db;
309 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
317 * Max size of iod being embedded in the request payload
319 #define NVME_INT_PAGES 2
320 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
323 * Will slightly overestimate the number of pages needed. This is OK
324 * as it only leads to a small amount of wasted memory for the lifetime of
327 static int nvme_npages(unsigned size, struct nvme_dev *dev)
329 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
330 dev->ctrl.page_size);
331 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
335 * Calculates the number of pages needed for the SGL segments. For example a 4k
336 * page can accommodate 256 SGL descriptors.
338 static int nvme_pci_npages_sgl(unsigned int num_seg)
340 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
343 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
344 unsigned int size, unsigned int nseg, bool use_sgl)
349 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
351 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
353 return alloc_size + sizeof(struct scatterlist) * nseg;
356 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
358 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
359 NVME_INT_BYTES(dev), NVME_INT_PAGES,
362 return sizeof(struct nvme_iod) + alloc_size;
365 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
366 unsigned int hctx_idx)
368 struct nvme_dev *dev = data;
369 struct nvme_queue *nvmeq = &dev->queues[0];
371 WARN_ON(hctx_idx != 0);
372 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
373 WARN_ON(nvmeq->tags);
375 hctx->driver_data = nvmeq;
376 nvmeq->tags = &dev->admin_tagset.tags[0];
380 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
382 struct nvme_queue *nvmeq = hctx->driver_data;
387 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
388 unsigned int hctx_idx)
390 struct nvme_dev *dev = data;
391 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
394 nvmeq->tags = &dev->tagset.tags[hctx_idx];
396 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
397 hctx->driver_data = nvmeq;
401 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
402 unsigned int hctx_idx, unsigned int numa_node)
404 struct nvme_dev *dev = set->driver_data;
405 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
406 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
407 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
414 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
416 struct nvme_dev *dev = set->driver_data;
418 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev),
419 dev->num_vecs > 1 ? 1 /* admin queue */ : 0);
423 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
424 * @nvmeq: The queue to use
425 * @cmd: The command to send
427 * Safe to use from interrupt context
429 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
430 struct nvme_command *cmd)
432 u16 tail = nvmeq->sq_tail;
434 if (nvmeq->sq_cmds_io)
435 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
437 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
439 if (++tail == nvmeq->q_depth)
441 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
443 writel(tail, nvmeq->q_db);
444 nvmeq->sq_tail = tail;
447 static void **nvme_pci_iod_list(struct request *req)
449 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
450 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
453 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
455 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
456 int nseg = blk_rq_nr_phys_segments(req);
457 unsigned int avg_seg_size;
462 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
464 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
466 if (!iod->nvmeq->qid)
468 if (!sgl_threshold || avg_seg_size < sgl_threshold)
473 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
475 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
476 int nseg = blk_rq_nr_phys_segments(rq);
477 unsigned int size = blk_rq_payload_bytes(rq);
479 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
481 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
482 size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg,
485 iod->sg = kmalloc(alloc_size, GFP_ATOMIC);
487 return BLK_STS_RESOURCE;
489 iod->sg = iod->inline_sg;
500 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
502 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
503 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
504 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
508 if (iod->npages == 0)
509 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
512 for (i = 0; i < iod->npages; i++) {
513 void *addr = nvme_pci_iod_list(req)[i];
516 struct nvme_sgl_desc *sg_list = addr;
519 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
521 __le64 *prp_list = addr;
523 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
526 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
527 dma_addr = next_dma_addr;
530 if (iod->sg != iod->inline_sg)
534 #ifdef CONFIG_BLK_DEV_INTEGRITY
535 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
537 if (be32_to_cpu(pi->ref_tag) == v)
538 pi->ref_tag = cpu_to_be32(p);
541 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
543 if (be32_to_cpu(pi->ref_tag) == p)
544 pi->ref_tag = cpu_to_be32(v);
548 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
550 * The virtual start sector is the one that was originally submitted by the
551 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
552 * start sector may be different. Remap protection information to match the
553 * physical LBA on writes, and back to the original seed on reads.
555 * Type 0 and 3 do not have a ref tag, so no remapping required.
557 static void nvme_dif_remap(struct request *req,
558 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
560 struct nvme_ns *ns = req->rq_disk->private_data;
561 struct bio_integrity_payload *bip;
562 struct t10_pi_tuple *pi;
564 u32 i, nlb, ts, phys, virt;
566 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
569 bip = bio_integrity(req->bio);
573 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
576 virt = bip_get_seed(bip);
577 phys = nvme_block_nr(ns, blk_rq_pos(req));
578 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
579 ts = ns->disk->queue->integrity.tuple_size;
581 for (i = 0; i < nlb; i++, virt++, phys++) {
582 pi = (struct t10_pi_tuple *)p;
583 dif_swap(phys, virt, pi);
588 #else /* CONFIG_BLK_DEV_INTEGRITY */
589 static void nvme_dif_remap(struct request *req,
590 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
593 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
596 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
601 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
604 struct scatterlist *sg;
606 for_each_sg(sgl, sg, nents, i) {
607 dma_addr_t phys = sg_phys(sg);
608 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
609 "dma_address:%pad dma_length:%d\n",
610 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
615 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
616 struct request *req, struct nvme_rw_command *cmnd)
618 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
619 struct dma_pool *pool;
620 int length = blk_rq_payload_bytes(req);
621 struct scatterlist *sg = iod->sg;
622 int dma_len = sg_dma_len(sg);
623 u64 dma_addr = sg_dma_address(sg);
624 u32 page_size = dev->ctrl.page_size;
625 int offset = dma_addr & (page_size - 1);
627 void **list = nvme_pci_iod_list(req);
631 length -= (page_size - offset);
637 dma_len -= (page_size - offset);
639 dma_addr += (page_size - offset);
642 dma_addr = sg_dma_address(sg);
643 dma_len = sg_dma_len(sg);
646 if (length <= page_size) {
647 iod->first_dma = dma_addr;
651 nprps = DIV_ROUND_UP(length, page_size);
652 if (nprps <= (256 / 8)) {
653 pool = dev->prp_small_pool;
656 pool = dev->prp_page_pool;
660 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
662 iod->first_dma = dma_addr;
664 return BLK_STS_RESOURCE;
667 iod->first_dma = prp_dma;
670 if (i == page_size >> 3) {
671 __le64 *old_prp_list = prp_list;
672 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
674 return BLK_STS_RESOURCE;
675 list[iod->npages++] = prp_list;
676 prp_list[0] = old_prp_list[i - 1];
677 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
680 prp_list[i++] = cpu_to_le64(dma_addr);
681 dma_len -= page_size;
682 dma_addr += page_size;
688 if (unlikely(dma_len < 0))
691 dma_addr = sg_dma_address(sg);
692 dma_len = sg_dma_len(sg);
696 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
697 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
702 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
703 "Invalid SGL for payload:%d nents:%d\n",
704 blk_rq_payload_bytes(req), iod->nents);
705 return BLK_STS_IOERR;
708 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
709 struct scatterlist *sg)
711 sge->addr = cpu_to_le64(sg_dma_address(sg));
712 sge->length = cpu_to_le32(sg_dma_len(sg));
713 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
716 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
717 dma_addr_t dma_addr, int entries)
719 sge->addr = cpu_to_le64(dma_addr);
720 if (entries < SGES_PER_PAGE) {
721 sge->length = cpu_to_le32(entries * sizeof(*sge));
722 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
724 sge->length = cpu_to_le32(PAGE_SIZE);
725 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
729 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
730 struct request *req, struct nvme_rw_command *cmd, int entries)
732 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
733 struct dma_pool *pool;
734 struct nvme_sgl_desc *sg_list;
735 struct scatterlist *sg = iod->sg;
739 /* setting the transfer type as SGL */
740 cmd->flags = NVME_CMD_SGL_METABUF;
743 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
747 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
748 pool = dev->prp_small_pool;
751 pool = dev->prp_page_pool;
755 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
758 return BLK_STS_RESOURCE;
761 nvme_pci_iod_list(req)[0] = sg_list;
762 iod->first_dma = sgl_dma;
764 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
767 if (i == SGES_PER_PAGE) {
768 struct nvme_sgl_desc *old_sg_desc = sg_list;
769 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
771 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
773 return BLK_STS_RESOURCE;
776 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
777 sg_list[i++] = *link;
778 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
781 nvme_pci_sgl_set_data(&sg_list[i++], sg);
783 } while (--entries > 0);
788 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
789 struct nvme_command *cmnd)
791 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
792 struct request_queue *q = req->q;
793 enum dma_data_direction dma_dir = rq_data_dir(req) ?
794 DMA_TO_DEVICE : DMA_FROM_DEVICE;
795 blk_status_t ret = BLK_STS_IOERR;
798 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
799 iod->nents = blk_rq_map_sg(q, req, iod->sg);
803 ret = BLK_STS_RESOURCE;
804 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
810 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
812 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
814 if (ret != BLK_STS_OK)
818 if (blk_integrity_rq(req)) {
819 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
822 sg_init_table(&iod->meta_sg, 1);
823 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
826 if (req_op(req) == REQ_OP_WRITE)
827 nvme_dif_remap(req, nvme_dif_prep);
829 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
833 if (blk_integrity_rq(req))
834 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
838 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
843 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
845 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
846 enum dma_data_direction dma_dir = rq_data_dir(req) ?
847 DMA_TO_DEVICE : DMA_FROM_DEVICE;
850 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
851 if (blk_integrity_rq(req)) {
852 if (req_op(req) == REQ_OP_READ)
853 nvme_dif_remap(req, nvme_dif_complete);
854 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
858 nvme_cleanup_cmd(req);
859 nvme_free_iod(dev, req);
863 * NOTE: ns is NULL when called on the admin queue.
865 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
866 const struct blk_mq_queue_data *bd)
868 struct nvme_ns *ns = hctx->queue->queuedata;
869 struct nvme_queue *nvmeq = hctx->driver_data;
870 struct nvme_dev *dev = nvmeq->dev;
871 struct request *req = bd->rq;
872 struct nvme_command cmnd;
875 ret = nvme_setup_cmd(ns, req, &cmnd);
879 ret = nvme_init_iod(req, dev);
883 if (blk_rq_nr_phys_segments(req)) {
884 ret = nvme_map_data(dev, req, &cmnd);
886 goto out_cleanup_iod;
889 blk_mq_start_request(req);
891 spin_lock_irq(&nvmeq->q_lock);
892 if (unlikely(nvmeq->cq_vector < 0)) {
894 spin_unlock_irq(&nvmeq->q_lock);
895 goto out_cleanup_iod;
897 __nvme_submit_cmd(nvmeq, &cmnd);
898 nvme_process_cq(nvmeq);
899 spin_unlock_irq(&nvmeq->q_lock);
902 nvme_free_iod(dev, req);
904 nvme_cleanup_cmd(req);
908 static void nvme_pci_complete_rq(struct request *req)
910 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
912 nvme_unmap_data(iod->nvmeq->dev, req);
913 nvme_complete_rq(req);
916 /* We read the CQE phase first to check if the rest of the entry is valid */
917 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
920 return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
923 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
925 u16 head = nvmeq->cq_head;
927 if (likely(nvmeq->cq_vector >= 0)) {
928 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
930 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
934 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
935 struct nvme_completion *cqe)
939 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
940 dev_warn(nvmeq->dev->ctrl.device,
941 "invalid id %d completed on queue %d\n",
942 cqe->command_id, le16_to_cpu(cqe->sq_id));
947 * AEN requests are special as they don't time out and can
948 * survive any kind of queue freeze and often don't respond to
949 * aborts. We don't even bother to allocate a struct request
950 * for them but rather special case them here.
952 if (unlikely(nvmeq->qid == 0 &&
953 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
954 nvme_complete_async_event(&nvmeq->dev->ctrl,
955 cqe->status, &cqe->result);
960 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
961 nvme_end_request(req, cqe->status, cqe->result);
964 static inline bool nvme_read_cqe(struct nvme_queue *nvmeq,
965 struct nvme_completion *cqe)
967 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
968 *cqe = nvmeq->cqes[nvmeq->cq_head];
970 if (++nvmeq->cq_head == nvmeq->q_depth) {
972 nvmeq->cq_phase = !nvmeq->cq_phase;
979 static void nvme_process_cq(struct nvme_queue *nvmeq)
981 struct nvme_completion cqe;
984 while (nvme_read_cqe(nvmeq, &cqe)) {
985 nvme_handle_cqe(nvmeq, &cqe);
990 nvme_ring_cq_doorbell(nvmeq);
993 static irqreturn_t nvme_irq(int irq, void *data)
996 struct nvme_queue *nvmeq = data;
997 spin_lock(&nvmeq->q_lock);
998 nvme_process_cq(nvmeq);
999 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
1000 nvmeq->cqe_seen = 0;
1001 spin_unlock(&nvmeq->q_lock);
1005 static irqreturn_t nvme_irq_check(int irq, void *data)
1007 struct nvme_queue *nvmeq = data;
1008 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
1009 return IRQ_WAKE_THREAD;
1013 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
1015 struct nvme_completion cqe;
1016 int found = 0, consumed = 0;
1018 if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
1021 spin_lock_irq(&nvmeq->q_lock);
1022 while (nvme_read_cqe(nvmeq, &cqe)) {
1023 nvme_handle_cqe(nvmeq, &cqe);
1026 if (tag == cqe.command_id) {
1033 nvme_ring_cq_doorbell(nvmeq);
1034 spin_unlock_irq(&nvmeq->q_lock);
1039 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1041 struct nvme_queue *nvmeq = hctx->driver_data;
1043 return __nvme_poll(nvmeq, tag);
1046 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1048 struct nvme_dev *dev = to_nvme_dev(ctrl);
1049 struct nvme_queue *nvmeq = &dev->queues[0];
1050 struct nvme_command c;
1052 memset(&c, 0, sizeof(c));
1053 c.common.opcode = nvme_admin_async_event;
1054 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1056 spin_lock_irq(&nvmeq->q_lock);
1057 __nvme_submit_cmd(nvmeq, &c);
1058 spin_unlock_irq(&nvmeq->q_lock);
1061 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1063 struct nvme_command c;
1065 memset(&c, 0, sizeof(c));
1066 c.delete_queue.opcode = opcode;
1067 c.delete_queue.qid = cpu_to_le16(id);
1069 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1072 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1073 struct nvme_queue *nvmeq)
1075 struct nvme_command c;
1076 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1079 * Note: we (ab)use the fact that the prp fields survive if no data
1080 * is attached to the request.
1082 memset(&c, 0, sizeof(c));
1083 c.create_cq.opcode = nvme_admin_create_cq;
1084 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1085 c.create_cq.cqid = cpu_to_le16(qid);
1086 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1087 c.create_cq.cq_flags = cpu_to_le16(flags);
1088 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1090 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1093 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1094 struct nvme_queue *nvmeq)
1096 struct nvme_ctrl *ctrl = &dev->ctrl;
1097 struct nvme_command c;
1098 int flags = NVME_QUEUE_PHYS_CONTIG;
1101 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1102 * set. Since URGENT priority is zeroes, it makes all queues
1105 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1106 flags |= NVME_SQ_PRIO_MEDIUM;
1109 * Note: we (ab)use the fact that the prp fields survive if no data
1110 * is attached to the request.
1112 memset(&c, 0, sizeof(c));
1113 c.create_sq.opcode = nvme_admin_create_sq;
1114 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1115 c.create_sq.sqid = cpu_to_le16(qid);
1116 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1117 c.create_sq.sq_flags = cpu_to_le16(flags);
1118 c.create_sq.cqid = cpu_to_le16(qid);
1120 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1123 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1125 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1128 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1130 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1133 static void abort_endio(struct request *req, blk_status_t error)
1135 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1136 struct nvme_queue *nvmeq = iod->nvmeq;
1138 dev_warn(nvmeq->dev->ctrl.device,
1139 "Abort status: 0x%x", nvme_req(req)->status);
1140 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1141 blk_mq_free_request(req);
1144 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1147 /* If true, indicates loss of adapter communication, possibly by a
1148 * NVMe Subsystem reset.
1150 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1152 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1153 switch (dev->ctrl.state) {
1154 case NVME_CTRL_RESETTING:
1155 case NVME_CTRL_CONNECTING:
1161 /* We shouldn't reset unless the controller is on fatal error state
1162 * _or_ if we lost the communication with it.
1164 if (!(csts & NVME_CSTS_CFS) && !nssro)
1170 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1172 /* Read a config register to help see what died. */
1176 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1178 if (result == PCIBIOS_SUCCESSFUL)
1179 dev_warn(dev->ctrl.device,
1180 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1183 dev_warn(dev->ctrl.device,
1184 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1188 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1190 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1191 struct nvme_queue *nvmeq = iod->nvmeq;
1192 struct nvme_dev *dev = nvmeq->dev;
1193 struct request *abort_req;
1194 struct nvme_command cmd;
1195 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1197 /* If PCI error recovery process is happening, we cannot reset or
1198 * the recovery mechanism will surely fail.
1201 if (pci_channel_offline(to_pci_dev(dev->dev)))
1202 return BLK_EH_RESET_TIMER;
1205 * Reset immediately if the controller is failed
1207 if (nvme_should_reset(dev, csts)) {
1208 nvme_warn_reset(dev, csts);
1209 nvme_dev_disable(dev, false);
1210 nvme_reset_ctrl(&dev->ctrl);
1211 return BLK_EH_HANDLED;
1215 * Did we miss an interrupt?
1217 if (__nvme_poll(nvmeq, req->tag)) {
1218 dev_warn(dev->ctrl.device,
1219 "I/O %d QID %d timeout, completion polled\n",
1220 req->tag, nvmeq->qid);
1221 return BLK_EH_HANDLED;
1225 * Shutdown immediately if controller times out while starting. The
1226 * reset work will see the pci device disabled when it gets the forced
1227 * cancellation error. All outstanding requests are completed on
1228 * shutdown, so we return BLK_EH_HANDLED.
1230 switch (dev->ctrl.state) {
1231 case NVME_CTRL_CONNECTING:
1232 case NVME_CTRL_RESETTING:
1233 dev_warn(dev->ctrl.device,
1234 "I/O %d QID %d timeout, disable controller\n",
1235 req->tag, nvmeq->qid);
1236 nvme_dev_disable(dev, false);
1237 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1238 return BLK_EH_HANDLED;
1244 * Shutdown the controller immediately and schedule a reset if the
1245 * command was already aborted once before and still hasn't been
1246 * returned to the driver, or if this is the admin queue.
1248 if (!nvmeq->qid || iod->aborted) {
1249 dev_warn(dev->ctrl.device,
1250 "I/O %d QID %d timeout, reset controller\n",
1251 req->tag, nvmeq->qid);
1252 nvme_dev_disable(dev, false);
1253 nvme_reset_ctrl(&dev->ctrl);
1256 * Mark the request as handled, since the inline shutdown
1257 * forces all outstanding requests to complete.
1259 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1260 return BLK_EH_HANDLED;
1263 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1264 atomic_inc(&dev->ctrl.abort_limit);
1265 return BLK_EH_RESET_TIMER;
1269 memset(&cmd, 0, sizeof(cmd));
1270 cmd.abort.opcode = nvme_admin_abort_cmd;
1271 cmd.abort.cid = req->tag;
1272 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1274 dev_warn(nvmeq->dev->ctrl.device,
1275 "I/O %d QID %d timeout, aborting\n",
1276 req->tag, nvmeq->qid);
1278 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1279 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1280 if (IS_ERR(abort_req)) {
1281 atomic_inc(&dev->ctrl.abort_limit);
1282 return BLK_EH_RESET_TIMER;
1285 abort_req->timeout = ADMIN_TIMEOUT;
1286 abort_req->end_io_data = NULL;
1287 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1290 * The aborted req will be completed on receiving the abort req.
1291 * We enable the timer again. If hit twice, it'll cause a device reset,
1292 * as the device then is in a faulty state.
1294 return BLK_EH_RESET_TIMER;
1297 static void nvme_free_queue(struct nvme_queue *nvmeq)
1299 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1300 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1302 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1303 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1306 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1310 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1311 dev->ctrl.queue_count--;
1312 nvme_free_queue(&dev->queues[i]);
1317 * nvme_suspend_queue - put queue into suspended state
1318 * @nvmeq - queue to suspend
1320 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1324 spin_lock_irq(&nvmeq->q_lock);
1325 if (nvmeq->cq_vector == -1) {
1326 spin_unlock_irq(&nvmeq->q_lock);
1329 vector = nvmeq->cq_vector;
1330 nvmeq->dev->online_queues--;
1331 nvmeq->cq_vector = -1;
1332 spin_unlock_irq(&nvmeq->q_lock);
1334 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1335 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1337 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1342 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1344 struct nvme_queue *nvmeq = &dev->queues[0];
1347 nvme_shutdown_ctrl(&dev->ctrl);
1349 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1351 spin_lock_irq(&nvmeq->q_lock);
1352 nvme_process_cq(nvmeq);
1353 spin_unlock_irq(&nvmeq->q_lock);
1356 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1359 int q_depth = dev->q_depth;
1360 unsigned q_size_aligned = roundup(q_depth * entry_size,
1361 dev->ctrl.page_size);
1363 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1364 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1365 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1366 q_depth = div_u64(mem_per_q, entry_size);
1369 * Ensure the reduced q_depth is above some threshold where it
1370 * would be better to map queues in system memory with the
1380 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1383 /* CMB SQEs will be mapped before creation */
1384 if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS))
1387 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1388 &nvmeq->sq_dma_addr, GFP_KERNEL);
1389 if (!nvmeq->sq_cmds)
1394 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1396 struct nvme_queue *nvmeq = &dev->queues[qid];
1398 if (dev->ctrl.queue_count > qid)
1401 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1402 &nvmeq->cq_dma_addr, GFP_KERNEL);
1406 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1409 nvmeq->q_dmadev = dev->dev;
1411 spin_lock_init(&nvmeq->q_lock);
1413 nvmeq->cq_phase = 1;
1414 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1415 nvmeq->q_depth = depth;
1417 nvmeq->cq_vector = -1;
1418 dev->ctrl.queue_count++;
1423 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1424 nvmeq->cq_dma_addr);
1429 static int queue_request_irq(struct nvme_queue *nvmeq)
1431 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1432 int nr = nvmeq->dev->ctrl.instance;
1434 if (use_threaded_interrupts) {
1435 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1436 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1438 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1439 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1443 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1445 struct nvme_dev *dev = nvmeq->dev;
1447 spin_lock_irq(&nvmeq->q_lock);
1450 nvmeq->cq_phase = 1;
1451 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1452 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1453 nvme_dbbuf_init(dev, nvmeq, qid);
1454 dev->online_queues++;
1455 spin_unlock_irq(&nvmeq->q_lock);
1458 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1460 struct nvme_dev *dev = nvmeq->dev;
1463 if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1464 unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth),
1465 dev->ctrl.page_size);
1466 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
1467 nvmeq->sq_cmds_io = dev->cmb + offset;
1471 * A queue's vector matches the queue identifier unless the controller
1472 * has only one vector available.
1474 nvmeq->cq_vector = dev->num_vecs == 1 ? 0 : qid;
1475 result = adapter_alloc_cq(dev, qid, nvmeq);
1477 goto release_vector;
1479 result = adapter_alloc_sq(dev, qid, nvmeq);
1483 nvme_init_queue(nvmeq, qid);
1484 result = queue_request_irq(nvmeq);
1491 dev->online_queues--;
1492 adapter_delete_sq(dev, qid);
1494 adapter_delete_cq(dev, qid);
1496 nvmeq->cq_vector = -1;
1500 static const struct blk_mq_ops nvme_mq_admin_ops = {
1501 .queue_rq = nvme_queue_rq,
1502 .complete = nvme_pci_complete_rq,
1503 .init_hctx = nvme_admin_init_hctx,
1504 .exit_hctx = nvme_admin_exit_hctx,
1505 .init_request = nvme_init_request,
1506 .timeout = nvme_timeout,
1509 static const struct blk_mq_ops nvme_mq_ops = {
1510 .queue_rq = nvme_queue_rq,
1511 .complete = nvme_pci_complete_rq,
1512 .init_hctx = nvme_init_hctx,
1513 .init_request = nvme_init_request,
1514 .map_queues = nvme_pci_map_queues,
1515 .timeout = nvme_timeout,
1519 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1521 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1523 * If the controller was reset during removal, it's possible
1524 * user requests may be waiting on a stopped queue. Start the
1525 * queue to flush these to completion.
1527 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1528 blk_cleanup_queue(dev->ctrl.admin_q);
1529 blk_mq_free_tag_set(&dev->admin_tagset);
1533 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1535 if (!dev->ctrl.admin_q) {
1536 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1537 dev->admin_tagset.nr_hw_queues = 1;
1539 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1540 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1541 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1542 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
1543 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1544 dev->admin_tagset.driver_data = dev;
1546 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1548 dev->ctrl.admin_tagset = &dev->admin_tagset;
1550 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1551 if (IS_ERR(dev->ctrl.admin_q)) {
1552 blk_mq_free_tag_set(&dev->admin_tagset);
1555 if (!blk_get_queue(dev->ctrl.admin_q)) {
1556 nvme_dev_remove_admin(dev);
1557 dev->ctrl.admin_q = NULL;
1561 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1566 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1568 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1571 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1573 struct pci_dev *pdev = to_pci_dev(dev->dev);
1575 if (size <= dev->bar_mapped_size)
1577 if (size > pci_resource_len(pdev, 0))
1581 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1583 dev->bar_mapped_size = 0;
1586 dev->bar_mapped_size = size;
1587 dev->dbs = dev->bar + NVME_REG_DBS;
1592 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1596 struct nvme_queue *nvmeq;
1598 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1602 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1603 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1605 if (dev->subsystem &&
1606 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1607 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1609 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1613 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1617 nvmeq = &dev->queues[0];
1618 aqa = nvmeq->q_depth - 1;
1621 writel(aqa, dev->bar + NVME_REG_AQA);
1622 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1623 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1625 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1629 nvmeq->cq_vector = 0;
1630 nvme_init_queue(nvmeq, 0);
1631 result = queue_request_irq(nvmeq);
1633 nvmeq->cq_vector = -1;
1640 static int nvme_create_io_queues(struct nvme_dev *dev)
1645 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1646 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1652 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1653 for (i = dev->online_queues; i <= max; i++) {
1654 ret = nvme_create_queue(&dev->queues[i], i);
1660 * Ignore failing Create SQ/CQ commands, we can continue with less
1661 * than the desired amount of queues, and even a controller without
1662 * I/O queues can still be used to issue admin commands. This might
1663 * be useful to upgrade a buggy firmware for example.
1665 return ret >= 0 ? 0 : ret;
1668 static ssize_t nvme_cmb_show(struct device *dev,
1669 struct device_attribute *attr,
1672 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1674 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1675 ndev->cmbloc, ndev->cmbsz);
1677 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1679 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1681 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1683 return 1ULL << (12 + 4 * szu);
1686 static u32 nvme_cmb_size(struct nvme_dev *dev)
1688 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1691 static void nvme_map_cmb(struct nvme_dev *dev)
1694 resource_size_t bar_size;
1695 struct pci_dev *pdev = to_pci_dev(dev->dev);
1698 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1701 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1706 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1707 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1708 bar = NVME_CMB_BIR(dev->cmbloc);
1709 bar_size = pci_resource_len(pdev, bar);
1711 if (offset > bar_size)
1715 * Controllers may support a CMB size larger than their BAR,
1716 * for example, due to being behind a bridge. Reduce the CMB to
1717 * the reported size of the BAR
1719 if (size > bar_size - offset)
1720 size = bar_size - offset;
1722 dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
1725 dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
1726 dev->cmb_size = size;
1728 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1729 &dev_attr_cmb.attr, NULL))
1730 dev_warn(dev->ctrl.device,
1731 "failed to add sysfs attribute for CMB\n");
1734 static inline void nvme_release_cmb(struct nvme_dev *dev)
1739 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1740 &dev_attr_cmb.attr, NULL);
1745 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1747 u64 dma_addr = dev->host_mem_descs_dma;
1748 struct nvme_command c;
1751 memset(&c, 0, sizeof(c));
1752 c.features.opcode = nvme_admin_set_features;
1753 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1754 c.features.dword11 = cpu_to_le32(bits);
1755 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1756 ilog2(dev->ctrl.page_size));
1757 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1758 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1759 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1761 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1763 dev_warn(dev->ctrl.device,
1764 "failed to set host mem (err %d, flags %#x).\n",
1770 static void nvme_free_host_mem(struct nvme_dev *dev)
1774 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1775 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1776 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1778 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1779 le64_to_cpu(desc->addr));
1782 kfree(dev->host_mem_desc_bufs);
1783 dev->host_mem_desc_bufs = NULL;
1784 dma_free_coherent(dev->dev,
1785 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1786 dev->host_mem_descs, dev->host_mem_descs_dma);
1787 dev->host_mem_descs = NULL;
1788 dev->nr_host_mem_descs = 0;
1791 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1794 struct nvme_host_mem_buf_desc *descs;
1795 u32 max_entries, len;
1796 dma_addr_t descs_dma;
1801 tmp = (preferred + chunk_size - 1);
1802 do_div(tmp, chunk_size);
1805 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1806 max_entries = dev->ctrl.hmmaxd;
1808 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1809 &descs_dma, GFP_KERNEL);
1813 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1815 goto out_free_descs;
1817 for (size = 0; size < preferred && i < max_entries; size += len) {
1818 dma_addr_t dma_addr;
1820 len = min_t(u64, chunk_size, preferred - size);
1821 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1822 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1826 descs[i].addr = cpu_to_le64(dma_addr);
1827 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1834 dev->nr_host_mem_descs = i;
1835 dev->host_mem_size = size;
1836 dev->host_mem_descs = descs;
1837 dev->host_mem_descs_dma = descs_dma;
1838 dev->host_mem_desc_bufs = bufs;
1843 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1845 dma_free_coherent(dev->dev, size, bufs[i],
1846 le64_to_cpu(descs[i].addr));
1851 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1854 dev->host_mem_descs = NULL;
1858 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1862 /* start big and work our way down */
1863 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1864 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1866 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1867 if (!min || dev->host_mem_size >= min)
1869 nvme_free_host_mem(dev);
1876 static int nvme_setup_host_mem(struct nvme_dev *dev)
1878 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1879 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1880 u64 min = (u64)dev->ctrl.hmmin * 4096;
1881 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1884 preferred = min(preferred, max);
1886 dev_warn(dev->ctrl.device,
1887 "min host memory (%lld MiB) above limit (%d MiB).\n",
1888 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1889 nvme_free_host_mem(dev);
1894 * If we already have a buffer allocated check if we can reuse it.
1896 if (dev->host_mem_descs) {
1897 if (dev->host_mem_size >= min)
1898 enable_bits |= NVME_HOST_MEM_RETURN;
1900 nvme_free_host_mem(dev);
1903 if (!dev->host_mem_descs) {
1904 if (nvme_alloc_host_mem(dev, min, preferred)) {
1905 dev_warn(dev->ctrl.device,
1906 "failed to allocate host memory buffer.\n");
1907 return 0; /* controller must work without HMB */
1910 dev_info(dev->ctrl.device,
1911 "allocated %lld MiB host memory buffer.\n",
1912 dev->host_mem_size >> ilog2(SZ_1M));
1915 ret = nvme_set_host_mem(dev, enable_bits);
1917 nvme_free_host_mem(dev);
1921 static int nvme_setup_io_queues(struct nvme_dev *dev)
1923 struct nvme_queue *adminq = &dev->queues[0];
1924 struct pci_dev *pdev = to_pci_dev(dev->dev);
1925 int result, nr_io_queues;
1928 struct irq_affinity affd = {
1932 nr_io_queues = num_possible_cpus();
1933 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1937 if (nr_io_queues == 0)
1940 if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1941 result = nvme_cmb_qdepth(dev, nr_io_queues,
1942 sizeof(struct nvme_command));
1944 dev->q_depth = result;
1946 nvme_release_cmb(dev);
1950 size = db_bar_size(dev, nr_io_queues);
1951 result = nvme_remap_bar(dev, size);
1954 if (!--nr_io_queues)
1957 adminq->q_db = dev->dbs;
1959 /* Deregister the admin queue's interrupt */
1960 pci_free_irq(pdev, 0, adminq);
1963 * If we enable msix early due to not intx, disable it again before
1964 * setting up the full range we need.
1966 pci_free_irq_vectors(pdev);
1967 result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1,
1968 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
1971 dev->num_vecs = result;
1972 dev->max_qid = max(result - 1, 1);
1975 * Should investigate if there's a performance win from allocating
1976 * more queues than interrupt vectors; it might allow the submission
1977 * path to scale better, even if the receive path is limited by the
1978 * number of interrupts.
1981 result = queue_request_irq(adminq);
1983 adminq->cq_vector = -1;
1986 return nvme_create_io_queues(dev);
1989 static void nvme_del_queue_end(struct request *req, blk_status_t error)
1991 struct nvme_queue *nvmeq = req->end_io_data;
1993 blk_mq_free_request(req);
1994 complete(&nvmeq->dev->ioq_wait);
1997 static void nvme_del_cq_end(struct request *req, blk_status_t error)
1999 struct nvme_queue *nvmeq = req->end_io_data;
2002 unsigned long flags;
2005 * We might be called with the AQ q_lock held
2006 * and the I/O queue q_lock should always
2007 * nest inside the AQ one.
2009 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
2010 SINGLE_DEPTH_NESTING);
2011 nvme_process_cq(nvmeq);
2012 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
2015 nvme_del_queue_end(req, error);
2018 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2020 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2021 struct request *req;
2022 struct nvme_command cmd;
2024 memset(&cmd, 0, sizeof(cmd));
2025 cmd.delete_queue.opcode = opcode;
2026 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2028 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2030 return PTR_ERR(req);
2032 req->timeout = ADMIN_TIMEOUT;
2033 req->end_io_data = nvmeq;
2035 blk_execute_rq_nowait(q, NULL, req, false,
2036 opcode == nvme_admin_delete_cq ?
2037 nvme_del_cq_end : nvme_del_queue_end);
2041 static void nvme_disable_io_queues(struct nvme_dev *dev)
2043 int pass, queues = dev->online_queues - 1;
2044 unsigned long timeout;
2045 u8 opcode = nvme_admin_delete_sq;
2047 for (pass = 0; pass < 2; pass++) {
2048 int sent = 0, i = queues;
2050 reinit_completion(&dev->ioq_wait);
2052 timeout = ADMIN_TIMEOUT;
2053 for (; i > 0; i--, sent++)
2054 if (nvme_delete_queue(&dev->queues[i], opcode))
2058 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2064 opcode = nvme_admin_delete_cq;
2069 * return error value only when tagset allocation failed
2071 static int nvme_dev_add(struct nvme_dev *dev)
2075 if (!dev->ctrl.tagset) {
2076 dev->tagset.ops = &nvme_mq_ops;
2077 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2078 dev->tagset.timeout = NVME_IO_TIMEOUT;
2079 dev->tagset.numa_node = dev_to_node(dev->dev);
2080 dev->tagset.queue_depth =
2081 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2082 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2083 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2084 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2085 nvme_pci_cmd_size(dev, true));
2087 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2088 dev->tagset.driver_data = dev;
2090 ret = blk_mq_alloc_tag_set(&dev->tagset);
2092 dev_warn(dev->ctrl.device,
2093 "IO queues tagset allocation failed %d\n", ret);
2096 dev->ctrl.tagset = &dev->tagset;
2098 nvme_dbbuf_set(dev);
2100 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2102 /* Free previously allocated queues that are no longer usable */
2103 nvme_free_queues(dev, dev->online_queues);
2109 static int nvme_pci_enable(struct nvme_dev *dev)
2111 int result = -ENOMEM;
2112 struct pci_dev *pdev = to_pci_dev(dev->dev);
2114 if (pci_enable_device_mem(pdev))
2117 pci_set_master(pdev);
2119 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2120 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2123 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2129 * Some devices and/or platforms don't advertise or work with INTx
2130 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2131 * adjust this later.
2133 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2137 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2139 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2141 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2142 dev->dbs = dev->bar + 4096;
2145 * Temporary fix for the Apple controller found in the MacBook8,1 and
2146 * some MacBook7,1 to avoid controller resets and data loss.
2148 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2150 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2151 "set queue depth=%u to work around controller resets\n",
2153 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2154 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2155 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2157 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2158 "set queue depth=%u\n", dev->q_depth);
2163 pci_enable_pcie_error_reporting(pdev);
2164 pci_save_state(pdev);
2168 pci_disable_device(pdev);
2172 static void nvme_dev_unmap(struct nvme_dev *dev)
2176 pci_release_mem_regions(to_pci_dev(dev->dev));
2179 static void nvme_pci_disable(struct nvme_dev *dev)
2181 struct pci_dev *pdev = to_pci_dev(dev->dev);
2183 nvme_release_cmb(dev);
2184 pci_free_irq_vectors(pdev);
2186 if (pci_is_enabled(pdev)) {
2187 pci_disable_pcie_error_reporting(pdev);
2188 pci_disable_device(pdev);
2192 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2196 struct pci_dev *pdev = to_pci_dev(dev->dev);
2198 mutex_lock(&dev->shutdown_lock);
2199 if (pci_is_enabled(pdev)) {
2200 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2202 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2203 dev->ctrl.state == NVME_CTRL_RESETTING)
2204 nvme_start_freeze(&dev->ctrl);
2205 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2206 pdev->error_state != pci_channel_io_normal);
2210 * Give the controller a chance to complete all entered requests if
2211 * doing a safe shutdown.
2215 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2218 nvme_stop_queues(&dev->ctrl);
2220 if (!dead && dev->ctrl.queue_count > 0) {
2222 * If the controller is still alive tell it to stop using the
2223 * host memory buffer. In theory the shutdown / reset should
2224 * make sure that it doesn't access the host memoery anymore,
2225 * but I'd rather be safe than sorry..
2227 if (dev->host_mem_descs)
2228 nvme_set_host_mem(dev, 0);
2229 nvme_disable_io_queues(dev);
2230 nvme_disable_admin_queue(dev, shutdown);
2232 for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2233 nvme_suspend_queue(&dev->queues[i]);
2235 nvme_pci_disable(dev);
2237 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2238 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2241 * The driver will not be starting up queues again if shutting down so
2242 * must flush all entered requests to their failed completion to avoid
2243 * deadlocking blk-mq hot-cpu notifier.
2246 nvme_start_queues(&dev->ctrl);
2247 mutex_unlock(&dev->shutdown_lock);
2250 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2252 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2253 PAGE_SIZE, PAGE_SIZE, 0);
2254 if (!dev->prp_page_pool)
2257 /* Optimisation for I/Os between 4k and 128k */
2258 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2260 if (!dev->prp_small_pool) {
2261 dma_pool_destroy(dev->prp_page_pool);
2267 static void nvme_release_prp_pools(struct nvme_dev *dev)
2269 dma_pool_destroy(dev->prp_page_pool);
2270 dma_pool_destroy(dev->prp_small_pool);
2273 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2275 struct nvme_dev *dev = to_nvme_dev(ctrl);
2277 nvme_dbbuf_dma_free(dev);
2278 put_device(dev->dev);
2279 if (dev->tagset.tags)
2280 blk_mq_free_tag_set(&dev->tagset);
2281 if (dev->ctrl.admin_q)
2282 blk_put_queue(dev->ctrl.admin_q);
2284 free_opal_dev(dev->ctrl.opal_dev);
2288 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2290 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2292 nvme_get_ctrl(&dev->ctrl);
2293 nvme_dev_disable(dev, false);
2294 if (!queue_work(nvme_wq, &dev->remove_work))
2295 nvme_put_ctrl(&dev->ctrl);
2298 static void nvme_reset_work(struct work_struct *work)
2300 struct nvme_dev *dev =
2301 container_of(work, struct nvme_dev, ctrl.reset_work);
2302 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2303 int result = -ENODEV;
2304 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
2306 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2310 * If we're called to reset a live controller first shut it down before
2313 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2314 nvme_dev_disable(dev, false);
2317 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2318 * initializing procedure here.
2320 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2321 dev_warn(dev->ctrl.device,
2322 "failed to mark controller CONNECTING\n");
2326 result = nvme_pci_enable(dev);
2330 result = nvme_pci_configure_admin_queue(dev);
2334 result = nvme_alloc_admin_tags(dev);
2338 result = nvme_init_identify(&dev->ctrl);
2342 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2343 if (!dev->ctrl.opal_dev)
2344 dev->ctrl.opal_dev =
2345 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2346 else if (was_suspend)
2347 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2349 free_opal_dev(dev->ctrl.opal_dev);
2350 dev->ctrl.opal_dev = NULL;
2353 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2354 result = nvme_dbbuf_dma_alloc(dev);
2357 "unable to allocate dma for dbbuf\n");
2360 if (dev->ctrl.hmpre) {
2361 result = nvme_setup_host_mem(dev);
2366 result = nvme_setup_io_queues(dev);
2371 * Keep the controller around but remove all namespaces if we don't have
2372 * any working I/O queue.
2374 if (dev->online_queues < 2) {
2375 dev_warn(dev->ctrl.device, "IO queues not created\n");
2376 nvme_kill_queues(&dev->ctrl);
2377 nvme_remove_namespaces(&dev->ctrl);
2378 new_state = NVME_CTRL_ADMIN_ONLY;
2380 nvme_start_queues(&dev->ctrl);
2381 nvme_wait_freeze(&dev->ctrl);
2382 /* hit this only when allocate tagset fails */
2383 if (nvme_dev_add(dev))
2384 new_state = NVME_CTRL_ADMIN_ONLY;
2385 nvme_unfreeze(&dev->ctrl);
2389 * If only admin queue live, keep it to do further investigation or
2392 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2393 dev_warn(dev->ctrl.device,
2394 "failed to mark controller state %d\n", new_state);
2398 nvme_start_ctrl(&dev->ctrl);
2402 nvme_remove_dead_ctrl(dev, result);
2405 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2407 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2408 struct pci_dev *pdev = to_pci_dev(dev->dev);
2410 nvme_kill_queues(&dev->ctrl);
2411 if (pci_get_drvdata(pdev))
2412 device_release_driver(&pdev->dev);
2413 nvme_put_ctrl(&dev->ctrl);
2416 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2418 *val = readl(to_nvme_dev(ctrl)->bar + off);
2422 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2424 writel(val, to_nvme_dev(ctrl)->bar + off);
2428 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2430 *val = readq(to_nvme_dev(ctrl)->bar + off);
2434 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2436 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2438 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2441 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2443 .module = THIS_MODULE,
2444 .flags = NVME_F_METADATA_SUPPORTED,
2445 .reg_read32 = nvme_pci_reg_read32,
2446 .reg_write32 = nvme_pci_reg_write32,
2447 .reg_read64 = nvme_pci_reg_read64,
2448 .free_ctrl = nvme_pci_free_ctrl,
2449 .submit_async_event = nvme_pci_submit_async_event,
2450 .get_address = nvme_pci_get_address,
2453 static int nvme_dev_map(struct nvme_dev *dev)
2455 struct pci_dev *pdev = to_pci_dev(dev->dev);
2457 if (pci_request_mem_regions(pdev, "nvme"))
2460 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2465 pci_release_mem_regions(pdev);
2469 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2471 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2473 * Several Samsung devices seem to drop off the PCIe bus
2474 * randomly when APST is on and uses the deepest sleep state.
2475 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2476 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2477 * 950 PRO 256GB", but it seems to be restricted to two Dell
2480 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2481 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2482 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2483 return NVME_QUIRK_NO_DEEPEST_PS;
2484 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2486 * Samsung SSD 960 EVO drops off the PCIe bus after system
2487 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2488 * within few minutes after bootup on a Coffee Lake board -
2491 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2492 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2493 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2494 return NVME_QUIRK_NO_APST;
2500 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2502 int node, result = -ENOMEM;
2503 struct nvme_dev *dev;
2504 unsigned long quirks = id->driver_data;
2506 node = dev_to_node(&pdev->dev);
2507 if (node == NUMA_NO_NODE)
2508 set_dev_node(&pdev->dev, first_memory_node);
2510 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2514 dev->queues = kcalloc_node(num_possible_cpus() + 1,
2515 sizeof(struct nvme_queue), GFP_KERNEL, node);
2519 dev->dev = get_device(&pdev->dev);
2520 pci_set_drvdata(pdev, dev);
2522 result = nvme_dev_map(dev);
2526 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2527 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2528 mutex_init(&dev->shutdown_lock);
2529 init_completion(&dev->ioq_wait);
2531 result = nvme_setup_prp_pools(dev);
2535 quirks |= check_vendor_combination_bug(pdev);
2537 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2542 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2544 nvme_reset_ctrl(&dev->ctrl);
2549 nvme_release_prp_pools(dev);
2551 nvme_dev_unmap(dev);
2553 put_device(dev->dev);
2560 static void nvme_reset_prepare(struct pci_dev *pdev)
2562 struct nvme_dev *dev = pci_get_drvdata(pdev);
2563 nvme_dev_disable(dev, false);
2566 static void nvme_reset_done(struct pci_dev *pdev)
2568 struct nvme_dev *dev = pci_get_drvdata(pdev);
2569 nvme_reset_ctrl_sync(&dev->ctrl);
2572 static void nvme_shutdown(struct pci_dev *pdev)
2574 struct nvme_dev *dev = pci_get_drvdata(pdev);
2575 nvme_dev_disable(dev, true);
2579 * The driver's remove may be called on a device in a partially initialized
2580 * state. This function must not have any dependencies on the device state in
2583 static void nvme_remove(struct pci_dev *pdev)
2585 struct nvme_dev *dev = pci_get_drvdata(pdev);
2587 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2589 cancel_work_sync(&dev->ctrl.reset_work);
2590 pci_set_drvdata(pdev, NULL);
2592 if (!pci_device_is_present(pdev)) {
2593 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2594 nvme_dev_disable(dev, false);
2597 flush_work(&dev->ctrl.reset_work);
2598 nvme_stop_ctrl(&dev->ctrl);
2599 nvme_remove_namespaces(&dev->ctrl);
2600 nvme_dev_disable(dev, true);
2601 nvme_free_host_mem(dev);
2602 nvme_dev_remove_admin(dev);
2603 nvme_free_queues(dev, 0);
2604 nvme_uninit_ctrl(&dev->ctrl);
2605 nvme_release_prp_pools(dev);
2606 nvme_dev_unmap(dev);
2607 nvme_put_ctrl(&dev->ctrl);
2610 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2615 if (pci_vfs_assigned(pdev)) {
2616 dev_warn(&pdev->dev,
2617 "Cannot disable SR-IOV VFs while assigned\n");
2620 pci_disable_sriov(pdev);
2624 ret = pci_enable_sriov(pdev, numvfs);
2625 return ret ? ret : numvfs;
2628 #ifdef CONFIG_PM_SLEEP
2629 static int nvme_suspend(struct device *dev)
2631 struct pci_dev *pdev = to_pci_dev(dev);
2632 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2634 nvme_dev_disable(ndev, true);
2638 static int nvme_resume(struct device *dev)
2640 struct pci_dev *pdev = to_pci_dev(dev);
2641 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2643 nvme_reset_ctrl(&ndev->ctrl);
2648 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2650 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2651 pci_channel_state_t state)
2653 struct nvme_dev *dev = pci_get_drvdata(pdev);
2656 * A frozen channel requires a reset. When detected, this method will
2657 * shutdown the controller to quiesce. The controller will be restarted
2658 * after the slot reset through driver's slot_reset callback.
2661 case pci_channel_io_normal:
2662 return PCI_ERS_RESULT_CAN_RECOVER;
2663 case pci_channel_io_frozen:
2664 dev_warn(dev->ctrl.device,
2665 "frozen state error detected, reset controller\n");
2666 nvme_dev_disable(dev, false);
2667 return PCI_ERS_RESULT_NEED_RESET;
2668 case pci_channel_io_perm_failure:
2669 dev_warn(dev->ctrl.device,
2670 "failure state error detected, request disconnect\n");
2671 return PCI_ERS_RESULT_DISCONNECT;
2673 return PCI_ERS_RESULT_NEED_RESET;
2676 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2678 struct nvme_dev *dev = pci_get_drvdata(pdev);
2680 dev_info(dev->ctrl.device, "restart after slot reset\n");
2681 pci_restore_state(pdev);
2682 nvme_reset_ctrl(&dev->ctrl);
2683 return PCI_ERS_RESULT_RECOVERED;
2686 static void nvme_error_resume(struct pci_dev *pdev)
2688 pci_cleanup_aer_uncorrect_error_status(pdev);
2691 static const struct pci_error_handlers nvme_err_handler = {
2692 .error_detected = nvme_error_detected,
2693 .slot_reset = nvme_slot_reset,
2694 .resume = nvme_error_resume,
2695 .reset_prepare = nvme_reset_prepare,
2696 .reset_done = nvme_reset_done,
2699 static const struct pci_device_id nvme_id_table[] = {
2700 { PCI_VDEVICE(INTEL, 0x0953),
2701 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2702 NVME_QUIRK_DEALLOCATE_ZEROES, },
2703 { PCI_VDEVICE(INTEL, 0x0a53),
2704 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2705 NVME_QUIRK_DEALLOCATE_ZEROES, },
2706 { PCI_VDEVICE(INTEL, 0x0a54),
2707 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2708 NVME_QUIRK_DEALLOCATE_ZEROES, },
2709 { PCI_VDEVICE(INTEL, 0x0a55),
2710 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2711 NVME_QUIRK_DEALLOCATE_ZEROES, },
2712 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2713 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2714 NVME_QUIRK_MEDIUM_PRIO_SQ },
2715 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2716 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2717 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2718 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2719 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2720 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2721 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2722 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2723 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2724 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2725 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2726 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2727 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2728 .driver_data = NVME_QUIRK_LIGHTNVM, },
2729 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2730 .driver_data = NVME_QUIRK_LIGHTNVM, },
2731 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2732 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2733 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2736 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2738 static struct pci_driver nvme_driver = {
2740 .id_table = nvme_id_table,
2741 .probe = nvme_probe,
2742 .remove = nvme_remove,
2743 .shutdown = nvme_shutdown,
2745 .pm = &nvme_dev_pm_ops,
2747 .sriov_configure = nvme_pci_sriov_configure,
2748 .err_handler = &nvme_err_handler,
2751 static int __init nvme_init(void)
2753 return pci_register_driver(&nvme_driver);
2756 static void __exit nvme_exit(void)
2758 pci_unregister_driver(&nvme_driver);
2759 flush_workqueue(nvme_wq);
2763 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2764 MODULE_LICENSE("GPL");
2765 MODULE_VERSION("1.0");
2766 module_init(nvme_init);
2767 module_exit(nvme_exit);