drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/blkdev.h>
  17 #include <linux/blk-mq.h>
  18 #include <linux/blk-mq-pci.h>
  19 #include <linux/dmi.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/mm.h>
  24 #include <linux/module.h>
  25 #include <linux/mutex.h>
  26 #include <linux/once.h>
  27 #include <linux/pci.h>
  28 #include <linux/t10-pi.h>
  29 #include <linux/types.h>
  30 #include <linux/io-64-nonatomic-lo-hi.h>
  31 #include <linux/sed-opal.h>
  32
  33 #include "nvme.h"
  34
  35 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  36 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  37
  38 #define SGES_PER_PAGE   (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  39
  40 static int use_threaded_interrupts;
  41 module_param(use_threaded_interrupts, int, 0);
  42
  43 static bool use_cmb_sqes = true;
  44 module_param(use_cmb_sqes, bool, 0644);
  45 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  46
  47 static unsigned int max_host_mem_size_mb = 128;
  48 module_param(max_host_mem_size_mb, uint, 0444);
  49 MODULE_PARM_DESC(max_host_mem_size_mb,
  50         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  51
  52 static unsigned int sgl_threshold = SZ_32K;
  53 module_param(sgl_threshold, uint, 0644);
  54 MODULE_PARM_DESC(sgl_threshold,
  55                 "Use SGLs when average request segment size is larger or equal to "
  56                 "this size. Use 0 to disable SGLs.");
  57
  58 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  59 static const struct kernel_param_ops io_queue_depth_ops = {
  60         .set = io_queue_depth_set,
  61         .get = param_get_int,
  62 };
  63
  64 static int io_queue_depth = 1024;
  65 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  66 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
  67
  68 struct nvme_dev;
  69 struct nvme_queue;
  70
  71 static void nvme_process_cq(struct nvme_queue *nvmeq);
  72 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  73
  74 /*
  75  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  76  */
  77 struct nvme_dev {
  78         struct nvme_queue *queues;
  79         struct blk_mq_tag_set tagset;
  80         struct blk_mq_tag_set admin_tagset;
  81         u32 __iomem *dbs;
  82         struct device *dev;
  83         struct dma_pool *prp_page_pool;
  84         struct dma_pool *prp_small_pool;
  85         unsigned online_queues;
  86         unsigned max_qid;
  87         unsigned int num_vecs;
  88         int q_depth;
  89         u32 db_stride;
  90         void __iomem *bar;
  91         unsigned long bar_mapped_size;
  92         struct work_struct remove_work;
  93         struct mutex shutdown_lock;
  94         bool subsystem;
  95         void __iomem *cmb;
  96         pci_bus_addr_t cmb_bus_addr;
  97         u64 cmb_size;
  98         u32 cmbsz;
  99         u32 cmbloc;
 100         struct nvme_ctrl ctrl;
 101         struct completion ioq_wait;
 102
 103         /* shadow doorbell buffer support: */
 104         u32 *dbbuf_dbs;
 105         dma_addr_t dbbuf_dbs_dma_addr;
 106         u32 *dbbuf_eis;
 107         dma_addr_t dbbuf_eis_dma_addr;
 108
 109         /* host memory buffer support: */
 110         u64 host_mem_size;
 111         u32 nr_host_mem_descs;
 112         dma_addr_t host_mem_descs_dma;
 113         struct nvme_host_mem_buf_desc *host_mem_descs;
 114         void **host_mem_desc_bufs;
 115 };
 116
 117 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 118 {
 119         int n = 0, ret;
 120
 121         ret = kstrtoint(val, 10, &n);
 122         if (ret != 0 || n < 2)
 123                 return -EINVAL;
 124
 125         return param_set_int(val, kp);
 126 }
 127
 128 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 129 {
 130         return qid * 2 * stride;
 131 }
 132
 133 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 134 {
 135         return (qid * 2 + 1) * stride;
 136 }
 137
 138 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 139 {
 140         return container_of(ctrl, struct nvme_dev, ctrl);
 141 }
 142
 143 /*
 144  * An NVM Express queue.  Each device has at least two (one for admin
 145  * commands and one for I/O commands).
 146  */
 147 struct nvme_queue {
 148         struct device *q_dmadev;
 149         struct nvme_dev *dev;
 150         spinlock_t q_lock;
 151         struct nvme_command *sq_cmds;
 152         struct nvme_command __iomem *sq_cmds_io;
 153         volatile struct nvme_completion *cqes;
 154         struct blk_mq_tags **tags;
 155         dma_addr_t sq_dma_addr;
 156         dma_addr_t cq_dma_addr;
 157         u32 __iomem *q_db;
 158         u16 q_depth;
 159         s16 cq_vector;
 160         u16 sq_tail;
 161         u16 cq_head;
 162         u16 qid;
 163         u8 cq_phase;
 164         u8 cqe_seen;
 165         u32 *dbbuf_sq_db;
 166         u32 *dbbuf_cq_db;
 167         u32 *dbbuf_sq_ei;
 168         u32 *dbbuf_cq_ei;
 169 };
 170
 171 /*
 172  * The nvme_iod describes the data in an I/O, including the list of PRP
 173  * entries.  You can't see it in this data structure because C doesn't let
 174  * me express that.  Use nvme_init_iod to ensure there's enough space
 175  * allocated to store the PRP list.
 176  */
 177 struct nvme_iod {
 178         struct nvme_request req;
 179         struct nvme_queue *nvmeq;
 180         bool use_sgl;
 181         int aborted;
 182         int npages;             /* In the PRP list. 0 means small pool in use */
 183         int nents;              /* Used in scatterlist */
 184         int length;             /* Of data, in bytes */
 185         dma_addr_t first_dma;
 186         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 187         struct scatterlist *sg;
 188         struct scatterlist inline_sg[0];
 189 };
 190
 191 /*
 192  * Check we didin't inadvertently grow the command struct
 193  */
 194 static inline void _nvme_check_size(void)
 195 {
 196         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 197         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 198         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 199         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 200         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 201         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 202         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 203         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 204         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
 205         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
 206         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 207         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 208         BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
 209 }
 210
 211 static inline unsigned int nvme_dbbuf_size(u32 stride)
 212 {
 213         return ((num_possible_cpus() + 1) * 8 * stride);
 214 }
 215
 216 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 217 {
 218         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
 219
 220         if (dev->dbbuf_dbs)
 221                 return 0;
 222
 223         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 224                                             &dev->dbbuf_dbs_dma_addr,
 225                                             GFP_KERNEL);
 226         if (!dev->dbbuf_dbs)
 227                 return -ENOMEM;
 228         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 229                                             &dev->dbbuf_eis_dma_addr,
 230                                             GFP_KERNEL);
 231         if (!dev->dbbuf_eis) {
 232                 dma_free_coherent(dev->dev, mem_size,
 233                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 234                 dev->dbbuf_dbs = NULL;
 235                 return -ENOMEM;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 242 {
 243         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
 244
 245         if (dev->dbbuf_dbs) {
 246                 dma_free_coherent(dev->dev, mem_size,
 247                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 248                 dev->dbbuf_dbs = NULL;
 249         }
 250         if (dev->dbbuf_eis) {
 251                 dma_free_coherent(dev->dev, mem_size,
 252                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 253                 dev->dbbuf_eis = NULL;
 254         }
 255 }
 256
 257 static void nvme_dbbuf_init(struct nvme_dev *dev,
 258                             struct nvme_queue *nvmeq, int qid)
 259 {
 260         if (!dev->dbbuf_dbs || !qid)
 261                 return;
 262
 263         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 264         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 265         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 266         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 267 }
 268
 269 static void nvme_dbbuf_set(struct nvme_dev *dev)
 270 {
 271         struct nvme_command c;
 272
 273         if (!dev->dbbuf_dbs)
 274                 return;
 275
 276         memset(&c, 0, sizeof(c));
 277         c.dbbuf.opcode = nvme_admin_dbbuf;
 278         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 279         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 280
 281         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 282                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 283                 /* Free memory and continue on */
 284                 nvme_dbbuf_dma_free(dev);
 285         }
 286 }
 287
 288 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 289 {
 290         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 291 }
 292
 293 /* Update dbbuf and return true if an MMIO is required */
 294 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 295                                               volatile u32 *dbbuf_ei)
 296 {
 297         if (dbbuf_db) {
 298                 u16 old_value;
 299
 300                 /*
 301                  * Ensure that the queue is written before updating
 302                  * the doorbell in memory
 303                  */
 304                 wmb();
 305
 306                 old_value = *dbbuf_db;
 307                 *dbbuf_db = value;
 308
 309                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 310                         return false;
 311         }
 312
 313         return true;
 314 }
 315
 316 /*
 317  * Max size of iod being embedded in the request payload
 318  */
 319 #define NVME_INT_PAGES          2
 320 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 321
 322 /*
 323  * Will slightly overestimate the number of pages needed.  This is OK
 324  * as it only leads to a small amount of wasted memory for the lifetime of
 325  * the I/O.
 326  */
 327 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 328 {
 329         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 330                                       dev->ctrl.page_size);
 331         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 332 }
 333
 334 /*
 335  * Calculates the number of pages needed for the SGL segments. For example a 4k
 336  * page can accommodate 256 SGL descriptors.
 337  */
 338 static int nvme_pci_npages_sgl(unsigned int num_seg)
 339 {
 340         return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
 341 }
 342
 343 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
 344                 unsigned int size, unsigned int nseg, bool use_sgl)
 345 {
 346         size_t alloc_size;
 347
 348         if (use_sgl)
 349                 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
 350         else
 351                 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
 352
 353         return alloc_size + sizeof(struct scatterlist) * nseg;
 354 }
 355
 356 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
 357 {
 358         unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
 359                                     NVME_INT_BYTES(dev), NVME_INT_PAGES,
 360                                     use_sgl);
 361
 362         return sizeof(struct nvme_iod) + alloc_size;
 363 }
 364
 365 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 366                                 unsigned int hctx_idx)
 367 {
 368         struct nvme_dev *dev = data;
 369         struct nvme_queue *nvmeq = &dev->queues[0];
 370
 371         WARN_ON(hctx_idx != 0);
 372         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 373         WARN_ON(nvmeq->tags);
 374
 375         hctx->driver_data = nvmeq;
 376         nvmeq->tags = &dev->admin_tagset.tags[0];
 377         return 0;
 378 }
 379
 380 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 381 {
 382         struct nvme_queue *nvmeq = hctx->driver_data;
 383
 384         nvmeq->tags = NULL;
 385 }
 386
 387 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 388                           unsigned int hctx_idx)
 389 {
 390         struct nvme_dev *dev = data;
 391         struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
 392
 393         if (!nvmeq->tags)
 394                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 395
 396         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 397         hctx->driver_data = nvmeq;
 398         return 0;
 399 }
 400
 401 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
 402                 unsigned int hctx_idx, unsigned int numa_node)
 403 {
 404         struct nvme_dev *dev = set->driver_data;
 405         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 406         int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
 407         struct nvme_queue *nvmeq = &dev->queues[queue_idx];
 408
 409         BUG_ON(!nvmeq);
 410         iod->nvmeq = nvmeq;
 411         return 0;
 412 }
 413
 414 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 415 {
 416         struct nvme_dev *dev = set->driver_data;
 417
 418         return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev),
 419                         dev->num_vecs > 1 ? 1 /* admin queue */ : 0);
 420 }
 421
 422 /**
 423  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 424  * @nvmeq: The queue to use
 425  * @cmd: The command to send
 426  *
 427  * Safe to use from interrupt context
 428  */
 429 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 430                                                 struct nvme_command *cmd)
 431 {
 432         u16 tail = nvmeq->sq_tail;
 433
 434         if (nvmeq->sq_cmds_io)
 435                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 436         else
 437                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 438
 439         if (++tail == nvmeq->q_depth)
 440                 tail = 0;
 441         if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
 442                                               nvmeq->dbbuf_sq_ei))
 443                 writel(tail, nvmeq->q_db);
 444         nvmeq->sq_tail = tail;
 445 }
 446
 447 static void **nvme_pci_iod_list(struct request *req)
 448 {
 449         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 450         return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
 451 }
 452
 453 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
 454 {
 455         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 456         int nseg = blk_rq_nr_phys_segments(req);
 457         unsigned int avg_seg_size;
 458
 459         if (nseg == 0)
 460                 return false;
 461
 462         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
 463
 464         if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
 465                 return false;
 466         if (!iod->nvmeq->qid)
 467                 return false;
 468         if (!sgl_threshold || avg_seg_size < sgl_threshold)
 469                 return false;
 470         return true;
 471 }
 472
 473 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
 474 {
 475         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 476         int nseg = blk_rq_nr_phys_segments(rq);
 477         unsigned int size = blk_rq_payload_bytes(rq);
 478
 479         iod->use_sgl = nvme_pci_use_sgls(dev, rq);
 480
 481         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 482                 size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg,
 483                                 iod->use_sgl);
 484
 485                 iod->sg = kmalloc(alloc_size, GFP_ATOMIC);
 486                 if (!iod->sg)
 487                         return BLK_STS_RESOURCE;
 488         } else {
 489                 iod->sg = iod->inline_sg;
 490         }
 491
 492         iod->aborted = 0;
 493         iod->npages = -1;
 494         iod->nents = 0;
 495         iod->length = size;
 496
 497         return BLK_STS_OK;
 498 }
 499
 500 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 501 {
 502         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 503         const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
 504         dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
 505
 506         int i;
 507
 508         if (iod->npages == 0)
 509                 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
 510                         dma_addr);
 511
 512         for (i = 0; i < iod->npages; i++) {
 513                 void *addr = nvme_pci_iod_list(req)[i];
 514
 515                 if (iod->use_sgl) {
 516                         struct nvme_sgl_desc *sg_list = addr;
 517
 518                         next_dma_addr =
 519                             le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
 520                 } else {
 521                         __le64 *prp_list = addr;
 522
 523                         next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 524                 }
 525
 526                 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
 527                 dma_addr = next_dma_addr;
 528         }
 529
 530         if (iod->sg != iod->inline_sg)
 531                 kfree(iod->sg);
 532 }
 533
 534 #ifdef CONFIG_BLK_DEV_INTEGRITY
 535 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 536 {
 537         if (be32_to_cpu(pi->ref_tag) == v)
 538                 pi->ref_tag = cpu_to_be32(p);
 539 }
 540
 541 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 542 {
 543         if (be32_to_cpu(pi->ref_tag) == p)
 544                 pi->ref_tag = cpu_to_be32(v);
 545 }
 546
 547 /**
 548  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 549  *
 550  * The virtual start sector is the one that was originally submitted by the
 551  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 552  * start sector may be different. Remap protection information to match the
 553  * physical LBA on writes, and back to the original seed on reads.
 554  *
 555  * Type 0 and 3 do not have a ref tag, so no remapping required.
 556  */
 557 static void nvme_dif_remap(struct request *req,
 558                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 559 {
 560         struct nvme_ns *ns = req->rq_disk->private_data;
 561         struct bio_integrity_payload *bip;
 562         struct t10_pi_tuple *pi;
 563         void *p, *pmap;
 564         u32 i, nlb, ts, phys, virt;
 565
 566         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 567                 return;
 568
 569         bip = bio_integrity(req->bio);
 570         if (!bip)
 571                 return;
 572
 573         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 574
 575         p = pmap;
 576         virt = bip_get_seed(bip);
 577         phys = nvme_block_nr(ns, blk_rq_pos(req));
 578         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 579         ts = ns->disk->queue->integrity.tuple_size;
 580
 581         for (i = 0; i < nlb; i++, virt++, phys++) {
 582                 pi = (struct t10_pi_tuple *)p;
 583                 dif_swap(phys, virt, pi);
 584                 p += ts;
 585         }
 586         kunmap_atomic(pmap);
 587 }
 588 #else /* CONFIG_BLK_DEV_INTEGRITY */
 589 static void nvme_dif_remap(struct request *req,
 590                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 591 {
 592 }
 593 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 594 {
 595 }
 596 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 597 {
 598 }
 599 #endif
 600
 601 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 602 {
 603         int i;
 604         struct scatterlist *sg;
 605
 606         for_each_sg(sgl, sg, nents, i) {
 607                 dma_addr_t phys = sg_phys(sg);
 608                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 609                         "dma_address:%pad dma_length:%d\n",
 610                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 611                         sg_dma_len(sg));
 612         }
 613 }
 614
 615 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 616                 struct request *req, struct nvme_rw_command *cmnd)
 617 {
 618         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 619         struct dma_pool *pool;
 620         int length = blk_rq_payload_bytes(req);
 621         struct scatterlist *sg = iod->sg;
 622         int dma_len = sg_dma_len(sg);
 623         u64 dma_addr = sg_dma_address(sg);
 624         u32 page_size = dev->ctrl.page_size;
 625         int offset = dma_addr & (page_size - 1);
 626         __le64 *prp_list;
 627         void **list = nvme_pci_iod_list(req);
 628         dma_addr_t prp_dma;
 629         int nprps, i;
 630
 631         length -= (page_size - offset);
 632         if (length <= 0) {
 633                 iod->first_dma = 0;
 634                 goto done;
 635         }
 636
 637         dma_len -= (page_size - offset);
 638         if (dma_len) {
 639                 dma_addr += (page_size - offset);
 640         } else {
 641                 sg = sg_next(sg);
 642                 dma_addr = sg_dma_address(sg);
 643                 dma_len = sg_dma_len(sg);
 644         }
 645
 646         if (length <= page_size) {
 647                 iod->first_dma = dma_addr;
 648                 goto done;
 649         }
 650
 651         nprps = DIV_ROUND_UP(length, page_size);
 652         if (nprps <= (256 / 8)) {
 653                 pool = dev->prp_small_pool;
 654                 iod->npages = 0;
 655         } else {
 656                 pool = dev->prp_page_pool;
 657                 iod->npages = 1;
 658         }
 659
 660         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 661         if (!prp_list) {
 662                 iod->first_dma = dma_addr;
 663                 iod->npages = -1;
 664                 return BLK_STS_RESOURCE;
 665         }
 666         list[0] = prp_list;
 667         iod->first_dma = prp_dma;
 668         i = 0;
 669         for (;;) {
 670                 if (i == page_size >> 3) {
 671                         __le64 *old_prp_list = prp_list;
 672                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 673                         if (!prp_list)
 674                                 return BLK_STS_RESOURCE;
 675                         list[iod->npages++] = prp_list;
 676                         prp_list[0] = old_prp_list[i - 1];
 677                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 678                         i = 1;
 679                 }
 680                 prp_list[i++] = cpu_to_le64(dma_addr);
 681                 dma_len -= page_size;
 682                 dma_addr += page_size;
 683                 length -= page_size;
 684                 if (length <= 0)
 685                         break;
 686                 if (dma_len > 0)
 687                         continue;
 688                 if (unlikely(dma_len < 0))
 689                         goto bad_sgl;
 690                 sg = sg_next(sg);
 691                 dma_addr = sg_dma_address(sg);
 692                 dma_len = sg_dma_len(sg);
 693         }
 694
 695 done:
 696         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 697         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 698
 699         return BLK_STS_OK;
 700
 701  bad_sgl:
 702         WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
 703                         "Invalid SGL for payload:%d nents:%d\n",
 704                         blk_rq_payload_bytes(req), iod->nents);
 705         return BLK_STS_IOERR;
 706 }
 707
 708 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 709                 struct scatterlist *sg)
 710 {
 711         sge->addr = cpu_to_le64(sg_dma_address(sg));
 712         sge->length = cpu_to_le32(sg_dma_len(sg));
 713         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 714 }
 715
 716 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 717                 dma_addr_t dma_addr, int entries)
 718 {
 719         sge->addr = cpu_to_le64(dma_addr);
 720         if (entries < SGES_PER_PAGE) {
 721                 sge->length = cpu_to_le32(entries * sizeof(*sge));
 722                 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 723         } else {
 724                 sge->length = cpu_to_le32(PAGE_SIZE);
 725                 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
 726         }
 727 }
 728
 729 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 730                 struct request *req, struct nvme_rw_command *cmd, int entries)
 731 {
 732         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 733         struct dma_pool *pool;
 734         struct nvme_sgl_desc *sg_list;
 735         struct scatterlist *sg = iod->sg;
 736         dma_addr_t sgl_dma;
 737         int i = 0;
 738
 739         /* setting the transfer type as SGL */
 740         cmd->flags = NVME_CMD_SGL_METABUF;
 741
 742         if (entries == 1) {
 743                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 744                 return BLK_STS_OK;
 745         }
 746
 747         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 748                 pool = dev->prp_small_pool;
 749                 iod->npages = 0;
 750         } else {
 751                 pool = dev->prp_page_pool;
 752                 iod->npages = 1;
 753         }
 754
 755         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 756         if (!sg_list) {
 757                 iod->npages = -1;
 758                 return BLK_STS_RESOURCE;
 759         }
 760
 761         nvme_pci_iod_list(req)[0] = sg_list;
 762         iod->first_dma = sgl_dma;
 763
 764         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 765
 766         do {
 767                 if (i == SGES_PER_PAGE) {
 768                         struct nvme_sgl_desc *old_sg_desc = sg_list;
 769                         struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
 770
 771                         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 772                         if (!sg_list)
 773                                 return BLK_STS_RESOURCE;
 774
 775                         i = 0;
 776                         nvme_pci_iod_list(req)[iod->npages++] = sg_list;
 777                         sg_list[i++] = *link;
 778                         nvme_pci_sgl_set_seg(link, sgl_dma, entries);
 779                 }
 780
 781                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
 782                 sg = sg_next(sg);
 783         } while (--entries > 0);
 784
 785         return BLK_STS_OK;
 786 }
 787
 788 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 789                 struct nvme_command *cmnd)
 790 {
 791         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 792         struct request_queue *q = req->q;
 793         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 794                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 795         blk_status_t ret = BLK_STS_IOERR;
 796         int nr_mapped;
 797
 798         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 799         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 800         if (!iod->nents)
 801                 goto out;
 802
 803         ret = BLK_STS_RESOURCE;
 804         nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
 805                         DMA_ATTR_NO_WARN);
 806         if (!nr_mapped)
 807                 goto out;
 808
 809         if (iod->use_sgl)
 810                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
 811         else
 812                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 813
 814         if (ret != BLK_STS_OK)
 815                 goto out_unmap;
 816
 817         ret = BLK_STS_IOERR;
 818         if (blk_integrity_rq(req)) {
 819                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 820                         goto out_unmap;
 821
 822                 sg_init_table(&iod->meta_sg, 1);
 823                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 824                         goto out_unmap;
 825
 826                 if (req_op(req) == REQ_OP_WRITE)
 827                         nvme_dif_remap(req, nvme_dif_prep);
 828
 829                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 830                         goto out_unmap;
 831         }
 832
 833         if (blk_integrity_rq(req))
 834                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 835         return BLK_STS_OK;
 836
 837 out_unmap:
 838         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 839 out:
 840         return ret;
 841 }
 842
 843 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 844 {
 845         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 846         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 847                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 848
 849         if (iod->nents) {
 850                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 851                 if (blk_integrity_rq(req)) {
 852                         if (req_op(req) == REQ_OP_READ)
 853                                 nvme_dif_remap(req, nvme_dif_complete);
 854                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 855                 }
 856         }
 857
 858         nvme_cleanup_cmd(req);
 859         nvme_free_iod(dev, req);
 860 }
 861
 862 /*
 863  * NOTE: ns is NULL when called on the admin queue.
 864  */
 865 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 866                          const struct blk_mq_queue_data *bd)
 867 {
 868         struct nvme_ns *ns = hctx->queue->queuedata;
 869         struct nvme_queue *nvmeq = hctx->driver_data;
 870         struct nvme_dev *dev = nvmeq->dev;
 871         struct request *req = bd->rq;
 872         struct nvme_command cmnd;
 873         blk_status_t ret;
 874
 875         ret = nvme_setup_cmd(ns, req, &cmnd);
 876         if (ret)
 877                 return ret;
 878
 879         ret = nvme_init_iod(req, dev);
 880         if (ret)
 881                 goto out_free_cmd;
 882
 883         if (blk_rq_nr_phys_segments(req)) {
 884                 ret = nvme_map_data(dev, req, &cmnd);
 885                 if (ret)
 886                         goto out_cleanup_iod;
 887         }
 888
 889         blk_mq_start_request(req);
 890
 891         spin_lock_irq(&nvmeq->q_lock);
 892         if (unlikely(nvmeq->cq_vector < 0)) {
 893                 ret = BLK_STS_IOERR;
 894                 spin_unlock_irq(&nvmeq->q_lock);
 895                 goto out_cleanup_iod;
 896         }
 897         __nvme_submit_cmd(nvmeq, &cmnd);
 898         nvme_process_cq(nvmeq);
 899         spin_unlock_irq(&nvmeq->q_lock);
 900         return BLK_STS_OK;
 901 out_cleanup_iod:
 902         nvme_free_iod(dev, req);
 903 out_free_cmd:
 904         nvme_cleanup_cmd(req);
 905         return ret;
 906 }
 907
 908 static void nvme_pci_complete_rq(struct request *req)
 909 {
 910         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 911
 912         nvme_unmap_data(iod->nvmeq->dev, req);
 913         nvme_complete_rq(req);
 914 }
 915
 916 /* We read the CQE phase first to check if the rest of the entry is valid */
 917 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 918                 u16 phase)
 919 {
 920         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 921 }
 922
 923 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
 924 {
 925         u16 head = nvmeq->cq_head;
 926
 927         if (likely(nvmeq->cq_vector >= 0)) {
 928                 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
 929                                                       nvmeq->dbbuf_cq_ei))
 930                         writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 931         }
 932 }
 933
 934 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
 935                 struct nvme_completion *cqe)
 936 {
 937         struct request *req;
 938
 939         if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
 940                 dev_warn(nvmeq->dev->ctrl.device,
 941                         "invalid id %d completed on queue %d\n",
 942                         cqe->command_id, le16_to_cpu(cqe->sq_id));
 943                 return;
 944         }
 945
 946         /*
 947          * AEN requests are special as they don't time out and can
 948          * survive any kind of queue freeze and often don't respond to
 949          * aborts.  We don't even bother to allocate a struct request
 950          * for them but rather special case them here.
 951          */
 952         if (unlikely(nvmeq->qid == 0 &&
 953                         cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
 954                 nvme_complete_async_event(&nvmeq->dev->ctrl,
 955                                 cqe->status, &cqe->result);
 956                 return;
 957         }
 958
 959         nvmeq->cqe_seen = 1;
 960         req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
 961         nvme_end_request(req, cqe->status, cqe->result);
 962 }
 963
 964 static inline bool nvme_read_cqe(struct nvme_queue *nvmeq,
 965                 struct nvme_completion *cqe)
 966 {
 967         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 968                 *cqe = nvmeq->cqes[nvmeq->cq_head];
 969
 970                 if (++nvmeq->cq_head == nvmeq->q_depth) {
 971                         nvmeq->cq_head = 0;
 972                         nvmeq->cq_phase = !nvmeq->cq_phase;
 973                 }
 974                 return true;
 975         }
 976         return false;
 977 }
 978
 979 static void nvme_process_cq(struct nvme_queue *nvmeq)
 980 {
 981         struct nvme_completion cqe;
 982         int consumed = 0;
 983
 984         while (nvme_read_cqe(nvmeq, &cqe)) {
 985                 nvme_handle_cqe(nvmeq, &cqe);
 986                 consumed++;
 987         }
 988
 989         if (consumed)
 990                 nvme_ring_cq_doorbell(nvmeq);
 991 }
 992
 993 static irqreturn_t nvme_irq(int irq, void *data)
 994 {
 995         irqreturn_t result;
 996         struct nvme_queue *nvmeq = data;
 997         spin_lock(&nvmeq->q_lock);
 998         nvme_process_cq(nvmeq);
 999         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
1000         nvmeq->cqe_seen = 0;
1001         spin_unlock(&nvmeq->q_lock);
1002         return result;
1003 }
1004
1005 static irqreturn_t nvme_irq_check(int irq, void *data)
1006 {
1007         struct nvme_queue *nvmeq = data;
1008         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
1009                 return IRQ_WAKE_THREAD;
1010         return IRQ_NONE;
1011 }
1012
1013 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
1014 {
1015         struct nvme_completion cqe;
1016         int found = 0, consumed = 0;
1017
1018         if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
1019                 return 0;
1020
1021         spin_lock_irq(&nvmeq->q_lock);
1022         while (nvme_read_cqe(nvmeq, &cqe)) {
1023                 nvme_handle_cqe(nvmeq, &cqe);
1024                 consumed++;
1025
1026                 if (tag == cqe.command_id) {
1027                         found = 1;
1028                         break;
1029                 }
1030        }
1031
1032         if (consumed)
1033                 nvme_ring_cq_doorbell(nvmeq);
1034         spin_unlock_irq(&nvmeq->q_lock);
1035
1036         return found;
1037 }
1038
1039 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1040 {
1041         struct nvme_queue *nvmeq = hctx->driver_data;
1042
1043         return __nvme_poll(nvmeq, tag);
1044 }
1045
1046 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1047 {
1048         struct nvme_dev *dev = to_nvme_dev(ctrl);
1049         struct nvme_queue *nvmeq = &dev->queues[0];
1050         struct nvme_command c;
1051
1052         memset(&c, 0, sizeof(c));
1053         c.common.opcode = nvme_admin_async_event;
1054         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1055
1056         spin_lock_irq(&nvmeq->q_lock);
1057         __nvme_submit_cmd(nvmeq, &c);
1058         spin_unlock_irq(&nvmeq->q_lock);
1059 }
1060
1061 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1062 {
1063         struct nvme_command c;
1064
1065         memset(&c, 0, sizeof(c));
1066         c.delete_queue.opcode = opcode;
1067         c.delete_queue.qid = cpu_to_le16(id);
1068
1069         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1070 }
1071
1072 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1073                                                 struct nvme_queue *nvmeq)
1074 {
1075         struct nvme_command c;
1076         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1077
1078         /*
1079          * Note: we (ab)use the fact that the prp fields survive if no data
1080          * is attached to the request.
1081          */
1082         memset(&c, 0, sizeof(c));
1083         c.create_cq.opcode = nvme_admin_create_cq;
1084         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1085         c.create_cq.cqid = cpu_to_le16(qid);
1086         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1087         c.create_cq.cq_flags = cpu_to_le16(flags);
1088         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1089
1090         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1091 }
1092
1093 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1094                                                 struct nvme_queue *nvmeq)
1095 {
1096         struct nvme_command c;
1097         int flags = NVME_QUEUE_PHYS_CONTIG;
1098
1099         /*
1100          * Note: we (ab)use the fact that the prp fields survive if no data
1101          * is attached to the request.
1102          */
1103         memset(&c, 0, sizeof(c));
1104         c.create_sq.opcode = nvme_admin_create_sq;
1105         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1106         c.create_sq.sqid = cpu_to_le16(qid);
1107         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1108         c.create_sq.sq_flags = cpu_to_le16(flags);
1109         c.create_sq.cqid = cpu_to_le16(qid);
1110
1111         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1112 }
1113
1114 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1115 {
1116         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1117 }
1118
1119 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1120 {
1121         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1122 }
1123
1124 static void abort_endio(struct request *req, blk_status_t error)
1125 {
1126         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1127         struct nvme_queue *nvmeq = iod->nvmeq;
1128
1129         dev_warn(nvmeq->dev->ctrl.device,
1130                  "Abort status: 0x%x", nvme_req(req)->status);
1131         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1132         blk_mq_free_request(req);
1133 }
1134
1135 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1136 {
1137
1138         /* If true, indicates loss of adapter communication, possibly by a
1139          * NVMe Subsystem reset.
1140          */
1141         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1142
1143         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1144         switch (dev->ctrl.state) {
1145         case NVME_CTRL_RESETTING:
1146         case NVME_CTRL_CONNECTING:
1147                 return false;
1148         default:
1149                 break;
1150         }
1151
1152         /* We shouldn't reset unless the controller is on fatal error state
1153          * _or_ if we lost the communication with it.
1154          */
1155         if (!(csts & NVME_CSTS_CFS) && !nssro)
1156                 return false;
1157
1158         return true;
1159 }
1160
1161 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1162 {
1163         /* Read a config register to help see what died. */
1164         u16 pci_status;
1165         int result;
1166
1167         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1168                                       &pci_status);
1169         if (result == PCIBIOS_SUCCESSFUL)
1170                 dev_warn(dev->ctrl.device,
1171                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1172                          csts, pci_status);
1173         else
1174                 dev_warn(dev->ctrl.device,
1175                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1176                          csts, result);
1177 }
1178
1179 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1180 {
1181         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1182         struct nvme_queue *nvmeq = iod->nvmeq;
1183         struct nvme_dev *dev = nvmeq->dev;
1184         struct request *abort_req;
1185         struct nvme_command cmd;
1186         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1187
1188         /* If PCI error recovery process is happening, we cannot reset or
1189          * the recovery mechanism will surely fail.
1190          */
1191         mb();
1192         if (pci_channel_offline(to_pci_dev(dev->dev)))
1193                 return BLK_EH_RESET_TIMER;
1194
1195         /*
1196          * Reset immediately if the controller is failed
1197          */
1198         if (nvme_should_reset(dev, csts)) {
1199                 nvme_warn_reset(dev, csts);
1200                 nvme_dev_disable(dev, false);
1201                 nvme_reset_ctrl(&dev->ctrl);
1202                 return BLK_EH_HANDLED;
1203         }
1204
1205         /*
1206          * Did we miss an interrupt?
1207          */
1208         if (__nvme_poll(nvmeq, req->tag)) {
1209                 dev_warn(dev->ctrl.device,
1210                          "I/O %d QID %d timeout, completion polled\n",
1211                          req->tag, nvmeq->qid);
1212                 return BLK_EH_HANDLED;
1213         }
1214
1215         /*
1216          * Shutdown immediately if controller times out while starting. The
1217          * reset work will see the pci device disabled when it gets the forced
1218          * cancellation error. All outstanding requests are completed on
1219          * shutdown, so we return BLK_EH_HANDLED.
1220          */
1221         switch (dev->ctrl.state) {
1222         case NVME_CTRL_CONNECTING:
1223         case NVME_CTRL_RESETTING:
1224                 dev_warn(dev->ctrl.device,
1225                          "I/O %d QID %d timeout, disable controller\n",
1226                          req->tag, nvmeq->qid);
1227                 nvme_dev_disable(dev, false);
1228                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1229                 return BLK_EH_HANDLED;
1230         default:
1231                 break;
1232         }
1233
1234         /*
1235          * Shutdown the controller immediately and schedule a reset if the
1236          * command was already aborted once before and still hasn't been
1237          * returned to the driver, or if this is the admin queue.
1238          */
1239         if (!nvmeq->qid || iod->aborted) {
1240                 dev_warn(dev->ctrl.device,
1241                          "I/O %d QID %d timeout, reset controller\n",
1242                          req->tag, nvmeq->qid);
1243                 nvme_dev_disable(dev, false);
1244                 nvme_reset_ctrl(&dev->ctrl);
1245
1246                 /*
1247                  * Mark the request as handled, since the inline shutdown
1248                  * forces all outstanding requests to complete.
1249                  */
1250                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1251                 return BLK_EH_HANDLED;
1252         }
1253
1254         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1255                 atomic_inc(&dev->ctrl.abort_limit);
1256                 return BLK_EH_RESET_TIMER;
1257         }
1258         iod->aborted = 1;
1259
1260         memset(&cmd, 0, sizeof(cmd));
1261         cmd.abort.opcode = nvme_admin_abort_cmd;
1262         cmd.abort.cid = req->tag;
1263         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1264
1265         dev_warn(nvmeq->dev->ctrl.device,
1266                 "I/O %d QID %d timeout, aborting\n",
1267                  req->tag, nvmeq->qid);
1268
1269         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1270                         BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1271         if (IS_ERR(abort_req)) {
1272                 atomic_inc(&dev->ctrl.abort_limit);
1273                 return BLK_EH_RESET_TIMER;
1274         }
1275
1276         abort_req->timeout = ADMIN_TIMEOUT;
1277         abort_req->end_io_data = NULL;
1278         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1279
1280         /*
1281          * The aborted req will be completed on receiving the abort req.
1282          * We enable the timer again. If hit twice, it'll cause a device reset,
1283          * as the device then is in a faulty state.
1284          */
1285         return BLK_EH_RESET_TIMER;
1286 }
1287
1288 static void nvme_free_queue(struct nvme_queue *nvmeq)
1289 {
1290         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1291                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1292         if (nvmeq->sq_cmds)
1293                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1294                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1295 }
1296
1297 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1298 {
1299         int i;
1300
1301         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1302                 dev->ctrl.queue_count--;
1303                 nvme_free_queue(&dev->queues[i]);
1304         }
1305 }
1306
1307 /**
1308  * nvme_suspend_queue - put queue into suspended state
1309  * @nvmeq - queue to suspend
1310  */
1311 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1312 {
1313         int vector;
1314
1315         spin_lock_irq(&nvmeq->q_lock);
1316         if (nvmeq->cq_vector == -1) {
1317                 spin_unlock_irq(&nvmeq->q_lock);
1318                 return 1;
1319         }
1320         vector = nvmeq->cq_vector;
1321         nvmeq->dev->online_queues--;
1322         nvmeq->cq_vector = -1;
1323         spin_unlock_irq(&nvmeq->q_lock);
1324
1325         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1326                 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1327
1328         pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1329
1330         return 0;
1331 }
1332
1333 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1334 {
1335         struct nvme_queue *nvmeq = &dev->queues[0];
1336
1337         if (shutdown)
1338                 nvme_shutdown_ctrl(&dev->ctrl);
1339         else
1340                 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1341
1342         spin_lock_irq(&nvmeq->q_lock);
1343         nvme_process_cq(nvmeq);
1344         spin_unlock_irq(&nvmeq->q_lock);
1345 }
1346
1347 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1348                                 int entry_size)
1349 {
1350         int q_depth = dev->q_depth;
1351         unsigned q_size_aligned = roundup(q_depth * entry_size,
1352                                           dev->ctrl.page_size);
1353
1354         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1355                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1356                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1357                 q_depth = div_u64(mem_per_q, entry_size);
1358
1359                 /*
1360                  * Ensure the reduced q_depth is above some threshold where it
1361                  * would be better to map queues in system memory with the
1362                  * original depth
1363                  */
1364                 if (q_depth < 64)
1365                         return -ENOMEM;
1366         }
1367
1368         return q_depth;
1369 }
1370
1371 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1372                                 int qid, int depth)
1373 {
1374         /* CMB SQEs will be mapped before creation */
1375         if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS))
1376                 return 0;
1377
1378         nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1379                                             &nvmeq->sq_dma_addr, GFP_KERNEL);
1380         if (!nvmeq->sq_cmds)
1381                 return -ENOMEM;
1382         return 0;
1383 }
1384
1385 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1386 {
1387         struct nvme_queue *nvmeq = &dev->queues[qid];
1388
1389         if (dev->ctrl.queue_count > qid)
1390                 return 0;
1391
1392         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1393                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1394         if (!nvmeq->cqes)
1395                 goto free_nvmeq;
1396
1397         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1398                 goto free_cqdma;
1399
1400         nvmeq->q_dmadev = dev->dev;
1401         nvmeq->dev = dev;
1402         spin_lock_init(&nvmeq->q_lock);
1403         nvmeq->cq_head = 0;
1404         nvmeq->cq_phase = 1;
1405         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1406         nvmeq->q_depth = depth;
1407         nvmeq->qid = qid;
1408         nvmeq->cq_vector = -1;
1409         dev->ctrl.queue_count++;
1410
1411         return 0;
1412
1413  free_cqdma:
1414         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1415                                                         nvmeq->cq_dma_addr);
1416  free_nvmeq:
1417         return -ENOMEM;
1418 }
1419
1420 static int queue_request_irq(struct nvme_queue *nvmeq)
1421 {
1422         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1423         int nr = nvmeq->dev->ctrl.instance;
1424
1425         if (use_threaded_interrupts) {
1426                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1427                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1428         } else {
1429                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1430                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1431         }
1432 }
1433
1434 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1435 {
1436         struct nvme_dev *dev = nvmeq->dev;
1437
1438         spin_lock_irq(&nvmeq->q_lock);
1439         nvmeq->sq_tail = 0;
1440         nvmeq->cq_head = 0;
1441         nvmeq->cq_phase = 1;
1442         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1443         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1444         nvme_dbbuf_init(dev, nvmeq, qid);
1445         dev->online_queues++;
1446         spin_unlock_irq(&nvmeq->q_lock);
1447 }
1448
1449 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1450 {
1451         struct nvme_dev *dev = nvmeq->dev;
1452         int result;
1453
1454         if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1455                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth),
1456                                                       dev->ctrl.page_size);
1457                 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
1458                 nvmeq->sq_cmds_io = dev->cmb + offset;
1459         }
1460
1461         /*
1462          * A queue's vector matches the queue identifier unless the controller
1463          * has only one vector available.
1464          */
1465         nvmeq->cq_vector = dev->num_vecs == 1 ? 0 : qid;
1466         result = adapter_alloc_cq(dev, qid, nvmeq);
1467         if (result < 0)
1468                 goto release_vector;
1469
1470         result = adapter_alloc_sq(dev, qid, nvmeq);
1471         if (result < 0)
1472                 goto release_cq;
1473
1474         nvme_init_queue(nvmeq, qid);
1475         result = queue_request_irq(nvmeq);
1476         if (result < 0)
1477                 goto release_sq;
1478
1479         return result;
1480
1481  release_sq:
1482         dev->online_queues--;
1483         adapter_delete_sq(dev, qid);
1484  release_cq:
1485         adapter_delete_cq(dev, qid);
1486  release_vector:
1487         nvmeq->cq_vector = -1;
1488         return result;
1489 }
1490
1491 static const struct blk_mq_ops nvme_mq_admin_ops = {
1492         .queue_rq       = nvme_queue_rq,
1493         .complete       = nvme_pci_complete_rq,
1494         .init_hctx      = nvme_admin_init_hctx,
1495         .exit_hctx      = nvme_admin_exit_hctx,
1496         .init_request   = nvme_init_request,
1497         .timeout        = nvme_timeout,
1498 };
1499
1500 static const struct blk_mq_ops nvme_mq_ops = {
1501         .queue_rq       = nvme_queue_rq,
1502         .complete       = nvme_pci_complete_rq,
1503         .init_hctx      = nvme_init_hctx,
1504         .init_request   = nvme_init_request,
1505         .map_queues     = nvme_pci_map_queues,
1506         .timeout        = nvme_timeout,
1507         .poll           = nvme_poll,
1508 };
1509
1510 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1511 {
1512         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1513                 /*
1514                  * If the controller was reset during removal, it's possible
1515                  * user requests may be waiting on a stopped queue. Start the
1516                  * queue to flush these to completion.
1517                  */
1518                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1519                 blk_cleanup_queue(dev->ctrl.admin_q);
1520                 blk_mq_free_tag_set(&dev->admin_tagset);
1521         }
1522 }
1523
1524 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1525 {
1526         if (!dev->ctrl.admin_q) {
1527                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1528                 dev->admin_tagset.nr_hw_queues = 1;
1529
1530                 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1531                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1532                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1533                 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
1534                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1535                 dev->admin_tagset.driver_data = dev;
1536
1537                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1538                         return -ENOMEM;
1539                 dev->ctrl.admin_tagset = &dev->admin_tagset;
1540
1541                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1542                 if (IS_ERR(dev->ctrl.admin_q)) {
1543                         blk_mq_free_tag_set(&dev->admin_tagset);
1544                         return -ENOMEM;
1545                 }
1546                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1547                         nvme_dev_remove_admin(dev);
1548                         dev->ctrl.admin_q = NULL;
1549                         return -ENODEV;
1550                 }
1551         } else
1552                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1553
1554         return 0;
1555 }
1556
1557 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1558 {
1559         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1560 }
1561
1562 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1563 {
1564         struct pci_dev *pdev = to_pci_dev(dev->dev);
1565
1566         if (size <= dev->bar_mapped_size)
1567                 return 0;
1568         if (size > pci_resource_len(pdev, 0))
1569                 return -ENOMEM;
1570         if (dev->bar)
1571                 iounmap(dev->bar);
1572         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1573         if (!dev->bar) {
1574                 dev->bar_mapped_size = 0;
1575                 return -ENOMEM;
1576         }
1577         dev->bar_mapped_size = size;
1578         dev->dbs = dev->bar + NVME_REG_DBS;
1579
1580         return 0;
1581 }
1582
1583 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1584 {
1585         int result;
1586         u32 aqa;
1587         struct nvme_queue *nvmeq;
1588
1589         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1590         if (result < 0)
1591                 return result;
1592
1593         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1594                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1595
1596         if (dev->subsystem &&
1597             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1598                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1599
1600         result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1601         if (result < 0)
1602                 return result;
1603
1604         result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1605         if (result)
1606                 return result;
1607
1608         nvmeq = &dev->queues[0];
1609         aqa = nvmeq->q_depth - 1;
1610         aqa |= aqa << 16;
1611
1612         writel(aqa, dev->bar + NVME_REG_AQA);
1613         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1614         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1615
1616         result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1617         if (result)
1618                 return result;
1619
1620         nvmeq->cq_vector = 0;
1621         nvme_init_queue(nvmeq, 0);
1622         result = queue_request_irq(nvmeq);
1623         if (result) {
1624                 nvmeq->cq_vector = -1;
1625                 return result;
1626         }
1627
1628         return result;
1629 }
1630
1631 static int nvme_create_io_queues(struct nvme_dev *dev)
1632 {
1633         unsigned i, max;
1634         int ret = 0;
1635
1636         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1637                 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1638                         ret = -ENOMEM;
1639                         break;
1640                 }
1641         }
1642
1643         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1644         for (i = dev->online_queues; i <= max; i++) {
1645                 ret = nvme_create_queue(&dev->queues[i], i);
1646                 if (ret)
1647                         break;
1648         }
1649
1650         /*
1651          * Ignore failing Create SQ/CQ commands, we can continue with less
1652          * than the desired amount of queues, and even a controller without
1653          * I/O queues can still be used to issue admin commands.  This might
1654          * be useful to upgrade a buggy firmware for example.
1655          */
1656         return ret >= 0 ? 0 : ret;
1657 }
1658
1659 static ssize_t nvme_cmb_show(struct device *dev,
1660                              struct device_attribute *attr,
1661                              char *buf)
1662 {
1663         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1664
1665         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1666                        ndev->cmbloc, ndev->cmbsz);
1667 }
1668 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1669
1670 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1671 {
1672         u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1673
1674         return 1ULL << (12 + 4 * szu);
1675 }
1676
1677 static u32 nvme_cmb_size(struct nvme_dev *dev)
1678 {
1679         return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1680 }
1681
1682 static void nvme_map_cmb(struct nvme_dev *dev)
1683 {
1684         u64 size, offset;
1685         resource_size_t bar_size;
1686         struct pci_dev *pdev = to_pci_dev(dev->dev);
1687         int bar;
1688
1689         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1690         if (!dev->cmbsz)
1691                 return;
1692         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1693
1694         if (!use_cmb_sqes)
1695                 return;
1696
1697         size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1698         offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1699         bar = NVME_CMB_BIR(dev->cmbloc);
1700         bar_size = pci_resource_len(pdev, bar);
1701
1702         if (offset > bar_size)
1703                 return;
1704
1705         /*
1706          * Controllers may support a CMB size larger than their BAR,
1707          * for example, due to being behind a bridge. Reduce the CMB to
1708          * the reported size of the BAR
1709          */
1710         if (size > bar_size - offset)
1711                 size = bar_size - offset;
1712
1713         dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
1714         if (!dev->cmb)
1715                 return;
1716         dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
1717         dev->cmb_size = size;
1718
1719         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1720                                     &dev_attr_cmb.attr, NULL))
1721                 dev_warn(dev->ctrl.device,
1722                          "failed to add sysfs attribute for CMB\n");
1723 }
1724
1725 static inline void nvme_release_cmb(struct nvme_dev *dev)
1726 {
1727         if (dev->cmb) {
1728                 iounmap(dev->cmb);
1729                 dev->cmb = NULL;
1730                 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1731                                              &dev_attr_cmb.attr, NULL);
1732                 dev->cmbsz = 0;
1733         }
1734 }
1735
1736 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1737 {
1738         u64 dma_addr = dev->host_mem_descs_dma;
1739         struct nvme_command c;
1740         int ret;
1741
1742         memset(&c, 0, sizeof(c));
1743         c.features.opcode       = nvme_admin_set_features;
1744         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1745         c.features.dword11      = cpu_to_le32(bits);
1746         c.features.dword12      = cpu_to_le32(dev->host_mem_size >>
1747                                               ilog2(dev->ctrl.page_size));
1748         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1749         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1750         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1751
1752         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1753         if (ret) {
1754                 dev_warn(dev->ctrl.device,
1755                          "failed to set host mem (err %d, flags %#x).\n",
1756                          ret, bits);
1757         }
1758         return ret;
1759 }
1760
1761 static void nvme_free_host_mem(struct nvme_dev *dev)
1762 {
1763         int i;
1764
1765         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1766                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1767                 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1768
1769                 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1770                                 le64_to_cpu(desc->addr));
1771         }
1772
1773         kfree(dev->host_mem_desc_bufs);
1774         dev->host_mem_desc_bufs = NULL;
1775         dma_free_coherent(dev->dev,
1776                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1777                         dev->host_mem_descs, dev->host_mem_descs_dma);
1778         dev->host_mem_descs = NULL;
1779         dev->nr_host_mem_descs = 0;
1780 }
1781
1782 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1783                 u32 chunk_size)
1784 {
1785         struct nvme_host_mem_buf_desc *descs;
1786         u32 max_entries, len;
1787         dma_addr_t descs_dma;
1788         int i = 0;
1789         void **bufs;
1790         u64 size, tmp;
1791
1792         tmp = (preferred + chunk_size - 1);
1793         do_div(tmp, chunk_size);
1794         max_entries = tmp;
1795
1796         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1797                 max_entries = dev->ctrl.hmmaxd;
1798
1799         descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1800                         &descs_dma, GFP_KERNEL);
1801         if (!descs)
1802                 goto out;
1803
1804         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1805         if (!bufs)
1806                 goto out_free_descs;
1807
1808         for (size = 0; size < preferred && i < max_entries; size += len) {
1809                 dma_addr_t dma_addr;
1810
1811                 len = min_t(u64, chunk_size, preferred - size);
1812                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1813                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1814                 if (!bufs[i])
1815                         break;
1816
1817                 descs[i].addr = cpu_to_le64(dma_addr);
1818                 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1819                 i++;
1820         }
1821
1822         if (!size)
1823                 goto out_free_bufs;
1824
1825         dev->nr_host_mem_descs = i;
1826         dev->host_mem_size = size;
1827         dev->host_mem_descs = descs;
1828         dev->host_mem_descs_dma = descs_dma;
1829         dev->host_mem_desc_bufs = bufs;
1830         return 0;
1831
1832 out_free_bufs:
1833         while (--i >= 0) {
1834                 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1835
1836                 dma_free_coherent(dev->dev, size, bufs[i],
1837                                 le64_to_cpu(descs[i].addr));
1838         }
1839
1840         kfree(bufs);
1841 out_free_descs:
1842         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1843                         descs_dma);
1844 out:
1845         dev->host_mem_descs = NULL;
1846         return -ENOMEM;
1847 }
1848
1849 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1850 {
1851         u32 chunk_size;
1852
1853         /* start big and work our way down */
1854         for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1855              chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1856              chunk_size /= 2) {
1857                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1858                         if (!min || dev->host_mem_size >= min)
1859                                 return 0;
1860                         nvme_free_host_mem(dev);
1861                 }
1862         }
1863
1864         return -ENOMEM;
1865 }
1866
1867 static int nvme_setup_host_mem(struct nvme_dev *dev)
1868 {
1869         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1870         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1871         u64 min = (u64)dev->ctrl.hmmin * 4096;
1872         u32 enable_bits = NVME_HOST_MEM_ENABLE;
1873         int ret;
1874
1875         preferred = min(preferred, max);
1876         if (min > max) {
1877                 dev_warn(dev->ctrl.device,
1878                         "min host memory (%lld MiB) above limit (%d MiB).\n",
1879                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
1880                 nvme_free_host_mem(dev);
1881                 return 0;
1882         }
1883
1884         /*
1885          * If we already have a buffer allocated check if we can reuse it.
1886          */
1887         if (dev->host_mem_descs) {
1888                 if (dev->host_mem_size >= min)
1889                         enable_bits |= NVME_HOST_MEM_RETURN;
1890                 else
1891                         nvme_free_host_mem(dev);
1892         }
1893
1894         if (!dev->host_mem_descs) {
1895                 if (nvme_alloc_host_mem(dev, min, preferred)) {
1896                         dev_warn(dev->ctrl.device,
1897                                 "failed to allocate host memory buffer.\n");
1898                         return 0; /* controller must work without HMB */
1899                 }
1900
1901                 dev_info(dev->ctrl.device,
1902                         "allocated %lld MiB host memory buffer.\n",
1903                         dev->host_mem_size >> ilog2(SZ_1M));
1904         }
1905
1906         ret = nvme_set_host_mem(dev, enable_bits);
1907         if (ret)
1908                 nvme_free_host_mem(dev);
1909         return ret;
1910 }
1911
1912 static int nvme_setup_io_queues(struct nvme_dev *dev)
1913 {
1914         struct nvme_queue *adminq = &dev->queues[0];
1915         struct pci_dev *pdev = to_pci_dev(dev->dev);
1916         int result, nr_io_queues;
1917         unsigned long size;
1918
1919         struct irq_affinity affd = {
1920                 .pre_vectors = 1
1921         };
1922
1923         nr_io_queues = num_possible_cpus();
1924         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1925         if (result < 0)
1926                 return result;
1927
1928         if (nr_io_queues == 0)
1929                 return 0;
1930
1931         if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1932                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1933                                 sizeof(struct nvme_command));
1934                 if (result > 0)
1935                         dev->q_depth = result;
1936                 else
1937                         nvme_release_cmb(dev);
1938         }
1939
1940         do {
1941                 size = db_bar_size(dev, nr_io_queues);
1942                 result = nvme_remap_bar(dev, size);
1943                 if (!result)
1944                         break;
1945                 if (!--nr_io_queues)
1946                         return -ENOMEM;
1947         } while (1);
1948         adminq->q_db = dev->dbs;
1949
1950         /* Deregister the admin queue's interrupt */
1951         pci_free_irq(pdev, 0, adminq);
1952
1953         /*
1954          * If we enable msix early due to not intx, disable it again before
1955          * setting up the full range we need.
1956          */
1957         pci_free_irq_vectors(pdev);
1958         result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1,
1959                         PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
1960         if (result <= 0)
1961                 return -EIO;
1962         dev->num_vecs = result;
1963         dev->max_qid = max(result - 1, 1);
1964
1965         /*
1966          * Should investigate if there's a performance win from allocating
1967          * more queues than interrupt vectors; it might allow the submission
1968          * path to scale better, even if the receive path is limited by the
1969          * number of interrupts.
1970          */
1971
1972         result = queue_request_irq(adminq);
1973         if (result) {
1974                 adminq->cq_vector = -1;
1975                 return result;
1976         }
1977         return nvme_create_io_queues(dev);
1978 }
1979
1980 static void nvme_del_queue_end(struct request *req, blk_status_t error)
1981 {
1982         struct nvme_queue *nvmeq = req->end_io_data;
1983
1984         blk_mq_free_request(req);
1985         complete(&nvmeq->dev->ioq_wait);
1986 }
1987
1988 static void nvme_del_cq_end(struct request *req, blk_status_t error)
1989 {
1990         struct nvme_queue *nvmeq = req->end_io_data;
1991
1992         if (!error) {
1993                 unsigned long flags;
1994
1995                 /*
1996                  * We might be called with the AQ q_lock held
1997                  * and the I/O queue q_lock should always
1998                  * nest inside the AQ one.
1999                  */
2000                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
2001                                         SINGLE_DEPTH_NESTING);
2002                 nvme_process_cq(nvmeq);
2003                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
2004         }
2005
2006         nvme_del_queue_end(req, error);
2007 }
2008
2009 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2010 {
2011         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2012         struct request *req;
2013         struct nvme_command cmd;
2014
2015         memset(&cmd, 0, sizeof(cmd));
2016         cmd.delete_queue.opcode = opcode;
2017         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2018
2019         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2020         if (IS_ERR(req))
2021                 return PTR_ERR(req);
2022
2023         req->timeout = ADMIN_TIMEOUT;
2024         req->end_io_data = nvmeq;
2025
2026         blk_execute_rq_nowait(q, NULL, req, false,
2027                         opcode == nvme_admin_delete_cq ?
2028                                 nvme_del_cq_end : nvme_del_queue_end);
2029         return 0;
2030 }
2031
2032 static void nvme_disable_io_queues(struct nvme_dev *dev)
2033 {
2034         int pass, queues = dev->online_queues - 1;
2035         unsigned long timeout;
2036         u8 opcode = nvme_admin_delete_sq;
2037
2038         for (pass = 0; pass < 2; pass++) {
2039                 int sent = 0, i = queues;
2040
2041                 reinit_completion(&dev->ioq_wait);
2042  retry:
2043                 timeout = ADMIN_TIMEOUT;
2044                 for (; i > 0; i--, sent++)
2045                         if (nvme_delete_queue(&dev->queues[i], opcode))
2046                                 break;
2047
2048                 while (sent--) {
2049                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2050                         if (timeout == 0)
2051                                 return;
2052                         if (i)
2053                                 goto retry;
2054                 }
2055                 opcode = nvme_admin_delete_cq;
2056         }
2057 }
2058
2059 /*
2060  * return error value only when tagset allocation failed
2061  */
2062 static int nvme_dev_add(struct nvme_dev *dev)
2063 {
2064         int ret;
2065
2066         if (!dev->ctrl.tagset) {
2067                 dev->tagset.ops = &nvme_mq_ops;
2068                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2069                 dev->tagset.timeout = NVME_IO_TIMEOUT;
2070                 dev->tagset.numa_node = dev_to_node(dev->dev);
2071                 dev->tagset.queue_depth =
2072                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2073                 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2074                 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2075                         dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2076                                         nvme_pci_cmd_size(dev, true));
2077                 }
2078                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2079                 dev->tagset.driver_data = dev;
2080
2081                 ret = blk_mq_alloc_tag_set(&dev->tagset);
2082                 if (ret) {
2083                         dev_warn(dev->ctrl.device,
2084                                 "IO queues tagset allocation failed %d\n", ret);
2085                         return ret;
2086                 }
2087                 dev->ctrl.tagset = &dev->tagset;
2088
2089                 nvme_dbbuf_set(dev);
2090         } else {
2091                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2092
2093                 /* Free previously allocated queues that are no longer usable */
2094                 nvme_free_queues(dev, dev->online_queues);
2095         }
2096
2097         return 0;
2098 }
2099
2100 static int nvme_pci_enable(struct nvme_dev *dev)
2101 {
2102         int result = -ENOMEM;
2103         struct pci_dev *pdev = to_pci_dev(dev->dev);
2104
2105         if (pci_enable_device_mem(pdev))
2106                 return result;
2107
2108         pci_set_master(pdev);
2109
2110         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2111             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2112                 goto disable;
2113
2114         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2115                 result = -ENODEV;
2116                 goto disable;
2117         }
2118
2119         /*
2120          * Some devices and/or platforms don't advertise or work with INTx
2121          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2122          * adjust this later.
2123          */
2124         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2125         if (result < 0)
2126                 return result;
2127
2128         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2129
2130         dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2131                                 io_queue_depth);
2132         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2133         dev->dbs = dev->bar + 4096;
2134
2135         /*
2136          * Temporary fix for the Apple controller found in the MacBook8,1 and
2137          * some MacBook7,1 to avoid controller resets and data loss.
2138          */
2139         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2140                 dev->q_depth = 2;
2141                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2142                         "set queue depth=%u to work around controller resets\n",
2143                         dev->q_depth);
2144         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2145                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2146                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2147                 dev->q_depth = 64;
2148                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2149                         "set queue depth=%u\n", dev->q_depth);
2150         }
2151
2152         nvme_map_cmb(dev);
2153
2154         pci_enable_pcie_error_reporting(pdev);
2155         pci_save_state(pdev);
2156         return 0;
2157
2158  disable:
2159         pci_disable_device(pdev);
2160         return result;
2161 }
2162
2163 static void nvme_dev_unmap(struct nvme_dev *dev)
2164 {
2165         if (dev->bar)
2166                 iounmap(dev->bar);
2167         pci_release_mem_regions(to_pci_dev(dev->dev));
2168 }
2169
2170 static void nvme_pci_disable(struct nvme_dev *dev)
2171 {
2172         struct pci_dev *pdev = to_pci_dev(dev->dev);
2173
2174         nvme_release_cmb(dev);
2175         pci_free_irq_vectors(pdev);
2176
2177         if (pci_is_enabled(pdev)) {
2178                 pci_disable_pcie_error_reporting(pdev);
2179                 pci_disable_device(pdev);
2180         }
2181 }
2182
2183 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2184 {
2185         int i;
2186         bool dead = true;
2187         struct pci_dev *pdev = to_pci_dev(dev->dev);
2188
2189         mutex_lock(&dev->shutdown_lock);
2190         if (pci_is_enabled(pdev)) {
2191                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2192
2193                 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2194                     dev->ctrl.state == NVME_CTRL_RESETTING)
2195                         nvme_start_freeze(&dev->ctrl);
2196                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2197                         pdev->error_state  != pci_channel_io_normal);
2198         }
2199
2200         /*
2201          * Give the controller a chance to complete all entered requests if
2202          * doing a safe shutdown.
2203          */
2204         if (!dead) {
2205                 if (shutdown)
2206                         nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2207         }
2208
2209         nvme_stop_queues(&dev->ctrl);
2210
2211         if (!dead && dev->ctrl.queue_count > 0) {
2212                 /*
2213                  * If the controller is still alive tell it to stop using the
2214                  * host memory buffer.  In theory the shutdown / reset should
2215                  * make sure that it doesn't access the host memoery anymore,
2216                  * but I'd rather be safe than sorry..
2217                  */
2218                 if (dev->host_mem_descs)
2219                         nvme_set_host_mem(dev, 0);
2220                 nvme_disable_io_queues(dev);
2221                 nvme_disable_admin_queue(dev, shutdown);
2222         }
2223         for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2224                 nvme_suspend_queue(&dev->queues[i]);
2225
2226         nvme_pci_disable(dev);
2227
2228         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2229         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2230
2231         /*
2232          * The driver will not be starting up queues again if shutting down so
2233          * must flush all entered requests to their failed completion to avoid
2234          * deadlocking blk-mq hot-cpu notifier.
2235          */
2236         if (shutdown)
2237                 nvme_start_queues(&dev->ctrl);
2238         mutex_unlock(&dev->shutdown_lock);
2239 }
2240
2241 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2242 {
2243         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2244                                                 PAGE_SIZE, PAGE_SIZE, 0);
2245         if (!dev->prp_page_pool)
2246                 return -ENOMEM;
2247
2248         /* Optimisation for I/Os between 4k and 128k */
2249         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2250                                                 256, 256, 0);
2251         if (!dev->prp_small_pool) {
2252                 dma_pool_destroy(dev->prp_page_pool);
2253                 return -ENOMEM;
2254         }
2255         return 0;
2256 }
2257
2258 static void nvme_release_prp_pools(struct nvme_dev *dev)
2259 {
2260         dma_pool_destroy(dev->prp_page_pool);
2261         dma_pool_destroy(dev->prp_small_pool);
2262 }
2263
2264 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2265 {
2266         struct nvme_dev *dev = to_nvme_dev(ctrl);
2267
2268         nvme_dbbuf_dma_free(dev);
2269         put_device(dev->dev);
2270         if (dev->tagset.tags)
2271                 blk_mq_free_tag_set(&dev->tagset);
2272         if (dev->ctrl.admin_q)
2273                 blk_put_queue(dev->ctrl.admin_q);
2274         kfree(dev->queues);
2275         free_opal_dev(dev->ctrl.opal_dev);
2276         kfree(dev);
2277 }
2278
2279 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2280 {
2281         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2282
2283         nvme_get_ctrl(&dev->ctrl);
2284         nvme_dev_disable(dev, false);
2285         if (!queue_work(nvme_wq, &dev->remove_work))
2286                 nvme_put_ctrl(&dev->ctrl);
2287 }
2288
2289 static void nvme_reset_work(struct work_struct *work)
2290 {
2291         struct nvme_dev *dev =
2292                 container_of(work, struct nvme_dev, ctrl.reset_work);
2293         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2294         int result = -ENODEV;
2295         enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
2296
2297         if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2298                 goto out;
2299
2300         /*
2301          * If we're called to reset a live controller first shut it down before
2302          * moving on.
2303          */
2304         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2305                 nvme_dev_disable(dev, false);
2306
2307         /*
2308          * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2309          * initializing procedure here.
2310          */
2311         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2312                 dev_warn(dev->ctrl.device,
2313                         "failed to mark controller CONNECTING\n");
2314                 goto out;
2315         }
2316
2317         result = nvme_pci_enable(dev);
2318         if (result)
2319                 goto out;
2320
2321         result = nvme_pci_configure_admin_queue(dev);
2322         if (result)
2323                 goto out;
2324
2325         result = nvme_alloc_admin_tags(dev);
2326         if (result)
2327                 goto out;
2328
2329         result = nvme_init_identify(&dev->ctrl);
2330         if (result)
2331                 goto out;
2332
2333         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2334                 if (!dev->ctrl.opal_dev)
2335                         dev->ctrl.opal_dev =
2336                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2337                 else if (was_suspend)
2338                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2339         } else {
2340                 free_opal_dev(dev->ctrl.opal_dev);
2341                 dev->ctrl.opal_dev = NULL;
2342         }
2343
2344         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2345                 result = nvme_dbbuf_dma_alloc(dev);
2346                 if (result)
2347                         dev_warn(dev->dev,
2348                                  "unable to allocate dma for dbbuf\n");
2349         }
2350
2351         if (dev->ctrl.hmpre) {
2352                 result = nvme_setup_host_mem(dev);
2353                 if (result < 0)
2354                         goto out;
2355         }
2356
2357         result = nvme_setup_io_queues(dev);
2358         if (result)
2359                 goto out;
2360
2361         /*
2362          * Keep the controller around but remove all namespaces if we don't have
2363          * any working I/O queue.
2364          */
2365         if (dev->online_queues < 2) {
2366                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2367                 nvme_kill_queues(&dev->ctrl);
2368                 nvme_remove_namespaces(&dev->ctrl);
2369                 new_state = NVME_CTRL_ADMIN_ONLY;
2370         } else {
2371                 nvme_start_queues(&dev->ctrl);
2372                 nvme_wait_freeze(&dev->ctrl);
2373                 /* hit this only when allocate tagset fails */
2374                 if (nvme_dev_add(dev))
2375                         new_state = NVME_CTRL_ADMIN_ONLY;
2376                 nvme_unfreeze(&dev->ctrl);
2377         }
2378
2379         /*
2380          * If only admin queue live, keep it to do further investigation or
2381          * recovery.
2382          */
2383         if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2384                 dev_warn(dev->ctrl.device,
2385                         "failed to mark controller state %d\n", new_state);
2386                 goto out;
2387         }
2388
2389         nvme_start_ctrl(&dev->ctrl);
2390         return;
2391
2392  out:
2393         nvme_remove_dead_ctrl(dev, result);
2394 }
2395
2396 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2397 {
2398         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2399         struct pci_dev *pdev = to_pci_dev(dev->dev);
2400
2401         nvme_kill_queues(&dev->ctrl);
2402         if (pci_get_drvdata(pdev))
2403                 device_release_driver(&pdev->dev);
2404         nvme_put_ctrl(&dev->ctrl);
2405 }
2406
2407 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2408 {
2409         *val = readl(to_nvme_dev(ctrl)->bar + off);
2410         return 0;
2411 }
2412
2413 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2414 {
2415         writel(val, to_nvme_dev(ctrl)->bar + off);
2416         return 0;
2417 }
2418
2419 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2420 {
2421         *val = readq(to_nvme_dev(ctrl)->bar + off);
2422         return 0;
2423 }
2424
2425 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2426 {
2427         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2428
2429         return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2430 }
2431
2432 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2433         .name                   = "pcie",
2434         .module                 = THIS_MODULE,
2435         .flags                  = NVME_F_METADATA_SUPPORTED,
2436         .reg_read32             = nvme_pci_reg_read32,
2437         .reg_write32            = nvme_pci_reg_write32,
2438         .reg_read64             = nvme_pci_reg_read64,
2439         .free_ctrl              = nvme_pci_free_ctrl,
2440         .submit_async_event     = nvme_pci_submit_async_event,
2441         .get_address            = nvme_pci_get_address,
2442 };
2443
2444 static int nvme_dev_map(struct nvme_dev *dev)
2445 {
2446         struct pci_dev *pdev = to_pci_dev(dev->dev);
2447
2448         if (pci_request_mem_regions(pdev, "nvme"))
2449                 return -ENODEV;
2450
2451         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2452                 goto release;
2453
2454         return 0;
2455   release:
2456         pci_release_mem_regions(pdev);
2457         return -ENODEV;
2458 }
2459
2460 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2461 {
2462         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2463                 /*
2464                  * Several Samsung devices seem to drop off the PCIe bus
2465                  * randomly when APST is on and uses the deepest sleep state.
2466                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2467                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2468                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2469                  * laptops.
2470                  */
2471                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2472                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2473                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2474                         return NVME_QUIRK_NO_DEEPEST_PS;
2475         } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2476                 /*
2477                  * Samsung SSD 960 EVO drops off the PCIe bus after system
2478                  * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2479                  * within few minutes after bootup on a Coffee Lake board -
2480                  * ASUS PRIME Z370-A
2481                  */
2482                 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2483                     (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2484                      dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2485                         return NVME_QUIRK_NO_APST;
2486         }
2487
2488         return 0;
2489 }
2490
2491 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2492 {
2493         int node, result = -ENOMEM;
2494         struct nvme_dev *dev;
2495         unsigned long quirks = id->driver_data;
2496
2497         node = dev_to_node(&pdev->dev);
2498         if (node == NUMA_NO_NODE)
2499                 set_dev_node(&pdev->dev, first_memory_node);
2500
2501         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2502         if (!dev)
2503                 return -ENOMEM;
2504
2505         dev->queues = kcalloc_node(num_possible_cpus() + 1,
2506                         sizeof(struct nvme_queue), GFP_KERNEL, node);
2507         if (!dev->queues)
2508                 goto free;
2509
2510         dev->dev = get_device(&pdev->dev);
2511         pci_set_drvdata(pdev, dev);
2512
2513         result = nvme_dev_map(dev);
2514         if (result)
2515                 goto put_pci;
2516
2517         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2518         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2519         mutex_init(&dev->shutdown_lock);
2520         init_completion(&dev->ioq_wait);
2521
2522         result = nvme_setup_prp_pools(dev);
2523         if (result)
2524                 goto unmap;
2525
2526         quirks |= check_vendor_combination_bug(pdev);
2527
2528         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2529                         quirks);
2530         if (result)
2531                 goto release_pools;
2532
2533         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2534
2535         nvme_reset_ctrl(&dev->ctrl);
2536
2537         return 0;
2538
2539  release_pools:
2540         nvme_release_prp_pools(dev);
2541  unmap:
2542         nvme_dev_unmap(dev);
2543  put_pci:
2544         put_device(dev->dev);
2545  free:
2546         kfree(dev->queues);
2547         kfree(dev);
2548         return result;
2549 }
2550
2551 static void nvme_reset_prepare(struct pci_dev *pdev)
2552 {
2553         struct nvme_dev *dev = pci_get_drvdata(pdev);
2554         nvme_dev_disable(dev, false);
2555 }
2556
2557 static void nvme_reset_done(struct pci_dev *pdev)
2558 {
2559         struct nvme_dev *dev = pci_get_drvdata(pdev);
2560         nvme_reset_ctrl_sync(&dev->ctrl);
2561 }
2562
2563 static void nvme_shutdown(struct pci_dev *pdev)
2564 {
2565         struct nvme_dev *dev = pci_get_drvdata(pdev);
2566         nvme_dev_disable(dev, true);
2567 }
2568
2569 /*
2570  * The driver's remove may be called on a device in a partially initialized
2571  * state. This function must not have any dependencies on the device state in
2572  * order to proceed.
2573  */
2574 static void nvme_remove(struct pci_dev *pdev)
2575 {
2576         struct nvme_dev *dev = pci_get_drvdata(pdev);
2577
2578         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2579
2580         cancel_work_sync(&dev->ctrl.reset_work);
2581         pci_set_drvdata(pdev, NULL);
2582
2583         if (!pci_device_is_present(pdev)) {
2584                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2585                 nvme_dev_disable(dev, false);
2586         }
2587
2588         flush_work(&dev->ctrl.reset_work);
2589         nvme_stop_ctrl(&dev->ctrl);
2590         nvme_remove_namespaces(&dev->ctrl);
2591         nvme_dev_disable(dev, true);
2592         nvme_free_host_mem(dev);
2593         nvme_dev_remove_admin(dev);
2594         nvme_free_queues(dev, 0);
2595         nvme_uninit_ctrl(&dev->ctrl);
2596         nvme_release_prp_pools(dev);
2597         nvme_dev_unmap(dev);
2598         nvme_put_ctrl(&dev->ctrl);
2599 }
2600
2601 #ifdef CONFIG_PM_SLEEP
2602 static int nvme_suspend(struct device *dev)
2603 {
2604         struct pci_dev *pdev = to_pci_dev(dev);
2605         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2606
2607         nvme_dev_disable(ndev, true);
2608         return 0;
2609 }
2610
2611 static int nvme_resume(struct device *dev)
2612 {
2613         struct pci_dev *pdev = to_pci_dev(dev);
2614         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2615
2616         nvme_reset_ctrl(&ndev->ctrl);
2617         return 0;
2618 }
2619 #endif
2620
2621 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2622
2623 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2624                                                 pci_channel_state_t state)
2625 {
2626         struct nvme_dev *dev = pci_get_drvdata(pdev);
2627
2628         /*
2629          * A frozen channel requires a reset. When detected, this method will
2630          * shutdown the controller to quiesce. The controller will be restarted
2631          * after the slot reset through driver's slot_reset callback.
2632          */
2633         switch (state) {
2634         case pci_channel_io_normal:
2635                 return PCI_ERS_RESULT_CAN_RECOVER;
2636         case pci_channel_io_frozen:
2637                 dev_warn(dev->ctrl.device,
2638                         "frozen state error detected, reset controller\n");
2639                 nvme_dev_disable(dev, false);
2640                 return PCI_ERS_RESULT_NEED_RESET;
2641         case pci_channel_io_perm_failure:
2642                 dev_warn(dev->ctrl.device,
2643                         "failure state error detected, request disconnect\n");
2644                 return PCI_ERS_RESULT_DISCONNECT;
2645         }
2646         return PCI_ERS_RESULT_NEED_RESET;
2647 }
2648
2649 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2650 {
2651         struct nvme_dev *dev = pci_get_drvdata(pdev);
2652
2653         dev_info(dev->ctrl.device, "restart after slot reset\n");
2654         pci_restore_state(pdev);
2655         nvme_reset_ctrl(&dev->ctrl);
2656         return PCI_ERS_RESULT_RECOVERED;
2657 }
2658
2659 static void nvme_error_resume(struct pci_dev *pdev)
2660 {
2661         pci_cleanup_aer_uncorrect_error_status(pdev);
2662 }
2663
2664 static const struct pci_error_handlers nvme_err_handler = {
2665         .error_detected = nvme_error_detected,
2666         .slot_reset     = nvme_slot_reset,
2667         .resume         = nvme_error_resume,
2668         .reset_prepare  = nvme_reset_prepare,
2669         .reset_done     = nvme_reset_done,
2670 };
2671
2672 static const struct pci_device_id nvme_id_table[] = {
2673         { PCI_VDEVICE(INTEL, 0x0953),
2674                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2675                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2676         { PCI_VDEVICE(INTEL, 0x0a53),
2677                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2678                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2679         { PCI_VDEVICE(INTEL, 0x0a54),
2680                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2681                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2682         { PCI_VDEVICE(INTEL, 0x0a55),
2683                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2684                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2685         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
2686                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
2687         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2688                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2689         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
2690                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2691         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
2692                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2693         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
2694                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2695         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
2696                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2697         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
2698                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2699         { PCI_DEVICE(0x1d1d, 0x1f1f),   /* LighNVM qemu device */
2700                 .driver_data = NVME_QUIRK_LIGHTNVM, },
2701         { PCI_DEVICE(0x1d1d, 0x2807),   /* CNEX WL */
2702                 .driver_data = NVME_QUIRK_LIGHTNVM, },
2703         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2704         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2705         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2706         { 0, }
2707 };
2708 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2709
2710 static struct pci_driver nvme_driver = {
2711         .name           = "nvme",
2712         .id_table       = nvme_id_table,
2713         .probe          = nvme_probe,
2714         .remove         = nvme_remove,
2715         .shutdown       = nvme_shutdown,
2716         .driver         = {
2717                 .pm     = &nvme_dev_pm_ops,
2718         },
2719         .sriov_configure = pci_sriov_configure_simple,
2720         .err_handler    = &nvme_err_handler,
2721 };
2722
2723 static int __init nvme_init(void)
2724 {
2725         return pci_register_driver(&nvme_driver);
2726 }
2727
2728 static void __exit nvme_exit(void)
2729 {
2730         pci_unregister_driver(&nvme_driver);
2731         flush_workqueue(nvme_wq);
2732         _nvme_check_size();
2733 }
2734
2735 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2736 MODULE_LICENSE("GPL");
2737 MODULE_VERSION("1.0");
2738 module_init(nvme_init);
2739 module_exit(nvme_exit);