drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/blk-mq-pci.h>
  20 #include <linux/dmi.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/mm.h>
  25 #include <linux/module.h>
  26 #include <linux/mutex.h>
  27 #include <linux/pci.h>
  28 #include <linux/poison.h>
  29 #include <linux/t10-pi.h>
  30 #include <linux/timer.h>
  31 #include <linux/types.h>
  32 #include <linux/io-64-nonatomic-lo-hi.h>
  33 #include <asm/unaligned.h>
  34 #include <linux/sed-opal.h>
  35
  36 #include "nvme.h"
  37
  38 #define NVME_Q_DEPTH            1024
  39 #define NVME_AQ_DEPTH           256
  40 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  41 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  42
  43 /*
  44  * We handle AEN commands ourselves and don't even let the
  45  * block layer know about them.
  46  */
  47 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AERS)
  48
  49 static int use_threaded_interrupts;
  50 module_param(use_threaded_interrupts, int, 0);
  51
  52 static bool use_cmb_sqes = true;
  53 module_param(use_cmb_sqes, bool, 0644);
  54 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  55
  56 static unsigned int max_host_mem_size_mb = 128;
  57 module_param(max_host_mem_size_mb, uint, 0444);
  58 MODULE_PARM_DESC(max_host_mem_size_mb,
  59         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  60
  61 struct nvme_dev;
  62 struct nvme_queue;
  63
  64 static int nvme_reset(struct nvme_dev *dev);
  65 static void nvme_process_cq(struct nvme_queue *nvmeq);
  66 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  67
  68 /*
  69  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  70  */
  71 struct nvme_dev {
  72         struct nvme_queue **queues;
  73         struct blk_mq_tag_set tagset;
  74         struct blk_mq_tag_set admin_tagset;
  75         u32 __iomem *dbs;
  76         struct device *dev;
  77         struct dma_pool *prp_page_pool;
  78         struct dma_pool *prp_small_pool;
  79         unsigned queue_count;
  80         unsigned online_queues;
  81         unsigned max_qid;
  82         int q_depth;
  83         u32 db_stride;
  84         void __iomem *bar;
  85         unsigned long bar_mapped_size;
  86         struct work_struct reset_work;
  87         struct work_struct remove_work;
  88         struct mutex shutdown_lock;
  89         bool subsystem;
  90         void __iomem *cmb;
  91         dma_addr_t cmb_dma_addr;
  92         u64 cmb_size;
  93         u32 cmbsz;
  94         u32 cmbloc;
  95         struct nvme_ctrl ctrl;
  96         struct completion ioq_wait;
  97
  98         /* shadow doorbell buffer support: */
  99         u32 *dbbuf_dbs;
 100         dma_addr_t dbbuf_dbs_dma_addr;
 101         u32 *dbbuf_eis;
 102         dma_addr_t dbbuf_eis_dma_addr;
 103
 104         /* host memory buffer support: */
 105         u64 host_mem_size;
 106         u32 nr_host_mem_descs;
 107         struct nvme_host_mem_buf_desc *host_mem_descs;
 108         void **host_mem_desc_bufs;
 109 };
 110
 111 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 112 {
 113         return qid * 2 * stride;
 114 }
 115
 116 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 117 {
 118         return (qid * 2 + 1) * stride;
 119 }
 120
 121 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 122 {
 123         return container_of(ctrl, struct nvme_dev, ctrl);
 124 }
 125
 126 /*
 127  * An NVM Express queue.  Each device has at least two (one for admin
 128  * commands and one for I/O commands).
 129  */
 130 struct nvme_queue {
 131         struct device *q_dmadev;
 132         struct nvme_dev *dev;
 133         spinlock_t q_lock;
 134         struct nvme_command *sq_cmds;
 135         struct nvme_command __iomem *sq_cmds_io;
 136         volatile struct nvme_completion *cqes;
 137         struct blk_mq_tags **tags;
 138         dma_addr_t sq_dma_addr;
 139         dma_addr_t cq_dma_addr;
 140         u32 __iomem *q_db;
 141         u16 q_depth;
 142         s16 cq_vector;
 143         u16 sq_tail;
 144         u16 cq_head;
 145         u16 qid;
 146         u8 cq_phase;
 147         u8 cqe_seen;
 148         u32 *dbbuf_sq_db;
 149         u32 *dbbuf_cq_db;
 150         u32 *dbbuf_sq_ei;
 151         u32 *dbbuf_cq_ei;
 152 };
 153
 154 /*
 155  * The nvme_iod describes the data in an I/O, including the list of PRP
 156  * entries.  You can't see it in this data structure because C doesn't let
 157  * me express that.  Use nvme_init_iod to ensure there's enough space
 158  * allocated to store the PRP list.
 159  */
 160 struct nvme_iod {
 161         struct nvme_request req;
 162         struct nvme_queue *nvmeq;
 163         int aborted;
 164         int npages;             /* In the PRP list. 0 means small pool in use */
 165         int nents;              /* Used in scatterlist */
 166         int length;             /* Of data, in bytes */
 167         dma_addr_t first_dma;
 168         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 169         struct scatterlist *sg;
 170         struct scatterlist inline_sg[0];
 171 };
 172
 173 /*
 174  * Check we didin't inadvertently grow the command struct
 175  */
 176 static inline void _nvme_check_size(void)
 177 {
 178         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 179         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 180         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 181         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 182         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 183         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 184         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 185         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 186         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
 187         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
 188         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 189         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 190         BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
 191 }
 192
 193 static inline unsigned int nvme_dbbuf_size(u32 stride)
 194 {
 195         return ((num_possible_cpus() + 1) * 8 * stride);
 196 }
 197
 198 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 199 {
 200         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
 201
 202         if (dev->dbbuf_dbs)
 203                 return 0;
 204
 205         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 206                                             &dev->dbbuf_dbs_dma_addr,
 207                                             GFP_KERNEL);
 208         if (!dev->dbbuf_dbs)
 209                 return -ENOMEM;
 210         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 211                                             &dev->dbbuf_eis_dma_addr,
 212                                             GFP_KERNEL);
 213         if (!dev->dbbuf_eis) {
 214                 dma_free_coherent(dev->dev, mem_size,
 215                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 216                 dev->dbbuf_dbs = NULL;
 217                 return -ENOMEM;
 218         }
 219
 220         return 0;
 221 }
 222
 223 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 224 {
 225         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
 226
 227         if (dev->dbbuf_dbs) {
 228                 dma_free_coherent(dev->dev, mem_size,
 229                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 230                 dev->dbbuf_dbs = NULL;
 231         }
 232         if (dev->dbbuf_eis) {
 233                 dma_free_coherent(dev->dev, mem_size,
 234                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 235                 dev->dbbuf_eis = NULL;
 236         }
 237 }
 238
 239 static void nvme_dbbuf_init(struct nvme_dev *dev,
 240                             struct nvme_queue *nvmeq, int qid)
 241 {
 242         if (!dev->dbbuf_dbs || !qid)
 243                 return;
 244
 245         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 246         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 247         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 248         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 249 }
 250
 251 static void nvme_dbbuf_set(struct nvme_dev *dev)
 252 {
 253         struct nvme_command c;
 254
 255         if (!dev->dbbuf_dbs)
 256                 return;
 257
 258         memset(&c, 0, sizeof(c));
 259         c.dbbuf.opcode = nvme_admin_dbbuf;
 260         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 261         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 262
 263         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 264                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 265                 /* Free memory and continue on */
 266                 nvme_dbbuf_dma_free(dev);
 267         }
 268 }
 269
 270 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 271 {
 272         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 273 }
 274
 275 /* Update dbbuf and return true if an MMIO is required */
 276 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 277                                               volatile u32 *dbbuf_ei)
 278 {
 279         if (dbbuf_db) {
 280                 u16 old_value;
 281
 282                 /*
 283                  * Ensure that the queue is written before updating
 284                  * the doorbell in memory
 285                  */
 286                 wmb();
 287
 288                 old_value = *dbbuf_db;
 289                 *dbbuf_db = value;
 290
 291                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 292                         return false;
 293         }
 294
 295         return true;
 296 }
 297
 298 /*
 299  * Max size of iod being embedded in the request payload
 300  */
 301 #define NVME_INT_PAGES          2
 302 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 303
 304 /*
 305  * Will slightly overestimate the number of pages needed.  This is OK
 306  * as it only leads to a small amount of wasted memory for the lifetime of
 307  * the I/O.
 308  */
 309 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 310 {
 311         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 312                                       dev->ctrl.page_size);
 313         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 314 }
 315
 316 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 317                 unsigned int size, unsigned int nseg)
 318 {
 319         return sizeof(__le64 *) * nvme_npages(size, dev) +
 320                         sizeof(struct scatterlist) * nseg;
 321 }
 322
 323 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 324 {
 325         return sizeof(struct nvme_iod) +
 326                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 327 }
 328
 329 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 330                                 unsigned int hctx_idx)
 331 {
 332         struct nvme_dev *dev = data;
 333         struct nvme_queue *nvmeq = dev->queues[0];
 334
 335         WARN_ON(hctx_idx != 0);
 336         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 337         WARN_ON(nvmeq->tags);
 338
 339         hctx->driver_data = nvmeq;
 340         nvmeq->tags = &dev->admin_tagset.tags[0];
 341         return 0;
 342 }
 343
 344 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 345 {
 346         struct nvme_queue *nvmeq = hctx->driver_data;
 347
 348         nvmeq->tags = NULL;
 349 }
 350
 351 static int nvme_admin_init_request(struct blk_mq_tag_set *set,
 352                 struct request *req, unsigned int hctx_idx,
 353                 unsigned int numa_node)
 354 {
 355         struct nvme_dev *dev = set->driver_data;
 356         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 357         struct nvme_queue *nvmeq = dev->queues[0];
 358
 359         BUG_ON(!nvmeq);
 360         iod->nvmeq = nvmeq;
 361         return 0;
 362 }
 363
 364 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 365                           unsigned int hctx_idx)
 366 {
 367         struct nvme_dev *dev = data;
 368         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 369
 370         if (!nvmeq->tags)
 371                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 372
 373         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 374         hctx->driver_data = nvmeq;
 375         return 0;
 376 }
 377
 378 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
 379                 unsigned int hctx_idx, unsigned int numa_node)
 380 {
 381         struct nvme_dev *dev = set->driver_data;
 382         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 383         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 384
 385         BUG_ON(!nvmeq);
 386         iod->nvmeq = nvmeq;
 387         return 0;
 388 }
 389
 390 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 391 {
 392         struct nvme_dev *dev = set->driver_data;
 393
 394         return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
 395 }
 396
 397 /**
 398  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 399  * @nvmeq: The queue to use
 400  * @cmd: The command to send
 401  *
 402  * Safe to use from interrupt context
 403  */
 404 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 405                                                 struct nvme_command *cmd)
 406 {
 407         u16 tail = nvmeq->sq_tail;
 408
 409         if (nvmeq->sq_cmds_io)
 410                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 411         else
 412                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 413
 414         if (++tail == nvmeq->q_depth)
 415                 tail = 0;
 416         if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
 417                                               nvmeq->dbbuf_sq_ei))
 418                 writel(tail, nvmeq->q_db);
 419         nvmeq->sq_tail = tail;
 420 }
 421
 422 static __le64 **iod_list(struct request *req)
 423 {
 424         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 425         return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
 426 }
 427
 428 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
 429 {
 430         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 431         int nseg = blk_rq_nr_phys_segments(rq);
 432         unsigned int size = blk_rq_payload_bytes(rq);
 433
 434         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 435                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 436                 if (!iod->sg)
 437                         return BLK_STS_RESOURCE;
 438         } else {
 439                 iod->sg = iod->inline_sg;
 440         }
 441
 442         iod->aborted = 0;
 443         iod->npages = -1;
 444         iod->nents = 0;
 445         iod->length = size;
 446
 447         return BLK_STS_OK;
 448 }
 449
 450 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 451 {
 452         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 453         const int last_prp = dev->ctrl.page_size / 8 - 1;
 454         int i;
 455         __le64 **list = iod_list(req);
 456         dma_addr_t prp_dma = iod->first_dma;
 457
 458         if (iod->npages == 0)
 459                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 460         for (i = 0; i < iod->npages; i++) {
 461                 __le64 *prp_list = list[i];
 462                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 463                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 464                 prp_dma = next_prp_dma;
 465         }
 466
 467         if (iod->sg != iod->inline_sg)
 468                 kfree(iod->sg);
 469 }
 470
 471 #ifdef CONFIG_BLK_DEV_INTEGRITY
 472 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 473 {
 474         if (be32_to_cpu(pi->ref_tag) == v)
 475                 pi->ref_tag = cpu_to_be32(p);
 476 }
 477
 478 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 479 {
 480         if (be32_to_cpu(pi->ref_tag) == p)
 481                 pi->ref_tag = cpu_to_be32(v);
 482 }
 483
 484 /**
 485  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 486  *
 487  * The virtual start sector is the one that was originally submitted by the
 488  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 489  * start sector may be different. Remap protection information to match the
 490  * physical LBA on writes, and back to the original seed on reads.
 491  *
 492  * Type 0 and 3 do not have a ref tag, so no remapping required.
 493  */
 494 static void nvme_dif_remap(struct request *req,
 495                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 496 {
 497         struct nvme_ns *ns = req->rq_disk->private_data;
 498         struct bio_integrity_payload *bip;
 499         struct t10_pi_tuple *pi;
 500         void *p, *pmap;
 501         u32 i, nlb, ts, phys, virt;
 502
 503         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 504                 return;
 505
 506         bip = bio_integrity(req->bio);
 507         if (!bip)
 508                 return;
 509
 510         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 511
 512         p = pmap;
 513         virt = bip_get_seed(bip);
 514         phys = nvme_block_nr(ns, blk_rq_pos(req));
 515         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 516         ts = ns->disk->queue->integrity.tuple_size;
 517
 518         for (i = 0; i < nlb; i++, virt++, phys++) {
 519                 pi = (struct t10_pi_tuple *)p;
 520                 dif_swap(phys, virt, pi);
 521                 p += ts;
 522         }
 523         kunmap_atomic(pmap);
 524 }
 525 #else /* CONFIG_BLK_DEV_INTEGRITY */
 526 static void nvme_dif_remap(struct request *req,
 527                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 528 {
 529 }
 530 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 531 {
 532 }
 533 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 534 {
 535 }
 536 #endif
 537
 538 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req)
 539 {
 540         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 541         struct dma_pool *pool;
 542         int length = blk_rq_payload_bytes(req);
 543         struct scatterlist *sg = iod->sg;
 544         int dma_len = sg_dma_len(sg);
 545         u64 dma_addr = sg_dma_address(sg);
 546         u32 page_size = dev->ctrl.page_size;
 547         int offset = dma_addr & (page_size - 1);
 548         __le64 *prp_list;
 549         __le64 **list = iod_list(req);
 550         dma_addr_t prp_dma;
 551         int nprps, i;
 552
 553         length -= (page_size - offset);
 554         if (length <= 0)
 555                 return true;
 556
 557         dma_len -= (page_size - offset);
 558         if (dma_len) {
 559                 dma_addr += (page_size - offset);
 560         } else {
 561                 sg = sg_next(sg);
 562                 dma_addr = sg_dma_address(sg);
 563                 dma_len = sg_dma_len(sg);
 564         }
 565
 566         if (length <= page_size) {
 567                 iod->first_dma = dma_addr;
 568                 return true;
 569         }
 570
 571         nprps = DIV_ROUND_UP(length, page_size);
 572         if (nprps <= (256 / 8)) {
 573                 pool = dev->prp_small_pool;
 574                 iod->npages = 0;
 575         } else {
 576                 pool = dev->prp_page_pool;
 577                 iod->npages = 1;
 578         }
 579
 580         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 581         if (!prp_list) {
 582                 iod->first_dma = dma_addr;
 583                 iod->npages = -1;
 584                 return false;
 585         }
 586         list[0] = prp_list;
 587         iod->first_dma = prp_dma;
 588         i = 0;
 589         for (;;) {
 590                 if (i == page_size >> 3) {
 591                         __le64 *old_prp_list = prp_list;
 592                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 593                         if (!prp_list)
 594                                 return false;
 595                         list[iod->npages++] = prp_list;
 596                         prp_list[0] = old_prp_list[i - 1];
 597                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 598                         i = 1;
 599                 }
 600                 prp_list[i++] = cpu_to_le64(dma_addr);
 601                 dma_len -= page_size;
 602                 dma_addr += page_size;
 603                 length -= page_size;
 604                 if (length <= 0)
 605                         break;
 606                 if (dma_len > 0)
 607                         continue;
 608                 BUG_ON(dma_len < 0);
 609                 sg = sg_next(sg);
 610                 dma_addr = sg_dma_address(sg);
 611                 dma_len = sg_dma_len(sg);
 612         }
 613
 614         return true;
 615 }
 616
 617 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 618                 struct nvme_command *cmnd)
 619 {
 620         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 621         struct request_queue *q = req->q;
 622         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 623                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 624         blk_status_t ret = BLK_STS_IOERR;
 625
 626         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 627         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 628         if (!iod->nents)
 629                 goto out;
 630
 631         ret = BLK_STS_RESOURCE;
 632         if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
 633                                 DMA_ATTR_NO_WARN))
 634                 goto out;
 635
 636         if (!nvme_setup_prps(dev, req))
 637                 goto out_unmap;
 638
 639         ret = BLK_STS_IOERR;
 640         if (blk_integrity_rq(req)) {
 641                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 642                         goto out_unmap;
 643
 644                 sg_init_table(&iod->meta_sg, 1);
 645                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 646                         goto out_unmap;
 647
 648                 if (rq_data_dir(req))
 649                         nvme_dif_remap(req, nvme_dif_prep);
 650
 651                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 652                         goto out_unmap;
 653         }
 654
 655         cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 656         cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
 657         if (blk_integrity_rq(req))
 658                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 659         return BLK_STS_OK;
 660
 661 out_unmap:
 662         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 663 out:
 664         return ret;
 665 }
 666
 667 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 668 {
 669         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 670         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 671                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 672
 673         if (iod->nents) {
 674                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 675                 if (blk_integrity_rq(req)) {
 676                         if (!rq_data_dir(req))
 677                                 nvme_dif_remap(req, nvme_dif_complete);
 678                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 679                 }
 680         }
 681
 682         nvme_cleanup_cmd(req);
 683         nvme_free_iod(dev, req);
 684 }
 685
 686 /*
 687  * NOTE: ns is NULL when called on the admin queue.
 688  */
 689 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 690                          const struct blk_mq_queue_data *bd)
 691 {
 692         struct nvme_ns *ns = hctx->queue->queuedata;
 693         struct nvme_queue *nvmeq = hctx->driver_data;
 694         struct nvme_dev *dev = nvmeq->dev;
 695         struct request *req = bd->rq;
 696         struct nvme_command cmnd;
 697         blk_status_t ret;
 698
 699         ret = nvme_setup_cmd(ns, req, &cmnd);
 700         if (ret)
 701                 return ret;
 702
 703         ret = nvme_init_iod(req, dev);
 704         if (ret)
 705                 goto out_free_cmd;
 706
 707         if (blk_rq_nr_phys_segments(req)) {
 708                 ret = nvme_map_data(dev, req, &cmnd);
 709                 if (ret)
 710                         goto out_cleanup_iod;
 711         }
 712
 713         blk_mq_start_request(req);
 714
 715         spin_lock_irq(&nvmeq->q_lock);
 716         if (unlikely(nvmeq->cq_vector < 0)) {
 717                 ret = BLK_STS_IOERR;
 718                 spin_unlock_irq(&nvmeq->q_lock);
 719                 goto out_cleanup_iod;
 720         }
 721         __nvme_submit_cmd(nvmeq, &cmnd);
 722         nvme_process_cq(nvmeq);
 723         spin_unlock_irq(&nvmeq->q_lock);
 724         return BLK_STS_OK;
 725 out_cleanup_iod:
 726         nvme_free_iod(dev, req);
 727 out_free_cmd:
 728         nvme_cleanup_cmd(req);
 729         return ret;
 730 }
 731
 732 static void nvme_pci_complete_rq(struct request *req)
 733 {
 734         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 735
 736         nvme_unmap_data(iod->nvmeq->dev, req);
 737         nvme_complete_rq(req);
 738 }
 739
 740 /* We read the CQE phase first to check if the rest of the entry is valid */
 741 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 742                 u16 phase)
 743 {
 744         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 745 }
 746
 747 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 748 {
 749         u16 head, phase;
 750
 751         head = nvmeq->cq_head;
 752         phase = nvmeq->cq_phase;
 753
 754         while (nvme_cqe_valid(nvmeq, head, phase)) {
 755                 struct nvme_completion cqe = nvmeq->cqes[head];
 756                 struct request *req;
 757
 758                 if (++head == nvmeq->q_depth) {
 759                         head = 0;
 760                         phase = !phase;
 761                 }
 762
 763                 if (tag && *tag == cqe.command_id)
 764                         *tag = -1;
 765
 766                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 767                         dev_warn(nvmeq->dev->ctrl.device,
 768                                 "invalid id %d completed on queue %d\n",
 769                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 770                         continue;
 771                 }
 772
 773                 /*
 774                  * AEN requests are special as they don't time out and can
 775                  * survive any kind of queue freeze and often don't respond to
 776                  * aborts.  We don't even bother to allocate a struct request
 777                  * for them but rather special case them here.
 778                  */
 779                 if (unlikely(nvmeq->qid == 0 &&
 780                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 781                         nvme_complete_async_event(&nvmeq->dev->ctrl,
 782                                         cqe.status, &cqe.result);
 783                         continue;
 784                 }
 785
 786                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 787                 nvme_end_request(req, cqe.status, cqe.result);
 788         }
 789
 790         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 791                 return;
 792
 793         if (likely(nvmeq->cq_vector >= 0))
 794                 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
 795                                                       nvmeq->dbbuf_cq_ei))
 796                         writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 797         nvmeq->cq_head = head;
 798         nvmeq->cq_phase = phase;
 799
 800         nvmeq->cqe_seen = 1;
 801 }
 802
 803 static void nvme_process_cq(struct nvme_queue *nvmeq)
 804 {
 805         __nvme_process_cq(nvmeq, NULL);
 806 }
 807
 808 static irqreturn_t nvme_irq(int irq, void *data)
 809 {
 810         irqreturn_t result;
 811         struct nvme_queue *nvmeq = data;
 812         spin_lock(&nvmeq->q_lock);
 813         nvme_process_cq(nvmeq);
 814         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 815         nvmeq->cqe_seen = 0;
 816         spin_unlock(&nvmeq->q_lock);
 817         return result;
 818 }
 819
 820 static irqreturn_t nvme_irq_check(int irq, void *data)
 821 {
 822         struct nvme_queue *nvmeq = data;
 823         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
 824                 return IRQ_WAKE_THREAD;
 825         return IRQ_NONE;
 826 }
 827
 828 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
 829 {
 830         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 831                 spin_lock_irq(&nvmeq->q_lock);
 832                 __nvme_process_cq(nvmeq, &tag);
 833                 spin_unlock_irq(&nvmeq->q_lock);
 834
 835                 if (tag == -1)
 836                         return 1;
 837         }
 838
 839         return 0;
 840 }
 841
 842 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 843 {
 844         struct nvme_queue *nvmeq = hctx->driver_data;
 845
 846         return __nvme_poll(nvmeq, tag);
 847 }
 848
 849 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
 850 {
 851         struct nvme_dev *dev = to_nvme_dev(ctrl);
 852         struct nvme_queue *nvmeq = dev->queues[0];
 853         struct nvme_command c;
 854
 855         memset(&c, 0, sizeof(c));
 856         c.common.opcode = nvme_admin_async_event;
 857         c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
 858
 859         spin_lock_irq(&nvmeq->q_lock);
 860         __nvme_submit_cmd(nvmeq, &c);
 861         spin_unlock_irq(&nvmeq->q_lock);
 862 }
 863
 864 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 865 {
 866         struct nvme_command c;
 867
 868         memset(&c, 0, sizeof(c));
 869         c.delete_queue.opcode = opcode;
 870         c.delete_queue.qid = cpu_to_le16(id);
 871
 872         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 873 }
 874
 875 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 876                                                 struct nvme_queue *nvmeq)
 877 {
 878         struct nvme_command c;
 879         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 880
 881         /*
 882          * Note: we (ab)use the fact the the prp fields survive if no data
 883          * is attached to the request.
 884          */
 885         memset(&c, 0, sizeof(c));
 886         c.create_cq.opcode = nvme_admin_create_cq;
 887         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 888         c.create_cq.cqid = cpu_to_le16(qid);
 889         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 890         c.create_cq.cq_flags = cpu_to_le16(flags);
 891         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 892
 893         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 894 }
 895
 896 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 897                                                 struct nvme_queue *nvmeq)
 898 {
 899         struct nvme_command c;
 900         int flags = NVME_QUEUE_PHYS_CONTIG;
 901
 902         /*
 903          * Note: we (ab)use the fact the the prp fields survive if no data
 904          * is attached to the request.
 905          */
 906         memset(&c, 0, sizeof(c));
 907         c.create_sq.opcode = nvme_admin_create_sq;
 908         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 909         c.create_sq.sqid = cpu_to_le16(qid);
 910         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 911         c.create_sq.sq_flags = cpu_to_le16(flags);
 912         c.create_sq.cqid = cpu_to_le16(qid);
 913
 914         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 915 }
 916
 917 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 918 {
 919         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 920 }
 921
 922 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 923 {
 924         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 925 }
 926
 927 static void abort_endio(struct request *req, blk_status_t error)
 928 {
 929         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 930         struct nvme_queue *nvmeq = iod->nvmeq;
 931
 932         dev_warn(nvmeq->dev->ctrl.device,
 933                  "Abort status: 0x%x", nvme_req(req)->status);
 934         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 935         blk_mq_free_request(req);
 936 }
 937
 938 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
 939 {
 940
 941         /* If true, indicates loss of adapter communication, possibly by a
 942          * NVMe Subsystem reset.
 943          */
 944         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
 945
 946         /* If there is a reset ongoing, we shouldn't reset again. */
 947         if (dev->ctrl.state == NVME_CTRL_RESETTING)
 948                 return false;
 949
 950         /* We shouldn't reset unless the controller is on fatal error state
 951          * _or_ if we lost the communication with it.
 952          */
 953         if (!(csts & NVME_CSTS_CFS) && !nssro)
 954                 return false;
 955
 956         /* If PCI error recovery process is happening, we cannot reset or
 957          * the recovery mechanism will surely fail.
 958          */
 959         if (pci_channel_offline(to_pci_dev(dev->dev)))
 960                 return false;
 961
 962         return true;
 963 }
 964
 965 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
 966 {
 967         /* Read a config register to help see what died. */
 968         u16 pci_status;
 969         int result;
 970
 971         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
 972                                       &pci_status);
 973         if (result == PCIBIOS_SUCCESSFUL)
 974                 dev_warn(dev->ctrl.device,
 975                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
 976                          csts, pci_status);
 977         else
 978                 dev_warn(dev->ctrl.device,
 979                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
 980                          csts, result);
 981 }
 982
 983 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 984 {
 985         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 986         struct nvme_queue *nvmeq = iod->nvmeq;
 987         struct nvme_dev *dev = nvmeq->dev;
 988         struct request *abort_req;
 989         struct nvme_command cmd;
 990         u32 csts = readl(dev->bar + NVME_REG_CSTS);
 991
 992         /*
 993          * Reset immediately if the controller is failed
 994          */
 995         if (nvme_should_reset(dev, csts)) {
 996                 nvme_warn_reset(dev, csts);
 997                 nvme_dev_disable(dev, false);
 998                 nvme_reset(dev);
 999                 return BLK_EH_HANDLED;
1000         }
1001
1002         /*
1003          * Did we miss an interrupt?
1004          */
1005         if (__nvme_poll(nvmeq, req->tag)) {
1006                 dev_warn(dev->ctrl.device,
1007                          "I/O %d QID %d timeout, completion polled\n",
1008                          req->tag, nvmeq->qid);
1009                 return BLK_EH_HANDLED;
1010         }
1011
1012         /*
1013          * Shutdown immediately if controller times out while starting. The
1014          * reset work will see the pci device disabled when it gets the forced
1015          * cancellation error. All outstanding requests are completed on
1016          * shutdown, so we return BLK_EH_HANDLED.
1017          */
1018         if (dev->ctrl.state == NVME_CTRL_RESETTING) {
1019                 dev_warn(dev->ctrl.device,
1020                          "I/O %d QID %d timeout, disable controller\n",
1021                          req->tag, nvmeq->qid);
1022                 nvme_dev_disable(dev, false);
1023                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1024                 return BLK_EH_HANDLED;
1025         }
1026
1027         /*
1028          * Shutdown the controller immediately and schedule a reset if the
1029          * command was already aborted once before and still hasn't been
1030          * returned to the driver, or if this is the admin queue.
1031          */
1032         if (!nvmeq->qid || iod->aborted) {
1033                 dev_warn(dev->ctrl.device,
1034                          "I/O %d QID %d timeout, reset controller\n",
1035                          req->tag, nvmeq->qid);
1036                 nvme_dev_disable(dev, false);
1037                 nvme_reset(dev);
1038
1039                 /*
1040                  * Mark the request as handled, since the inline shutdown
1041                  * forces all outstanding requests to complete.
1042                  */
1043                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1044                 return BLK_EH_HANDLED;
1045         }
1046
1047         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1048                 atomic_inc(&dev->ctrl.abort_limit);
1049                 return BLK_EH_RESET_TIMER;
1050         }
1051         iod->aborted = 1;
1052
1053         memset(&cmd, 0, sizeof(cmd));
1054         cmd.abort.opcode = nvme_admin_abort_cmd;
1055         cmd.abort.cid = req->tag;
1056         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1057
1058         dev_warn(nvmeq->dev->ctrl.device,
1059                 "I/O %d QID %d timeout, aborting\n",
1060                  req->tag, nvmeq->qid);
1061
1062         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1063                         BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1064         if (IS_ERR(abort_req)) {
1065                 atomic_inc(&dev->ctrl.abort_limit);
1066                 return BLK_EH_RESET_TIMER;
1067         }
1068
1069         abort_req->timeout = ADMIN_TIMEOUT;
1070         abort_req->end_io_data = NULL;
1071         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1072
1073         /*
1074          * The aborted req will be completed on receiving the abort req.
1075          * We enable the timer again. If hit twice, it'll cause a device reset,
1076          * as the device then is in a faulty state.
1077          */
1078         return BLK_EH_RESET_TIMER;
1079 }
1080
1081 static void nvme_free_queue(struct nvme_queue *nvmeq)
1082 {
1083         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1084                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1085         if (nvmeq->sq_cmds)
1086                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1087                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1088         kfree(nvmeq);
1089 }
1090
1091 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1092 {
1093         int i;
1094
1095         for (i = dev->queue_count - 1; i >= lowest; i--) {
1096                 struct nvme_queue *nvmeq = dev->queues[i];
1097                 dev->queue_count--;
1098                 dev->queues[i] = NULL;
1099                 nvme_free_queue(nvmeq);
1100         }
1101 }
1102
1103 /**
1104  * nvme_suspend_queue - put queue into suspended state
1105  * @nvmeq - queue to suspend
1106  */
1107 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1108 {
1109         int vector;
1110
1111         spin_lock_irq(&nvmeq->q_lock);
1112         if (nvmeq->cq_vector == -1) {
1113                 spin_unlock_irq(&nvmeq->q_lock);
1114                 return 1;
1115         }
1116         vector = nvmeq->cq_vector;
1117         nvmeq->dev->online_queues--;
1118         nvmeq->cq_vector = -1;
1119         spin_unlock_irq(&nvmeq->q_lock);
1120
1121         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1122                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
1123
1124         pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1125
1126         return 0;
1127 }
1128
1129 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1130 {
1131         struct nvme_queue *nvmeq = dev->queues[0];
1132
1133         if (!nvmeq)
1134                 return;
1135         if (nvme_suspend_queue(nvmeq))
1136                 return;
1137
1138         if (shutdown)
1139                 nvme_shutdown_ctrl(&dev->ctrl);
1140         else
1141                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1142                                                 dev->bar + NVME_REG_CAP));
1143
1144         spin_lock_irq(&nvmeq->q_lock);
1145         nvme_process_cq(nvmeq);
1146         spin_unlock_irq(&nvmeq->q_lock);
1147 }
1148
1149 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1150                                 int entry_size)
1151 {
1152         int q_depth = dev->q_depth;
1153         unsigned q_size_aligned = roundup(q_depth * entry_size,
1154                                           dev->ctrl.page_size);
1155
1156         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1157                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1158                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1159                 q_depth = div_u64(mem_per_q, entry_size);
1160
1161                 /*
1162                  * Ensure the reduced q_depth is above some threshold where it
1163                  * would be better to map queues in system memory with the
1164                  * original depth
1165                  */
1166                 if (q_depth < 64)
1167                         return -ENOMEM;
1168         }
1169
1170         return q_depth;
1171 }
1172
1173 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1174                                 int qid, int depth)
1175 {
1176         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1177                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1178                                                       dev->ctrl.page_size);
1179                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1180                 nvmeq->sq_cmds_io = dev->cmb + offset;
1181         } else {
1182                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1183                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1184                 if (!nvmeq->sq_cmds)
1185                         return -ENOMEM;
1186         }
1187
1188         return 0;
1189 }
1190
1191 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1192                                                         int depth, int node)
1193 {
1194         struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
1195                                                         node);
1196         if (!nvmeq)
1197                 return NULL;
1198
1199         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1200                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1201         if (!nvmeq->cqes)
1202                 goto free_nvmeq;
1203
1204         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1205                 goto free_cqdma;
1206
1207         nvmeq->q_dmadev = dev->dev;
1208         nvmeq->dev = dev;
1209         spin_lock_init(&nvmeq->q_lock);
1210         nvmeq->cq_head = 0;
1211         nvmeq->cq_phase = 1;
1212         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1213         nvmeq->q_depth = depth;
1214         nvmeq->qid = qid;
1215         nvmeq->cq_vector = -1;
1216         dev->queues[qid] = nvmeq;
1217         dev->queue_count++;
1218
1219         return nvmeq;
1220
1221  free_cqdma:
1222         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1223                                                         nvmeq->cq_dma_addr);
1224  free_nvmeq:
1225         kfree(nvmeq);
1226         return NULL;
1227 }
1228
1229 static int queue_request_irq(struct nvme_queue *nvmeq)
1230 {
1231         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1232         int nr = nvmeq->dev->ctrl.instance;
1233
1234         if (use_threaded_interrupts) {
1235                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1236                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1237         } else {
1238                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1239                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1240         }
1241 }
1242
1243 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1244 {
1245         struct nvme_dev *dev = nvmeq->dev;
1246
1247         spin_lock_irq(&nvmeq->q_lock);
1248         nvmeq->sq_tail = 0;
1249         nvmeq->cq_head = 0;
1250         nvmeq->cq_phase = 1;
1251         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1252         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1253         nvme_dbbuf_init(dev, nvmeq, qid);
1254         dev->online_queues++;
1255         spin_unlock_irq(&nvmeq->q_lock);
1256 }
1257
1258 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1259 {
1260         struct nvme_dev *dev = nvmeq->dev;
1261         int result;
1262
1263         nvmeq->cq_vector = qid - 1;
1264         result = adapter_alloc_cq(dev, qid, nvmeq);
1265         if (result < 0)
1266                 return result;
1267
1268         result = adapter_alloc_sq(dev, qid, nvmeq);
1269         if (result < 0)
1270                 goto release_cq;
1271
1272         result = queue_request_irq(nvmeq);
1273         if (result < 0)
1274                 goto release_sq;
1275
1276         nvme_init_queue(nvmeq, qid);
1277         return result;
1278
1279  release_sq:
1280         adapter_delete_sq(dev, qid);
1281  release_cq:
1282         adapter_delete_cq(dev, qid);
1283         return result;
1284 }
1285
1286 static const struct blk_mq_ops nvme_mq_admin_ops = {
1287         .queue_rq       = nvme_queue_rq,
1288         .complete       = nvme_pci_complete_rq,
1289         .init_hctx      = nvme_admin_init_hctx,
1290         .exit_hctx      = nvme_admin_exit_hctx,
1291         .init_request   = nvme_admin_init_request,
1292         .timeout        = nvme_timeout,
1293 };
1294
1295 static const struct blk_mq_ops nvme_mq_ops = {
1296         .queue_rq       = nvme_queue_rq,
1297         .complete       = nvme_pci_complete_rq,
1298         .init_hctx      = nvme_init_hctx,
1299         .init_request   = nvme_init_request,
1300         .map_queues     = nvme_pci_map_queues,
1301         .timeout        = nvme_timeout,
1302         .poll           = nvme_poll,
1303 };
1304
1305 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1306 {
1307         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1308                 /*
1309                  * If the controller was reset during removal, it's possible
1310                  * user requests may be waiting on a stopped queue. Start the
1311                  * queue to flush these to completion.
1312                  */
1313                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1314                 blk_cleanup_queue(dev->ctrl.admin_q);
1315                 blk_mq_free_tag_set(&dev->admin_tagset);
1316         }
1317 }
1318
1319 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1320 {
1321         if (!dev->ctrl.admin_q) {
1322                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1323                 dev->admin_tagset.nr_hw_queues = 1;
1324
1325                 /*
1326                  * Subtract one to leave an empty queue entry for 'Full Queue'
1327                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1328                  */
1329                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1330                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1331                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1332                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1333                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1334                 dev->admin_tagset.driver_data = dev;
1335
1336                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1337                         return -ENOMEM;
1338
1339                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1340                 if (IS_ERR(dev->ctrl.admin_q)) {
1341                         blk_mq_free_tag_set(&dev->admin_tagset);
1342                         return -ENOMEM;
1343                 }
1344                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1345                         nvme_dev_remove_admin(dev);
1346                         dev->ctrl.admin_q = NULL;
1347                         return -ENODEV;
1348                 }
1349         } else
1350                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1351
1352         return 0;
1353 }
1354
1355 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1356 {
1357         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1358 }
1359
1360 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1361 {
1362         struct pci_dev *pdev = to_pci_dev(dev->dev);
1363
1364         if (size <= dev->bar_mapped_size)
1365                 return 0;
1366         if (size > pci_resource_len(pdev, 0))
1367                 return -ENOMEM;
1368         if (dev->bar)
1369                 iounmap(dev->bar);
1370         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1371         if (!dev->bar) {
1372                 dev->bar_mapped_size = 0;
1373                 return -ENOMEM;
1374         }
1375         dev->bar_mapped_size = size;
1376         dev->dbs = dev->bar + NVME_REG_DBS;
1377
1378         return 0;
1379 }
1380
1381 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1382 {
1383         int result;
1384         u32 aqa;
1385         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1386         struct nvme_queue *nvmeq;
1387
1388         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1389         if (result < 0)
1390                 return result;
1391
1392         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1393                                                 NVME_CAP_NSSRC(cap) : 0;
1394
1395         if (dev->subsystem &&
1396             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1397                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1398
1399         result = nvme_disable_ctrl(&dev->ctrl, cap);
1400         if (result < 0)
1401                 return result;
1402
1403         nvmeq = dev->queues[0];
1404         if (!nvmeq) {
1405                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1406                                         dev_to_node(dev->dev));
1407                 if (!nvmeq)
1408                         return -ENOMEM;
1409         }
1410
1411         aqa = nvmeq->q_depth - 1;
1412         aqa |= aqa << 16;
1413
1414         writel(aqa, dev->bar + NVME_REG_AQA);
1415         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1416         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1417
1418         result = nvme_enable_ctrl(&dev->ctrl, cap);
1419         if (result)
1420                 return result;
1421
1422         nvmeq->cq_vector = 0;
1423         result = queue_request_irq(nvmeq);
1424         if (result) {
1425                 nvmeq->cq_vector = -1;
1426                 return result;
1427         }
1428
1429         return result;
1430 }
1431
1432 static int nvme_create_io_queues(struct nvme_dev *dev)
1433 {
1434         unsigned i, max;
1435         int ret = 0;
1436
1437         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1438                 /* vector == qid - 1, match nvme_create_queue */
1439                 if (!nvme_alloc_queue(dev, i, dev->q_depth,
1440                      pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
1441                         ret = -ENOMEM;
1442                         break;
1443                 }
1444         }
1445
1446         max = min(dev->max_qid, dev->queue_count - 1);
1447         for (i = dev->online_queues; i <= max; i++) {
1448                 ret = nvme_create_queue(dev->queues[i], i);
1449                 if (ret)
1450                         break;
1451         }
1452
1453         /*
1454          * Ignore failing Create SQ/CQ commands, we can continue with less
1455          * than the desired aount of queues, and even a controller without
1456          * I/O queues an still be used to issue admin commands.  This might
1457          * be useful to upgrade a buggy firmware for example.
1458          */
1459         return ret >= 0 ? 0 : ret;
1460 }
1461
1462 static ssize_t nvme_cmb_show(struct device *dev,
1463                              struct device_attribute *attr,
1464                              char *buf)
1465 {
1466         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1467
1468         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1469                        ndev->cmbloc, ndev->cmbsz);
1470 }
1471 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1472
1473 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1474 {
1475         u64 szu, size, offset;
1476         resource_size_t bar_size;
1477         struct pci_dev *pdev = to_pci_dev(dev->dev);
1478         void __iomem *cmb;
1479         dma_addr_t dma_addr;
1480
1481         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1482         if (!(NVME_CMB_SZ(dev->cmbsz)))
1483                 return NULL;
1484         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1485
1486         if (!use_cmb_sqes)
1487                 return NULL;
1488
1489         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1490         size = szu * NVME_CMB_SZ(dev->cmbsz);
1491         offset = szu * NVME_CMB_OFST(dev->cmbloc);
1492         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1493
1494         if (offset > bar_size)
1495                 return NULL;
1496
1497         /*
1498          * Controllers may support a CMB size larger than their BAR,
1499          * for example, due to being behind a bridge. Reduce the CMB to
1500          * the reported size of the BAR
1501          */
1502         if (size > bar_size - offset)
1503                 size = bar_size - offset;
1504
1505         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1506         cmb = ioremap_wc(dma_addr, size);
1507         if (!cmb)
1508                 return NULL;
1509
1510         dev->cmb_dma_addr = dma_addr;
1511         dev->cmb_size = size;
1512         return cmb;
1513 }
1514
1515 static inline void nvme_release_cmb(struct nvme_dev *dev)
1516 {
1517         if (dev->cmb) {
1518                 iounmap(dev->cmb);
1519                 dev->cmb = NULL;
1520                 if (dev->cmbsz) {
1521                         sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1522                                                      &dev_attr_cmb.attr, NULL);
1523                         dev->cmbsz = 0;
1524                 }
1525         }
1526 }
1527
1528 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1529 {
1530         size_t len = dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs);
1531         struct nvme_command c;
1532         u64 dma_addr;
1533         int ret;
1534
1535         dma_addr = dma_map_single(dev->dev, dev->host_mem_descs, len,
1536                         DMA_TO_DEVICE);
1537         if (dma_mapping_error(dev->dev, dma_addr))
1538                 return -ENOMEM;
1539
1540         memset(&c, 0, sizeof(c));
1541         c.features.opcode       = nvme_admin_set_features;
1542         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1543         c.features.dword11      = cpu_to_le32(bits);
1544         c.features.dword12      = cpu_to_le32(dev->host_mem_size >>
1545                                               ilog2(dev->ctrl.page_size));
1546         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1547         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1548         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1549
1550         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1551         if (ret) {
1552                 dev_warn(dev->ctrl.device,
1553                          "failed to set host mem (err %d, flags %#x).\n",
1554                          ret, bits);
1555         }
1556         dma_unmap_single(dev->dev, dma_addr, len, DMA_TO_DEVICE);
1557         return ret;
1558 }
1559
1560 static void nvme_free_host_mem(struct nvme_dev *dev)
1561 {
1562         int i;
1563
1564         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1565                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1566                 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1567
1568                 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1569                                 le64_to_cpu(desc->addr));
1570         }
1571
1572         kfree(dev->host_mem_desc_bufs);
1573         dev->host_mem_desc_bufs = NULL;
1574         kfree(dev->host_mem_descs);
1575         dev->host_mem_descs = NULL;
1576 }
1577
1578 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1579 {
1580         struct nvme_host_mem_buf_desc *descs;
1581         u32 chunk_size, max_entries, i = 0;
1582         void **bufs;
1583         u64 size, tmp;
1584
1585         /* start big and work our way down */
1586         chunk_size = min(preferred, (u64)PAGE_SIZE << MAX_ORDER);
1587 retry:
1588         tmp = (preferred + chunk_size - 1);
1589         do_div(tmp, chunk_size);
1590         max_entries = tmp;
1591         descs = kcalloc(max_entries, sizeof(*descs), GFP_KERNEL);
1592         if (!descs)
1593                 goto out;
1594
1595         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1596         if (!bufs)
1597                 goto out_free_descs;
1598
1599         for (size = 0; size < preferred; size += chunk_size) {
1600                 u32 len = min_t(u64, chunk_size, preferred - size);
1601                 dma_addr_t dma_addr;
1602
1603                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1604                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1605                 if (!bufs[i])
1606                         break;
1607
1608                 descs[i].addr = cpu_to_le64(dma_addr);
1609                 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1610                 i++;
1611         }
1612
1613         if (!size || (min && size < min)) {
1614                 dev_warn(dev->ctrl.device,
1615                         "failed to allocate host memory buffer.\n");
1616                 goto out_free_bufs;
1617         }
1618
1619         dev_info(dev->ctrl.device,
1620                 "allocated %lld MiB host memory buffer.\n",
1621                 size >> ilog2(SZ_1M));
1622         dev->nr_host_mem_descs = i;
1623         dev->host_mem_size = size;
1624         dev->host_mem_descs = descs;
1625         dev->host_mem_desc_bufs = bufs;
1626         return 0;
1627
1628 out_free_bufs:
1629         while (--i >= 0) {
1630                 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1631
1632                 dma_free_coherent(dev->dev, size, bufs[i],
1633                                 le64_to_cpu(descs[i].addr));
1634         }
1635
1636         kfree(bufs);
1637 out_free_descs:
1638         kfree(descs);
1639 out:
1640         /* try a smaller chunk size if we failed early */
1641         if (chunk_size >= PAGE_SIZE * 2 && (i == 0 || size < min)) {
1642                 chunk_size /= 2;
1643                 goto retry;
1644         }
1645         dev->host_mem_descs = NULL;
1646         return -ENOMEM;
1647 }
1648
1649 static void nvme_setup_host_mem(struct nvme_dev *dev)
1650 {
1651         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1652         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1653         u64 min = (u64)dev->ctrl.hmmin * 4096;
1654         u32 enable_bits = NVME_HOST_MEM_ENABLE;
1655
1656         preferred = min(preferred, max);
1657         if (min > max) {
1658                 dev_warn(dev->ctrl.device,
1659                         "min host memory (%lld MiB) above limit (%d MiB).\n",
1660                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
1661                 nvme_free_host_mem(dev);
1662                 return;
1663         }
1664
1665         /*
1666          * If we already have a buffer allocated check if we can reuse it.
1667          */
1668         if (dev->host_mem_descs) {
1669                 if (dev->host_mem_size >= min)
1670                         enable_bits |= NVME_HOST_MEM_RETURN;
1671                 else
1672                         nvme_free_host_mem(dev);
1673         }
1674
1675         if (!dev->host_mem_descs) {
1676                 if (nvme_alloc_host_mem(dev, min, preferred))
1677                         return;
1678         }
1679
1680         if (nvme_set_host_mem(dev, enable_bits))
1681                 nvme_free_host_mem(dev);
1682 }
1683
1684 static int nvme_setup_io_queues(struct nvme_dev *dev)
1685 {
1686         struct nvme_queue *adminq = dev->queues[0];
1687         struct pci_dev *pdev = to_pci_dev(dev->dev);
1688         int result, nr_io_queues;
1689         unsigned long size;
1690
1691         nr_io_queues = num_online_cpus();
1692         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1693         if (result < 0)
1694                 return result;
1695
1696         if (nr_io_queues == 0)
1697                 return 0;
1698
1699         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1700                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1701                                 sizeof(struct nvme_command));
1702                 if (result > 0)
1703                         dev->q_depth = result;
1704                 else
1705                         nvme_release_cmb(dev);
1706         }
1707
1708         do {
1709                 size = db_bar_size(dev, nr_io_queues);
1710                 result = nvme_remap_bar(dev, size);
1711                 if (!result)
1712                         break;
1713                 if (!--nr_io_queues)
1714                         return -ENOMEM;
1715         } while (1);
1716         adminq->q_db = dev->dbs;
1717
1718         /* Deregister the admin queue's interrupt */
1719         pci_free_irq(pdev, 0, adminq);
1720
1721         /*
1722          * If we enable msix early due to not intx, disable it again before
1723          * setting up the full range we need.
1724          */
1725         pci_free_irq_vectors(pdev);
1726         nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1727                         PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1728         if (nr_io_queues <= 0)
1729                 return -EIO;
1730         dev->max_qid = nr_io_queues;
1731
1732         /*
1733          * Should investigate if there's a performance win from allocating
1734          * more queues than interrupt vectors; it might allow the submission
1735          * path to scale better, even if the receive path is limited by the
1736          * number of interrupts.
1737          */
1738
1739         result = queue_request_irq(adminq);
1740         if (result) {
1741                 adminq->cq_vector = -1;
1742                 return result;
1743         }
1744         return nvme_create_io_queues(dev);
1745 }
1746
1747 static void nvme_del_queue_end(struct request *req, blk_status_t error)
1748 {
1749         struct nvme_queue *nvmeq = req->end_io_data;
1750
1751         blk_mq_free_request(req);
1752         complete(&nvmeq->dev->ioq_wait);
1753 }
1754
1755 static void nvme_del_cq_end(struct request *req, blk_status_t error)
1756 {
1757         struct nvme_queue *nvmeq = req->end_io_data;
1758
1759         if (!error) {
1760                 unsigned long flags;
1761
1762                 /*
1763                  * We might be called with the AQ q_lock held
1764                  * and the I/O queue q_lock should always
1765                  * nest inside the AQ one.
1766                  */
1767                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1768                                         SINGLE_DEPTH_NESTING);
1769                 nvme_process_cq(nvmeq);
1770                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1771         }
1772
1773         nvme_del_queue_end(req, error);
1774 }
1775
1776 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1777 {
1778         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1779         struct request *req;
1780         struct nvme_command cmd;
1781
1782         memset(&cmd, 0, sizeof(cmd));
1783         cmd.delete_queue.opcode = opcode;
1784         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1785
1786         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1787         if (IS_ERR(req))
1788                 return PTR_ERR(req);
1789
1790         req->timeout = ADMIN_TIMEOUT;
1791         req->end_io_data = nvmeq;
1792
1793         blk_execute_rq_nowait(q, NULL, req, false,
1794                         opcode == nvme_admin_delete_cq ?
1795                                 nvme_del_cq_end : nvme_del_queue_end);
1796         return 0;
1797 }
1798
1799 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1800 {
1801         int pass;
1802         unsigned long timeout;
1803         u8 opcode = nvme_admin_delete_sq;
1804
1805         for (pass = 0; pass < 2; pass++) {
1806                 int sent = 0, i = queues;
1807
1808                 reinit_completion(&dev->ioq_wait);
1809  retry:
1810                 timeout = ADMIN_TIMEOUT;
1811                 for (; i > 0; i--, sent++)
1812                         if (nvme_delete_queue(dev->queues[i], opcode))
1813                                 break;
1814
1815                 while (sent--) {
1816                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1817                         if (timeout == 0)
1818                                 return;
1819                         if (i)
1820                                 goto retry;
1821                 }
1822                 opcode = nvme_admin_delete_cq;
1823         }
1824 }
1825
1826 /*
1827  * Return: error value if an error occurred setting up the queues or calling
1828  * Identify Device.  0 if these succeeded, even if adding some of the
1829  * namespaces failed.  At the moment, these failures are silent.  TBD which
1830  * failures should be reported.
1831  */
1832 static int nvme_dev_add(struct nvme_dev *dev)
1833 {
1834         if (!dev->ctrl.tagset) {
1835                 dev->tagset.ops = &nvme_mq_ops;
1836                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1837                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1838                 dev->tagset.numa_node = dev_to_node(dev->dev);
1839                 dev->tagset.queue_depth =
1840                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1841                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1842                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1843                 dev->tagset.driver_data = dev;
1844
1845                 if (blk_mq_alloc_tag_set(&dev->tagset))
1846                         return 0;
1847                 dev->ctrl.tagset = &dev->tagset;
1848
1849                 nvme_dbbuf_set(dev);
1850         } else {
1851                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1852
1853                 /* Free previously allocated queues that are no longer usable */
1854                 nvme_free_queues(dev, dev->online_queues);
1855         }
1856
1857         return 0;
1858 }
1859
1860 static int nvme_pci_enable(struct nvme_dev *dev)
1861 {
1862         u64 cap;
1863         int result = -ENOMEM;
1864         struct pci_dev *pdev = to_pci_dev(dev->dev);
1865
1866         if (pci_enable_device_mem(pdev))
1867                 return result;
1868
1869         pci_set_master(pdev);
1870
1871         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1872             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1873                 goto disable;
1874
1875         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1876                 result = -ENODEV;
1877                 goto disable;
1878         }
1879
1880         /*
1881          * Some devices and/or platforms don't advertise or work with INTx
1882          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1883          * adjust this later.
1884          */
1885         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1886         if (result < 0)
1887                 return result;
1888
1889         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1890
1891         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1892         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1893         dev->dbs = dev->bar + 4096;
1894
1895         /*
1896          * Temporary fix for the Apple controller found in the MacBook8,1 and
1897          * some MacBook7,1 to avoid controller resets and data loss.
1898          */
1899         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1900                 dev->q_depth = 2;
1901                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
1902                         "set queue depth=%u to work around controller resets\n",
1903                         dev->q_depth);
1904         }
1905
1906         /*
1907          * CMBs can currently only exist on >=1.2 PCIe devices. We only
1908          * populate sysfs if a CMB is implemented. Note that we add the
1909          * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1910          * it on exit. Since nvme_dev_attrs_group has no name we can pass
1911          * NULL as final argument to sysfs_add_file_to_group.
1912          */
1913
1914         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1915                 dev->cmb = nvme_map_cmb(dev);
1916
1917                 if (dev->cmbsz) {
1918                         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1919                                                     &dev_attr_cmb.attr, NULL))
1920                                 dev_warn(dev->ctrl.device,
1921                                          "failed to add sysfs attribute for CMB\n");
1922                 }
1923         }
1924
1925         pci_enable_pcie_error_reporting(pdev);
1926         pci_save_state(pdev);
1927         return 0;
1928
1929  disable:
1930         pci_disable_device(pdev);
1931         return result;
1932 }
1933
1934 static void nvme_dev_unmap(struct nvme_dev *dev)
1935 {
1936         if (dev->bar)
1937                 iounmap(dev->bar);
1938         pci_release_mem_regions(to_pci_dev(dev->dev));
1939 }
1940
1941 static void nvme_pci_disable(struct nvme_dev *dev)
1942 {
1943         struct pci_dev *pdev = to_pci_dev(dev->dev);
1944
1945         nvme_release_cmb(dev);
1946         pci_free_irq_vectors(pdev);
1947
1948         if (pci_is_enabled(pdev)) {
1949                 pci_disable_pcie_error_reporting(pdev);
1950                 pci_disable_device(pdev);
1951         }
1952 }
1953
1954 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1955 {
1956         int i, queues;
1957         bool dead = true;
1958         struct pci_dev *pdev = to_pci_dev(dev->dev);
1959
1960         mutex_lock(&dev->shutdown_lock);
1961         if (pci_is_enabled(pdev)) {
1962                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1963
1964                 if (dev->ctrl.state == NVME_CTRL_LIVE)
1965                         nvme_start_freeze(&dev->ctrl);
1966                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
1967                         pdev->error_state  != pci_channel_io_normal);
1968         }
1969
1970         /*
1971          * Give the controller a chance to complete all entered requests if
1972          * doing a safe shutdown.
1973          */
1974         if (!dead) {
1975                 if (shutdown)
1976                         nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
1977
1978                 /*
1979                  * If the controller is still alive tell it to stop using the
1980                  * host memory buffer.  In theory the shutdown / reset should
1981                  * make sure that it doesn't access the host memoery anymore,
1982                  * but I'd rather be safe than sorry..
1983                  */
1984                 if (dev->host_mem_descs)
1985                         nvme_set_host_mem(dev, 0);
1986
1987         }
1988         nvme_stop_queues(&dev->ctrl);
1989
1990         queues = dev->online_queues - 1;
1991         for (i = dev->queue_count - 1; i > 0; i--)
1992                 nvme_suspend_queue(dev->queues[i]);
1993
1994         if (dead) {
1995                 /* A device might become IO incapable very soon during
1996                  * probe, before the admin queue is configured. Thus,
1997                  * queue_count can be 0 here.
1998                  */
1999                 if (dev->queue_count)
2000                         nvme_suspend_queue(dev->queues[0]);
2001         } else {
2002                 nvme_disable_io_queues(dev, queues);
2003                 nvme_disable_admin_queue(dev, shutdown);
2004         }
2005         nvme_pci_disable(dev);
2006
2007         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2008         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2009
2010         /*
2011          * The driver will not be starting up queues again if shutting down so
2012          * must flush all entered requests to their failed completion to avoid
2013          * deadlocking blk-mq hot-cpu notifier.
2014          */
2015         if (shutdown)
2016                 nvme_start_queues(&dev->ctrl);
2017         mutex_unlock(&dev->shutdown_lock);
2018 }
2019
2020 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2021 {
2022         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2023                                                 PAGE_SIZE, PAGE_SIZE, 0);
2024         if (!dev->prp_page_pool)
2025                 return -ENOMEM;
2026
2027         /* Optimisation for I/Os between 4k and 128k */
2028         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2029                                                 256, 256, 0);
2030         if (!dev->prp_small_pool) {
2031                 dma_pool_destroy(dev->prp_page_pool);
2032                 return -ENOMEM;
2033         }
2034         return 0;
2035 }
2036
2037 static void nvme_release_prp_pools(struct nvme_dev *dev)
2038 {
2039         dma_pool_destroy(dev->prp_page_pool);
2040         dma_pool_destroy(dev->prp_small_pool);
2041 }
2042
2043 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2044 {
2045         struct nvme_dev *dev = to_nvme_dev(ctrl);
2046
2047         nvme_dbbuf_dma_free(dev);
2048         put_device(dev->dev);
2049         if (dev->tagset.tags)
2050                 blk_mq_free_tag_set(&dev->tagset);
2051         if (dev->ctrl.admin_q)
2052                 blk_put_queue(dev->ctrl.admin_q);
2053         kfree(dev->queues);
2054         free_opal_dev(dev->ctrl.opal_dev);
2055         kfree(dev);
2056 }
2057
2058 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2059 {
2060         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2061
2062         kref_get(&dev->ctrl.kref);
2063         nvme_dev_disable(dev, false);
2064         if (!schedule_work(&dev->remove_work))
2065                 nvme_put_ctrl(&dev->ctrl);
2066 }
2067
2068 static void nvme_reset_work(struct work_struct *work)
2069 {
2070         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2071         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2072         int result = -ENODEV;
2073
2074         if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2075                 goto out;
2076
2077         /*
2078          * If we're called to reset a live controller first shut it down before
2079          * moving on.
2080          */
2081         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2082                 nvme_dev_disable(dev, false);
2083
2084         result = nvme_pci_enable(dev);
2085         if (result)
2086                 goto out;
2087
2088         result = nvme_configure_admin_queue(dev);
2089         if (result)
2090                 goto out;
2091
2092         nvme_init_queue(dev->queues[0], 0);
2093         result = nvme_alloc_admin_tags(dev);
2094         if (result)
2095                 goto out;
2096
2097         result = nvme_init_identify(&dev->ctrl);
2098         if (result)
2099                 goto out;
2100
2101         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2102                 if (!dev->ctrl.opal_dev)
2103                         dev->ctrl.opal_dev =
2104                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2105                 else if (was_suspend)
2106                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2107         } else {
2108                 free_opal_dev(dev->ctrl.opal_dev);
2109                 dev->ctrl.opal_dev = NULL;
2110         }
2111
2112         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2113                 result = nvme_dbbuf_dma_alloc(dev);
2114                 if (result)
2115                         dev_warn(dev->dev,
2116                                  "unable to allocate dma for dbbuf\n");
2117         }
2118
2119         if (dev->ctrl.hmpre)
2120                 nvme_setup_host_mem(dev);
2121
2122         result = nvme_setup_io_queues(dev);
2123         if (result)
2124                 goto out;
2125
2126         /*
2127          * A controller that can not execute IO typically requires user
2128          * intervention to correct. For such degraded controllers, the driver
2129          * should not submit commands the user did not request, so skip
2130          * registering for asynchronous event notification on this condition.
2131          */
2132         if (dev->online_queues > 1)
2133                 nvme_queue_async_events(&dev->ctrl);
2134
2135         /*
2136          * Keep the controller around but remove all namespaces if we don't have
2137          * any working I/O queue.
2138          */
2139         if (dev->online_queues < 2) {
2140                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2141                 nvme_kill_queues(&dev->ctrl);
2142                 nvme_remove_namespaces(&dev->ctrl);
2143         } else {
2144                 nvme_start_queues(&dev->ctrl);
2145                 nvme_wait_freeze(&dev->ctrl);
2146                 nvme_dev_add(dev);
2147                 nvme_unfreeze(&dev->ctrl);
2148         }
2149
2150         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2151                 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
2152                 goto out;
2153         }
2154
2155         if (dev->online_queues > 1)
2156                 nvme_queue_scan(&dev->ctrl);
2157         return;
2158
2159  out:
2160         nvme_remove_dead_ctrl(dev, result);
2161 }
2162
2163 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2164 {
2165         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2166         struct pci_dev *pdev = to_pci_dev(dev->dev);
2167
2168         nvme_kill_queues(&dev->ctrl);
2169         if (pci_get_drvdata(pdev))
2170                 device_release_driver(&pdev->dev);
2171         nvme_put_ctrl(&dev->ctrl);
2172 }
2173
2174 static int nvme_reset(struct nvme_dev *dev)
2175 {
2176         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
2177                 return -ENODEV;
2178         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
2179                 return -EBUSY;
2180         if (!queue_work(nvme_wq, &dev->reset_work))
2181                 return -EBUSY;
2182         return 0;
2183 }
2184
2185 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2186 {
2187         *val = readl(to_nvme_dev(ctrl)->bar + off);
2188         return 0;
2189 }
2190
2191 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2192 {
2193         writel(val, to_nvme_dev(ctrl)->bar + off);
2194         return 0;
2195 }
2196
2197 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2198 {
2199         *val = readq(to_nvme_dev(ctrl)->bar + off);
2200         return 0;
2201 }
2202
2203 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
2204 {
2205         struct nvme_dev *dev = to_nvme_dev(ctrl);
2206         int ret = nvme_reset(dev);
2207
2208         if (!ret)
2209                 flush_work(&dev->reset_work);
2210         return ret;
2211 }
2212
2213 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2214         .name                   = "pcie",
2215         .module                 = THIS_MODULE,
2216         .flags                  = NVME_F_METADATA_SUPPORTED,
2217         .reg_read32             = nvme_pci_reg_read32,
2218         .reg_write32            = nvme_pci_reg_write32,
2219         .reg_read64             = nvme_pci_reg_read64,
2220         .reset_ctrl             = nvme_pci_reset_ctrl,
2221         .free_ctrl              = nvme_pci_free_ctrl,
2222         .submit_async_event     = nvme_pci_submit_async_event,
2223 };
2224
2225 static int nvme_dev_map(struct nvme_dev *dev)
2226 {
2227         struct pci_dev *pdev = to_pci_dev(dev->dev);
2228
2229         if (pci_request_mem_regions(pdev, "nvme"))
2230                 return -ENODEV;
2231
2232         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2233                 goto release;
2234
2235         return 0;
2236   release:
2237         pci_release_mem_regions(pdev);
2238         return -ENODEV;
2239 }
2240
2241 static unsigned long check_dell_samsung_bug(struct pci_dev *pdev)
2242 {
2243         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2244                 /*
2245                  * Several Samsung devices seem to drop off the PCIe bus
2246                  * randomly when APST is on and uses the deepest sleep state.
2247                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2248                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2249                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2250                  * laptops.
2251                  */
2252                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2253                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2254                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2255                         return NVME_QUIRK_NO_DEEPEST_PS;
2256         }
2257
2258         return 0;
2259 }
2260
2261 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2262 {
2263         int node, result = -ENOMEM;
2264         struct nvme_dev *dev;
2265         unsigned long quirks = id->driver_data;
2266
2267         node = dev_to_node(&pdev->dev);
2268         if (node == NUMA_NO_NODE)
2269                 set_dev_node(&pdev->dev, first_memory_node);
2270
2271         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2272         if (!dev)
2273                 return -ENOMEM;
2274         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2275                                                         GFP_KERNEL, node);
2276         if (!dev->queues)
2277                 goto free;
2278
2279         dev->dev = get_device(&pdev->dev);
2280         pci_set_drvdata(pdev, dev);
2281
2282         result = nvme_dev_map(dev);
2283         if (result)
2284                 goto free;
2285
2286         INIT_WORK(&dev->reset_work, nvme_reset_work);
2287         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2288         mutex_init(&dev->shutdown_lock);
2289         init_completion(&dev->ioq_wait);
2290
2291         result = nvme_setup_prp_pools(dev);
2292         if (result)
2293                 goto put_pci;
2294
2295         quirks |= check_dell_samsung_bug(pdev);
2296
2297         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2298                         quirks);
2299         if (result)
2300                 goto release_pools;
2301
2302         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING);
2303         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2304
2305         queue_work(nvme_wq, &dev->reset_work);
2306         return 0;
2307
2308  release_pools:
2309         nvme_release_prp_pools(dev);
2310  put_pci:
2311         put_device(dev->dev);
2312         nvme_dev_unmap(dev);
2313  free:
2314         kfree(dev->queues);
2315         kfree(dev);
2316         return result;
2317 }
2318
2319 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2320 {
2321         struct nvme_dev *dev = pci_get_drvdata(pdev);
2322
2323         if (prepare)
2324                 nvme_dev_disable(dev, false);
2325         else
2326                 nvme_reset(dev);
2327 }
2328
2329 static void nvme_shutdown(struct pci_dev *pdev)
2330 {
2331         struct nvme_dev *dev = pci_get_drvdata(pdev);
2332         nvme_dev_disable(dev, true);
2333 }
2334
2335 /*
2336  * The driver's remove may be called on a device in a partially initialized
2337  * state. This function must not have any dependencies on the device state in
2338  * order to proceed.
2339  */
2340 static void nvme_remove(struct pci_dev *pdev)
2341 {
2342         struct nvme_dev *dev = pci_get_drvdata(pdev);
2343
2344         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2345
2346         cancel_work_sync(&dev->reset_work);
2347         pci_set_drvdata(pdev, NULL);
2348
2349         if (!pci_device_is_present(pdev)) {
2350                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2351                 nvme_dev_disable(dev, false);
2352         }
2353
2354         flush_work(&dev->reset_work);
2355         nvme_uninit_ctrl(&dev->ctrl);
2356         nvme_dev_disable(dev, true);
2357         nvme_free_host_mem(dev);
2358         nvme_dev_remove_admin(dev);
2359         nvme_free_queues(dev, 0);
2360         nvme_release_prp_pools(dev);
2361         nvme_dev_unmap(dev);
2362         nvme_put_ctrl(&dev->ctrl);
2363 }
2364
2365 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2366 {
2367         int ret = 0;
2368
2369         if (numvfs == 0) {
2370                 if (pci_vfs_assigned(pdev)) {
2371                         dev_warn(&pdev->dev,
2372                                 "Cannot disable SR-IOV VFs while assigned\n");
2373                         return -EPERM;
2374                 }
2375                 pci_disable_sriov(pdev);
2376                 return 0;
2377         }
2378
2379         ret = pci_enable_sriov(pdev, numvfs);
2380         return ret ? ret : numvfs;
2381 }
2382
2383 #ifdef CONFIG_PM_SLEEP
2384 static int nvme_suspend(struct device *dev)
2385 {
2386         struct pci_dev *pdev = to_pci_dev(dev);
2387         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2388
2389         nvme_dev_disable(ndev, true);
2390         return 0;
2391 }
2392
2393 static int nvme_resume(struct device *dev)
2394 {
2395         struct pci_dev *pdev = to_pci_dev(dev);
2396         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2397
2398         nvme_reset(ndev);
2399         return 0;
2400 }
2401 #endif
2402
2403 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2404
2405 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2406                                                 pci_channel_state_t state)
2407 {
2408         struct nvme_dev *dev = pci_get_drvdata(pdev);
2409
2410         /*
2411          * A frozen channel requires a reset. When detected, this method will
2412          * shutdown the controller to quiesce. The controller will be restarted
2413          * after the slot reset through driver's slot_reset callback.
2414          */
2415         switch (state) {
2416         case pci_channel_io_normal:
2417                 return PCI_ERS_RESULT_CAN_RECOVER;
2418         case pci_channel_io_frozen:
2419                 dev_warn(dev->ctrl.device,
2420                         "frozen state error detected, reset controller\n");
2421                 nvme_dev_disable(dev, false);
2422                 return PCI_ERS_RESULT_NEED_RESET;
2423         case pci_channel_io_perm_failure:
2424                 dev_warn(dev->ctrl.device,
2425                         "failure state error detected, request disconnect\n");
2426                 return PCI_ERS_RESULT_DISCONNECT;
2427         }
2428         return PCI_ERS_RESULT_NEED_RESET;
2429 }
2430
2431 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2432 {
2433         struct nvme_dev *dev = pci_get_drvdata(pdev);
2434
2435         dev_info(dev->ctrl.device, "restart after slot reset\n");
2436         pci_restore_state(pdev);
2437         nvme_reset(dev);
2438         return PCI_ERS_RESULT_RECOVERED;
2439 }
2440
2441 static void nvme_error_resume(struct pci_dev *pdev)
2442 {
2443         pci_cleanup_aer_uncorrect_error_status(pdev);
2444 }
2445
2446 static const struct pci_error_handlers nvme_err_handler = {
2447         .error_detected = nvme_error_detected,
2448         .slot_reset     = nvme_slot_reset,
2449         .resume         = nvme_error_resume,
2450         .reset_notify   = nvme_reset_notify,
2451 };
2452
2453 static const struct pci_device_id nvme_id_table[] = {
2454         { PCI_VDEVICE(INTEL, 0x0953),
2455                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2456                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2457         { PCI_VDEVICE(INTEL, 0x0a53),
2458                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2459                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2460         { PCI_VDEVICE(INTEL, 0x0a54),
2461                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2462                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2463         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
2464                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
2465         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2466                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2467         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
2468                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2469         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
2470                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2471         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2472         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2473         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2474         { 0, }
2475 };
2476 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2477
2478 static struct pci_driver nvme_driver = {
2479         .name           = "nvme",
2480         .id_table       = nvme_id_table,
2481         .probe          = nvme_probe,
2482         .remove         = nvme_remove,
2483         .shutdown       = nvme_shutdown,
2484         .driver         = {
2485                 .pm     = &nvme_dev_pm_ops,
2486         },
2487         .sriov_configure = nvme_pci_sriov_configure,
2488         .err_handler    = &nvme_err_handler,
2489 };
2490
2491 static int __init nvme_init(void)
2492 {
2493         return pci_register_driver(&nvme_driver);
2494 }
2495
2496 static void __exit nvme_exit(void)
2497 {
2498         pci_unregister_driver(&nvme_driver);
2499         _nvme_check_size();
2500 }
2501
2502 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2503 MODULE_LICENSE("GPL");
2504 MODULE_VERSION("1.0");
2505 module_init(nvme_init);
2506 module_exit(nvme_exit);