drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/blk-mq-pci.h>
  20 #include <linux/dmi.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/mm.h>
  25 #include <linux/module.h>
  26 #include <linux/mutex.h>
  27 #include <linux/pci.h>
  28 #include <linux/poison.h>
  29 #include <linux/t10-pi.h>
  30 #include <linux/timer.h>
  31 #include <linux/types.h>
  32 #include <linux/io-64-nonatomic-lo-hi.h>
  33 #include <asm/unaligned.h>
  34 #include <linux/sed-opal.h>
  35
  36 #include "nvme.h"
  37
  38 #define NVME_Q_DEPTH            1024
  39 #define NVME_AQ_DEPTH           256
  40 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  41 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  42
  43 /*
  44  * We handle AEN commands ourselves and don't even let the
  45  * block layer know about them.
  46  */
  47 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AERS)
  48
  49 static int use_threaded_interrupts;
  50 module_param(use_threaded_interrupts, int, 0);
  51
  52 static bool use_cmb_sqes = true;
  53 module_param(use_cmb_sqes, bool, 0644);
  54 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  55
  56 static unsigned int max_host_mem_size_mb = 128;
  57 module_param(max_host_mem_size_mb, uint, 0444);
  58 MODULE_PARM_DESC(max_host_mem_size_mb,
  59         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  60
  61 struct nvme_dev;
  62 struct nvme_queue;
  63
  64 static int nvme_reset(struct nvme_dev *dev);
  65 static void nvme_process_cq(struct nvme_queue *nvmeq);
  66 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  67
  68 /*
  69  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  70  */
  71 struct nvme_dev {
  72         struct nvme_queue **queues;
  73         struct blk_mq_tag_set tagset;
  74         struct blk_mq_tag_set admin_tagset;
  75         u32 __iomem *dbs;
  76         struct device *dev;
  77         struct dma_pool *prp_page_pool;
  78         struct dma_pool *prp_small_pool;
  79         unsigned queue_count;
  80         unsigned online_queues;
  81         unsigned max_qid;
  82         int q_depth;
  83         u32 db_stride;
  84         void __iomem *bar;
  85         unsigned long bar_mapped_size;
  86         struct work_struct reset_work;
  87         struct work_struct remove_work;
  88         struct mutex shutdown_lock;
  89         bool subsystem;
  90         void __iomem *cmb;
  91         dma_addr_t cmb_dma_addr;
  92         u64 cmb_size;
  93         u32 cmbsz;
  94         u32 cmbloc;
  95         struct nvme_ctrl ctrl;
  96         struct completion ioq_wait;
  97
  98         /* shadow doorbell buffer support: */
  99         u32 *dbbuf_dbs;
 100         dma_addr_t dbbuf_dbs_dma_addr;
 101         u32 *dbbuf_eis;
 102         dma_addr_t dbbuf_eis_dma_addr;
 103
 104         /* host memory buffer support: */
 105         u64 host_mem_size;
 106         u32 nr_host_mem_descs;
 107         struct nvme_host_mem_buf_desc *host_mem_descs;
 108         void **host_mem_desc_bufs;
 109 };
 110
 111 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 112 {
 113         return qid * 2 * stride;
 114 }
 115
 116 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 117 {
 118         return (qid * 2 + 1) * stride;
 119 }
 120
 121 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 122 {
 123         return container_of(ctrl, struct nvme_dev, ctrl);
 124 }
 125
 126 /*
 127  * An NVM Express queue.  Each device has at least two (one for admin
 128  * commands and one for I/O commands).
 129  */
 130 struct nvme_queue {
 131         struct device *q_dmadev;
 132         struct nvme_dev *dev;
 133         spinlock_t q_lock;
 134         struct nvme_command *sq_cmds;
 135         struct nvme_command __iomem *sq_cmds_io;
 136         volatile struct nvme_completion *cqes;
 137         struct blk_mq_tags **tags;
 138         dma_addr_t sq_dma_addr;
 139         dma_addr_t cq_dma_addr;
 140         u32 __iomem *q_db;
 141         u16 q_depth;
 142         s16 cq_vector;
 143         u16 sq_tail;
 144         u16 cq_head;
 145         u16 qid;
 146         u8 cq_phase;
 147         u8 cqe_seen;
 148         u32 *dbbuf_sq_db;
 149         u32 *dbbuf_cq_db;
 150         u32 *dbbuf_sq_ei;
 151         u32 *dbbuf_cq_ei;
 152 };
 153
 154 /*
 155  * The nvme_iod describes the data in an I/O, including the list of PRP
 156  * entries.  You can't see it in this data structure because C doesn't let
 157  * me express that.  Use nvme_init_iod to ensure there's enough space
 158  * allocated to store the PRP list.
 159  */
 160 struct nvme_iod {
 161         struct nvme_request req;
 162         struct nvme_queue *nvmeq;
 163         int aborted;
 164         int npages;             /* In the PRP list. 0 means small pool in use */
 165         int nents;              /* Used in scatterlist */
 166         int length;             /* Of data, in bytes */
 167         dma_addr_t first_dma;
 168         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 169         struct scatterlist *sg;
 170         struct scatterlist inline_sg[0];
 171 };
 172
 173 /*
 174  * Check we didin't inadvertently grow the command struct
 175  */
 176 static inline void _nvme_check_size(void)
 177 {
 178         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 179         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 180         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 181         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 182         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 183         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 184         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 185         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 186         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
 187         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
 188         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 189         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 190         BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
 191 }
 192
 193 static inline unsigned int nvme_dbbuf_size(u32 stride)
 194 {
 195         return ((num_possible_cpus() + 1) * 8 * stride);
 196 }
 197
 198 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 199 {
 200         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
 201
 202         if (dev->dbbuf_dbs)
 203                 return 0;
 204
 205         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 206                                             &dev->dbbuf_dbs_dma_addr,
 207                                             GFP_KERNEL);
 208         if (!dev->dbbuf_dbs)
 209                 return -ENOMEM;
 210         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 211                                             &dev->dbbuf_eis_dma_addr,
 212                                             GFP_KERNEL);
 213         if (!dev->dbbuf_eis) {
 214                 dma_free_coherent(dev->dev, mem_size,
 215                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 216                 dev->dbbuf_dbs = NULL;
 217                 return -ENOMEM;
 218         }
 219
 220         return 0;
 221 }
 222
 223 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 224 {
 225         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
 226
 227         if (dev->dbbuf_dbs) {
 228                 dma_free_coherent(dev->dev, mem_size,
 229                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 230                 dev->dbbuf_dbs = NULL;
 231         }
 232         if (dev->dbbuf_eis) {
 233                 dma_free_coherent(dev->dev, mem_size,
 234                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 235                 dev->dbbuf_eis = NULL;
 236         }
 237 }
 238
 239 static void nvme_dbbuf_init(struct nvme_dev *dev,
 240                             struct nvme_queue *nvmeq, int qid)
 241 {
 242         if (!dev->dbbuf_dbs || !qid)
 243                 return;
 244
 245         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 246         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 247         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 248         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 249 }
 250
 251 static void nvme_dbbuf_set(struct nvme_dev *dev)
 252 {
 253         struct nvme_command c;
 254
 255         if (!dev->dbbuf_dbs)
 256                 return;
 257
 258         memset(&c, 0, sizeof(c));
 259         c.dbbuf.opcode = nvme_admin_dbbuf;
 260         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 261         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 262
 263         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 264                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 265                 /* Free memory and continue on */
 266                 nvme_dbbuf_dma_free(dev);
 267         }
 268 }
 269
 270 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 271 {
 272         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 273 }
 274
 275 /* Update dbbuf and return true if an MMIO is required */
 276 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 277                                               volatile u32 *dbbuf_ei)
 278 {
 279         if (dbbuf_db) {
 280                 u16 old_value;
 281
 282                 /*
 283                  * Ensure that the queue is written before updating
 284                  * the doorbell in memory
 285                  */
 286                 wmb();
 287
 288                 old_value = *dbbuf_db;
 289                 *dbbuf_db = value;
 290
 291                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 292                         return false;
 293         }
 294
 295         return true;
 296 }
 297
 298 /*
 299  * Max size of iod being embedded in the request payload
 300  */
 301 #define NVME_INT_PAGES          2
 302 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 303
 304 /*
 305  * Will slightly overestimate the number of pages needed.  This is OK
 306  * as it only leads to a small amount of wasted memory for the lifetime of
 307  * the I/O.
 308  */
 309 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 310 {
 311         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 312                                       dev->ctrl.page_size);
 313         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 314 }
 315
 316 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 317                 unsigned int size, unsigned int nseg)
 318 {
 319         return sizeof(__le64 *) * nvme_npages(size, dev) +
 320                         sizeof(struct scatterlist) * nseg;
 321 }
 322
 323 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 324 {
 325         return sizeof(struct nvme_iod) +
 326                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 327 }
 328
 329 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 330                                 unsigned int hctx_idx)
 331 {
 332         struct nvme_dev *dev = data;
 333         struct nvme_queue *nvmeq = dev->queues[0];
 334
 335         WARN_ON(hctx_idx != 0);
 336         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 337         WARN_ON(nvmeq->tags);
 338
 339         hctx->driver_data = nvmeq;
 340         nvmeq->tags = &dev->admin_tagset.tags[0];
 341         return 0;
 342 }
 343
 344 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 345 {
 346         struct nvme_queue *nvmeq = hctx->driver_data;
 347
 348         nvmeq->tags = NULL;
 349 }
 350
 351 static int nvme_admin_init_request(struct blk_mq_tag_set *set,
 352                 struct request *req, unsigned int hctx_idx,
 353                 unsigned int numa_node)
 354 {
 355         struct nvme_dev *dev = set->driver_data;
 356         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 357         struct nvme_queue *nvmeq = dev->queues[0];
 358
 359         BUG_ON(!nvmeq);
 360         iod->nvmeq = nvmeq;
 361         return 0;
 362 }
 363
 364 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 365                           unsigned int hctx_idx)
 366 {
 367         struct nvme_dev *dev = data;
 368         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 369
 370         if (!nvmeq->tags)
 371                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 372
 373         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 374         hctx->driver_data = nvmeq;
 375         return 0;
 376 }
 377
 378 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
 379                 unsigned int hctx_idx, unsigned int numa_node)
 380 {
 381         struct nvme_dev *dev = set->driver_data;
 382         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 383         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 384
 385         BUG_ON(!nvmeq);
 386         iod->nvmeq = nvmeq;
 387         return 0;
 388 }
 389
 390 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 391 {
 392         struct nvme_dev *dev = set->driver_data;
 393
 394         return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
 395 }
 396
 397 /**
 398  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 399  * @nvmeq: The queue to use
 400  * @cmd: The command to send
 401  *
 402  * Safe to use from interrupt context
 403  */
 404 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 405                                                 struct nvme_command *cmd)
 406 {
 407         u16 tail = nvmeq->sq_tail;
 408
 409         if (nvmeq->sq_cmds_io)
 410                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 411         else
 412                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 413
 414         if (++tail == nvmeq->q_depth)
 415                 tail = 0;
 416         if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
 417                                               nvmeq->dbbuf_sq_ei))
 418                 writel(tail, nvmeq->q_db);
 419         nvmeq->sq_tail = tail;
 420 }
 421
 422 static __le64 **iod_list(struct request *req)
 423 {
 424         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 425         return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
 426 }
 427
 428 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
 429 {
 430         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 431         int nseg = blk_rq_nr_phys_segments(rq);
 432         unsigned int size = blk_rq_payload_bytes(rq);
 433
 434         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 435                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 436                 if (!iod->sg)
 437                         return BLK_STS_RESOURCE;
 438         } else {
 439                 iod->sg = iod->inline_sg;
 440         }
 441
 442         iod->aborted = 0;
 443         iod->npages = -1;
 444         iod->nents = 0;
 445         iod->length = size;
 446
 447         return BLK_STS_OK;
 448 }
 449
 450 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 451 {
 452         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 453         const int last_prp = dev->ctrl.page_size / 8 - 1;
 454         int i;
 455         __le64 **list = iod_list(req);
 456         dma_addr_t prp_dma = iod->first_dma;
 457
 458         if (iod->npages == 0)
 459                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 460         for (i = 0; i < iod->npages; i++) {
 461                 __le64 *prp_list = list[i];
 462                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 463                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 464                 prp_dma = next_prp_dma;
 465         }
 466
 467         if (iod->sg != iod->inline_sg)
 468                 kfree(iod->sg);
 469 }
 470
 471 #ifdef CONFIG_BLK_DEV_INTEGRITY
 472 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 473 {
 474         if (be32_to_cpu(pi->ref_tag) == v)
 475                 pi->ref_tag = cpu_to_be32(p);
 476 }
 477
 478 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 479 {
 480         if (be32_to_cpu(pi->ref_tag) == p)
 481                 pi->ref_tag = cpu_to_be32(v);
 482 }
 483
 484 /**
 485  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 486  *
 487  * The virtual start sector is the one that was originally submitted by the
 488  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 489  * start sector may be different. Remap protection information to match the
 490  * physical LBA on writes, and back to the original seed on reads.
 491  *
 492  * Type 0 and 3 do not have a ref tag, so no remapping required.
 493  */
 494 static void nvme_dif_remap(struct request *req,
 495                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 496 {
 497         struct nvme_ns *ns = req->rq_disk->private_data;
 498         struct bio_integrity_payload *bip;
 499         struct t10_pi_tuple *pi;
 500         void *p, *pmap;
 501         u32 i, nlb, ts, phys, virt;
 502
 503         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 504                 return;
 505
 506         bip = bio_integrity(req->bio);
 507         if (!bip)
 508                 return;
 509
 510         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 511
 512         p = pmap;
 513         virt = bip_get_seed(bip);
 514         phys = nvme_block_nr(ns, blk_rq_pos(req));
 515         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 516         ts = ns->disk->queue->integrity.tuple_size;
 517
 518         for (i = 0; i < nlb; i++, virt++, phys++) {
 519                 pi = (struct t10_pi_tuple *)p;
 520                 dif_swap(phys, virt, pi);
 521                 p += ts;
 522         }
 523         kunmap_atomic(pmap);
 524 }
 525 #else /* CONFIG_BLK_DEV_INTEGRITY */
 526 static void nvme_dif_remap(struct request *req,
 527                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 528 {
 529 }
 530 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 531 {
 532 }
 533 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 534 {
 535 }
 536 #endif
 537
 538 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req)
 539 {
 540         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 541         struct dma_pool *pool;
 542         int length = blk_rq_payload_bytes(req);
 543         struct scatterlist *sg = iod->sg;
 544         int dma_len = sg_dma_len(sg);
 545         u64 dma_addr = sg_dma_address(sg);
 546         u32 page_size = dev->ctrl.page_size;
 547         int offset = dma_addr & (page_size - 1);
 548         __le64 *prp_list;
 549         __le64 **list = iod_list(req);
 550         dma_addr_t prp_dma;
 551         int nprps, i;
 552
 553         length -= (page_size - offset);
 554         if (length <= 0)
 555                 return true;
 556
 557         dma_len -= (page_size - offset);
 558         if (dma_len) {
 559                 dma_addr += (page_size - offset);
 560         } else {
 561                 sg = sg_next(sg);
 562                 dma_addr = sg_dma_address(sg);
 563                 dma_len = sg_dma_len(sg);
 564         }
 565
 566         if (length <= page_size) {
 567                 iod->first_dma = dma_addr;
 568                 return true;
 569         }
 570
 571         nprps = DIV_ROUND_UP(length, page_size);
 572         if (nprps <= (256 / 8)) {
 573                 pool = dev->prp_small_pool;
 574                 iod->npages = 0;
 575         } else {
 576                 pool = dev->prp_page_pool;
 577                 iod->npages = 1;
 578         }
 579
 580         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 581         if (!prp_list) {
 582                 iod->first_dma = dma_addr;
 583                 iod->npages = -1;
 584                 return false;
 585         }
 586         list[0] = prp_list;
 587         iod->first_dma = prp_dma;
 588         i = 0;
 589         for (;;) {
 590                 if (i == page_size >> 3) {
 591                         __le64 *old_prp_list = prp_list;
 592                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 593                         if (!prp_list)
 594                                 return false;
 595                         list[iod->npages++] = prp_list;
 596                         prp_list[0] = old_prp_list[i - 1];
 597                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 598                         i = 1;
 599                 }
 600                 prp_list[i++] = cpu_to_le64(dma_addr);
 601                 dma_len -= page_size;
 602                 dma_addr += page_size;
 603                 length -= page_size;
 604                 if (length <= 0)
 605                         break;
 606                 if (dma_len > 0)
 607                         continue;
 608                 BUG_ON(dma_len < 0);
 609                 sg = sg_next(sg);
 610                 dma_addr = sg_dma_address(sg);
 611                 dma_len = sg_dma_len(sg);
 612         }
 613
 614         return true;
 615 }
 616
 617 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 618                 struct nvme_command *cmnd)
 619 {
 620         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 621         struct request_queue *q = req->q;
 622         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 623                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 624         blk_status_t ret = BLK_STS_IOERR;
 625
 626         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 627         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 628         if (!iod->nents)
 629                 goto out;
 630
 631         ret = BLK_STS_RESOURCE;
 632         if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
 633                                 DMA_ATTR_NO_WARN))
 634                 goto out;
 635
 636         if (!nvme_setup_prps(dev, req))
 637                 goto out_unmap;
 638
 639         ret = BLK_STS_IOERR;
 640         if (blk_integrity_rq(req)) {
 641                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 642                         goto out_unmap;
 643
 644                 sg_init_table(&iod->meta_sg, 1);
 645                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 646                         goto out_unmap;
 647
 648                 if (rq_data_dir(req))
 649                         nvme_dif_remap(req, nvme_dif_prep);
 650
 651                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 652                         goto out_unmap;
 653         }
 654
 655         cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 656         cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
 657         if (blk_integrity_rq(req))
 658                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 659         return BLK_STS_OK;
 660
 661 out_unmap:
 662         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 663 out:
 664         return ret;
 665 }
 666
 667 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 668 {
 669         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 670         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 671                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 672
 673         if (iod->nents) {
 674                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 675                 if (blk_integrity_rq(req)) {
 676                         if (!rq_data_dir(req))
 677                                 nvme_dif_remap(req, nvme_dif_complete);
 678                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 679                 }
 680         }
 681
 682         nvme_cleanup_cmd(req);
 683         nvme_free_iod(dev, req);
 684 }
 685
 686 /*
 687  * NOTE: ns is NULL when called on the admin queue.
 688  */
 689 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 690                          const struct blk_mq_queue_data *bd)
 691 {
 692         struct nvme_ns *ns = hctx->queue->queuedata;
 693         struct nvme_queue *nvmeq = hctx->driver_data;
 694         struct nvme_dev *dev = nvmeq->dev;
 695         struct request *req = bd->rq;
 696         struct nvme_command cmnd;
 697         blk_status_t ret = BLK_STS_OK;
 698
 699         /*
 700          * If formated with metadata, require the block layer provide a buffer
 701          * unless this namespace is formated such that the metadata can be
 702          * stripped/generated by the controller with PRACT=1.
 703          */
 704         if (ns && ns->ms && !blk_integrity_rq(req)) {
 705                 if (!(ns->pi_type && ns->ms == 8) &&
 706                     !blk_rq_is_passthrough(req))
 707                         return BLK_STS_NOTSUPP;
 708         }
 709
 710         ret = nvme_setup_cmd(ns, req, &cmnd);
 711         if (ret)
 712                 return ret;
 713
 714         ret = nvme_init_iod(req, dev);
 715         if (ret)
 716                 goto out_free_cmd;
 717
 718         if (blk_rq_nr_phys_segments(req)) {
 719                 ret = nvme_map_data(dev, req, &cmnd);
 720                 if (ret)
 721                         goto out_cleanup_iod;
 722         }
 723
 724         blk_mq_start_request(req);
 725
 726         spin_lock_irq(&nvmeq->q_lock);
 727         if (unlikely(nvmeq->cq_vector < 0)) {
 728                 ret = BLK_STS_IOERR;
 729                 spin_unlock_irq(&nvmeq->q_lock);
 730                 goto out_cleanup_iod;
 731         }
 732         __nvme_submit_cmd(nvmeq, &cmnd);
 733         nvme_process_cq(nvmeq);
 734         spin_unlock_irq(&nvmeq->q_lock);
 735         return BLK_STS_OK;
 736 out_cleanup_iod:
 737         nvme_free_iod(dev, req);
 738 out_free_cmd:
 739         nvme_cleanup_cmd(req);
 740         return ret;
 741 }
 742
 743 static void nvme_pci_complete_rq(struct request *req)
 744 {
 745         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 746
 747         nvme_unmap_data(iod->nvmeq->dev, req);
 748         nvme_complete_rq(req);
 749 }
 750
 751 /* We read the CQE phase first to check if the rest of the entry is valid */
 752 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 753                 u16 phase)
 754 {
 755         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 756 }
 757
 758 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 759 {
 760         u16 head, phase;
 761
 762         head = nvmeq->cq_head;
 763         phase = nvmeq->cq_phase;
 764
 765         while (nvme_cqe_valid(nvmeq, head, phase)) {
 766                 struct nvme_completion cqe = nvmeq->cqes[head];
 767                 struct request *req;
 768
 769                 if (++head == nvmeq->q_depth) {
 770                         head = 0;
 771                         phase = !phase;
 772                 }
 773
 774                 if (tag && *tag == cqe.command_id)
 775                         *tag = -1;
 776
 777                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 778                         dev_warn(nvmeq->dev->ctrl.device,
 779                                 "invalid id %d completed on queue %d\n",
 780                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 781                         continue;
 782                 }
 783
 784                 /*
 785                  * AEN requests are special as they don't time out and can
 786                  * survive any kind of queue freeze and often don't respond to
 787                  * aborts.  We don't even bother to allocate a struct request
 788                  * for them but rather special case them here.
 789                  */
 790                 if (unlikely(nvmeq->qid == 0 &&
 791                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 792                         nvme_complete_async_event(&nvmeq->dev->ctrl,
 793                                         cqe.status, &cqe.result);
 794                         continue;
 795                 }
 796
 797                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 798                 nvme_end_request(req, cqe.status, cqe.result);
 799         }
 800
 801         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 802                 return;
 803
 804         if (likely(nvmeq->cq_vector >= 0))
 805                 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
 806                                                       nvmeq->dbbuf_cq_ei))
 807                         writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 808         nvmeq->cq_head = head;
 809         nvmeq->cq_phase = phase;
 810
 811         nvmeq->cqe_seen = 1;
 812 }
 813
 814 static void nvme_process_cq(struct nvme_queue *nvmeq)
 815 {
 816         __nvme_process_cq(nvmeq, NULL);
 817 }
 818
 819 static irqreturn_t nvme_irq(int irq, void *data)
 820 {
 821         irqreturn_t result;
 822         struct nvme_queue *nvmeq = data;
 823         spin_lock(&nvmeq->q_lock);
 824         nvme_process_cq(nvmeq);
 825         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 826         nvmeq->cqe_seen = 0;
 827         spin_unlock(&nvmeq->q_lock);
 828         return result;
 829 }
 830
 831 static irqreturn_t nvme_irq_check(int irq, void *data)
 832 {
 833         struct nvme_queue *nvmeq = data;
 834         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
 835                 return IRQ_WAKE_THREAD;
 836         return IRQ_NONE;
 837 }
 838
 839 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
 840 {
 841         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 842                 spin_lock_irq(&nvmeq->q_lock);
 843                 __nvme_process_cq(nvmeq, &tag);
 844                 spin_unlock_irq(&nvmeq->q_lock);
 845
 846                 if (tag == -1)
 847                         return 1;
 848         }
 849
 850         return 0;
 851 }
 852
 853 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 854 {
 855         struct nvme_queue *nvmeq = hctx->driver_data;
 856
 857         return __nvme_poll(nvmeq, tag);
 858 }
 859
 860 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
 861 {
 862         struct nvme_dev *dev = to_nvme_dev(ctrl);
 863         struct nvme_queue *nvmeq = dev->queues[0];
 864         struct nvme_command c;
 865
 866         memset(&c, 0, sizeof(c));
 867         c.common.opcode = nvme_admin_async_event;
 868         c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
 869
 870         spin_lock_irq(&nvmeq->q_lock);
 871         __nvme_submit_cmd(nvmeq, &c);
 872         spin_unlock_irq(&nvmeq->q_lock);
 873 }
 874
 875 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 876 {
 877         struct nvme_command c;
 878
 879         memset(&c, 0, sizeof(c));
 880         c.delete_queue.opcode = opcode;
 881         c.delete_queue.qid = cpu_to_le16(id);
 882
 883         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 884 }
 885
 886 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 887                                                 struct nvme_queue *nvmeq)
 888 {
 889         struct nvme_command c;
 890         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 891
 892         /*
 893          * Note: we (ab)use the fact the the prp fields survive if no data
 894          * is attached to the request.
 895          */
 896         memset(&c, 0, sizeof(c));
 897         c.create_cq.opcode = nvme_admin_create_cq;
 898         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 899         c.create_cq.cqid = cpu_to_le16(qid);
 900         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 901         c.create_cq.cq_flags = cpu_to_le16(flags);
 902         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 903
 904         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 905 }
 906
 907 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 908                                                 struct nvme_queue *nvmeq)
 909 {
 910         struct nvme_command c;
 911         int flags = NVME_QUEUE_PHYS_CONTIG;
 912
 913         /*
 914          * Note: we (ab)use the fact the the prp fields survive if no data
 915          * is attached to the request.
 916          */
 917         memset(&c, 0, sizeof(c));
 918         c.create_sq.opcode = nvme_admin_create_sq;
 919         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 920         c.create_sq.sqid = cpu_to_le16(qid);
 921         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 922         c.create_sq.sq_flags = cpu_to_le16(flags);
 923         c.create_sq.cqid = cpu_to_le16(qid);
 924
 925         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 926 }
 927
 928 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 929 {
 930         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 931 }
 932
 933 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 934 {
 935         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 936 }
 937
 938 static void abort_endio(struct request *req, blk_status_t error)
 939 {
 940         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 941         struct nvme_queue *nvmeq = iod->nvmeq;
 942
 943         dev_warn(nvmeq->dev->ctrl.device,
 944                  "Abort status: 0x%x", nvme_req(req)->status);
 945         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 946         blk_mq_free_request(req);
 947 }
 948
 949 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
 950 {
 951
 952         /* If true, indicates loss of adapter communication, possibly by a
 953          * NVMe Subsystem reset.
 954          */
 955         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
 956
 957         /* If there is a reset ongoing, we shouldn't reset again. */
 958         if (dev->ctrl.state == NVME_CTRL_RESETTING)
 959                 return false;
 960
 961         /* We shouldn't reset unless the controller is on fatal error state
 962          * _or_ if we lost the communication with it.
 963          */
 964         if (!(csts & NVME_CSTS_CFS) && !nssro)
 965                 return false;
 966
 967         /* If PCI error recovery process is happening, we cannot reset or
 968          * the recovery mechanism will surely fail.
 969          */
 970         if (pci_channel_offline(to_pci_dev(dev->dev)))
 971                 return false;
 972
 973         return true;
 974 }
 975
 976 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
 977 {
 978         /* Read a config register to help see what died. */
 979         u16 pci_status;
 980         int result;
 981
 982         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
 983                                       &pci_status);
 984         if (result == PCIBIOS_SUCCESSFUL)
 985                 dev_warn(dev->ctrl.device,
 986                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
 987                          csts, pci_status);
 988         else
 989                 dev_warn(dev->ctrl.device,
 990                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
 991                          csts, result);
 992 }
 993
 994 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 995 {
 996         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 997         struct nvme_queue *nvmeq = iod->nvmeq;
 998         struct nvme_dev *dev = nvmeq->dev;
 999         struct request *abort_req;
1000         struct nvme_command cmd;
1001         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1002
1003         /*
1004          * Reset immediately if the controller is failed
1005          */
1006         if (nvme_should_reset(dev, csts)) {
1007                 nvme_warn_reset(dev, csts);
1008                 nvme_dev_disable(dev, false);
1009                 nvme_reset(dev);
1010                 return BLK_EH_HANDLED;
1011         }
1012
1013         /*
1014          * Did we miss an interrupt?
1015          */
1016         if (__nvme_poll(nvmeq, req->tag)) {
1017                 dev_warn(dev->ctrl.device,
1018                          "I/O %d QID %d timeout, completion polled\n",
1019                          req->tag, nvmeq->qid);
1020                 return BLK_EH_HANDLED;
1021         }
1022
1023         /*
1024          * Shutdown immediately if controller times out while starting. The
1025          * reset work will see the pci device disabled when it gets the forced
1026          * cancellation error. All outstanding requests are completed on
1027          * shutdown, so we return BLK_EH_HANDLED.
1028          */
1029         if (dev->ctrl.state == NVME_CTRL_RESETTING) {
1030                 dev_warn(dev->ctrl.device,
1031                          "I/O %d QID %d timeout, disable controller\n",
1032                          req->tag, nvmeq->qid);
1033                 nvme_dev_disable(dev, false);
1034                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1035                 return BLK_EH_HANDLED;
1036         }
1037
1038         /*
1039          * Shutdown the controller immediately and schedule a reset if the
1040          * command was already aborted once before and still hasn't been
1041          * returned to the driver, or if this is the admin queue.
1042          */
1043         if (!nvmeq->qid || iod->aborted) {
1044                 dev_warn(dev->ctrl.device,
1045                          "I/O %d QID %d timeout, reset controller\n",
1046                          req->tag, nvmeq->qid);
1047                 nvme_dev_disable(dev, false);
1048                 nvme_reset(dev);
1049
1050                 /*
1051                  * Mark the request as handled, since the inline shutdown
1052                  * forces all outstanding requests to complete.
1053                  */
1054                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1055                 return BLK_EH_HANDLED;
1056         }
1057
1058         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1059                 atomic_inc(&dev->ctrl.abort_limit);
1060                 return BLK_EH_RESET_TIMER;
1061         }
1062         iod->aborted = 1;
1063
1064         memset(&cmd, 0, sizeof(cmd));
1065         cmd.abort.opcode = nvme_admin_abort_cmd;
1066         cmd.abort.cid = req->tag;
1067         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1068
1069         dev_warn(nvmeq->dev->ctrl.device,
1070                 "I/O %d QID %d timeout, aborting\n",
1071                  req->tag, nvmeq->qid);
1072
1073         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1074                         BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1075         if (IS_ERR(abort_req)) {
1076                 atomic_inc(&dev->ctrl.abort_limit);
1077                 return BLK_EH_RESET_TIMER;
1078         }
1079
1080         abort_req->timeout = ADMIN_TIMEOUT;
1081         abort_req->end_io_data = NULL;
1082         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1083
1084         /*
1085          * The aborted req will be completed on receiving the abort req.
1086          * We enable the timer again. If hit twice, it'll cause a device reset,
1087          * as the device then is in a faulty state.
1088          */
1089         return BLK_EH_RESET_TIMER;
1090 }
1091
1092 static void nvme_free_queue(struct nvme_queue *nvmeq)
1093 {
1094         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1095                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1096         if (nvmeq->sq_cmds)
1097                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1098                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1099         kfree(nvmeq);
1100 }
1101
1102 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1103 {
1104         int i;
1105
1106         for (i = dev->queue_count - 1; i >= lowest; i--) {
1107                 struct nvme_queue *nvmeq = dev->queues[i];
1108                 dev->queue_count--;
1109                 dev->queues[i] = NULL;
1110                 nvme_free_queue(nvmeq);
1111         }
1112 }
1113
1114 /**
1115  * nvme_suspend_queue - put queue into suspended state
1116  * @nvmeq - queue to suspend
1117  */
1118 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1119 {
1120         int vector;
1121
1122         spin_lock_irq(&nvmeq->q_lock);
1123         if (nvmeq->cq_vector == -1) {
1124                 spin_unlock_irq(&nvmeq->q_lock);
1125                 return 1;
1126         }
1127         vector = nvmeq->cq_vector;
1128         nvmeq->dev->online_queues--;
1129         nvmeq->cq_vector = -1;
1130         spin_unlock_irq(&nvmeq->q_lock);
1131
1132         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1133                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
1134
1135         pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1136
1137         return 0;
1138 }
1139
1140 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1141 {
1142         struct nvme_queue *nvmeq = dev->queues[0];
1143
1144         if (!nvmeq)
1145                 return;
1146         if (nvme_suspend_queue(nvmeq))
1147                 return;
1148
1149         if (shutdown)
1150                 nvme_shutdown_ctrl(&dev->ctrl);
1151         else
1152                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1153                                                 dev->bar + NVME_REG_CAP));
1154
1155         spin_lock_irq(&nvmeq->q_lock);
1156         nvme_process_cq(nvmeq);
1157         spin_unlock_irq(&nvmeq->q_lock);
1158 }
1159
1160 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1161                                 int entry_size)
1162 {
1163         int q_depth = dev->q_depth;
1164         unsigned q_size_aligned = roundup(q_depth * entry_size,
1165                                           dev->ctrl.page_size);
1166
1167         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1168                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1169                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1170                 q_depth = div_u64(mem_per_q, entry_size);
1171
1172                 /*
1173                  * Ensure the reduced q_depth is above some threshold where it
1174                  * would be better to map queues in system memory with the
1175                  * original depth
1176                  */
1177                 if (q_depth < 64)
1178                         return -ENOMEM;
1179         }
1180
1181         return q_depth;
1182 }
1183
1184 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1185                                 int qid, int depth)
1186 {
1187         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1188                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1189                                                       dev->ctrl.page_size);
1190                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1191                 nvmeq->sq_cmds_io = dev->cmb + offset;
1192         } else {
1193                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1194                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1195                 if (!nvmeq->sq_cmds)
1196                         return -ENOMEM;
1197         }
1198
1199         return 0;
1200 }
1201
1202 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1203                                                         int depth, int node)
1204 {
1205         struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
1206                                                         node);
1207         if (!nvmeq)
1208                 return NULL;
1209
1210         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1211                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1212         if (!nvmeq->cqes)
1213                 goto free_nvmeq;
1214
1215         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1216                 goto free_cqdma;
1217
1218         nvmeq->q_dmadev = dev->dev;
1219         nvmeq->dev = dev;
1220         spin_lock_init(&nvmeq->q_lock);
1221         nvmeq->cq_head = 0;
1222         nvmeq->cq_phase = 1;
1223         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1224         nvmeq->q_depth = depth;
1225         nvmeq->qid = qid;
1226         nvmeq->cq_vector = -1;
1227         dev->queues[qid] = nvmeq;
1228         dev->queue_count++;
1229
1230         return nvmeq;
1231
1232  free_cqdma:
1233         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1234                                                         nvmeq->cq_dma_addr);
1235  free_nvmeq:
1236         kfree(nvmeq);
1237         return NULL;
1238 }
1239
1240 static int queue_request_irq(struct nvme_queue *nvmeq)
1241 {
1242         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1243         int nr = nvmeq->dev->ctrl.instance;
1244
1245         if (use_threaded_interrupts) {
1246                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1247                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1248         } else {
1249                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1250                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1251         }
1252 }
1253
1254 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1255 {
1256         struct nvme_dev *dev = nvmeq->dev;
1257
1258         spin_lock_irq(&nvmeq->q_lock);
1259         nvmeq->sq_tail = 0;
1260         nvmeq->cq_head = 0;
1261         nvmeq->cq_phase = 1;
1262         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1263         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1264         nvme_dbbuf_init(dev, nvmeq, qid);
1265         dev->online_queues++;
1266         spin_unlock_irq(&nvmeq->q_lock);
1267 }
1268
1269 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1270 {
1271         struct nvme_dev *dev = nvmeq->dev;
1272         int result;
1273
1274         nvmeq->cq_vector = qid - 1;
1275         result = adapter_alloc_cq(dev, qid, nvmeq);
1276         if (result < 0)
1277                 return result;
1278
1279         result = adapter_alloc_sq(dev, qid, nvmeq);
1280         if (result < 0)
1281                 goto release_cq;
1282
1283         result = queue_request_irq(nvmeq);
1284         if (result < 0)
1285                 goto release_sq;
1286
1287         nvme_init_queue(nvmeq, qid);
1288         return result;
1289
1290  release_sq:
1291         adapter_delete_sq(dev, qid);
1292  release_cq:
1293         adapter_delete_cq(dev, qid);
1294         return result;
1295 }
1296
1297 static const struct blk_mq_ops nvme_mq_admin_ops = {
1298         .queue_rq       = nvme_queue_rq,
1299         .complete       = nvme_pci_complete_rq,
1300         .init_hctx      = nvme_admin_init_hctx,
1301         .exit_hctx      = nvme_admin_exit_hctx,
1302         .init_request   = nvme_admin_init_request,
1303         .timeout        = nvme_timeout,
1304 };
1305
1306 static const struct blk_mq_ops nvme_mq_ops = {
1307         .queue_rq       = nvme_queue_rq,
1308         .complete       = nvme_pci_complete_rq,
1309         .init_hctx      = nvme_init_hctx,
1310         .init_request   = nvme_init_request,
1311         .map_queues     = nvme_pci_map_queues,
1312         .timeout        = nvme_timeout,
1313         .poll           = nvme_poll,
1314 };
1315
1316 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1317 {
1318         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1319                 /*
1320                  * If the controller was reset during removal, it's possible
1321                  * user requests may be waiting on a stopped queue. Start the
1322                  * queue to flush these to completion.
1323                  */
1324                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1325                 blk_cleanup_queue(dev->ctrl.admin_q);
1326                 blk_mq_free_tag_set(&dev->admin_tagset);
1327         }
1328 }
1329
1330 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1331 {
1332         if (!dev->ctrl.admin_q) {
1333                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1334                 dev->admin_tagset.nr_hw_queues = 1;
1335
1336                 /*
1337                  * Subtract one to leave an empty queue entry for 'Full Queue'
1338                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1339                  */
1340                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1341                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1342                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1343                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1344                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1345                 dev->admin_tagset.driver_data = dev;
1346
1347                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1348                         return -ENOMEM;
1349
1350                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1351                 if (IS_ERR(dev->ctrl.admin_q)) {
1352                         blk_mq_free_tag_set(&dev->admin_tagset);
1353                         return -ENOMEM;
1354                 }
1355                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1356                         nvme_dev_remove_admin(dev);
1357                         dev->ctrl.admin_q = NULL;
1358                         return -ENODEV;
1359                 }
1360         } else
1361                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1362
1363         return 0;
1364 }
1365
1366 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1367 {
1368         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1369 }
1370
1371 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1372 {
1373         struct pci_dev *pdev = to_pci_dev(dev->dev);
1374
1375         if (size <= dev->bar_mapped_size)
1376                 return 0;
1377         if (size > pci_resource_len(pdev, 0))
1378                 return -ENOMEM;
1379         if (dev->bar)
1380                 iounmap(dev->bar);
1381         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1382         if (!dev->bar) {
1383                 dev->bar_mapped_size = 0;
1384                 return -ENOMEM;
1385         }
1386         dev->bar_mapped_size = size;
1387         dev->dbs = dev->bar + NVME_REG_DBS;
1388
1389         return 0;
1390 }
1391
1392 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1393 {
1394         int result;
1395         u32 aqa;
1396         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1397         struct nvme_queue *nvmeq;
1398
1399         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1400         if (result < 0)
1401                 return result;
1402
1403         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1404                                                 NVME_CAP_NSSRC(cap) : 0;
1405
1406         if (dev->subsystem &&
1407             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1408                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1409
1410         result = nvme_disable_ctrl(&dev->ctrl, cap);
1411         if (result < 0)
1412                 return result;
1413
1414         nvmeq = dev->queues[0];
1415         if (!nvmeq) {
1416                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1417                                         dev_to_node(dev->dev));
1418                 if (!nvmeq)
1419                         return -ENOMEM;
1420         }
1421
1422         aqa = nvmeq->q_depth - 1;
1423         aqa |= aqa << 16;
1424
1425         writel(aqa, dev->bar + NVME_REG_AQA);
1426         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1427         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1428
1429         result = nvme_enable_ctrl(&dev->ctrl, cap);
1430         if (result)
1431                 return result;
1432
1433         nvmeq->cq_vector = 0;
1434         result = queue_request_irq(nvmeq);
1435         if (result) {
1436                 nvmeq->cq_vector = -1;
1437                 return result;
1438         }
1439
1440         return result;
1441 }
1442
1443 static int nvme_create_io_queues(struct nvme_dev *dev)
1444 {
1445         unsigned i, max;
1446         int ret = 0;
1447
1448         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1449                 /* vector == qid - 1, match nvme_create_queue */
1450                 if (!nvme_alloc_queue(dev, i, dev->q_depth,
1451                      pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
1452                         ret = -ENOMEM;
1453                         break;
1454                 }
1455         }
1456
1457         max = min(dev->max_qid, dev->queue_count - 1);
1458         for (i = dev->online_queues; i <= max; i++) {
1459                 ret = nvme_create_queue(dev->queues[i], i);
1460                 if (ret)
1461                         break;
1462         }
1463
1464         /*
1465          * Ignore failing Create SQ/CQ commands, we can continue with less
1466          * than the desired aount of queues, and even a controller without
1467          * I/O queues an still be used to issue admin commands.  This might
1468          * be useful to upgrade a buggy firmware for example.
1469          */
1470         return ret >= 0 ? 0 : ret;
1471 }
1472
1473 static ssize_t nvme_cmb_show(struct device *dev,
1474                              struct device_attribute *attr,
1475                              char *buf)
1476 {
1477         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1478
1479         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1480                        ndev->cmbloc, ndev->cmbsz);
1481 }
1482 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1483
1484 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1485 {
1486         u64 szu, size, offset;
1487         resource_size_t bar_size;
1488         struct pci_dev *pdev = to_pci_dev(dev->dev);
1489         void __iomem *cmb;
1490         dma_addr_t dma_addr;
1491
1492         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1493         if (!(NVME_CMB_SZ(dev->cmbsz)))
1494                 return NULL;
1495         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1496
1497         if (!use_cmb_sqes)
1498                 return NULL;
1499
1500         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1501         size = szu * NVME_CMB_SZ(dev->cmbsz);
1502         offset = szu * NVME_CMB_OFST(dev->cmbloc);
1503         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1504
1505         if (offset > bar_size)
1506                 return NULL;
1507
1508         /*
1509          * Controllers may support a CMB size larger than their BAR,
1510          * for example, due to being behind a bridge. Reduce the CMB to
1511          * the reported size of the BAR
1512          */
1513         if (size > bar_size - offset)
1514                 size = bar_size - offset;
1515
1516         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1517         cmb = ioremap_wc(dma_addr, size);
1518         if (!cmb)
1519                 return NULL;
1520
1521         dev->cmb_dma_addr = dma_addr;
1522         dev->cmb_size = size;
1523         return cmb;
1524 }
1525
1526 static inline void nvme_release_cmb(struct nvme_dev *dev)
1527 {
1528         if (dev->cmb) {
1529                 iounmap(dev->cmb);
1530                 dev->cmb = NULL;
1531                 if (dev->cmbsz) {
1532                         sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1533                                                      &dev_attr_cmb.attr, NULL);
1534                         dev->cmbsz = 0;
1535                 }
1536         }
1537 }
1538
1539 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1540 {
1541         size_t len = dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs);
1542         struct nvme_command c;
1543         u64 dma_addr;
1544         int ret;
1545
1546         dma_addr = dma_map_single(dev->dev, dev->host_mem_descs, len,
1547                         DMA_TO_DEVICE);
1548         if (dma_mapping_error(dev->dev, dma_addr))
1549                 return -ENOMEM;
1550
1551         memset(&c, 0, sizeof(c));
1552         c.features.opcode       = nvme_admin_set_features;
1553         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1554         c.features.dword11      = cpu_to_le32(bits);
1555         c.features.dword12      = cpu_to_le32(dev->host_mem_size >>
1556                                               ilog2(dev->ctrl.page_size));
1557         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1558         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1559         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1560
1561         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1562         if (ret) {
1563                 dev_warn(dev->ctrl.device,
1564                          "failed to set host mem (err %d, flags %#x).\n",
1565                          ret, bits);
1566         }
1567         dma_unmap_single(dev->dev, dma_addr, len, DMA_TO_DEVICE);
1568         return ret;
1569 }
1570
1571 static void nvme_free_host_mem(struct nvme_dev *dev)
1572 {
1573         int i;
1574
1575         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1576                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1577                 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1578
1579                 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1580                                 le64_to_cpu(desc->addr));
1581         }
1582
1583         kfree(dev->host_mem_desc_bufs);
1584         dev->host_mem_desc_bufs = NULL;
1585         kfree(dev->host_mem_descs);
1586         dev->host_mem_descs = NULL;
1587 }
1588
1589 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1590 {
1591         struct nvme_host_mem_buf_desc *descs;
1592         u32 chunk_size, max_entries, i = 0;
1593         void **bufs;
1594         u64 size, tmp;
1595
1596         /* start big and work our way down */
1597         chunk_size = min(preferred, (u64)PAGE_SIZE << MAX_ORDER);
1598 retry:
1599         tmp = (preferred + chunk_size - 1);
1600         do_div(tmp, chunk_size);
1601         max_entries = tmp;
1602         descs = kcalloc(max_entries, sizeof(*descs), GFP_KERNEL);
1603         if (!descs)
1604                 goto out;
1605
1606         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1607         if (!bufs)
1608                 goto out_free_descs;
1609
1610         for (size = 0; size < preferred; size += chunk_size) {
1611                 u32 len = min_t(u64, chunk_size, preferred - size);
1612                 dma_addr_t dma_addr;
1613
1614                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1615                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1616                 if (!bufs[i])
1617                         break;
1618
1619                 descs[i].addr = cpu_to_le64(dma_addr);
1620                 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1621                 i++;
1622         }
1623
1624         if (!size || (min && size < min)) {
1625                 dev_warn(dev->ctrl.device,
1626                         "failed to allocate host memory buffer.\n");
1627                 goto out_free_bufs;
1628         }
1629
1630         dev_info(dev->ctrl.device,
1631                 "allocated %lld MiB host memory buffer.\n",
1632                 size >> ilog2(SZ_1M));
1633         dev->nr_host_mem_descs = i;
1634         dev->host_mem_size = size;
1635         dev->host_mem_descs = descs;
1636         dev->host_mem_desc_bufs = bufs;
1637         return 0;
1638
1639 out_free_bufs:
1640         while (--i >= 0) {
1641                 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1642
1643                 dma_free_coherent(dev->dev, size, bufs[i],
1644                                 le64_to_cpu(descs[i].addr));
1645         }
1646
1647         kfree(bufs);
1648 out_free_descs:
1649         kfree(descs);
1650 out:
1651         /* try a smaller chunk size if we failed early */
1652         if (chunk_size >= PAGE_SIZE * 2 && (i == 0 || size < min)) {
1653                 chunk_size /= 2;
1654                 goto retry;
1655         }
1656         dev->host_mem_descs = NULL;
1657         return -ENOMEM;
1658 }
1659
1660 static void nvme_setup_host_mem(struct nvme_dev *dev)
1661 {
1662         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1663         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1664         u64 min = (u64)dev->ctrl.hmmin * 4096;
1665         u32 enable_bits = NVME_HOST_MEM_ENABLE;
1666
1667         preferred = min(preferred, max);
1668         if (min > max) {
1669                 dev_warn(dev->ctrl.device,
1670                         "min host memory (%lld MiB) above limit (%d MiB).\n",
1671                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
1672                 nvme_free_host_mem(dev);
1673                 return;
1674         }
1675
1676         /*
1677          * If we already have a buffer allocated check if we can reuse it.
1678          */
1679         if (dev->host_mem_descs) {
1680                 if (dev->host_mem_size >= min)
1681                         enable_bits |= NVME_HOST_MEM_RETURN;
1682                 else
1683                         nvme_free_host_mem(dev);
1684         }
1685
1686         if (!dev->host_mem_descs) {
1687                 if (nvme_alloc_host_mem(dev, min, preferred))
1688                         return;
1689         }
1690
1691         if (nvme_set_host_mem(dev, enable_bits))
1692                 nvme_free_host_mem(dev);
1693 }
1694
1695 static int nvme_setup_io_queues(struct nvme_dev *dev)
1696 {
1697         struct nvme_queue *adminq = dev->queues[0];
1698         struct pci_dev *pdev = to_pci_dev(dev->dev);
1699         int result, nr_io_queues;
1700         unsigned long size;
1701
1702         nr_io_queues = num_online_cpus();
1703         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1704         if (result < 0)
1705                 return result;
1706
1707         if (nr_io_queues == 0)
1708                 return 0;
1709
1710         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1711                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1712                                 sizeof(struct nvme_command));
1713                 if (result > 0)
1714                         dev->q_depth = result;
1715                 else
1716                         nvme_release_cmb(dev);
1717         }
1718
1719         do {
1720                 size = db_bar_size(dev, nr_io_queues);
1721                 result = nvme_remap_bar(dev, size);
1722                 if (!result)
1723                         break;
1724                 if (!--nr_io_queues)
1725                         return -ENOMEM;
1726         } while (1);
1727         adminq->q_db = dev->dbs;
1728
1729         /* Deregister the admin queue's interrupt */
1730         pci_free_irq(pdev, 0, adminq);
1731
1732         /*
1733          * If we enable msix early due to not intx, disable it again before
1734          * setting up the full range we need.
1735          */
1736         pci_free_irq_vectors(pdev);
1737         nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1738                         PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1739         if (nr_io_queues <= 0)
1740                 return -EIO;
1741         dev->max_qid = nr_io_queues;
1742
1743         /*
1744          * Should investigate if there's a performance win from allocating
1745          * more queues than interrupt vectors; it might allow the submission
1746          * path to scale better, even if the receive path is limited by the
1747          * number of interrupts.
1748          */
1749
1750         result = queue_request_irq(adminq);
1751         if (result) {
1752                 adminq->cq_vector = -1;
1753                 return result;
1754         }
1755         return nvme_create_io_queues(dev);
1756 }
1757
1758 static void nvme_del_queue_end(struct request *req, blk_status_t error)
1759 {
1760         struct nvme_queue *nvmeq = req->end_io_data;
1761
1762         blk_mq_free_request(req);
1763         complete(&nvmeq->dev->ioq_wait);
1764 }
1765
1766 static void nvme_del_cq_end(struct request *req, blk_status_t error)
1767 {
1768         struct nvme_queue *nvmeq = req->end_io_data;
1769
1770         if (!error) {
1771                 unsigned long flags;
1772
1773                 /*
1774                  * We might be called with the AQ q_lock held
1775                  * and the I/O queue q_lock should always
1776                  * nest inside the AQ one.
1777                  */
1778                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1779                                         SINGLE_DEPTH_NESTING);
1780                 nvme_process_cq(nvmeq);
1781                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1782         }
1783
1784         nvme_del_queue_end(req, error);
1785 }
1786
1787 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1788 {
1789         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1790         struct request *req;
1791         struct nvme_command cmd;
1792
1793         memset(&cmd, 0, sizeof(cmd));
1794         cmd.delete_queue.opcode = opcode;
1795         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1796
1797         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1798         if (IS_ERR(req))
1799                 return PTR_ERR(req);
1800
1801         req->timeout = ADMIN_TIMEOUT;
1802         req->end_io_data = nvmeq;
1803
1804         blk_execute_rq_nowait(q, NULL, req, false,
1805                         opcode == nvme_admin_delete_cq ?
1806                                 nvme_del_cq_end : nvme_del_queue_end);
1807         return 0;
1808 }
1809
1810 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1811 {
1812         int pass;
1813         unsigned long timeout;
1814         u8 opcode = nvme_admin_delete_sq;
1815
1816         for (pass = 0; pass < 2; pass++) {
1817                 int sent = 0, i = queues;
1818
1819                 reinit_completion(&dev->ioq_wait);
1820  retry:
1821                 timeout = ADMIN_TIMEOUT;
1822                 for (; i > 0; i--, sent++)
1823                         if (nvme_delete_queue(dev->queues[i], opcode))
1824                                 break;
1825
1826                 while (sent--) {
1827                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1828                         if (timeout == 0)
1829                                 return;
1830                         if (i)
1831                                 goto retry;
1832                 }
1833                 opcode = nvme_admin_delete_cq;
1834         }
1835 }
1836
1837 /*
1838  * Return: error value if an error occurred setting up the queues or calling
1839  * Identify Device.  0 if these succeeded, even if adding some of the
1840  * namespaces failed.  At the moment, these failures are silent.  TBD which
1841  * failures should be reported.
1842  */
1843 static int nvme_dev_add(struct nvme_dev *dev)
1844 {
1845         if (!dev->ctrl.tagset) {
1846                 dev->tagset.ops = &nvme_mq_ops;
1847                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1848                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1849                 dev->tagset.numa_node = dev_to_node(dev->dev);
1850                 dev->tagset.queue_depth =
1851                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1852                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1853                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1854                 dev->tagset.driver_data = dev;
1855
1856                 if (blk_mq_alloc_tag_set(&dev->tagset))
1857                         return 0;
1858                 dev->ctrl.tagset = &dev->tagset;
1859
1860                 nvme_dbbuf_set(dev);
1861         } else {
1862                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1863
1864                 /* Free previously allocated queues that are no longer usable */
1865                 nvme_free_queues(dev, dev->online_queues);
1866         }
1867
1868         return 0;
1869 }
1870
1871 static int nvme_pci_enable(struct nvme_dev *dev)
1872 {
1873         u64 cap;
1874         int result = -ENOMEM;
1875         struct pci_dev *pdev = to_pci_dev(dev->dev);
1876
1877         if (pci_enable_device_mem(pdev))
1878                 return result;
1879
1880         pci_set_master(pdev);
1881
1882         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1883             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1884                 goto disable;
1885
1886         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1887                 result = -ENODEV;
1888                 goto disable;
1889         }
1890
1891         /*
1892          * Some devices and/or platforms don't advertise or work with INTx
1893          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1894          * adjust this later.
1895          */
1896         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1897         if (result < 0)
1898                 return result;
1899
1900         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1901
1902         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1903         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1904         dev->dbs = dev->bar + 4096;
1905
1906         /*
1907          * Temporary fix for the Apple controller found in the MacBook8,1 and
1908          * some MacBook7,1 to avoid controller resets and data loss.
1909          */
1910         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1911                 dev->q_depth = 2;
1912                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
1913                         "set queue depth=%u to work around controller resets\n",
1914                         dev->q_depth);
1915         }
1916
1917         /*
1918          * CMBs can currently only exist on >=1.2 PCIe devices. We only
1919          * populate sysfs if a CMB is implemented. Note that we add the
1920          * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1921          * it on exit. Since nvme_dev_attrs_group has no name we can pass
1922          * NULL as final argument to sysfs_add_file_to_group.
1923          */
1924
1925         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1926                 dev->cmb = nvme_map_cmb(dev);
1927
1928                 if (dev->cmbsz) {
1929                         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1930                                                     &dev_attr_cmb.attr, NULL))
1931                                 dev_warn(dev->ctrl.device,
1932                                          "failed to add sysfs attribute for CMB\n");
1933                 }
1934         }
1935
1936         pci_enable_pcie_error_reporting(pdev);
1937         pci_save_state(pdev);
1938         return 0;
1939
1940  disable:
1941         pci_disable_device(pdev);
1942         return result;
1943 }
1944
1945 static void nvme_dev_unmap(struct nvme_dev *dev)
1946 {
1947         if (dev->bar)
1948                 iounmap(dev->bar);
1949         pci_release_mem_regions(to_pci_dev(dev->dev));
1950 }
1951
1952 static void nvme_pci_disable(struct nvme_dev *dev)
1953 {
1954         struct pci_dev *pdev = to_pci_dev(dev->dev);
1955
1956         nvme_release_cmb(dev);
1957         pci_free_irq_vectors(pdev);
1958
1959         if (pci_is_enabled(pdev)) {
1960                 pci_disable_pcie_error_reporting(pdev);
1961                 pci_disable_device(pdev);
1962         }
1963 }
1964
1965 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1966 {
1967         int i, queues;
1968         bool dead = true;
1969         struct pci_dev *pdev = to_pci_dev(dev->dev);
1970
1971         mutex_lock(&dev->shutdown_lock);
1972         if (pci_is_enabled(pdev)) {
1973                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1974
1975                 if (dev->ctrl.state == NVME_CTRL_LIVE)
1976                         nvme_start_freeze(&dev->ctrl);
1977                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
1978                         pdev->error_state  != pci_channel_io_normal);
1979         }
1980
1981         /*
1982          * Give the controller a chance to complete all entered requests if
1983          * doing a safe shutdown.
1984          */
1985         if (!dead) {
1986                 if (shutdown)
1987                         nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
1988
1989                 /*
1990                  * If the controller is still alive tell it to stop using the
1991                  * host memory buffer.  In theory the shutdown / reset should
1992                  * make sure that it doesn't access the host memoery anymore,
1993                  * but I'd rather be safe than sorry..
1994                  */
1995                 if (dev->host_mem_descs)
1996                         nvme_set_host_mem(dev, 0);
1997
1998         }
1999         nvme_stop_queues(&dev->ctrl);
2000
2001         queues = dev->online_queues - 1;
2002         for (i = dev->queue_count - 1; i > 0; i--)
2003                 nvme_suspend_queue(dev->queues[i]);
2004
2005         if (dead) {
2006                 /* A device might become IO incapable very soon during
2007                  * probe, before the admin queue is configured. Thus,
2008                  * queue_count can be 0 here.
2009                  */
2010                 if (dev->queue_count)
2011                         nvme_suspend_queue(dev->queues[0]);
2012         } else {
2013                 nvme_disable_io_queues(dev, queues);
2014                 nvme_disable_admin_queue(dev, shutdown);
2015         }
2016         nvme_pci_disable(dev);
2017
2018         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2019         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2020
2021         /*
2022          * The driver will not be starting up queues again if shutting down so
2023          * must flush all entered requests to their failed completion to avoid
2024          * deadlocking blk-mq hot-cpu notifier.
2025          */
2026         if (shutdown)
2027                 nvme_start_queues(&dev->ctrl);
2028         mutex_unlock(&dev->shutdown_lock);
2029 }
2030
2031 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2032 {
2033         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2034                                                 PAGE_SIZE, PAGE_SIZE, 0);
2035         if (!dev->prp_page_pool)
2036                 return -ENOMEM;
2037
2038         /* Optimisation for I/Os between 4k and 128k */
2039         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2040                                                 256, 256, 0);
2041         if (!dev->prp_small_pool) {
2042                 dma_pool_destroy(dev->prp_page_pool);
2043                 return -ENOMEM;
2044         }
2045         return 0;
2046 }
2047
2048 static void nvme_release_prp_pools(struct nvme_dev *dev)
2049 {
2050         dma_pool_destroy(dev->prp_page_pool);
2051         dma_pool_destroy(dev->prp_small_pool);
2052 }
2053
2054 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2055 {
2056         struct nvme_dev *dev = to_nvme_dev(ctrl);
2057
2058         nvme_dbbuf_dma_free(dev);
2059         put_device(dev->dev);
2060         if (dev->tagset.tags)
2061                 blk_mq_free_tag_set(&dev->tagset);
2062         if (dev->ctrl.admin_q)
2063                 blk_put_queue(dev->ctrl.admin_q);
2064         kfree(dev->queues);
2065         free_opal_dev(dev->ctrl.opal_dev);
2066         kfree(dev);
2067 }
2068
2069 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2070 {
2071         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2072
2073         kref_get(&dev->ctrl.kref);
2074         nvme_dev_disable(dev, false);
2075         if (!schedule_work(&dev->remove_work))
2076                 nvme_put_ctrl(&dev->ctrl);
2077 }
2078
2079 static void nvme_reset_work(struct work_struct *work)
2080 {
2081         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2082         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2083         int result = -ENODEV;
2084
2085         if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2086                 goto out;
2087
2088         /*
2089          * If we're called to reset a live controller first shut it down before
2090          * moving on.
2091          */
2092         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2093                 nvme_dev_disable(dev, false);
2094
2095         result = nvme_pci_enable(dev);
2096         if (result)
2097                 goto out;
2098
2099         result = nvme_configure_admin_queue(dev);
2100         if (result)
2101                 goto out;
2102
2103         nvme_init_queue(dev->queues[0], 0);
2104         result = nvme_alloc_admin_tags(dev);
2105         if (result)
2106                 goto out;
2107
2108         result = nvme_init_identify(&dev->ctrl);
2109         if (result)
2110                 goto out;
2111
2112         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2113                 if (!dev->ctrl.opal_dev)
2114                         dev->ctrl.opal_dev =
2115                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2116                 else if (was_suspend)
2117                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2118         } else {
2119                 free_opal_dev(dev->ctrl.opal_dev);
2120                 dev->ctrl.opal_dev = NULL;
2121         }
2122
2123         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2124                 result = nvme_dbbuf_dma_alloc(dev);
2125                 if (result)
2126                         dev_warn(dev->dev,
2127                                  "unable to allocate dma for dbbuf\n");
2128         }
2129
2130         if (dev->ctrl.hmpre)
2131                 nvme_setup_host_mem(dev);
2132
2133         result = nvme_setup_io_queues(dev);
2134         if (result)
2135                 goto out;
2136
2137         /*
2138          * A controller that can not execute IO typically requires user
2139          * intervention to correct. For such degraded controllers, the driver
2140          * should not submit commands the user did not request, so skip
2141          * registering for asynchronous event notification on this condition.
2142          */
2143         if (dev->online_queues > 1)
2144                 nvme_queue_async_events(&dev->ctrl);
2145
2146         /*
2147          * Keep the controller around but remove all namespaces if we don't have
2148          * any working I/O queue.
2149          */
2150         if (dev->online_queues < 2) {
2151                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2152                 nvme_kill_queues(&dev->ctrl);
2153                 nvme_remove_namespaces(&dev->ctrl);
2154         } else {
2155                 nvme_start_queues(&dev->ctrl);
2156                 nvme_wait_freeze(&dev->ctrl);
2157                 nvme_dev_add(dev);
2158                 nvme_unfreeze(&dev->ctrl);
2159         }
2160
2161         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2162                 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
2163                 goto out;
2164         }
2165
2166         if (dev->online_queues > 1)
2167                 nvme_queue_scan(&dev->ctrl);
2168         return;
2169
2170  out:
2171         nvme_remove_dead_ctrl(dev, result);
2172 }
2173
2174 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2175 {
2176         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2177         struct pci_dev *pdev = to_pci_dev(dev->dev);
2178
2179         nvme_kill_queues(&dev->ctrl);
2180         if (pci_get_drvdata(pdev))
2181                 device_release_driver(&pdev->dev);
2182         nvme_put_ctrl(&dev->ctrl);
2183 }
2184
2185 static int nvme_reset(struct nvme_dev *dev)
2186 {
2187         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
2188                 return -ENODEV;
2189         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
2190                 return -EBUSY;
2191         if (!queue_work(nvme_wq, &dev->reset_work))
2192                 return -EBUSY;
2193         return 0;
2194 }
2195
2196 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2197 {
2198         *val = readl(to_nvme_dev(ctrl)->bar + off);
2199         return 0;
2200 }
2201
2202 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2203 {
2204         writel(val, to_nvme_dev(ctrl)->bar + off);
2205         return 0;
2206 }
2207
2208 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2209 {
2210         *val = readq(to_nvme_dev(ctrl)->bar + off);
2211         return 0;
2212 }
2213
2214 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
2215 {
2216         struct nvme_dev *dev = to_nvme_dev(ctrl);
2217         int ret = nvme_reset(dev);
2218
2219         if (!ret)
2220                 flush_work(&dev->reset_work);
2221         return ret;
2222 }
2223
2224 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2225         .name                   = "pcie",
2226         .module                 = THIS_MODULE,
2227         .flags                  = NVME_F_METADATA_SUPPORTED,
2228         .reg_read32             = nvme_pci_reg_read32,
2229         .reg_write32            = nvme_pci_reg_write32,
2230         .reg_read64             = nvme_pci_reg_read64,
2231         .reset_ctrl             = nvme_pci_reset_ctrl,
2232         .free_ctrl              = nvme_pci_free_ctrl,
2233         .submit_async_event     = nvme_pci_submit_async_event,
2234 };
2235
2236 static int nvme_dev_map(struct nvme_dev *dev)
2237 {
2238         struct pci_dev *pdev = to_pci_dev(dev->dev);
2239
2240         if (pci_request_mem_regions(pdev, "nvme"))
2241                 return -ENODEV;
2242
2243         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2244                 goto release;
2245
2246         return 0;
2247   release:
2248         pci_release_mem_regions(pdev);
2249         return -ENODEV;
2250 }
2251
2252 static unsigned long check_dell_samsung_bug(struct pci_dev *pdev)
2253 {
2254         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2255                 /*
2256                  * Several Samsung devices seem to drop off the PCIe bus
2257                  * randomly when APST is on and uses the deepest sleep state.
2258                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2259                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2260                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2261                  * laptops.
2262                  */
2263                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2264                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2265                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2266                         return NVME_QUIRK_NO_DEEPEST_PS;
2267         }
2268
2269         return 0;
2270 }
2271
2272 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2273 {
2274         int node, result = -ENOMEM;
2275         struct nvme_dev *dev;
2276         unsigned long quirks = id->driver_data;
2277
2278         node = dev_to_node(&pdev->dev);
2279         if (node == NUMA_NO_NODE)
2280                 set_dev_node(&pdev->dev, first_memory_node);
2281
2282         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2283         if (!dev)
2284                 return -ENOMEM;
2285         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2286                                                         GFP_KERNEL, node);
2287         if (!dev->queues)
2288                 goto free;
2289
2290         dev->dev = get_device(&pdev->dev);
2291         pci_set_drvdata(pdev, dev);
2292
2293         result = nvme_dev_map(dev);
2294         if (result)
2295                 goto free;
2296
2297         INIT_WORK(&dev->reset_work, nvme_reset_work);
2298         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2299         mutex_init(&dev->shutdown_lock);
2300         init_completion(&dev->ioq_wait);
2301
2302         result = nvme_setup_prp_pools(dev);
2303         if (result)
2304                 goto put_pci;
2305
2306         quirks |= check_dell_samsung_bug(pdev);
2307
2308         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2309                         quirks);
2310         if (result)
2311                 goto release_pools;
2312
2313         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING);
2314         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2315
2316         queue_work(nvme_wq, &dev->reset_work);
2317         return 0;
2318
2319  release_pools:
2320         nvme_release_prp_pools(dev);
2321  put_pci:
2322         put_device(dev->dev);
2323         nvme_dev_unmap(dev);
2324  free:
2325         kfree(dev->queues);
2326         kfree(dev);
2327         return result;
2328 }
2329
2330 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2331 {
2332         struct nvme_dev *dev = pci_get_drvdata(pdev);
2333
2334         if (prepare)
2335                 nvme_dev_disable(dev, false);
2336         else
2337                 nvme_reset(dev);
2338 }
2339
2340 static void nvme_shutdown(struct pci_dev *pdev)
2341 {
2342         struct nvme_dev *dev = pci_get_drvdata(pdev);
2343         nvme_dev_disable(dev, true);
2344 }
2345
2346 /*
2347  * The driver's remove may be called on a device in a partially initialized
2348  * state. This function must not have any dependencies on the device state in
2349  * order to proceed.
2350  */
2351 static void nvme_remove(struct pci_dev *pdev)
2352 {
2353         struct nvme_dev *dev = pci_get_drvdata(pdev);
2354
2355         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2356
2357         cancel_work_sync(&dev->reset_work);
2358         pci_set_drvdata(pdev, NULL);
2359
2360         if (!pci_device_is_present(pdev)) {
2361                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2362                 nvme_dev_disable(dev, false);
2363         }
2364
2365         flush_work(&dev->reset_work);
2366         nvme_uninit_ctrl(&dev->ctrl);
2367         nvme_dev_disable(dev, true);
2368         nvme_free_host_mem(dev);
2369         nvme_dev_remove_admin(dev);
2370         nvme_free_queues(dev, 0);
2371         nvme_release_prp_pools(dev);
2372         nvme_dev_unmap(dev);
2373         nvme_put_ctrl(&dev->ctrl);
2374 }
2375
2376 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2377 {
2378         int ret = 0;
2379
2380         if (numvfs == 0) {
2381                 if (pci_vfs_assigned(pdev)) {
2382                         dev_warn(&pdev->dev,
2383                                 "Cannot disable SR-IOV VFs while assigned\n");
2384                         return -EPERM;
2385                 }
2386                 pci_disable_sriov(pdev);
2387                 return 0;
2388         }
2389
2390         ret = pci_enable_sriov(pdev, numvfs);
2391         return ret ? ret : numvfs;
2392 }
2393
2394 #ifdef CONFIG_PM_SLEEP
2395 static int nvme_suspend(struct device *dev)
2396 {
2397         struct pci_dev *pdev = to_pci_dev(dev);
2398         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2399
2400         nvme_dev_disable(ndev, true);
2401         return 0;
2402 }
2403
2404 static int nvme_resume(struct device *dev)
2405 {
2406         struct pci_dev *pdev = to_pci_dev(dev);
2407         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2408
2409         nvme_reset(ndev);
2410         return 0;
2411 }
2412 #endif
2413
2414 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2415
2416 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2417                                                 pci_channel_state_t state)
2418 {
2419         struct nvme_dev *dev = pci_get_drvdata(pdev);
2420
2421         /*
2422          * A frozen channel requires a reset. When detected, this method will
2423          * shutdown the controller to quiesce. The controller will be restarted
2424          * after the slot reset through driver's slot_reset callback.
2425          */
2426         switch (state) {
2427         case pci_channel_io_normal:
2428                 return PCI_ERS_RESULT_CAN_RECOVER;
2429         case pci_channel_io_frozen:
2430                 dev_warn(dev->ctrl.device,
2431                         "frozen state error detected, reset controller\n");
2432                 nvme_dev_disable(dev, false);
2433                 return PCI_ERS_RESULT_NEED_RESET;
2434         case pci_channel_io_perm_failure:
2435                 dev_warn(dev->ctrl.device,
2436                         "failure state error detected, request disconnect\n");
2437                 return PCI_ERS_RESULT_DISCONNECT;
2438         }
2439         return PCI_ERS_RESULT_NEED_RESET;
2440 }
2441
2442 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2443 {
2444         struct nvme_dev *dev = pci_get_drvdata(pdev);
2445
2446         dev_info(dev->ctrl.device, "restart after slot reset\n");
2447         pci_restore_state(pdev);
2448         nvme_reset(dev);
2449         return PCI_ERS_RESULT_RECOVERED;
2450 }
2451
2452 static void nvme_error_resume(struct pci_dev *pdev)
2453 {
2454         pci_cleanup_aer_uncorrect_error_status(pdev);
2455 }
2456
2457 static const struct pci_error_handlers nvme_err_handler = {
2458         .error_detected = nvme_error_detected,
2459         .slot_reset     = nvme_slot_reset,
2460         .resume         = nvme_error_resume,
2461         .reset_notify   = nvme_reset_notify,
2462 };
2463
2464 static const struct pci_device_id nvme_id_table[] = {
2465         { PCI_VDEVICE(INTEL, 0x0953),
2466                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2467                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2468         { PCI_VDEVICE(INTEL, 0x0a53),
2469                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2470                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2471         { PCI_VDEVICE(INTEL, 0x0a54),
2472                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2473                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2474         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
2475                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
2476         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2477                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2478         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
2479                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2480         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
2481                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2482         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2483         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2484         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2485         { 0, }
2486 };
2487 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2488
2489 static struct pci_driver nvme_driver = {
2490         .name           = "nvme",
2491         .id_table       = nvme_id_table,
2492         .probe          = nvme_probe,
2493         .remove         = nvme_remove,
2494         .shutdown       = nvme_shutdown,
2495         .driver         = {
2496                 .pm     = &nvme_dev_pm_ops,
2497         },
2498         .sriov_configure = nvme_pci_sriov_configure,
2499         .err_handler    = &nvme_err_handler,
2500 };
2501
2502 static int __init nvme_init(void)
2503 {
2504         return pci_register_driver(&nvme_driver);
2505 }
2506
2507 static void __exit nvme_exit(void)
2508 {
2509         pci_unregister_driver(&nvme_driver);
2510         _nvme_check_size();
2511 }
2512
2513 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2514 MODULE_LICENSE("GPL");
2515 MODULE_VERSION("1.0");
2516 module_init(nvme_init);
2517 module_exit(nvme_exit);