2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/cpu.h>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
23 #include <linux/genhd.h>
24 #include <linux/hdreg.h>
25 #include <linux/idr.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
29 #include <linux/kdev_t.h>
30 #include <linux/kthread.h>
31 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/mutex.h>
36 #include <linux/pci.h>
37 #include <linux/poison.h>
38 #include <linux/ptrace.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/t10-pi.h>
42 #include <linux/types.h>
43 #include <linux/io-64-nonatomic-lo-hi.h>
44 #include <asm/unaligned.h>
48 #define NVME_Q_DEPTH 1024
49 #define NVME_AQ_DEPTH 256
50 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
51 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
54 * We handle AEN commands ourselves and don't even let the
55 * block layer know about them.
57 #define NVME_NR_AEN_COMMANDS 1
58 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
60 unsigned char admin_timeout = 60;
61 module_param(admin_timeout, byte, 0644);
62 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
64 unsigned char nvme_io_timeout = 30;
65 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
66 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
68 unsigned char shutdown_timeout = 5;
69 module_param(shutdown_timeout, byte, 0644);
70 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
72 static int use_threaded_interrupts;
73 module_param(use_threaded_interrupts, int, 0);
75 static bool use_cmb_sqes = true;
76 module_param(use_cmb_sqes, bool, 0644);
77 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
79 static LIST_HEAD(dev_list);
80 static struct task_struct *nvme_thread;
81 static struct workqueue_struct *nvme_workq;
82 static wait_queue_head_t nvme_kthread_wait;
87 static int nvme_reset(struct nvme_dev *dev);
88 static void nvme_process_cq(struct nvme_queue *nvmeq);
89 static void nvme_remove_dead_ctrl(struct nvme_dev *dev);
90 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
93 * Represents an NVM Express device. Each nvme_dev is a PCI function.
96 struct list_head node;
97 struct nvme_queue **queues;
98 struct blk_mq_tag_set tagset;
99 struct blk_mq_tag_set admin_tagset;
102 struct dma_pool *prp_page_pool;
103 struct dma_pool *prp_small_pool;
104 unsigned queue_count;
105 unsigned online_queues;
109 struct msix_entry *entry;
111 struct work_struct reset_work;
112 struct work_struct scan_work;
113 struct work_struct remove_work;
114 struct mutex shutdown_lock;
117 dma_addr_t cmb_dma_addr;
122 #define NVME_CTRL_RESETTING 0
124 struct nvme_ctrl ctrl;
125 struct completion ioq_wait;
128 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
130 return container_of(ctrl, struct nvme_dev, ctrl);
134 * An NVM Express queue. Each device has at least two (one for admin
135 * commands and one for I/O commands).
138 struct device *q_dmadev;
139 struct nvme_dev *dev;
140 char irqname[24]; /* nvme4294967295-65535\0 */
142 struct nvme_command *sq_cmds;
143 struct nvme_command __iomem *sq_cmds_io;
144 volatile struct nvme_completion *cqes;
145 struct blk_mq_tags **tags;
146 dma_addr_t sq_dma_addr;
147 dma_addr_t cq_dma_addr;
160 * The nvme_iod describes the data in an I/O, including the list of PRP
161 * entries. You can't see it in this data structure because C doesn't let
162 * me express that. Use nvme_init_iod to ensure there's enough space
163 * allocated to store the PRP list.
166 struct nvme_queue *nvmeq;
168 int npages; /* In the PRP list. 0 means small pool in use */
169 int nents; /* Used in scatterlist */
170 int length; /* Of data, in bytes */
171 dma_addr_t first_dma;
172 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
173 struct scatterlist *sg;
174 struct scatterlist inline_sg[0];
178 * Check we didin't inadvertently grow the command struct
180 static inline void _nvme_check_size(void)
182 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
183 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
184 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
185 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
186 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
187 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
188 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
189 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
190 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
191 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
192 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
193 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
197 * Max size of iod being embedded in the request payload
199 #define NVME_INT_PAGES 2
200 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
203 * Will slightly overestimate the number of pages needed. This is OK
204 * as it only leads to a small amount of wasted memory for the lifetime of
207 static int nvme_npages(unsigned size, struct nvme_dev *dev)
209 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
210 dev->ctrl.page_size);
211 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
214 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
215 unsigned int size, unsigned int nseg)
217 return sizeof(__le64 *) * nvme_npages(size, dev) +
218 sizeof(struct scatterlist) * nseg;
221 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
223 return sizeof(struct nvme_iod) +
224 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
227 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
228 unsigned int hctx_idx)
230 struct nvme_dev *dev = data;
231 struct nvme_queue *nvmeq = dev->queues[0];
233 WARN_ON(hctx_idx != 0);
234 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
235 WARN_ON(nvmeq->tags);
237 hctx->driver_data = nvmeq;
238 nvmeq->tags = &dev->admin_tagset.tags[0];
242 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
244 struct nvme_queue *nvmeq = hctx->driver_data;
249 static int nvme_admin_init_request(void *data, struct request *req,
250 unsigned int hctx_idx, unsigned int rq_idx,
251 unsigned int numa_node)
253 struct nvme_dev *dev = data;
254 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
255 struct nvme_queue *nvmeq = dev->queues[0];
262 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
263 unsigned int hctx_idx)
265 struct nvme_dev *dev = data;
266 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
269 nvmeq->tags = &dev->tagset.tags[hctx_idx];
271 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
272 hctx->driver_data = nvmeq;
276 static int nvme_init_request(void *data, struct request *req,
277 unsigned int hctx_idx, unsigned int rq_idx,
278 unsigned int numa_node)
280 struct nvme_dev *dev = data;
281 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
282 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
289 static void nvme_complete_async_event(struct nvme_dev *dev,
290 struct nvme_completion *cqe)
292 u16 status = le16_to_cpu(cqe->status) >> 1;
293 u32 result = le32_to_cpu(cqe->result);
295 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
296 ++dev->ctrl.event_limit;
297 if (status != NVME_SC_SUCCESS)
300 switch (result & 0xff07) {
301 case NVME_AER_NOTICE_NS_CHANGED:
302 dev_info(dev->dev, "rescanning\n");
303 queue_work(nvme_workq, &dev->scan_work);
305 dev_warn(dev->dev, "async event result %08x\n", result);
310 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
311 * @nvmeq: The queue to use
312 * @cmd: The command to send
314 * Safe to use from interrupt context
316 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
317 struct nvme_command *cmd)
319 u16 tail = nvmeq->sq_tail;
321 if (nvmeq->sq_cmds_io)
322 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
324 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
326 if (++tail == nvmeq->q_depth)
328 writel(tail, nvmeq->q_db);
329 nvmeq->sq_tail = tail;
332 static __le64 **iod_list(struct request *req)
334 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
335 return (__le64 **)(iod->sg + req->nr_phys_segments);
338 static int nvme_init_iod(struct request *rq, struct nvme_dev *dev)
340 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
341 int nseg = rq->nr_phys_segments;
344 if (rq->cmd_flags & REQ_DISCARD)
345 size = sizeof(struct nvme_dsm_range);
347 size = blk_rq_bytes(rq);
349 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
350 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
352 return BLK_MQ_RQ_QUEUE_BUSY;
354 iod->sg = iod->inline_sg;
364 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
366 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
367 const int last_prp = dev->ctrl.page_size / 8 - 1;
369 __le64 **list = iod_list(req);
370 dma_addr_t prp_dma = iod->first_dma;
372 if (iod->npages == 0)
373 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
374 for (i = 0; i < iod->npages; i++) {
375 __le64 *prp_list = list[i];
376 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
377 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
378 prp_dma = next_prp_dma;
381 if (iod->sg != iod->inline_sg)
385 #ifdef CONFIG_BLK_DEV_INTEGRITY
386 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
388 if (be32_to_cpu(pi->ref_tag) == v)
389 pi->ref_tag = cpu_to_be32(p);
392 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
394 if (be32_to_cpu(pi->ref_tag) == p)
395 pi->ref_tag = cpu_to_be32(v);
399 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
401 * The virtual start sector is the one that was originally submitted by the
402 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
403 * start sector may be different. Remap protection information to match the
404 * physical LBA on writes, and back to the original seed on reads.
406 * Type 0 and 3 do not have a ref tag, so no remapping required.
408 static void nvme_dif_remap(struct request *req,
409 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
411 struct nvme_ns *ns = req->rq_disk->private_data;
412 struct bio_integrity_payload *bip;
413 struct t10_pi_tuple *pi;
415 u32 i, nlb, ts, phys, virt;
417 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
420 bip = bio_integrity(req->bio);
424 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
427 virt = bip_get_seed(bip);
428 phys = nvme_block_nr(ns, blk_rq_pos(req));
429 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
430 ts = ns->disk->queue->integrity.tuple_size;
432 for (i = 0; i < nlb; i++, virt++, phys++) {
433 pi = (struct t10_pi_tuple *)p;
434 dif_swap(phys, virt, pi);
439 #else /* CONFIG_BLK_DEV_INTEGRITY */
440 static void nvme_dif_remap(struct request *req,
441 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
444 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
447 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
452 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
455 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
456 struct dma_pool *pool;
457 int length = total_len;
458 struct scatterlist *sg = iod->sg;
459 int dma_len = sg_dma_len(sg);
460 u64 dma_addr = sg_dma_address(sg);
461 u32 page_size = dev->ctrl.page_size;
462 int offset = dma_addr & (page_size - 1);
464 __le64 **list = iod_list(req);
468 length -= (page_size - offset);
472 dma_len -= (page_size - offset);
474 dma_addr += (page_size - offset);
477 dma_addr = sg_dma_address(sg);
478 dma_len = sg_dma_len(sg);
481 if (length <= page_size) {
482 iod->first_dma = dma_addr;
486 nprps = DIV_ROUND_UP(length, page_size);
487 if (nprps <= (256 / 8)) {
488 pool = dev->prp_small_pool;
491 pool = dev->prp_page_pool;
495 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
497 iod->first_dma = dma_addr;
502 iod->first_dma = prp_dma;
505 if (i == page_size >> 3) {
506 __le64 *old_prp_list = prp_list;
507 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
510 list[iod->npages++] = prp_list;
511 prp_list[0] = old_prp_list[i - 1];
512 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
515 prp_list[i++] = cpu_to_le64(dma_addr);
516 dma_len -= page_size;
517 dma_addr += page_size;
525 dma_addr = sg_dma_address(sg);
526 dma_len = sg_dma_len(sg);
532 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
533 struct nvme_command *cmnd)
535 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
536 struct request_queue *q = req->q;
537 enum dma_data_direction dma_dir = rq_data_dir(req) ?
538 DMA_TO_DEVICE : DMA_FROM_DEVICE;
539 int ret = BLK_MQ_RQ_QUEUE_ERROR;
541 sg_init_table(iod->sg, req->nr_phys_segments);
542 iod->nents = blk_rq_map_sg(q, req, iod->sg);
546 ret = BLK_MQ_RQ_QUEUE_BUSY;
547 if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
550 if (!nvme_setup_prps(dev, req, blk_rq_bytes(req)))
553 ret = BLK_MQ_RQ_QUEUE_ERROR;
554 if (blk_integrity_rq(req)) {
555 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
558 sg_init_table(&iod->meta_sg, 1);
559 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
562 if (rq_data_dir(req))
563 nvme_dif_remap(req, nvme_dif_prep);
565 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
569 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
570 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
571 if (blk_integrity_rq(req))
572 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
573 return BLK_MQ_RQ_QUEUE_OK;
576 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
581 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
583 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
584 enum dma_data_direction dma_dir = rq_data_dir(req) ?
585 DMA_TO_DEVICE : DMA_FROM_DEVICE;
588 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
589 if (blk_integrity_rq(req)) {
590 if (!rq_data_dir(req))
591 nvme_dif_remap(req, nvme_dif_complete);
592 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
596 nvme_free_iod(dev, req);
600 * We reuse the small pool to allocate the 16-byte range here as it is not
601 * worth having a special pool for these or additional cases to handle freeing
604 static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
605 struct request *req, struct nvme_command *cmnd)
607 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
608 struct nvme_dsm_range *range;
610 range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
613 return BLK_MQ_RQ_QUEUE_BUSY;
614 iod_list(req)[0] = (__le64 *)range;
617 range->cattr = cpu_to_le32(0);
618 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
619 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
621 memset(cmnd, 0, sizeof(*cmnd));
622 cmnd->dsm.opcode = nvme_cmd_dsm;
623 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
624 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
626 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
627 return BLK_MQ_RQ_QUEUE_OK;
631 * NOTE: ns is NULL when called on the admin queue.
633 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
634 const struct blk_mq_queue_data *bd)
636 struct nvme_ns *ns = hctx->queue->queuedata;
637 struct nvme_queue *nvmeq = hctx->driver_data;
638 struct nvme_dev *dev = nvmeq->dev;
639 struct request *req = bd->rq;
640 struct nvme_command cmnd;
641 int ret = BLK_MQ_RQ_QUEUE_OK;
644 * If formated with metadata, require the block layer provide a buffer
645 * unless this namespace is formated such that the metadata can be
646 * stripped/generated by the controller with PRACT=1.
648 if (ns && ns->ms && !blk_integrity_rq(req)) {
649 if (!(ns->pi_type && ns->ms == 8) &&
650 req->cmd_type != REQ_TYPE_DRV_PRIV) {
651 blk_mq_end_request(req, -EFAULT);
652 return BLK_MQ_RQ_QUEUE_OK;
656 ret = nvme_init_iod(req, dev);
660 if (req->cmd_flags & REQ_DISCARD) {
661 ret = nvme_setup_discard(nvmeq, ns, req, &cmnd);
663 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
664 memcpy(&cmnd, req->cmd, sizeof(cmnd));
665 else if (req->cmd_flags & REQ_FLUSH)
666 nvme_setup_flush(ns, &cmnd);
668 nvme_setup_rw(ns, req, &cmnd);
670 if (req->nr_phys_segments)
671 ret = nvme_map_data(dev, req, &cmnd);
677 cmnd.common.command_id = req->tag;
678 blk_mq_start_request(req);
680 spin_lock_irq(&nvmeq->q_lock);
681 if (unlikely(nvmeq->cq_vector < 0)) {
682 ret = BLK_MQ_RQ_QUEUE_BUSY;
683 spin_unlock_irq(&nvmeq->q_lock);
686 __nvme_submit_cmd(nvmeq, &cmnd);
687 nvme_process_cq(nvmeq);
688 spin_unlock_irq(&nvmeq->q_lock);
689 return BLK_MQ_RQ_QUEUE_OK;
691 nvme_free_iod(dev, req);
695 static void nvme_complete_rq(struct request *req)
697 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
698 struct nvme_dev *dev = iod->nvmeq->dev;
701 nvme_unmap_data(dev, req);
703 if (unlikely(req->errors)) {
704 if (nvme_req_needs_retry(req, req->errors)) {
705 nvme_requeue_req(req);
709 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
712 error = nvme_error_status(req->errors);
715 if (unlikely(iod->aborted)) {
717 "completing aborted command with status: %04x\n",
721 blk_mq_end_request(req, error);
724 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
728 head = nvmeq->cq_head;
729 phase = nvmeq->cq_phase;
732 struct nvme_completion cqe = nvmeq->cqes[head];
733 u16 status = le16_to_cpu(cqe.status);
736 if ((status & 1) != phase)
738 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
739 if (++head == nvmeq->q_depth) {
744 if (tag && *tag == cqe.command_id)
747 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
748 dev_warn(nvmeq->q_dmadev,
749 "invalid id %d completed on queue %d\n",
750 cqe.command_id, le16_to_cpu(cqe.sq_id));
755 * AEN requests are special as they don't time out and can
756 * survive any kind of queue freeze and often don't respond to
757 * aborts. We don't even bother to allocate a struct request
758 * for them but rather special case them here.
760 if (unlikely(nvmeq->qid == 0 &&
761 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
762 nvme_complete_async_event(nvmeq->dev, &cqe);
766 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
767 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
768 u32 result = le32_to_cpu(cqe.result);
769 req->special = (void *)(uintptr_t)result;
771 blk_mq_complete_request(req, status >> 1);
775 /* If the controller ignores the cq head doorbell and continuously
776 * writes to the queue, it is theoretically possible to wrap around
777 * the queue twice and mistakenly return IRQ_NONE. Linux only
778 * requires that 0.1% of your interrupts are handled, so this isn't
781 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
784 if (likely(nvmeq->cq_vector >= 0))
785 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
786 nvmeq->cq_head = head;
787 nvmeq->cq_phase = phase;
792 static void nvme_process_cq(struct nvme_queue *nvmeq)
794 __nvme_process_cq(nvmeq, NULL);
797 static irqreturn_t nvme_irq(int irq, void *data)
800 struct nvme_queue *nvmeq = data;
801 spin_lock(&nvmeq->q_lock);
802 nvme_process_cq(nvmeq);
803 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
805 spin_unlock(&nvmeq->q_lock);
809 static irqreturn_t nvme_irq_check(int irq, void *data)
811 struct nvme_queue *nvmeq = data;
812 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
813 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
815 return IRQ_WAKE_THREAD;
818 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
820 struct nvme_queue *nvmeq = hctx->driver_data;
822 if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
824 spin_lock_irq(&nvmeq->q_lock);
825 __nvme_process_cq(nvmeq, &tag);
826 spin_unlock_irq(&nvmeq->q_lock);
835 static void nvme_submit_async_event(struct nvme_dev *dev)
837 struct nvme_command c;
839 memset(&c, 0, sizeof(c));
840 c.common.opcode = nvme_admin_async_event;
841 c.common.command_id = NVME_AQ_BLKMQ_DEPTH + --dev->ctrl.event_limit;
843 __nvme_submit_cmd(dev->queues[0], &c);
846 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
848 struct nvme_command c;
850 memset(&c, 0, sizeof(c));
851 c.delete_queue.opcode = opcode;
852 c.delete_queue.qid = cpu_to_le16(id);
854 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
857 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
858 struct nvme_queue *nvmeq)
860 struct nvme_command c;
861 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
864 * Note: we (ab)use the fact the the prp fields survive if no data
865 * is attached to the request.
867 memset(&c, 0, sizeof(c));
868 c.create_cq.opcode = nvme_admin_create_cq;
869 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
870 c.create_cq.cqid = cpu_to_le16(qid);
871 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
872 c.create_cq.cq_flags = cpu_to_le16(flags);
873 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
875 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
878 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
879 struct nvme_queue *nvmeq)
881 struct nvme_command c;
882 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
885 * Note: we (ab)use the fact the the prp fields survive if no data
886 * is attached to the request.
888 memset(&c, 0, sizeof(c));
889 c.create_sq.opcode = nvme_admin_create_sq;
890 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
891 c.create_sq.sqid = cpu_to_le16(qid);
892 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
893 c.create_sq.sq_flags = cpu_to_le16(flags);
894 c.create_sq.cqid = cpu_to_le16(qid);
896 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
899 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
901 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
904 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
906 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
909 static void abort_endio(struct request *req, int error)
911 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
912 struct nvme_queue *nvmeq = iod->nvmeq;
913 u32 result = (u32)(uintptr_t)req->special;
914 u16 status = req->errors;
916 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
917 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
919 blk_mq_free_request(req);
922 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
924 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
925 struct nvme_queue *nvmeq = iod->nvmeq;
926 struct nvme_dev *dev = nvmeq->dev;
927 struct request *abort_req;
928 struct nvme_command cmd;
931 * Shutdown immediately if controller times out while starting. The
932 * reset work will see the pci device disabled when it gets the forced
933 * cancellation error. All outstanding requests are completed on
934 * shutdown, so we return BLK_EH_HANDLED.
936 if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) {
938 "I/O %d QID %d timeout, disable controller\n",
939 req->tag, nvmeq->qid);
940 nvme_dev_disable(dev, false);
941 req->errors = NVME_SC_CANCELLED;
942 return BLK_EH_HANDLED;
946 * Shutdown the controller immediately and schedule a reset if the
947 * command was already aborted once before and still hasn't been
948 * returned to the driver, or if this is the admin queue.
950 if (!nvmeq->qid || iod->aborted) {
952 "I/O %d QID %d timeout, reset controller\n",
953 req->tag, nvmeq->qid);
954 nvme_dev_disable(dev, false);
955 queue_work(nvme_workq, &dev->reset_work);
958 * Mark the request as handled, since the inline shutdown
959 * forces all outstanding requests to complete.
961 req->errors = NVME_SC_CANCELLED;
962 return BLK_EH_HANDLED;
967 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
968 atomic_inc(&dev->ctrl.abort_limit);
969 return BLK_EH_RESET_TIMER;
972 memset(&cmd, 0, sizeof(cmd));
973 cmd.abort.opcode = nvme_admin_abort_cmd;
974 cmd.abort.cid = req->tag;
975 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
977 dev_warn(nvmeq->q_dmadev, "I/O %d QID %d timeout, aborting\n",
978 req->tag, nvmeq->qid);
980 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
982 if (IS_ERR(abort_req)) {
983 atomic_inc(&dev->ctrl.abort_limit);
984 return BLK_EH_RESET_TIMER;
987 abort_req->timeout = ADMIN_TIMEOUT;
988 abort_req->end_io_data = NULL;
989 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
992 * The aborted req will be completed on receiving the abort req.
993 * We enable the timer again. If hit twice, it'll cause a device reset,
994 * as the device then is in a faulty state.
996 return BLK_EH_RESET_TIMER;
999 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
1001 struct nvme_queue *nvmeq = data;
1004 if (!blk_mq_request_started(req))
1007 dev_dbg_ratelimited(nvmeq->q_dmadev,
1008 "Cancelling I/O %d QID %d\n", req->tag, nvmeq->qid);
1010 status = NVME_SC_ABORT_REQ;
1011 if (blk_queue_dying(req->q))
1012 status |= NVME_SC_DNR;
1013 blk_mq_complete_request(req, status);
1016 static void nvme_free_queue(struct nvme_queue *nvmeq)
1018 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1019 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1021 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1022 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1026 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1030 for (i = dev->queue_count - 1; i >= lowest; i--) {
1031 struct nvme_queue *nvmeq = dev->queues[i];
1033 dev->queues[i] = NULL;
1034 nvme_free_queue(nvmeq);
1039 * nvme_suspend_queue - put queue into suspended state
1040 * @nvmeq - queue to suspend
1042 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1046 spin_lock_irq(&nvmeq->q_lock);
1047 if (nvmeq->cq_vector == -1) {
1048 spin_unlock_irq(&nvmeq->q_lock);
1051 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1052 nvmeq->dev->online_queues--;
1053 nvmeq->cq_vector = -1;
1054 spin_unlock_irq(&nvmeq->q_lock);
1056 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1057 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
1059 irq_set_affinity_hint(vector, NULL);
1060 free_irq(vector, nvmeq);
1065 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1067 spin_lock_irq(&nvmeq->q_lock);
1068 if (nvmeq->tags && *nvmeq->tags)
1069 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1070 spin_unlock_irq(&nvmeq->q_lock);
1073 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1075 struct nvme_queue *nvmeq = dev->queues[0];
1079 if (nvme_suspend_queue(nvmeq))
1083 nvme_shutdown_ctrl(&dev->ctrl);
1085 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1086 dev->bar + NVME_REG_CAP));
1088 spin_lock_irq(&nvmeq->q_lock);
1089 nvme_process_cq(nvmeq);
1090 spin_unlock_irq(&nvmeq->q_lock);
1093 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1096 int q_depth = dev->q_depth;
1097 unsigned q_size_aligned = roundup(q_depth * entry_size,
1098 dev->ctrl.page_size);
1100 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1101 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1102 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1103 q_depth = div_u64(mem_per_q, entry_size);
1106 * Ensure the reduced q_depth is above some threshold where it
1107 * would be better to map queues in system memory with the
1117 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1120 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1121 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1122 dev->ctrl.page_size);
1123 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1124 nvmeq->sq_cmds_io = dev->cmb + offset;
1126 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1127 &nvmeq->sq_dma_addr, GFP_KERNEL);
1128 if (!nvmeq->sq_cmds)
1135 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1138 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1142 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1143 &nvmeq->cq_dma_addr, GFP_KERNEL);
1147 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1150 nvmeq->q_dmadev = dev->dev;
1152 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1153 dev->ctrl.instance, qid);
1154 spin_lock_init(&nvmeq->q_lock);
1156 nvmeq->cq_phase = 1;
1157 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1158 nvmeq->q_depth = depth;
1160 nvmeq->cq_vector = -1;
1161 dev->queues[qid] = nvmeq;
1163 /* make sure queue descriptor is set before queue count, for kthread */
1170 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1171 nvmeq->cq_dma_addr);
1177 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1180 if (use_threaded_interrupts)
1181 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1182 nvme_irq_check, nvme_irq, IRQF_SHARED,
1184 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1185 IRQF_SHARED, name, nvmeq);
1188 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1190 struct nvme_dev *dev = nvmeq->dev;
1192 spin_lock_irq(&nvmeq->q_lock);
1195 nvmeq->cq_phase = 1;
1196 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1197 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1198 dev->online_queues++;
1199 spin_unlock_irq(&nvmeq->q_lock);
1202 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1204 struct nvme_dev *dev = nvmeq->dev;
1207 nvmeq->cq_vector = qid - 1;
1208 result = adapter_alloc_cq(dev, qid, nvmeq);
1212 result = adapter_alloc_sq(dev, qid, nvmeq);
1216 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1220 nvme_init_queue(nvmeq, qid);
1224 adapter_delete_sq(dev, qid);
1226 adapter_delete_cq(dev, qid);
1230 static struct blk_mq_ops nvme_mq_admin_ops = {
1231 .queue_rq = nvme_queue_rq,
1232 .complete = nvme_complete_rq,
1233 .map_queue = blk_mq_map_queue,
1234 .init_hctx = nvme_admin_init_hctx,
1235 .exit_hctx = nvme_admin_exit_hctx,
1236 .init_request = nvme_admin_init_request,
1237 .timeout = nvme_timeout,
1240 static struct blk_mq_ops nvme_mq_ops = {
1241 .queue_rq = nvme_queue_rq,
1242 .complete = nvme_complete_rq,
1243 .map_queue = blk_mq_map_queue,
1244 .init_hctx = nvme_init_hctx,
1245 .init_request = nvme_init_request,
1246 .timeout = nvme_timeout,
1250 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1252 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1253 blk_cleanup_queue(dev->ctrl.admin_q);
1254 blk_mq_free_tag_set(&dev->admin_tagset);
1258 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1260 if (!dev->ctrl.admin_q) {
1261 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1262 dev->admin_tagset.nr_hw_queues = 1;
1265 * Subtract one to leave an empty queue entry for 'Full Queue'
1266 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1268 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1269 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1270 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1271 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1272 dev->admin_tagset.driver_data = dev;
1274 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1277 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1278 if (IS_ERR(dev->ctrl.admin_q)) {
1279 blk_mq_free_tag_set(&dev->admin_tagset);
1282 if (!blk_get_queue(dev->ctrl.admin_q)) {
1283 nvme_dev_remove_admin(dev);
1284 dev->ctrl.admin_q = NULL;
1288 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1293 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1297 u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1298 struct nvme_queue *nvmeq;
1300 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1301 NVME_CAP_NSSRC(cap) : 0;
1303 if (dev->subsystem &&
1304 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1305 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1307 result = nvme_disable_ctrl(&dev->ctrl, cap);
1311 nvmeq = dev->queues[0];
1313 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1318 aqa = nvmeq->q_depth - 1;
1321 writel(aqa, dev->bar + NVME_REG_AQA);
1322 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1323 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1325 result = nvme_enable_ctrl(&dev->ctrl, cap);
1329 nvmeq->cq_vector = 0;
1330 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1332 nvmeq->cq_vector = -1;
1339 nvme_free_queues(dev, 0);
1343 static int nvme_kthread(void *data)
1345 struct nvme_dev *dev, *next;
1347 while (!kthread_should_stop()) {
1348 set_current_state(TASK_INTERRUPTIBLE);
1349 spin_lock(&dev_list_lock);
1350 list_for_each_entry_safe(dev, next, &dev_list, node) {
1352 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1355 * Skip controllers currently under reset.
1357 if (work_pending(&dev->reset_work) || work_busy(&dev->reset_work))
1360 if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
1361 csts & NVME_CSTS_CFS) {
1362 if (queue_work(nvme_workq, &dev->reset_work)) {
1364 "Failed status: %x, reset controller\n",
1365 readl(dev->bar + NVME_REG_CSTS));
1369 for (i = 0; i < dev->queue_count; i++) {
1370 struct nvme_queue *nvmeq = dev->queues[i];
1373 spin_lock_irq(&nvmeq->q_lock);
1374 nvme_process_cq(nvmeq);
1376 while (i == 0 && dev->ctrl.event_limit > 0)
1377 nvme_submit_async_event(dev);
1378 spin_unlock_irq(&nvmeq->q_lock);
1381 spin_unlock(&dev_list_lock);
1382 schedule_timeout(round_jiffies_relative(HZ));
1387 static int nvme_create_io_queues(struct nvme_dev *dev)
1392 for (i = dev->queue_count; i <= dev->max_qid; i++) {
1393 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1399 for (i = dev->online_queues; i <= dev->queue_count - 1; i++) {
1400 ret = nvme_create_queue(dev->queues[i], i);
1402 nvme_free_queues(dev, i);
1408 * Ignore failing Create SQ/CQ commands, we can continue with less
1409 * than the desired aount of queues, and even a controller without
1410 * I/O queues an still be used to issue admin commands. This might
1411 * be useful to upgrade a buggy firmware for example.
1413 return ret >= 0 ? 0 : ret;
1416 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1418 u64 szu, size, offset;
1420 resource_size_t bar_size;
1421 struct pci_dev *pdev = to_pci_dev(dev->dev);
1423 dma_addr_t dma_addr;
1428 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1429 if (!(NVME_CMB_SZ(dev->cmbsz)))
1432 cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1434 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1435 size = szu * NVME_CMB_SZ(dev->cmbsz);
1436 offset = szu * NVME_CMB_OFST(cmbloc);
1437 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1439 if (offset > bar_size)
1443 * Controllers may support a CMB size larger than their BAR,
1444 * for example, due to being behind a bridge. Reduce the CMB to
1445 * the reported size of the BAR
1447 if (size > bar_size - offset)
1448 size = bar_size - offset;
1450 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1451 cmb = ioremap_wc(dma_addr, size);
1455 dev->cmb_dma_addr = dma_addr;
1456 dev->cmb_size = size;
1460 static inline void nvme_release_cmb(struct nvme_dev *dev)
1468 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1470 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1473 static int nvme_setup_io_queues(struct nvme_dev *dev)
1475 struct nvme_queue *adminq = dev->queues[0];
1476 struct pci_dev *pdev = to_pci_dev(dev->dev);
1477 int result, i, vecs, nr_io_queues, size;
1479 nr_io_queues = num_possible_cpus();
1480 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1485 * Degraded controllers might return an error when setting the queue
1486 * count. We still want to be able to bring them online and offer
1487 * access to the admin queue, as that might be only way to fix them up.
1490 dev_err(dev->dev, "Could not set queue count (%d)\n", result);
1495 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1496 result = nvme_cmb_qdepth(dev, nr_io_queues,
1497 sizeof(struct nvme_command));
1499 dev->q_depth = result;
1501 nvme_release_cmb(dev);
1504 size = db_bar_size(dev, nr_io_queues);
1508 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1511 if (!--nr_io_queues)
1513 size = db_bar_size(dev, nr_io_queues);
1515 dev->dbs = dev->bar + 4096;
1516 adminq->q_db = dev->dbs;
1519 /* Deregister the admin queue's interrupt */
1520 free_irq(dev->entry[0].vector, adminq);
1523 * If we enable msix early due to not intx, disable it again before
1524 * setting up the full range we need.
1527 pci_disable_msix(pdev);
1529 for (i = 0; i < nr_io_queues; i++)
1530 dev->entry[i].entry = i;
1531 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1533 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1537 for (i = 0; i < vecs; i++)
1538 dev->entry[i].vector = i + pdev->irq;
1543 * Should investigate if there's a performance win from allocating
1544 * more queues than interrupt vectors; it might allow the submission
1545 * path to scale better, even if the receive path is limited by the
1546 * number of interrupts.
1548 nr_io_queues = vecs;
1549 dev->max_qid = nr_io_queues;
1551 result = queue_request_irq(dev, adminq, adminq->irqname);
1553 adminq->cq_vector = -1;
1557 /* Free previously allocated queues that are no longer usable */
1558 nvme_free_queues(dev, nr_io_queues + 1);
1559 return nvme_create_io_queues(dev);
1562 nvme_free_queues(dev, 1);
1566 static void nvme_set_irq_hints(struct nvme_dev *dev)
1568 struct nvme_queue *nvmeq;
1571 for (i = 0; i < dev->online_queues; i++) {
1572 nvmeq = dev->queues[i];
1574 if (!nvmeq->tags || !(*nvmeq->tags))
1577 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1578 blk_mq_tags_cpumask(*nvmeq->tags));
1582 static void nvme_dev_scan(struct work_struct *work)
1584 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
1586 if (!dev->tagset.tags)
1588 nvme_scan_namespaces(&dev->ctrl);
1589 nvme_set_irq_hints(dev);
1592 static void nvme_del_queue_end(struct request *req, int error)
1594 struct nvme_queue *nvmeq = req->end_io_data;
1596 blk_mq_free_request(req);
1597 complete(&nvmeq->dev->ioq_wait);
1600 static void nvme_del_cq_end(struct request *req, int error)
1602 struct nvme_queue *nvmeq = req->end_io_data;
1605 unsigned long flags;
1607 spin_lock_irqsave(&nvmeq->q_lock, flags);
1608 nvme_process_cq(nvmeq);
1609 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1612 nvme_del_queue_end(req, error);
1615 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1617 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1618 struct request *req;
1619 struct nvme_command cmd;
1621 memset(&cmd, 0, sizeof(cmd));
1622 cmd.delete_queue.opcode = opcode;
1623 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1625 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
1627 return PTR_ERR(req);
1629 req->timeout = ADMIN_TIMEOUT;
1630 req->end_io_data = nvmeq;
1632 blk_execute_rq_nowait(q, NULL, req, false,
1633 opcode == nvme_admin_delete_cq ?
1634 nvme_del_cq_end : nvme_del_queue_end);
1638 static void nvme_disable_io_queues(struct nvme_dev *dev)
1641 unsigned long timeout;
1642 u8 opcode = nvme_admin_delete_sq;
1644 for (pass = 0; pass < 2; pass++) {
1645 int sent = 0, i = dev->queue_count - 1;
1647 reinit_completion(&dev->ioq_wait);
1649 timeout = ADMIN_TIMEOUT;
1650 for (; i > 0; i--) {
1651 struct nvme_queue *nvmeq = dev->queues[i];
1654 nvme_suspend_queue(nvmeq);
1655 if (nvme_delete_queue(nvmeq, opcode))
1660 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1666 opcode = nvme_admin_delete_cq;
1671 * Return: error value if an error occurred setting up the queues or calling
1672 * Identify Device. 0 if these succeeded, even if adding some of the
1673 * namespaces failed. At the moment, these failures are silent. TBD which
1674 * failures should be reported.
1676 static int nvme_dev_add(struct nvme_dev *dev)
1678 if (!dev->ctrl.tagset) {
1679 dev->tagset.ops = &nvme_mq_ops;
1680 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1681 dev->tagset.timeout = NVME_IO_TIMEOUT;
1682 dev->tagset.numa_node = dev_to_node(dev->dev);
1683 dev->tagset.queue_depth =
1684 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1685 dev->tagset.cmd_size = nvme_cmd_size(dev);
1686 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1687 dev->tagset.driver_data = dev;
1689 if (blk_mq_alloc_tag_set(&dev->tagset))
1691 dev->ctrl.tagset = &dev->tagset;
1693 queue_work(nvme_workq, &dev->scan_work);
1697 static int nvme_dev_map(struct nvme_dev *dev)
1700 int bars, result = -ENOMEM;
1701 struct pci_dev *pdev = to_pci_dev(dev->dev);
1703 if (pci_enable_device_mem(pdev))
1706 dev->entry[0].vector = pdev->irq;
1707 pci_set_master(pdev);
1708 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1712 if (pci_request_selected_regions(pdev, bars, "nvme"))
1715 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1716 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1719 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1723 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1729 * Some devices don't advertse INTx interrupts, pre-enable a single
1730 * MSIX vec for setup. We'll adjust this later.
1733 result = pci_enable_msix(pdev, dev->entry, 1);
1738 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1740 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1741 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1742 dev->dbs = dev->bar + 4096;
1745 * Temporary fix for the Apple controller found in the MacBook8,1 and
1746 * some MacBook7,1 to avoid controller resets and data loss.
1748 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1750 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1751 "queue depth=%u to work around controller resets\n",
1755 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1756 dev->cmb = nvme_map_cmb(dev);
1758 pci_enable_pcie_error_reporting(pdev);
1759 pci_save_state(pdev);
1766 pci_release_regions(pdev);
1768 pci_disable_device(pdev);
1772 static void nvme_dev_unmap(struct nvme_dev *dev)
1774 struct pci_dev *pdev = to_pci_dev(dev->dev);
1776 if (pdev->msi_enabled)
1777 pci_disable_msi(pdev);
1778 else if (pdev->msix_enabled)
1779 pci_disable_msix(pdev);
1784 pci_release_regions(pdev);
1787 if (pci_is_enabled(pdev)) {
1788 pci_disable_pcie_error_reporting(pdev);
1789 pci_disable_device(pdev);
1793 static int nvme_dev_list_add(struct nvme_dev *dev)
1795 bool start_thread = false;
1797 spin_lock(&dev_list_lock);
1798 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
1799 start_thread = true;
1802 list_add(&dev->node, &dev_list);
1803 spin_unlock(&dev_list_lock);
1806 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1807 wake_up_all(&nvme_kthread_wait);
1809 wait_event_killable(nvme_kthread_wait, nvme_thread);
1811 if (IS_ERR_OR_NULL(nvme_thread))
1812 return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
1818 * Remove the node from the device list and check
1819 * for whether or not we need to stop the nvme_thread.
1821 static void nvme_dev_list_remove(struct nvme_dev *dev)
1823 struct task_struct *tmp = NULL;
1825 spin_lock(&dev_list_lock);
1826 list_del_init(&dev->node);
1827 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
1831 spin_unlock(&dev_list_lock);
1837 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1842 nvme_dev_list_remove(dev);
1844 mutex_lock(&dev->shutdown_lock);
1846 nvme_stop_queues(&dev->ctrl);
1847 csts = readl(dev->bar + NVME_REG_CSTS);
1849 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1850 for (i = dev->queue_count - 1; i >= 0; i--) {
1851 struct nvme_queue *nvmeq = dev->queues[i];
1852 nvme_suspend_queue(nvmeq);
1855 nvme_disable_io_queues(dev);
1856 nvme_disable_admin_queue(dev, shutdown);
1858 nvme_dev_unmap(dev);
1860 for (i = dev->queue_count - 1; i >= 0; i--)
1861 nvme_clear_queue(dev->queues[i]);
1862 mutex_unlock(&dev->shutdown_lock);
1865 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1867 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1868 PAGE_SIZE, PAGE_SIZE, 0);
1869 if (!dev->prp_page_pool)
1872 /* Optimisation for I/Os between 4k and 128k */
1873 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1875 if (!dev->prp_small_pool) {
1876 dma_pool_destroy(dev->prp_page_pool);
1882 static void nvme_release_prp_pools(struct nvme_dev *dev)
1884 dma_pool_destroy(dev->prp_page_pool);
1885 dma_pool_destroy(dev->prp_small_pool);
1888 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1890 struct nvme_dev *dev = to_nvme_dev(ctrl);
1892 put_device(dev->dev);
1893 if (dev->tagset.tags)
1894 blk_mq_free_tag_set(&dev->tagset);
1895 if (dev->ctrl.admin_q)
1896 blk_put_queue(dev->ctrl.admin_q);
1902 static void nvme_reset_work(struct work_struct *work)
1904 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1907 if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags)))
1911 * If we're called to reset a live controller first shut it down before
1915 nvme_dev_disable(dev, false);
1917 set_bit(NVME_CTRL_RESETTING, &dev->flags);
1919 result = nvme_dev_map(dev);
1923 result = nvme_configure_admin_queue(dev);
1927 nvme_init_queue(dev->queues[0], 0);
1928 result = nvme_alloc_admin_tags(dev);
1932 result = nvme_init_identify(&dev->ctrl);
1936 result = nvme_setup_io_queues(dev);
1940 dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS;
1942 result = nvme_dev_list_add(dev);
1947 * Keep the controller around but remove all namespaces if we don't have
1948 * any working I/O queue.
1950 if (dev->online_queues < 2) {
1951 dev_warn(dev->dev, "IO queues not created\n");
1952 nvme_remove_namespaces(&dev->ctrl);
1954 nvme_start_queues(&dev->ctrl);
1958 clear_bit(NVME_CTRL_RESETTING, &dev->flags);
1962 nvme_dev_list_remove(dev);
1964 nvme_dev_remove_admin(dev);
1965 blk_put_queue(dev->ctrl.admin_q);
1966 dev->ctrl.admin_q = NULL;
1967 dev->queues[0]->tags = NULL;
1969 nvme_disable_admin_queue(dev, false);
1971 nvme_dev_unmap(dev);
1973 nvme_remove_dead_ctrl(dev);
1976 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1978 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1979 struct pci_dev *pdev = to_pci_dev(dev->dev);
1981 if (pci_get_drvdata(pdev))
1982 pci_stop_and_remove_bus_device_locked(pdev);
1983 nvme_put_ctrl(&dev->ctrl);
1986 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
1988 dev_warn(dev->dev, "Removing after probe failure\n");
1989 kref_get(&dev->ctrl.kref);
1990 if (!schedule_work(&dev->remove_work))
1991 nvme_put_ctrl(&dev->ctrl);
1994 static int nvme_reset(struct nvme_dev *dev)
1996 if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1999 if (!queue_work(nvme_workq, &dev->reset_work))
2002 flush_work(&dev->reset_work);
2006 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2008 *val = readl(to_nvme_dev(ctrl)->bar + off);
2012 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2014 writel(val, to_nvme_dev(ctrl)->bar + off);
2018 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2020 *val = readq(to_nvme_dev(ctrl)->bar + off);
2024 static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl)
2026 struct nvme_dev *dev = to_nvme_dev(ctrl);
2028 return !dev->bar || dev->online_queues < 2;
2031 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
2033 return nvme_reset(to_nvme_dev(ctrl));
2036 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2037 .reg_read32 = nvme_pci_reg_read32,
2038 .reg_write32 = nvme_pci_reg_write32,
2039 .reg_read64 = nvme_pci_reg_read64,
2040 .io_incapable = nvme_pci_io_incapable,
2041 .reset_ctrl = nvme_pci_reset_ctrl,
2042 .free_ctrl = nvme_pci_free_ctrl,
2045 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2047 int node, result = -ENOMEM;
2048 struct nvme_dev *dev;
2050 node = dev_to_node(&pdev->dev);
2051 if (node == NUMA_NO_NODE)
2052 set_dev_node(&pdev->dev, 0);
2054 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2057 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2061 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2066 dev->dev = get_device(&pdev->dev);
2067 pci_set_drvdata(pdev, dev);
2069 INIT_LIST_HEAD(&dev->node);
2070 INIT_WORK(&dev->scan_work, nvme_dev_scan);
2071 INIT_WORK(&dev->reset_work, nvme_reset_work);
2072 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2073 mutex_init(&dev->shutdown_lock);
2074 init_completion(&dev->ioq_wait);
2076 result = nvme_setup_prp_pools(dev);
2080 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2085 queue_work(nvme_workq, &dev->reset_work);
2089 nvme_release_prp_pools(dev);
2091 put_device(dev->dev);
2099 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2101 struct nvme_dev *dev = pci_get_drvdata(pdev);
2104 nvme_dev_disable(dev, false);
2106 queue_work(nvme_workq, &dev->reset_work);
2109 static void nvme_shutdown(struct pci_dev *pdev)
2111 struct nvme_dev *dev = pci_get_drvdata(pdev);
2112 nvme_dev_disable(dev, true);
2115 static void nvme_remove(struct pci_dev *pdev)
2117 struct nvme_dev *dev = pci_get_drvdata(pdev);
2119 pci_set_drvdata(pdev, NULL);
2120 flush_work(&dev->scan_work);
2121 nvme_remove_namespaces(&dev->ctrl);
2122 nvme_uninit_ctrl(&dev->ctrl);
2123 nvme_dev_disable(dev, true);
2124 flush_work(&dev->reset_work);
2125 nvme_dev_remove_admin(dev);
2126 nvme_free_queues(dev, 0);
2127 nvme_release_cmb(dev);
2128 nvme_release_prp_pools(dev);
2129 nvme_put_ctrl(&dev->ctrl);
2132 #ifdef CONFIG_PM_SLEEP
2133 static int nvme_suspend(struct device *dev)
2135 struct pci_dev *pdev = to_pci_dev(dev);
2136 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2138 nvme_dev_disable(ndev, true);
2142 static int nvme_resume(struct device *dev)
2144 struct pci_dev *pdev = to_pci_dev(dev);
2145 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2147 queue_work(nvme_workq, &ndev->reset_work);
2152 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2154 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2155 pci_channel_state_t state)
2157 struct nvme_dev *dev = pci_get_drvdata(pdev);
2160 * A frozen channel requires a reset. When detected, this method will
2161 * shutdown the controller to quiesce. The controller will be restarted
2162 * after the slot reset through driver's slot_reset callback.
2164 dev_warn(&pdev->dev, "error detected: state:%d\n", state);
2166 case pci_channel_io_normal:
2167 return PCI_ERS_RESULT_CAN_RECOVER;
2168 case pci_channel_io_frozen:
2169 nvme_dev_disable(dev, false);
2170 return PCI_ERS_RESULT_NEED_RESET;
2171 case pci_channel_io_perm_failure:
2172 return PCI_ERS_RESULT_DISCONNECT;
2174 return PCI_ERS_RESULT_NEED_RESET;
2177 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2179 struct nvme_dev *dev = pci_get_drvdata(pdev);
2181 dev_info(&pdev->dev, "restart after slot reset\n");
2182 pci_restore_state(pdev);
2183 queue_work(nvme_workq, &dev->reset_work);
2184 return PCI_ERS_RESULT_RECOVERED;
2187 static void nvme_error_resume(struct pci_dev *pdev)
2189 pci_cleanup_aer_uncorrect_error_status(pdev);
2192 static const struct pci_error_handlers nvme_err_handler = {
2193 .error_detected = nvme_error_detected,
2194 .slot_reset = nvme_slot_reset,
2195 .resume = nvme_error_resume,
2196 .reset_notify = nvme_reset_notify,
2199 /* Move to pci_ids.h later */
2200 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2202 static const struct pci_device_id nvme_id_table[] = {
2203 { PCI_VDEVICE(INTEL, 0x0953),
2204 .driver_data = NVME_QUIRK_STRIPE_SIZE, },
2205 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2206 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2207 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2208 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2211 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2213 static struct pci_driver nvme_driver = {
2215 .id_table = nvme_id_table,
2216 .probe = nvme_probe,
2217 .remove = nvme_remove,
2218 .shutdown = nvme_shutdown,
2220 .pm = &nvme_dev_pm_ops,
2222 .err_handler = &nvme_err_handler,
2225 static int __init nvme_init(void)
2229 init_waitqueue_head(&nvme_kthread_wait);
2231 nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2235 result = nvme_core_init();
2239 result = pci_register_driver(&nvme_driver);
2247 destroy_workqueue(nvme_workq);
2251 static void __exit nvme_exit(void)
2253 pci_unregister_driver(&nvme_driver);
2255 destroy_workqueue(nvme_workq);
2256 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
2260 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2261 MODULE_LICENSE("GPL");
2262 MODULE_VERSION("1.0");
2263 module_init(nvme_init);
2264 module_exit(nvme_exit);