1 // SPDX-License-Identifier: GPL-2.0
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/dmi.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/once.h>
20 #include <linux/pci.h>
21 #include <linux/suspend.h>
22 #include <linux/t10-pi.h>
23 #include <linux/types.h>
24 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <linux/sed-opal.h>
26 #include <linux/pci-p2pdma.h>
31 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
32 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
37 * These can be higher, but we need to ensure that any command doesn't
38 * require an sg allocation that needs more than a page of data.
40 #define NVME_MAX_KB_SZ 4096
41 #define NVME_MAX_SEGS 127
43 static int use_threaded_interrupts;
44 module_param(use_threaded_interrupts, int, 0);
46 static bool use_cmb_sqes = true;
47 module_param(use_cmb_sqes, bool, 0444);
48 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
50 static unsigned int max_host_mem_size_mb = 128;
51 module_param(max_host_mem_size_mb, uint, 0444);
52 MODULE_PARM_DESC(max_host_mem_size_mb,
53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
55 static unsigned int sgl_threshold = SZ_32K;
56 module_param(sgl_threshold, uint, 0644);
57 MODULE_PARM_DESC(sgl_threshold,
58 "Use SGLs when average request segment size is larger or equal to "
59 "this size. Use 0 to disable SGLs.");
61 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
62 static const struct kernel_param_ops io_queue_depth_ops = {
63 .set = io_queue_depth_set,
67 static int io_queue_depth = 1024;
68 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
69 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
71 static int write_queues;
72 module_param(write_queues, int, 0644);
73 MODULE_PARM_DESC(write_queues,
74 "Number of queues to use for writes. If not set, reads and writes "
75 "will share a queue set.");
77 static int poll_queues;
78 module_param(poll_queues, int, 0644);
79 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
84 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
85 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
88 * Represents an NVM Express device. Each nvme_dev is a PCI function.
91 struct nvme_queue *queues;
92 struct blk_mq_tag_set tagset;
93 struct blk_mq_tag_set admin_tagset;
96 struct dma_pool *prp_page_pool;
97 struct dma_pool *prp_small_pool;
98 unsigned online_queues;
100 unsigned io_queues[HCTX_MAX_TYPES];
101 unsigned int num_vecs;
105 unsigned long bar_mapped_size;
106 struct work_struct remove_work;
107 struct mutex shutdown_lock;
113 struct nvme_ctrl ctrl;
116 mempool_t *iod_mempool;
118 /* shadow doorbell buffer support: */
120 dma_addr_t dbbuf_dbs_dma_addr;
122 dma_addr_t dbbuf_eis_dma_addr;
124 /* host memory buffer support: */
126 u32 nr_host_mem_descs;
127 dma_addr_t host_mem_descs_dma;
128 struct nvme_host_mem_buf_desc *host_mem_descs;
129 void **host_mem_desc_bufs;
132 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
136 ret = kstrtoint(val, 10, &n);
137 if (ret != 0 || n < 2)
140 return param_set_int(val, kp);
143 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
145 return qid * 2 * stride;
148 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
150 return (qid * 2 + 1) * stride;
153 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
155 return container_of(ctrl, struct nvme_dev, ctrl);
159 * An NVM Express queue. Each device has at least two (one for admin
160 * commands and one for I/O commands).
163 struct nvme_dev *dev;
165 struct nvme_command *sq_cmds;
166 /* only used for poll queues: */
167 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
168 volatile struct nvme_completion *cqes;
169 struct blk_mq_tags **tags;
170 dma_addr_t sq_dma_addr;
171 dma_addr_t cq_dma_addr;
182 #define NVMEQ_ENABLED 0
183 #define NVMEQ_SQ_CMB 1
184 #define NVMEQ_DELETE_ERROR 2
185 #define NVMEQ_POLLED 3
190 struct completion delete_done;
194 * The nvme_iod describes the data in an I/O.
196 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
197 * to the actual struct scatterlist.
200 struct nvme_request req;
201 struct nvme_queue *nvmeq;
204 int npages; /* In the PRP list. 0 means small pool in use */
205 int nents; /* Used in scatterlist */
206 dma_addr_t first_dma;
207 unsigned int dma_len; /* length of single DMA segment mapping */
209 struct scatterlist *sg;
212 static unsigned int max_io_queues(void)
214 return num_possible_cpus() + write_queues + poll_queues;
217 static unsigned int max_queue_count(void)
219 /* IO queues + admin queue */
220 return 1 + max_io_queues();
223 static inline unsigned int nvme_dbbuf_size(u32 stride)
225 return (max_queue_count() * 8 * stride);
228 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
230 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
235 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
236 &dev->dbbuf_dbs_dma_addr,
240 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
241 &dev->dbbuf_eis_dma_addr,
243 if (!dev->dbbuf_eis) {
244 dma_free_coherent(dev->dev, mem_size,
245 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
246 dev->dbbuf_dbs = NULL;
253 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
255 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
257 if (dev->dbbuf_dbs) {
258 dma_free_coherent(dev->dev, mem_size,
259 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
260 dev->dbbuf_dbs = NULL;
262 if (dev->dbbuf_eis) {
263 dma_free_coherent(dev->dev, mem_size,
264 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
265 dev->dbbuf_eis = NULL;
269 static void nvme_dbbuf_init(struct nvme_dev *dev,
270 struct nvme_queue *nvmeq, int qid)
272 if (!dev->dbbuf_dbs || !qid)
275 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
276 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
277 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
278 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
281 static void nvme_dbbuf_set(struct nvme_dev *dev)
283 struct nvme_command c;
288 memset(&c, 0, sizeof(c));
289 c.dbbuf.opcode = nvme_admin_dbbuf;
290 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
291 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
293 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
294 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
295 /* Free memory and continue on */
296 nvme_dbbuf_dma_free(dev);
300 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
302 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
305 /* Update dbbuf and return true if an MMIO is required */
306 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
307 volatile u32 *dbbuf_ei)
313 * Ensure that the queue is written before updating
314 * the doorbell in memory
318 old_value = *dbbuf_db;
322 * Ensure that the doorbell is updated before reading the event
323 * index from memory. The controller needs to provide similar
324 * ordering to ensure the envent index is updated before reading
329 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
337 * Will slightly overestimate the number of pages needed. This is OK
338 * as it only leads to a small amount of wasted memory for the lifetime of
341 static int nvme_npages(unsigned size, struct nvme_dev *dev)
343 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
344 dev->ctrl.page_size);
345 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
349 * Calculates the number of pages needed for the SGL segments. For example a 4k
350 * page can accommodate 256 SGL descriptors.
352 static int nvme_pci_npages_sgl(unsigned int num_seg)
354 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
357 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
358 unsigned int size, unsigned int nseg, bool use_sgl)
363 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
365 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
367 return alloc_size + sizeof(struct scatterlist) * nseg;
370 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
371 unsigned int hctx_idx)
373 struct nvme_dev *dev = data;
374 struct nvme_queue *nvmeq = &dev->queues[0];
376 WARN_ON(hctx_idx != 0);
377 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
378 WARN_ON(nvmeq->tags);
380 hctx->driver_data = nvmeq;
381 nvmeq->tags = &dev->admin_tagset.tags[0];
385 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
387 struct nvme_queue *nvmeq = hctx->driver_data;
392 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
393 unsigned int hctx_idx)
395 struct nvme_dev *dev = data;
396 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
399 nvmeq->tags = &dev->tagset.tags[hctx_idx];
401 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
402 hctx->driver_data = nvmeq;
406 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
407 unsigned int hctx_idx, unsigned int numa_node)
409 struct nvme_dev *dev = set->driver_data;
410 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
411 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
412 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
417 nvme_req(req)->ctrl = &dev->ctrl;
421 static int queue_irq_offset(struct nvme_dev *dev)
423 /* if we have more than 1 vec, admin queue offsets us by 1 */
424 if (dev->num_vecs > 1)
430 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
432 struct nvme_dev *dev = set->driver_data;
435 offset = queue_irq_offset(dev);
436 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
437 struct blk_mq_queue_map *map = &set->map[i];
439 map->nr_queues = dev->io_queues[i];
440 if (!map->nr_queues) {
441 BUG_ON(i == HCTX_TYPE_DEFAULT);
446 * The poll queue(s) doesn't have an IRQ (and hence IRQ
447 * affinity), so use the regular blk-mq cpu mapping
449 map->queue_offset = qoff;
450 if (i != HCTX_TYPE_POLL && offset)
451 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
453 blk_mq_map_queues(map);
454 qoff += map->nr_queues;
455 offset += map->nr_queues;
462 * Write sq tail if we are asked to, or if the next command would wrap.
464 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
467 u16 next_tail = nvmeq->sq_tail + 1;
469 if (next_tail == nvmeq->q_depth)
471 if (next_tail != nvmeq->last_sq_tail)
475 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
476 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
477 writel(nvmeq->sq_tail, nvmeq->q_db);
478 nvmeq->last_sq_tail = nvmeq->sq_tail;
482 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
483 * @nvmeq: The queue to use
484 * @cmd: The command to send
485 * @write_sq: whether to write to the SQ doorbell
487 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
490 spin_lock(&nvmeq->sq_lock);
491 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
492 if (++nvmeq->sq_tail == nvmeq->q_depth)
494 nvme_write_sq_db(nvmeq, write_sq);
495 spin_unlock(&nvmeq->sq_lock);
498 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
500 struct nvme_queue *nvmeq = hctx->driver_data;
502 spin_lock(&nvmeq->sq_lock);
503 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
504 nvme_write_sq_db(nvmeq, true);
505 spin_unlock(&nvmeq->sq_lock);
508 static void **nvme_pci_iod_list(struct request *req)
510 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
511 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
514 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
516 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
517 int nseg = blk_rq_nr_phys_segments(req);
518 unsigned int avg_seg_size;
523 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
525 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
527 if (!iod->nvmeq->qid)
529 if (!sgl_threshold || avg_seg_size < sgl_threshold)
534 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
536 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
537 enum dma_data_direction dma_dir = rq_data_dir(req) ?
538 DMA_TO_DEVICE : DMA_FROM_DEVICE;
539 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
540 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
544 dma_unmap_page(dev->dev, dma_addr, iod->dma_len, dma_dir);
548 WARN_ON_ONCE(!iod->nents);
550 /* P2PDMA requests do not need to be unmapped */
551 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
552 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
555 if (iod->npages == 0)
556 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
559 for (i = 0; i < iod->npages; i++) {
560 void *addr = nvme_pci_iod_list(req)[i];
563 struct nvme_sgl_desc *sg_list = addr;
566 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
568 __le64 *prp_list = addr;
570 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
573 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
574 dma_addr = next_dma_addr;
577 mempool_free(iod->sg, dev->iod_mempool);
580 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
583 struct scatterlist *sg;
585 for_each_sg(sgl, sg, nents, i) {
586 dma_addr_t phys = sg_phys(sg);
587 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
588 "dma_address:%pad dma_length:%d\n",
589 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
594 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
595 struct request *req, struct nvme_rw_command *cmnd)
597 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
598 struct dma_pool *pool;
599 int length = blk_rq_payload_bytes(req);
600 struct scatterlist *sg = iod->sg;
601 int dma_len = sg_dma_len(sg);
602 u64 dma_addr = sg_dma_address(sg);
603 u32 page_size = dev->ctrl.page_size;
604 int offset = dma_addr & (page_size - 1);
606 void **list = nvme_pci_iod_list(req);
610 length -= (page_size - offset);
616 dma_len -= (page_size - offset);
618 dma_addr += (page_size - offset);
621 dma_addr = sg_dma_address(sg);
622 dma_len = sg_dma_len(sg);
625 if (length <= page_size) {
626 iod->first_dma = dma_addr;
630 nprps = DIV_ROUND_UP(length, page_size);
631 if (nprps <= (256 / 8)) {
632 pool = dev->prp_small_pool;
635 pool = dev->prp_page_pool;
639 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
641 iod->first_dma = dma_addr;
643 return BLK_STS_RESOURCE;
646 iod->first_dma = prp_dma;
649 if (i == page_size >> 3) {
650 __le64 *old_prp_list = prp_list;
651 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
653 return BLK_STS_RESOURCE;
654 list[iod->npages++] = prp_list;
655 prp_list[0] = old_prp_list[i - 1];
656 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
659 prp_list[i++] = cpu_to_le64(dma_addr);
660 dma_len -= page_size;
661 dma_addr += page_size;
667 if (unlikely(dma_len < 0))
670 dma_addr = sg_dma_address(sg);
671 dma_len = sg_dma_len(sg);
675 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
676 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
681 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
682 "Invalid SGL for payload:%d nents:%d\n",
683 blk_rq_payload_bytes(req), iod->nents);
684 return BLK_STS_IOERR;
687 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
688 struct scatterlist *sg)
690 sge->addr = cpu_to_le64(sg_dma_address(sg));
691 sge->length = cpu_to_le32(sg_dma_len(sg));
692 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
695 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
696 dma_addr_t dma_addr, int entries)
698 sge->addr = cpu_to_le64(dma_addr);
699 if (entries < SGES_PER_PAGE) {
700 sge->length = cpu_to_le32(entries * sizeof(*sge));
701 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
703 sge->length = cpu_to_le32(PAGE_SIZE);
704 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
708 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
709 struct request *req, struct nvme_rw_command *cmd, int entries)
711 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
712 struct dma_pool *pool;
713 struct nvme_sgl_desc *sg_list;
714 struct scatterlist *sg = iod->sg;
718 /* setting the transfer type as SGL */
719 cmd->flags = NVME_CMD_SGL_METABUF;
722 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
726 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
727 pool = dev->prp_small_pool;
730 pool = dev->prp_page_pool;
734 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
737 return BLK_STS_RESOURCE;
740 nvme_pci_iod_list(req)[0] = sg_list;
741 iod->first_dma = sgl_dma;
743 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
746 if (i == SGES_PER_PAGE) {
747 struct nvme_sgl_desc *old_sg_desc = sg_list;
748 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
750 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
752 return BLK_STS_RESOURCE;
755 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
756 sg_list[i++] = *link;
757 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
760 nvme_pci_sgl_set_data(&sg_list[i++], sg);
762 } while (--entries > 0);
767 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
768 struct request *req, struct nvme_rw_command *cmnd,
771 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
772 unsigned int first_prp_len = dev->ctrl.page_size - bv->bv_offset;
774 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
775 if (dma_mapping_error(dev->dev, iod->first_dma))
776 return BLK_STS_RESOURCE;
777 iod->dma_len = bv->bv_len;
779 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
780 if (bv->bv_len > first_prp_len)
781 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
785 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
786 struct request *req, struct nvme_rw_command *cmnd,
789 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
791 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
792 if (dma_mapping_error(dev->dev, iod->first_dma))
793 return BLK_STS_RESOURCE;
794 iod->dma_len = bv->bv_len;
796 cmnd->flags = NVME_CMD_SGL_METABUF;
797 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
798 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
799 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
803 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
804 struct nvme_command *cmnd)
806 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
807 blk_status_t ret = BLK_STS_RESOURCE;
810 if (blk_rq_nr_phys_segments(req) == 1) {
811 struct bio_vec bv = req_bvec(req);
813 if (!is_pci_p2pdma_page(bv.bv_page)) {
814 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
815 return nvme_setup_prp_simple(dev, req,
818 if (iod->nvmeq->qid &&
819 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
820 return nvme_setup_sgl_simple(dev, req,
826 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
828 return BLK_STS_RESOURCE;
829 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
830 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
834 if (is_pci_p2pdma_page(sg_page(iod->sg)))
835 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
838 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
839 rq_dma_dir(req), DMA_ATTR_NO_WARN);
843 iod->use_sgl = nvme_pci_use_sgls(dev, req);
845 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
847 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
849 if (ret != BLK_STS_OK)
850 nvme_unmap_data(dev, req);
854 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
855 struct nvme_command *cmnd)
857 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
859 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
861 if (dma_mapping_error(dev->dev, iod->meta_dma))
862 return BLK_STS_IOERR;
863 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
868 * NOTE: ns is NULL when called on the admin queue.
870 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
871 const struct blk_mq_queue_data *bd)
873 struct nvme_ns *ns = hctx->queue->queuedata;
874 struct nvme_queue *nvmeq = hctx->driver_data;
875 struct nvme_dev *dev = nvmeq->dev;
876 struct request *req = bd->rq;
877 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
878 struct nvme_command cmnd;
886 * We should not need to do this, but we're still using this to
887 * ensure we can drain requests on a dying queue.
889 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
890 return BLK_STS_IOERR;
892 ret = nvme_setup_cmd(ns, req, &cmnd);
896 if (blk_rq_nr_phys_segments(req)) {
897 ret = nvme_map_data(dev, req, &cmnd);
902 if (blk_integrity_rq(req)) {
903 ret = nvme_map_metadata(dev, req, &cmnd);
908 blk_mq_start_request(req);
909 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
912 nvme_unmap_data(dev, req);
914 nvme_cleanup_cmd(req);
918 static void nvme_pci_complete_rq(struct request *req)
920 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
921 struct nvme_dev *dev = iod->nvmeq->dev;
923 nvme_cleanup_cmd(req);
924 if (blk_integrity_rq(req))
925 dma_unmap_page(dev->dev, iod->meta_dma,
926 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
927 if (blk_rq_nr_phys_segments(req))
928 nvme_unmap_data(dev, req);
929 nvme_complete_rq(req);
932 /* We read the CQE phase first to check if the rest of the entry is valid */
933 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
935 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
939 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
941 u16 head = nvmeq->cq_head;
943 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
945 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
948 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
950 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
953 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
954 dev_warn(nvmeq->dev->ctrl.device,
955 "invalid id %d completed on queue %d\n",
956 cqe->command_id, le16_to_cpu(cqe->sq_id));
961 * AEN requests are special as they don't time out and can
962 * survive any kind of queue freeze and often don't respond to
963 * aborts. We don't even bother to allocate a struct request
964 * for them but rather special case them here.
966 if (unlikely(nvmeq->qid == 0 &&
967 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
968 nvme_complete_async_event(&nvmeq->dev->ctrl,
969 cqe->status, &cqe->result);
973 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
974 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
975 nvme_end_request(req, cqe->status, cqe->result);
978 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
980 while (start != end) {
981 nvme_handle_cqe(nvmeq, start);
982 if (++start == nvmeq->q_depth)
987 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
989 if (nvmeq->cq_head == nvmeq->q_depth - 1) {
991 nvmeq->cq_phase = !nvmeq->cq_phase;
997 static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
998 u16 *end, unsigned int tag)
1002 *start = nvmeq->cq_head;
1003 while (nvme_cqe_pending(nvmeq)) {
1004 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1006 nvme_update_cq_head(nvmeq);
1008 *end = nvmeq->cq_head;
1011 nvme_ring_cq_doorbell(nvmeq);
1015 static irqreturn_t nvme_irq(int irq, void *data)
1017 struct nvme_queue *nvmeq = data;
1018 irqreturn_t ret = IRQ_NONE;
1022 * The rmb/wmb pair ensures we see all updates from a previous run of
1023 * the irq handler, even if that was on another CPU.
1026 if (nvmeq->cq_head != nvmeq->last_cq_head)
1028 nvme_process_cq(nvmeq, &start, &end, -1);
1029 nvmeq->last_cq_head = nvmeq->cq_head;
1033 nvme_complete_cqes(nvmeq, start, end);
1040 static irqreturn_t nvme_irq_check(int irq, void *data)
1042 struct nvme_queue *nvmeq = data;
1043 if (nvme_cqe_pending(nvmeq))
1044 return IRQ_WAKE_THREAD;
1049 * Poll for completions any queue, including those not dedicated to polling.
1050 * Can be called from any context.
1052 static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
1054 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1059 * For a poll queue we need to protect against the polling thread
1060 * using the CQ lock. For normal interrupt driven threads we have
1061 * to disable the interrupt to avoid racing with it.
1063 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) {
1064 spin_lock(&nvmeq->cq_poll_lock);
1065 found = nvme_process_cq(nvmeq, &start, &end, tag);
1066 spin_unlock(&nvmeq->cq_poll_lock);
1068 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1069 found = nvme_process_cq(nvmeq, &start, &end, tag);
1070 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1073 nvme_complete_cqes(nvmeq, start, end);
1077 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1079 struct nvme_queue *nvmeq = hctx->driver_data;
1083 if (!nvme_cqe_pending(nvmeq))
1086 spin_lock(&nvmeq->cq_poll_lock);
1087 found = nvme_process_cq(nvmeq, &start, &end, -1);
1088 spin_unlock(&nvmeq->cq_poll_lock);
1090 nvme_complete_cqes(nvmeq, start, end);
1094 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1096 struct nvme_dev *dev = to_nvme_dev(ctrl);
1097 struct nvme_queue *nvmeq = &dev->queues[0];
1098 struct nvme_command c;
1100 memset(&c, 0, sizeof(c));
1101 c.common.opcode = nvme_admin_async_event;
1102 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1103 nvme_submit_cmd(nvmeq, &c, true);
1106 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1108 struct nvme_command c;
1110 memset(&c, 0, sizeof(c));
1111 c.delete_queue.opcode = opcode;
1112 c.delete_queue.qid = cpu_to_le16(id);
1114 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1117 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1118 struct nvme_queue *nvmeq, s16 vector)
1120 struct nvme_command c;
1121 int flags = NVME_QUEUE_PHYS_CONTIG;
1123 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1124 flags |= NVME_CQ_IRQ_ENABLED;
1127 * Note: we (ab)use the fact that the prp fields survive if no data
1128 * is attached to the request.
1130 memset(&c, 0, sizeof(c));
1131 c.create_cq.opcode = nvme_admin_create_cq;
1132 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1133 c.create_cq.cqid = cpu_to_le16(qid);
1134 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1135 c.create_cq.cq_flags = cpu_to_le16(flags);
1136 c.create_cq.irq_vector = cpu_to_le16(vector);
1138 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1141 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1142 struct nvme_queue *nvmeq)
1144 struct nvme_ctrl *ctrl = &dev->ctrl;
1145 struct nvme_command c;
1146 int flags = NVME_QUEUE_PHYS_CONTIG;
1149 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1150 * set. Since URGENT priority is zeroes, it makes all queues
1153 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1154 flags |= NVME_SQ_PRIO_MEDIUM;
1157 * Note: we (ab)use the fact that the prp fields survive if no data
1158 * is attached to the request.
1160 memset(&c, 0, sizeof(c));
1161 c.create_sq.opcode = nvme_admin_create_sq;
1162 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1163 c.create_sq.sqid = cpu_to_le16(qid);
1164 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1165 c.create_sq.sq_flags = cpu_to_le16(flags);
1166 c.create_sq.cqid = cpu_to_le16(qid);
1168 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1171 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1173 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1176 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1178 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1181 static void abort_endio(struct request *req, blk_status_t error)
1183 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1184 struct nvme_queue *nvmeq = iod->nvmeq;
1186 dev_warn(nvmeq->dev->ctrl.device,
1187 "Abort status: 0x%x", nvme_req(req)->status);
1188 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1189 blk_mq_free_request(req);
1192 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1195 /* If true, indicates loss of adapter communication, possibly by a
1196 * NVMe Subsystem reset.
1198 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1200 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1201 switch (dev->ctrl.state) {
1202 case NVME_CTRL_RESETTING:
1203 case NVME_CTRL_CONNECTING:
1209 /* We shouldn't reset unless the controller is on fatal error state
1210 * _or_ if we lost the communication with it.
1212 if (!(csts & NVME_CSTS_CFS) && !nssro)
1218 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1220 /* Read a config register to help see what died. */
1224 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1226 if (result == PCIBIOS_SUCCESSFUL)
1227 dev_warn(dev->ctrl.device,
1228 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1231 dev_warn(dev->ctrl.device,
1232 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1236 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1238 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1239 struct nvme_queue *nvmeq = iod->nvmeq;
1240 struct nvme_dev *dev = nvmeq->dev;
1241 struct request *abort_req;
1242 struct nvme_command cmd;
1243 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1245 /* If PCI error recovery process is happening, we cannot reset or
1246 * the recovery mechanism will surely fail.
1249 if (pci_channel_offline(to_pci_dev(dev->dev)))
1250 return BLK_EH_RESET_TIMER;
1253 * Reset immediately if the controller is failed
1255 if (nvme_should_reset(dev, csts)) {
1256 nvme_warn_reset(dev, csts);
1257 nvme_dev_disable(dev, false);
1258 nvme_reset_ctrl(&dev->ctrl);
1263 * Did we miss an interrupt?
1265 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
1266 dev_warn(dev->ctrl.device,
1267 "I/O %d QID %d timeout, completion polled\n",
1268 req->tag, nvmeq->qid);
1273 * Shutdown immediately if controller times out while starting. The
1274 * reset work will see the pci device disabled when it gets the forced
1275 * cancellation error. All outstanding requests are completed on
1276 * shutdown, so we return BLK_EH_DONE.
1278 switch (dev->ctrl.state) {
1279 case NVME_CTRL_CONNECTING:
1280 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1282 case NVME_CTRL_DELETING:
1283 dev_warn_ratelimited(dev->ctrl.device,
1284 "I/O %d QID %d timeout, disable controller\n",
1285 req->tag, nvmeq->qid);
1286 nvme_dev_disable(dev, true);
1287 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1289 case NVME_CTRL_RESETTING:
1290 return BLK_EH_RESET_TIMER;
1296 * Shutdown the controller immediately and schedule a reset if the
1297 * command was already aborted once before and still hasn't been
1298 * returned to the driver, or if this is the admin queue.
1300 if (!nvmeq->qid || iod->aborted) {
1301 dev_warn(dev->ctrl.device,
1302 "I/O %d QID %d timeout, reset controller\n",
1303 req->tag, nvmeq->qid);
1304 nvme_dev_disable(dev, false);
1305 nvme_reset_ctrl(&dev->ctrl);
1307 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1311 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1312 atomic_inc(&dev->ctrl.abort_limit);
1313 return BLK_EH_RESET_TIMER;
1317 memset(&cmd, 0, sizeof(cmd));
1318 cmd.abort.opcode = nvme_admin_abort_cmd;
1319 cmd.abort.cid = req->tag;
1320 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1322 dev_warn(nvmeq->dev->ctrl.device,
1323 "I/O %d QID %d timeout, aborting\n",
1324 req->tag, nvmeq->qid);
1326 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1327 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1328 if (IS_ERR(abort_req)) {
1329 atomic_inc(&dev->ctrl.abort_limit);
1330 return BLK_EH_RESET_TIMER;
1333 abort_req->timeout = ADMIN_TIMEOUT;
1334 abort_req->end_io_data = NULL;
1335 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1338 * The aborted req will be completed on receiving the abort req.
1339 * We enable the timer again. If hit twice, it'll cause a device reset,
1340 * as the device then is in a faulty state.
1342 return BLK_EH_RESET_TIMER;
1345 static void nvme_free_queue(struct nvme_queue *nvmeq)
1347 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth),
1348 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1349 if (!nvmeq->sq_cmds)
1352 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1353 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1354 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1356 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth),
1357 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1361 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1365 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1366 dev->ctrl.queue_count--;
1367 nvme_free_queue(&dev->queues[i]);
1372 * nvme_suspend_queue - put queue into suspended state
1373 * @nvmeq: queue to suspend
1375 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1377 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1380 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1383 nvmeq->dev->online_queues--;
1384 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1385 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1386 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1387 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1391 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1395 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1396 nvme_suspend_queue(&dev->queues[i]);
1399 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1401 struct nvme_queue *nvmeq = &dev->queues[0];
1404 nvme_shutdown_ctrl(&dev->ctrl);
1406 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1408 nvme_poll_irqdisable(nvmeq, -1);
1411 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1414 int q_depth = dev->q_depth;
1415 unsigned q_size_aligned = roundup(q_depth * entry_size,
1416 dev->ctrl.page_size);
1418 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1419 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1420 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1421 q_depth = div_u64(mem_per_q, entry_size);
1424 * Ensure the reduced q_depth is above some threshold where it
1425 * would be better to map queues in system memory with the
1435 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1438 struct pci_dev *pdev = to_pci_dev(dev->dev);
1440 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1441 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1442 if (nvmeq->sq_cmds) {
1443 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1445 if (nvmeq->sq_dma_addr) {
1446 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1450 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(depth));
1454 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1455 &nvmeq->sq_dma_addr, GFP_KERNEL);
1456 if (!nvmeq->sq_cmds)
1461 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1463 struct nvme_queue *nvmeq = &dev->queues[qid];
1465 if (dev->ctrl.queue_count > qid)
1468 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth),
1469 &nvmeq->cq_dma_addr, GFP_KERNEL);
1473 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1477 spin_lock_init(&nvmeq->sq_lock);
1478 spin_lock_init(&nvmeq->cq_poll_lock);
1480 nvmeq->cq_phase = 1;
1481 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1482 nvmeq->q_depth = depth;
1484 dev->ctrl.queue_count++;
1489 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1490 nvmeq->cq_dma_addr);
1495 static int queue_request_irq(struct nvme_queue *nvmeq)
1497 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1498 int nr = nvmeq->dev->ctrl.instance;
1500 if (use_threaded_interrupts) {
1501 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1502 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1504 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1505 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1509 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1511 struct nvme_dev *dev = nvmeq->dev;
1514 nvmeq->last_sq_tail = 0;
1516 nvmeq->cq_phase = 1;
1517 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1518 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1519 nvme_dbbuf_init(dev, nvmeq, qid);
1520 dev->online_queues++;
1521 wmb(); /* ensure the first interrupt sees the initialization */
1524 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1526 struct nvme_dev *dev = nvmeq->dev;
1530 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1533 * A queue's vector matches the queue identifier unless the controller
1534 * has only one vector available.
1537 vector = dev->num_vecs == 1 ? 0 : qid;
1539 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1541 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1545 result = adapter_alloc_sq(dev, qid, nvmeq);
1551 nvmeq->cq_vector = vector;
1552 nvme_init_queue(nvmeq, qid);
1555 nvmeq->cq_vector = vector;
1556 result = queue_request_irq(nvmeq);
1561 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1565 dev->online_queues--;
1566 adapter_delete_sq(dev, qid);
1568 adapter_delete_cq(dev, qid);
1572 static const struct blk_mq_ops nvme_mq_admin_ops = {
1573 .queue_rq = nvme_queue_rq,
1574 .complete = nvme_pci_complete_rq,
1575 .init_hctx = nvme_admin_init_hctx,
1576 .exit_hctx = nvme_admin_exit_hctx,
1577 .init_request = nvme_init_request,
1578 .timeout = nvme_timeout,
1581 static const struct blk_mq_ops nvme_mq_ops = {
1582 .queue_rq = nvme_queue_rq,
1583 .complete = nvme_pci_complete_rq,
1584 .commit_rqs = nvme_commit_rqs,
1585 .init_hctx = nvme_init_hctx,
1586 .init_request = nvme_init_request,
1587 .map_queues = nvme_pci_map_queues,
1588 .timeout = nvme_timeout,
1592 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1594 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1596 * If the controller was reset during removal, it's possible
1597 * user requests may be waiting on a stopped queue. Start the
1598 * queue to flush these to completion.
1600 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1601 blk_cleanup_queue(dev->ctrl.admin_q);
1602 blk_mq_free_tag_set(&dev->admin_tagset);
1606 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1608 if (!dev->ctrl.admin_q) {
1609 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1610 dev->admin_tagset.nr_hw_queues = 1;
1612 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1613 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1614 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1615 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1616 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1617 dev->admin_tagset.driver_data = dev;
1619 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1621 dev->ctrl.admin_tagset = &dev->admin_tagset;
1623 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1624 if (IS_ERR(dev->ctrl.admin_q)) {
1625 blk_mq_free_tag_set(&dev->admin_tagset);
1628 if (!blk_get_queue(dev->ctrl.admin_q)) {
1629 nvme_dev_remove_admin(dev);
1630 dev->ctrl.admin_q = NULL;
1634 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1639 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1641 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1644 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1646 struct pci_dev *pdev = to_pci_dev(dev->dev);
1648 if (size <= dev->bar_mapped_size)
1650 if (size > pci_resource_len(pdev, 0))
1654 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1656 dev->bar_mapped_size = 0;
1659 dev->bar_mapped_size = size;
1660 dev->dbs = dev->bar + NVME_REG_DBS;
1665 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1669 struct nvme_queue *nvmeq;
1671 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1675 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1676 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1678 if (dev->subsystem &&
1679 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1680 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1682 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1686 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1690 nvmeq = &dev->queues[0];
1691 aqa = nvmeq->q_depth - 1;
1694 writel(aqa, dev->bar + NVME_REG_AQA);
1695 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1696 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1698 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1702 nvmeq->cq_vector = 0;
1703 nvme_init_queue(nvmeq, 0);
1704 result = queue_request_irq(nvmeq);
1706 dev->online_queues--;
1710 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1714 static int nvme_create_io_queues(struct nvme_dev *dev)
1716 unsigned i, max, rw_queues;
1719 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1720 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1726 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1727 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1728 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1729 dev->io_queues[HCTX_TYPE_READ];
1734 for (i = dev->online_queues; i <= max; i++) {
1735 bool polled = i > rw_queues;
1737 ret = nvme_create_queue(&dev->queues[i], i, polled);
1743 * Ignore failing Create SQ/CQ commands, we can continue with less
1744 * than the desired amount of queues, and even a controller without
1745 * I/O queues can still be used to issue admin commands. This might
1746 * be useful to upgrade a buggy firmware for example.
1748 return ret >= 0 ? 0 : ret;
1751 static ssize_t nvme_cmb_show(struct device *dev,
1752 struct device_attribute *attr,
1755 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1757 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1758 ndev->cmbloc, ndev->cmbsz);
1760 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1762 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1764 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1766 return 1ULL << (12 + 4 * szu);
1769 static u32 nvme_cmb_size(struct nvme_dev *dev)
1771 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1774 static void nvme_map_cmb(struct nvme_dev *dev)
1777 resource_size_t bar_size;
1778 struct pci_dev *pdev = to_pci_dev(dev->dev);
1784 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1787 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1789 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1790 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1791 bar = NVME_CMB_BIR(dev->cmbloc);
1792 bar_size = pci_resource_len(pdev, bar);
1794 if (offset > bar_size)
1798 * Controllers may support a CMB size larger than their BAR,
1799 * for example, due to being behind a bridge. Reduce the CMB to
1800 * the reported size of the BAR
1802 if (size > bar_size - offset)
1803 size = bar_size - offset;
1805 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1806 dev_warn(dev->ctrl.device,
1807 "failed to register the CMB\n");
1811 dev->cmb_size = size;
1812 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1814 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1815 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1816 pci_p2pmem_publish(pdev, true);
1818 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1819 &dev_attr_cmb.attr, NULL))
1820 dev_warn(dev->ctrl.device,
1821 "failed to add sysfs attribute for CMB\n");
1824 static inline void nvme_release_cmb(struct nvme_dev *dev)
1826 if (dev->cmb_size) {
1827 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1828 &dev_attr_cmb.attr, NULL);
1833 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1835 u64 dma_addr = dev->host_mem_descs_dma;
1836 struct nvme_command c;
1839 memset(&c, 0, sizeof(c));
1840 c.features.opcode = nvme_admin_set_features;
1841 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1842 c.features.dword11 = cpu_to_le32(bits);
1843 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1844 ilog2(dev->ctrl.page_size));
1845 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1846 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1847 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1849 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1851 dev_warn(dev->ctrl.device,
1852 "failed to set host mem (err %d, flags %#x).\n",
1858 static void nvme_free_host_mem(struct nvme_dev *dev)
1862 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1863 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1864 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1866 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1867 le64_to_cpu(desc->addr),
1868 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1871 kfree(dev->host_mem_desc_bufs);
1872 dev->host_mem_desc_bufs = NULL;
1873 dma_free_coherent(dev->dev,
1874 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1875 dev->host_mem_descs, dev->host_mem_descs_dma);
1876 dev->host_mem_descs = NULL;
1877 dev->nr_host_mem_descs = 0;
1880 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1883 struct nvme_host_mem_buf_desc *descs;
1884 u32 max_entries, len;
1885 dma_addr_t descs_dma;
1890 tmp = (preferred + chunk_size - 1);
1891 do_div(tmp, chunk_size);
1894 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1895 max_entries = dev->ctrl.hmmaxd;
1897 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1898 &descs_dma, GFP_KERNEL);
1902 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1904 goto out_free_descs;
1906 for (size = 0; size < preferred && i < max_entries; size += len) {
1907 dma_addr_t dma_addr;
1909 len = min_t(u64, chunk_size, preferred - size);
1910 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1911 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1915 descs[i].addr = cpu_to_le64(dma_addr);
1916 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1923 dev->nr_host_mem_descs = i;
1924 dev->host_mem_size = size;
1925 dev->host_mem_descs = descs;
1926 dev->host_mem_descs_dma = descs_dma;
1927 dev->host_mem_desc_bufs = bufs;
1932 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1934 dma_free_attrs(dev->dev, size, bufs[i],
1935 le64_to_cpu(descs[i].addr),
1936 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1941 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1944 dev->host_mem_descs = NULL;
1948 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1952 /* start big and work our way down */
1953 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1954 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1956 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1957 if (!min || dev->host_mem_size >= min)
1959 nvme_free_host_mem(dev);
1966 static int nvme_setup_host_mem(struct nvme_dev *dev)
1968 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1969 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1970 u64 min = (u64)dev->ctrl.hmmin * 4096;
1971 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1974 preferred = min(preferred, max);
1976 dev_warn(dev->ctrl.device,
1977 "min host memory (%lld MiB) above limit (%d MiB).\n",
1978 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1979 nvme_free_host_mem(dev);
1984 * If we already have a buffer allocated check if we can reuse it.
1986 if (dev->host_mem_descs) {
1987 if (dev->host_mem_size >= min)
1988 enable_bits |= NVME_HOST_MEM_RETURN;
1990 nvme_free_host_mem(dev);
1993 if (!dev->host_mem_descs) {
1994 if (nvme_alloc_host_mem(dev, min, preferred)) {
1995 dev_warn(dev->ctrl.device,
1996 "failed to allocate host memory buffer.\n");
1997 return 0; /* controller must work without HMB */
2000 dev_info(dev->ctrl.device,
2001 "allocated %lld MiB host memory buffer.\n",
2002 dev->host_mem_size >> ilog2(SZ_1M));
2005 ret = nvme_set_host_mem(dev, enable_bits);
2007 nvme_free_host_mem(dev);
2012 * nirqs is the number of interrupts available for write and read
2013 * queues. The core already reserved an interrupt for the admin queue.
2015 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2017 struct nvme_dev *dev = affd->priv;
2018 unsigned int nr_read_queues;
2021 * If there is no interupt available for queues, ensure that
2022 * the default queue is set to 1. The affinity set size is
2023 * also set to one, but the irq core ignores it for this case.
2025 * If only one interrupt is available or 'write_queue' == 0, combine
2026 * write and read queues.
2028 * If 'write_queues' > 0, ensure it leaves room for at least one read
2034 } else if (nrirqs == 1 || !write_queues) {
2036 } else if (write_queues >= nrirqs) {
2039 nr_read_queues = nrirqs - write_queues;
2042 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2043 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2044 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2045 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2046 affd->nr_sets = nr_read_queues ? 2 : 1;
2049 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2051 struct pci_dev *pdev = to_pci_dev(dev->dev);
2052 struct irq_affinity affd = {
2054 .calc_sets = nvme_calc_irq_sets,
2057 unsigned int irq_queues, this_p_queues;
2058 unsigned int nr_cpus = num_possible_cpus();
2061 * Poll queues don't need interrupts, but we need at least one IO
2062 * queue left over for non-polled IO.
2064 this_p_queues = poll_queues;
2065 if (this_p_queues >= nr_io_queues) {
2066 this_p_queues = nr_io_queues - 1;
2069 if (nr_cpus < nr_io_queues - this_p_queues)
2070 irq_queues = nr_cpus + 1;
2072 irq_queues = nr_io_queues - this_p_queues + 1;
2074 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
2076 /* Initialize for the single interrupt case */
2077 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2078 dev->io_queues[HCTX_TYPE_READ] = 0;
2080 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2081 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2084 static void nvme_disable_io_queues(struct nvme_dev *dev)
2086 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2087 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2090 static int nvme_setup_io_queues(struct nvme_dev *dev)
2092 struct nvme_queue *adminq = &dev->queues[0];
2093 struct pci_dev *pdev = to_pci_dev(dev->dev);
2094 int result, nr_io_queues;
2097 nr_io_queues = max_io_queues();
2098 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2102 if (nr_io_queues == 0)
2105 clear_bit(NVMEQ_ENABLED, &adminq->flags);
2107 if (dev->cmb_use_sqes) {
2108 result = nvme_cmb_qdepth(dev, nr_io_queues,
2109 sizeof(struct nvme_command));
2111 dev->q_depth = result;
2113 dev->cmb_use_sqes = false;
2117 size = db_bar_size(dev, nr_io_queues);
2118 result = nvme_remap_bar(dev, size);
2121 if (!--nr_io_queues)
2124 adminq->q_db = dev->dbs;
2127 /* Deregister the admin queue's interrupt */
2128 pci_free_irq(pdev, 0, adminq);
2131 * If we enable msix early due to not intx, disable it again before
2132 * setting up the full range we need.
2134 pci_free_irq_vectors(pdev);
2136 result = nvme_setup_irqs(dev, nr_io_queues);
2140 dev->num_vecs = result;
2141 result = max(result - 1, 1);
2142 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2145 * Should investigate if there's a performance win from allocating
2146 * more queues than interrupt vectors; it might allow the submission
2147 * path to scale better, even if the receive path is limited by the
2148 * number of interrupts.
2150 result = queue_request_irq(adminq);
2153 set_bit(NVMEQ_ENABLED, &adminq->flags);
2155 result = nvme_create_io_queues(dev);
2156 if (result || dev->online_queues < 2)
2159 if (dev->online_queues - 1 < dev->max_qid) {
2160 nr_io_queues = dev->online_queues - 1;
2161 nvme_disable_io_queues(dev);
2162 nvme_suspend_io_queues(dev);
2165 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2166 dev->io_queues[HCTX_TYPE_DEFAULT],
2167 dev->io_queues[HCTX_TYPE_READ],
2168 dev->io_queues[HCTX_TYPE_POLL]);
2172 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2174 struct nvme_queue *nvmeq = req->end_io_data;
2176 blk_mq_free_request(req);
2177 complete(&nvmeq->delete_done);
2180 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2182 struct nvme_queue *nvmeq = req->end_io_data;
2185 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2187 nvme_del_queue_end(req, error);
2190 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2192 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2193 struct request *req;
2194 struct nvme_command cmd;
2196 memset(&cmd, 0, sizeof(cmd));
2197 cmd.delete_queue.opcode = opcode;
2198 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2200 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2202 return PTR_ERR(req);
2204 req->timeout = ADMIN_TIMEOUT;
2205 req->end_io_data = nvmeq;
2207 init_completion(&nvmeq->delete_done);
2208 blk_execute_rq_nowait(q, NULL, req, false,
2209 opcode == nvme_admin_delete_cq ?
2210 nvme_del_cq_end : nvme_del_queue_end);
2214 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2216 int nr_queues = dev->online_queues - 1, sent = 0;
2217 unsigned long timeout;
2220 timeout = ADMIN_TIMEOUT;
2221 while (nr_queues > 0) {
2222 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2228 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2230 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2235 /* handle any remaining CQEs */
2236 if (opcode == nvme_admin_delete_cq &&
2237 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2238 nvme_poll_irqdisable(nvmeq, -1);
2248 * return error value only when tagset allocation failed
2250 static int nvme_dev_add(struct nvme_dev *dev)
2254 if (!dev->ctrl.tagset) {
2255 dev->tagset.ops = &nvme_mq_ops;
2256 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2257 dev->tagset.nr_maps = 1; /* default */
2258 if (dev->io_queues[HCTX_TYPE_READ])
2259 dev->tagset.nr_maps++;
2260 if (dev->io_queues[HCTX_TYPE_POLL])
2261 dev->tagset.nr_maps++;
2262 dev->tagset.timeout = NVME_IO_TIMEOUT;
2263 dev->tagset.numa_node = dev_to_node(dev->dev);
2264 dev->tagset.queue_depth =
2265 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2266 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2267 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2268 dev->tagset.driver_data = dev;
2270 ret = blk_mq_alloc_tag_set(&dev->tagset);
2272 dev_warn(dev->ctrl.device,
2273 "IO queues tagset allocation failed %d\n", ret);
2276 dev->ctrl.tagset = &dev->tagset;
2278 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2280 /* Free previously allocated queues that are no longer usable */
2281 nvme_free_queues(dev, dev->online_queues);
2284 nvme_dbbuf_set(dev);
2288 static int nvme_pci_enable(struct nvme_dev *dev)
2290 int result = -ENOMEM;
2291 struct pci_dev *pdev = to_pci_dev(dev->dev);
2293 if (pci_enable_device_mem(pdev))
2296 pci_set_master(pdev);
2298 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
2301 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2307 * Some devices and/or platforms don't advertise or work with INTx
2308 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2309 * adjust this later.
2311 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2315 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2317 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2319 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2320 dev->dbs = dev->bar + 4096;
2323 * Temporary fix for the Apple controller found in the MacBook8,1 and
2324 * some MacBook7,1 to avoid controller resets and data loss.
2326 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2328 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2329 "set queue depth=%u to work around controller resets\n",
2331 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2332 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2333 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2335 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2336 "set queue depth=%u\n", dev->q_depth);
2341 pci_enable_pcie_error_reporting(pdev);
2342 pci_save_state(pdev);
2346 pci_disable_device(pdev);
2350 static void nvme_dev_unmap(struct nvme_dev *dev)
2354 pci_release_mem_regions(to_pci_dev(dev->dev));
2357 static void nvme_pci_disable(struct nvme_dev *dev)
2359 struct pci_dev *pdev = to_pci_dev(dev->dev);
2361 pci_free_irq_vectors(pdev);
2363 if (pci_is_enabled(pdev)) {
2364 pci_disable_pcie_error_reporting(pdev);
2365 pci_disable_device(pdev);
2369 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2371 bool dead = true, freeze = false;
2372 struct pci_dev *pdev = to_pci_dev(dev->dev);
2374 mutex_lock(&dev->shutdown_lock);
2375 if (pci_is_enabled(pdev)) {
2376 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2378 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2379 dev->ctrl.state == NVME_CTRL_RESETTING) {
2381 nvme_start_freeze(&dev->ctrl);
2383 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2384 pdev->error_state != pci_channel_io_normal);
2388 * Give the controller a chance to complete all entered requests if
2389 * doing a safe shutdown.
2391 if (!dead && shutdown && freeze)
2392 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2394 nvme_stop_queues(&dev->ctrl);
2396 if (!dead && dev->ctrl.queue_count > 0) {
2397 nvme_disable_io_queues(dev);
2398 nvme_disable_admin_queue(dev, shutdown);
2400 nvme_suspend_io_queues(dev);
2401 nvme_suspend_queue(&dev->queues[0]);
2402 nvme_pci_disable(dev);
2404 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2405 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2408 * The driver will not be starting up queues again if shutting down so
2409 * must flush all entered requests to their failed completion to avoid
2410 * deadlocking blk-mq hot-cpu notifier.
2413 nvme_start_queues(&dev->ctrl);
2414 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2415 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2417 mutex_unlock(&dev->shutdown_lock);
2420 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2422 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2423 PAGE_SIZE, PAGE_SIZE, 0);
2424 if (!dev->prp_page_pool)
2427 /* Optimisation for I/Os between 4k and 128k */
2428 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2430 if (!dev->prp_small_pool) {
2431 dma_pool_destroy(dev->prp_page_pool);
2437 static void nvme_release_prp_pools(struct nvme_dev *dev)
2439 dma_pool_destroy(dev->prp_page_pool);
2440 dma_pool_destroy(dev->prp_small_pool);
2443 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2445 struct nvme_dev *dev = to_nvme_dev(ctrl);
2447 nvme_dbbuf_dma_free(dev);
2448 put_device(dev->dev);
2449 if (dev->tagset.tags)
2450 blk_mq_free_tag_set(&dev->tagset);
2451 if (dev->ctrl.admin_q)
2452 blk_put_queue(dev->ctrl.admin_q);
2454 free_opal_dev(dev->ctrl.opal_dev);
2455 mempool_destroy(dev->iod_mempool);
2459 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2461 nvme_get_ctrl(&dev->ctrl);
2462 nvme_dev_disable(dev, false);
2463 nvme_kill_queues(&dev->ctrl);
2464 if (!queue_work(nvme_wq, &dev->remove_work))
2465 nvme_put_ctrl(&dev->ctrl);
2468 static void nvme_reset_work(struct work_struct *work)
2470 struct nvme_dev *dev =
2471 container_of(work, struct nvme_dev, ctrl.reset_work);
2472 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2474 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
2476 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2482 * If we're called to reset a live controller first shut it down before
2485 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2486 nvme_dev_disable(dev, false);
2487 nvme_sync_queues(&dev->ctrl);
2489 mutex_lock(&dev->shutdown_lock);
2490 result = nvme_pci_enable(dev);
2494 result = nvme_pci_configure_admin_queue(dev);
2498 result = nvme_alloc_admin_tags(dev);
2503 * Limit the max command size to prevent iod->sg allocations going
2504 * over a single page.
2506 dev->ctrl.max_hw_sectors = min_t(u32,
2507 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2508 dev->ctrl.max_segments = NVME_MAX_SEGS;
2511 * Don't limit the IOMMU merged segment size.
2513 dma_set_max_seg_size(dev->dev, 0xffffffff);
2515 mutex_unlock(&dev->shutdown_lock);
2518 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2519 * initializing procedure here.
2521 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2522 dev_warn(dev->ctrl.device,
2523 "failed to mark controller CONNECTING\n");
2528 result = nvme_init_identify(&dev->ctrl);
2532 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2533 if (!dev->ctrl.opal_dev)
2534 dev->ctrl.opal_dev =
2535 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2536 else if (was_suspend)
2537 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2539 free_opal_dev(dev->ctrl.opal_dev);
2540 dev->ctrl.opal_dev = NULL;
2543 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2544 result = nvme_dbbuf_dma_alloc(dev);
2547 "unable to allocate dma for dbbuf\n");
2550 if (dev->ctrl.hmpre) {
2551 result = nvme_setup_host_mem(dev);
2556 result = nvme_setup_io_queues(dev);
2561 * Keep the controller around but remove all namespaces if we don't have
2562 * any working I/O queue.
2564 if (dev->online_queues < 2) {
2565 dev_warn(dev->ctrl.device, "IO queues not created\n");
2566 nvme_kill_queues(&dev->ctrl);
2567 nvme_remove_namespaces(&dev->ctrl);
2568 new_state = NVME_CTRL_ADMIN_ONLY;
2570 nvme_start_queues(&dev->ctrl);
2571 nvme_wait_freeze(&dev->ctrl);
2572 /* hit this only when allocate tagset fails */
2573 if (nvme_dev_add(dev))
2574 new_state = NVME_CTRL_ADMIN_ONLY;
2575 nvme_unfreeze(&dev->ctrl);
2579 * If only admin queue live, keep it to do further investigation or
2582 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2583 dev_warn(dev->ctrl.device,
2584 "failed to mark controller state %d\n", new_state);
2589 nvme_start_ctrl(&dev->ctrl);
2593 mutex_unlock(&dev->shutdown_lock);
2596 dev_warn(dev->ctrl.device,
2597 "Removing after probe failure status: %d\n", result);
2598 nvme_remove_dead_ctrl(dev);
2601 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2603 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2604 struct pci_dev *pdev = to_pci_dev(dev->dev);
2606 if (pci_get_drvdata(pdev))
2607 device_release_driver(&pdev->dev);
2608 nvme_put_ctrl(&dev->ctrl);
2611 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2613 *val = readl(to_nvme_dev(ctrl)->bar + off);
2617 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2619 writel(val, to_nvme_dev(ctrl)->bar + off);
2623 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2625 *val = readq(to_nvme_dev(ctrl)->bar + off);
2629 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2631 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2633 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2636 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2638 .module = THIS_MODULE,
2639 .flags = NVME_F_METADATA_SUPPORTED |
2641 .reg_read32 = nvme_pci_reg_read32,
2642 .reg_write32 = nvme_pci_reg_write32,
2643 .reg_read64 = nvme_pci_reg_read64,
2644 .free_ctrl = nvme_pci_free_ctrl,
2645 .submit_async_event = nvme_pci_submit_async_event,
2646 .get_address = nvme_pci_get_address,
2649 static int nvme_dev_map(struct nvme_dev *dev)
2651 struct pci_dev *pdev = to_pci_dev(dev->dev);
2653 if (pci_request_mem_regions(pdev, "nvme"))
2656 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2661 pci_release_mem_regions(pdev);
2665 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2667 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2669 * Several Samsung devices seem to drop off the PCIe bus
2670 * randomly when APST is on and uses the deepest sleep state.
2671 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2672 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2673 * 950 PRO 256GB", but it seems to be restricted to two Dell
2676 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2677 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2678 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2679 return NVME_QUIRK_NO_DEEPEST_PS;
2680 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2682 * Samsung SSD 960 EVO drops off the PCIe bus after system
2683 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2684 * within few minutes after bootup on a Coffee Lake board -
2687 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2688 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2689 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2690 return NVME_QUIRK_NO_APST;
2696 static void nvme_async_probe(void *data, async_cookie_t cookie)
2698 struct nvme_dev *dev = data;
2700 nvme_reset_ctrl_sync(&dev->ctrl);
2701 flush_work(&dev->ctrl.scan_work);
2702 nvme_put_ctrl(&dev->ctrl);
2705 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2707 int node, result = -ENOMEM;
2708 struct nvme_dev *dev;
2709 unsigned long quirks = id->driver_data;
2712 node = dev_to_node(&pdev->dev);
2713 if (node == NUMA_NO_NODE)
2714 set_dev_node(&pdev->dev, first_memory_node);
2716 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2720 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2725 dev->dev = get_device(&pdev->dev);
2726 pci_set_drvdata(pdev, dev);
2728 result = nvme_dev_map(dev);
2732 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2733 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2734 mutex_init(&dev->shutdown_lock);
2736 result = nvme_setup_prp_pools(dev);
2740 quirks |= check_vendor_combination_bug(pdev);
2743 * Double check that our mempool alloc size will cover the biggest
2744 * command we support.
2746 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2747 NVME_MAX_SEGS, true);
2748 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2750 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2752 (void *) alloc_size,
2754 if (!dev->iod_mempool) {
2759 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2762 goto release_mempool;
2764 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2766 nvme_get_ctrl(&dev->ctrl);
2767 async_schedule(nvme_async_probe, dev);
2772 mempool_destroy(dev->iod_mempool);
2774 nvme_release_prp_pools(dev);
2776 nvme_dev_unmap(dev);
2778 put_device(dev->dev);
2785 static void nvme_reset_prepare(struct pci_dev *pdev)
2787 struct nvme_dev *dev = pci_get_drvdata(pdev);
2788 nvme_dev_disable(dev, false);
2791 static void nvme_reset_done(struct pci_dev *pdev)
2793 struct nvme_dev *dev = pci_get_drvdata(pdev);
2794 nvme_reset_ctrl_sync(&dev->ctrl);
2797 static void nvme_shutdown(struct pci_dev *pdev)
2799 struct nvme_dev *dev = pci_get_drvdata(pdev);
2800 nvme_dev_disable(dev, true);
2804 * The driver's remove may be called on a device in a partially initialized
2805 * state. This function must not have any dependencies on the device state in
2808 static void nvme_remove(struct pci_dev *pdev)
2810 struct nvme_dev *dev = pci_get_drvdata(pdev);
2812 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2813 pci_set_drvdata(pdev, NULL);
2815 if (!pci_device_is_present(pdev)) {
2816 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2817 nvme_dev_disable(dev, true);
2818 nvme_dev_remove_admin(dev);
2821 flush_work(&dev->ctrl.reset_work);
2822 nvme_stop_ctrl(&dev->ctrl);
2823 nvme_remove_namespaces(&dev->ctrl);
2824 nvme_dev_disable(dev, true);
2825 nvme_release_cmb(dev);
2826 nvme_free_host_mem(dev);
2827 nvme_dev_remove_admin(dev);
2828 nvme_free_queues(dev, 0);
2829 nvme_uninit_ctrl(&dev->ctrl);
2830 nvme_release_prp_pools(dev);
2831 nvme_dev_unmap(dev);
2832 nvme_put_ctrl(&dev->ctrl);
2835 #ifdef CONFIG_PM_SLEEP
2836 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2838 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2841 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2843 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2846 static int nvme_resume(struct device *dev)
2848 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2849 struct nvme_ctrl *ctrl = &ndev->ctrl;
2851 if (pm_resume_via_firmware() || !ctrl->npss ||
2852 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
2853 nvme_reset_ctrl(ctrl);
2857 static int nvme_suspend(struct device *dev)
2859 struct pci_dev *pdev = to_pci_dev(dev);
2860 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2861 struct nvme_ctrl *ctrl = &ndev->ctrl;
2865 * The platform does not remove power for a kernel managed suspend so
2866 * use host managed nvme power settings for lowest idle power if
2867 * possible. This should have quicker resume latency than a full device
2868 * shutdown. But if the firmware is involved after the suspend or the
2869 * device does not support any non-default power states, shut down the
2872 if (pm_suspend_via_firmware() || !ctrl->npss) {
2873 nvme_dev_disable(ndev, true);
2877 nvme_start_freeze(ctrl);
2878 nvme_wait_freeze(ctrl);
2879 nvme_sync_queues(ctrl);
2881 if (ctrl->state != NVME_CTRL_LIVE &&
2882 ctrl->state != NVME_CTRL_ADMIN_ONLY)
2886 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
2890 ret = nvme_set_power_state(ctrl, ctrl->npss);
2896 * Clearing npss forces a controller reset on resume. The
2897 * correct value will be resdicovered then.
2899 nvme_dev_disable(ndev, true);
2905 * A saved state prevents pci pm from generically controlling the
2906 * device's power. If we're using protocol specific settings, we don't
2907 * want pci interfering.
2909 pci_save_state(pdev);
2911 nvme_unfreeze(ctrl);
2915 static int nvme_simple_suspend(struct device *dev)
2917 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2919 nvme_dev_disable(ndev, true);
2923 static int nvme_simple_resume(struct device *dev)
2925 struct pci_dev *pdev = to_pci_dev(dev);
2926 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2928 nvme_reset_ctrl(&ndev->ctrl);
2932 static const struct dev_pm_ops nvme_dev_pm_ops = {
2933 .suspend = nvme_suspend,
2934 .resume = nvme_resume,
2935 .freeze = nvme_simple_suspend,
2936 .thaw = nvme_simple_resume,
2937 .poweroff = nvme_simple_suspend,
2938 .restore = nvme_simple_resume,
2940 #endif /* CONFIG_PM_SLEEP */
2942 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2943 pci_channel_state_t state)
2945 struct nvme_dev *dev = pci_get_drvdata(pdev);
2948 * A frozen channel requires a reset. When detected, this method will
2949 * shutdown the controller to quiesce. The controller will be restarted
2950 * after the slot reset through driver's slot_reset callback.
2953 case pci_channel_io_normal:
2954 return PCI_ERS_RESULT_CAN_RECOVER;
2955 case pci_channel_io_frozen:
2956 dev_warn(dev->ctrl.device,
2957 "frozen state error detected, reset controller\n");
2958 nvme_dev_disable(dev, false);
2959 return PCI_ERS_RESULT_NEED_RESET;
2960 case pci_channel_io_perm_failure:
2961 dev_warn(dev->ctrl.device,
2962 "failure state error detected, request disconnect\n");
2963 return PCI_ERS_RESULT_DISCONNECT;
2965 return PCI_ERS_RESULT_NEED_RESET;
2968 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2970 struct nvme_dev *dev = pci_get_drvdata(pdev);
2972 dev_info(dev->ctrl.device, "restart after slot reset\n");
2973 pci_restore_state(pdev);
2974 nvme_reset_ctrl(&dev->ctrl);
2975 return PCI_ERS_RESULT_RECOVERED;
2978 static void nvme_error_resume(struct pci_dev *pdev)
2980 struct nvme_dev *dev = pci_get_drvdata(pdev);
2982 flush_work(&dev->ctrl.reset_work);
2985 static const struct pci_error_handlers nvme_err_handler = {
2986 .error_detected = nvme_error_detected,
2987 .slot_reset = nvme_slot_reset,
2988 .resume = nvme_error_resume,
2989 .reset_prepare = nvme_reset_prepare,
2990 .reset_done = nvme_reset_done,
2993 static const struct pci_device_id nvme_id_table[] = {
2994 { PCI_VDEVICE(INTEL, 0x0953),
2995 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2996 NVME_QUIRK_DEALLOCATE_ZEROES, },
2997 { PCI_VDEVICE(INTEL, 0x0a53),
2998 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2999 NVME_QUIRK_DEALLOCATE_ZEROES, },
3000 { PCI_VDEVICE(INTEL, 0x0a54),
3001 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3002 NVME_QUIRK_DEALLOCATE_ZEROES, },
3003 { PCI_VDEVICE(INTEL, 0x0a55),
3004 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3005 NVME_QUIRK_DEALLOCATE_ZEROES, },
3006 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3007 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3008 NVME_QUIRK_MEDIUM_PRIO_SQ },
3009 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3010 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3011 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3012 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3013 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3014 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3015 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3016 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3017 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3018 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3019 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3020 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3021 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3022 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3023 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3024 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3025 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3026 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3027 .driver_data = NVME_QUIRK_LIGHTNVM, },
3028 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3029 .driver_data = NVME_QUIRK_LIGHTNVM, },
3030 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3031 .driver_data = NVME_QUIRK_LIGHTNVM, },
3032 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3033 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
3034 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3037 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3039 static struct pci_driver nvme_driver = {
3041 .id_table = nvme_id_table,
3042 .probe = nvme_probe,
3043 .remove = nvme_remove,
3044 .shutdown = nvme_shutdown,
3045 #ifdef CONFIG_PM_SLEEP
3047 .pm = &nvme_dev_pm_ops,
3050 .sriov_configure = pci_sriov_configure_simple,
3051 .err_handler = &nvme_err_handler,
3054 static int __init nvme_init(void)
3056 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3057 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3058 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3059 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3060 return pci_register_driver(&nvme_driver);
3063 static void __exit nvme_exit(void)
3065 pci_unregister_driver(&nvme_driver);
3066 flush_workqueue(nvme_wq);
3069 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3070 MODULE_LICENSE("GPL");
3071 MODULE_VERSION("1.0");
3072 module_init(nvme_init);
3073 module_exit(nvme_exit);