2 ** System Bus Adapter (SBA) I/O MMU manager
4 ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
5 ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
6 ** (c) Copyright 2000-2004 Hewlett-Packard Company
8 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
10 ** This program is free software; you can redistribute it and/or modify
11 ** it under the terms of the GNU General Public License as published by
12 ** the Free Software Foundation; either version 2 of the License, or
13 ** (at your option) any later version.
16 ** This module initializes the IOC (I/O Controller) found on B1000/C3000/
17 ** J5000/J7000/N-class/L-class machines and their successors.
19 ** FIXME: add DMA hint support programming in both sba and lba modules.
22 #include <linux/types.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/slab.h>
26 #include <linux/init.h>
29 #include <linux/string.h>
30 #include <linux/pci.h>
31 #include <linux/scatterlist.h>
32 #include <linux/iommu-helper.h>
34 #include <asm/byteorder.h>
36 #include <asm/dma.h> /* for DMA_CHUNK_SIZE */
38 #include <asm/hardware.h> /* for register_parisc_driver() stuff */
40 #include <linux/proc_fs.h>
41 #include <linux/seq_file.h>
42 #include <linux/module.h>
44 #include <asm/ropes.h>
45 #include <asm/mckinley.h> /* for proc_mckinley_root */
46 #include <asm/runway.h> /* for proc_runway_root */
47 #include <asm/page.h> /* for PAGE0 */
48 #include <asm/pdc.h> /* for PDC_MODEL_* */
49 #include <asm/pdcpat.h> /* for is_pdc_pat() */
50 #include <asm/parisc-device.h>
54 #define MODULE_NAME "SBA"
57 ** The number of debug flags is a clue - this code is fragile.
58 ** Don't even think about messing with it unless you have
59 ** plenty of 710's to sacrifice to the computer gods. :^)
63 #undef DEBUG_SBA_RUN_SG
64 #undef DEBUG_SBA_RESOURCE
65 #undef ASSERT_PDIR_SANITY
66 #undef DEBUG_LARGE_SG_ENTRIES
70 #define DBG_INIT(x...) printk(x)
72 #define DBG_INIT(x...)
76 #define DBG_RUN(x...) printk(x)
81 #ifdef DEBUG_SBA_RUN_SG
82 #define DBG_RUN_SG(x...) printk(x)
84 #define DBG_RUN_SG(x...)
88 #ifdef DEBUG_SBA_RESOURCE
89 #define DBG_RES(x...) printk(x)
94 #define SBA_INLINE __inline__
96 #define DEFAULT_DMA_HINT_REG 0
98 struct sba_device *sba_list;
99 EXPORT_SYMBOL_GPL(sba_list);
101 static unsigned long ioc_needs_fdc = 0;
103 /* global count of IOMMUs in the system */
104 static unsigned int global_ioc_cnt = 0;
106 /* PA8700 (Piranha 2.2) bug workaround */
107 static unsigned long piranha_bad_128k = 0;
109 /* Looks nice and keeps the compiler happy */
110 #define SBA_DEV(d) ((struct sba_device *) (d))
112 #ifdef CONFIG_AGP_PARISC
113 #define SBA_AGP_SUPPORT
114 #endif /*CONFIG_AGP_PARISC*/
116 #ifdef SBA_AGP_SUPPORT
117 static int sba_reserve_agpgart = 1;
118 module_param(sba_reserve_agpgart, int, 0444);
119 MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART");
123 /************************************
124 ** SBA register read and write support
126 ** BE WARNED: register writes are posted.
127 ** (ie follow writes which must reach HW with a read)
129 ** Superdome (in particular, REO) allows only 64-bit CSR accesses.
131 #define READ_REG32(addr) readl(addr)
132 #define READ_REG64(addr) readq(addr)
133 #define WRITE_REG32(val, addr) writel((val), (addr))
134 #define WRITE_REG64(val, addr) writeq((val), (addr))
137 #define READ_REG(addr) READ_REG64(addr)
138 #define WRITE_REG(value, addr) WRITE_REG64(value, addr)
140 #define READ_REG(addr) READ_REG32(addr)
141 #define WRITE_REG(value, addr) WRITE_REG32(value, addr)
144 #ifdef DEBUG_SBA_INIT
146 /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
149 * sba_dump_ranges - debugging only - print ranges assigned to this IOA
150 * @hpa: base address of the sba
152 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
153 * IO Adapter (aka Bus Converter).
156 sba_dump_ranges(void __iomem *hpa)
158 DBG_INIT("SBA at 0x%p\n", hpa);
159 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
160 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
161 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
163 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
164 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
165 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
169 * sba_dump_tlb - debugging only - print IOMMU operating parameters
170 * @hpa: base address of the IOMMU
172 * Print the size/location of the IO MMU PDIR.
174 static void sba_dump_tlb(void __iomem *hpa)
176 DBG_INIT("IO TLB at 0x%p\n", hpa);
177 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
178 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
179 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
180 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
184 #define sba_dump_ranges(x)
185 #define sba_dump_tlb(x)
186 #endif /* DEBUG_SBA_INIT */
189 #ifdef ASSERT_PDIR_SANITY
192 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
193 * @ioc: IO MMU structure which owns the pdir we are interested in.
194 * @msg: text to print ont the output line.
197 * Print one entry of the IO MMU PDIR in human readable form.
200 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
202 /* start printing from lowest pde in rval */
203 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
204 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
207 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
209 rptr, pide & (BITS_PER_LONG - 1), *rptr);
212 while (rcnt < BITS_PER_LONG) {
213 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
214 (rcnt == (pide & (BITS_PER_LONG - 1)))
220 printk(KERN_DEBUG "%s", msg);
225 * sba_check_pdir - debugging only - consistency checker
226 * @ioc: IO MMU structure which owns the pdir we are interested in.
227 * @msg: text to print ont the output line.
229 * Verify the resource map and pdir state is consistent
232 sba_check_pdir(struct ioc *ioc, char *msg)
234 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
235 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
236 u64 *pptr = ioc->pdir_base; /* pdir ptr */
239 while (rptr < rptr_end) {
241 int rcnt = 32; /* number of bits we might check */
244 /* Get last byte and highest bit from that */
245 u32 pde = ((u32) (((char *)pptr)[7])) << 24;
246 if ((rval ^ pde) & 0x80000000)
249 ** BUMMER! -- res_map != pdir --
250 ** Dump rval and matching pdir entries
252 sba_dump_pdir_entry(ioc, msg, pide);
256 rval <<= 1; /* try the next bit */
260 rptr++; /* look at next word of res_map */
262 /* It'd be nice if we always got here :^) */
268 * sba_dump_sg - debugging only - print Scatter-Gather list
269 * @ioc: IO MMU structure which owns the pdir we are interested in.
270 * @startsg: head of the SG list
271 * @nents: number of entries in SG list
273 * print the SG list so we can verify it's correct by hand.
276 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
278 while (nents-- > 0) {
279 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
281 (unsigned long) sg_dma_address(startsg),
283 sg_virt(startsg), startsg->length);
288 #endif /* ASSERT_PDIR_SANITY */
293 /**************************************************************
295 * I/O Pdir Resource Management
297 * Bits set in the resource map are in use.
298 * Each bit can represent a number of pages.
299 * LSbs represent lower addresses (IOVA's).
301 ***************************************************************/
302 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
304 /* Convert from IOVP to IOVA and vice versa. */
307 /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
308 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
309 #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
311 /* only support Astro and ancestors. Saves a few cycles in key places */
312 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
313 #define SBA_IOVP(ioc,iova) (iova)
316 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
318 #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
319 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
321 static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr,
322 unsigned int bitshiftcnt)
324 return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3)
329 * sba_search_bitmap - find free space in IO PDIR resource bitmap
330 * @ioc: IO MMU structure which owns the pdir we are interested in.
331 * @bits_wanted: number of entries we need.
333 * Find consecutive free bits in resource bitmap.
334 * Each bit represents one entry in the IO Pdir.
335 * Cool perf optimization: search for log2(size) bits at a time.
337 static SBA_INLINE unsigned long
338 sba_search_bitmap(struct ioc *ioc, struct device *dev,
339 unsigned long bits_wanted)
341 unsigned long *res_ptr = ioc->res_hint;
342 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
343 unsigned long pide = ~0UL, tpide;
344 unsigned long boundary_size;
348 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1,
349 1ULL << IOVP_SHIFT) >> IOVP_SHIFT;
351 #if defined(ZX1_SUPPORT)
352 BUG_ON(ioc->ibase & ~IOVP_MASK);
353 shift = ioc->ibase >> IOVP_SHIFT;
358 if (bits_wanted > (BITS_PER_LONG/2)) {
359 /* Search word at a time - no mask needed */
360 for(; res_ptr < res_end; ++res_ptr) {
361 tpide = ptr_to_pide(ioc, res_ptr, 0);
362 ret = iommu_is_span_boundary(tpide, bits_wanted,
365 if ((*res_ptr == 0) && !ret) {
366 *res_ptr = RESMAP_MASK(bits_wanted);
371 /* point to the next word on next pass */
373 ioc->res_bitshift = 0;
376 ** Search the resource bit map on well-aligned values.
377 ** "o" is the alignment.
378 ** We need the alignment to invalidate I/O TLB using
379 ** SBA HW features in the unmap path.
381 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
382 uint bitshiftcnt = ALIGN(ioc->res_bitshift, o);
385 if (bitshiftcnt >= BITS_PER_LONG) {
389 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
391 DBG_RES("%s() o %ld %p", __func__, o, res_ptr);
392 while(res_ptr < res_end)
394 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
396 tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt);
397 ret = iommu_is_span_boundary(tpide, bits_wanted,
400 if ((((*res_ptr) & mask) == 0) && !ret) {
401 *res_ptr |= mask; /* mark resources busy! */
408 mask = RESMAP_MASK(bits_wanted);
413 /* look in the same word on the next pass */
414 ioc->res_bitshift = bitshiftcnt + bits_wanted;
418 if (res_end <= res_ptr) {
419 ioc->res_hint = (unsigned long *) ioc->res_map;
420 ioc->res_bitshift = 0;
422 ioc->res_hint = res_ptr;
429 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
430 * @ioc: IO MMU structure which owns the pdir we are interested in.
431 * @size: number of bytes to create a mapping for
433 * Given a size, find consecutive unmarked and then mark those bits in the
437 sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size)
439 unsigned int pages_needed = size >> IOVP_SHIFT;
440 #ifdef SBA_COLLECT_STATS
441 unsigned long cr_start = mfctl(16);
445 pide = sba_search_bitmap(ioc, dev, pages_needed);
446 if (pide >= (ioc->res_size << 3)) {
447 pide = sba_search_bitmap(ioc, dev, pages_needed);
448 if (pide >= (ioc->res_size << 3))
449 panic("%s: I/O MMU @ %p is out of mapping resources\n",
450 __FILE__, ioc->ioc_hpa);
453 #ifdef ASSERT_PDIR_SANITY
454 /* verify the first enable bit is clear */
455 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
456 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
460 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
461 __func__, size, pages_needed, pide,
462 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
465 #ifdef SBA_COLLECT_STATS
467 unsigned long cr_end = mfctl(16);
468 unsigned long tmp = cr_end - cr_start;
469 /* check for roll over */
470 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
472 ioc->avg_search[ioc->avg_idx++] = cr_start;
473 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
475 ioc->used_pages += pages_needed;
483 * sba_free_range - unmark bits in IO PDIR resource bitmap
484 * @ioc: IO MMU structure which owns the pdir we are interested in.
485 * @iova: IO virtual address which was previously allocated.
486 * @size: number of bytes to create a mapping for
488 * clear bits in the ioc's resource map
490 static SBA_INLINE void
491 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
493 unsigned long iovp = SBA_IOVP(ioc, iova);
494 unsigned int pide = PDIR_INDEX(iovp);
495 unsigned int ridx = pide >> 3; /* convert bit to byte address */
496 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
498 int bits_not_wanted = size >> IOVP_SHIFT;
500 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
501 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
503 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
504 __func__, (uint) iova, size,
505 bits_not_wanted, m, pide, res_ptr, *res_ptr);
507 #ifdef SBA_COLLECT_STATS
508 ioc->used_pages -= bits_not_wanted;
515 /**************************************************************
517 * "Dynamic DMA Mapping" support (aka "Coherent I/O")
519 ***************************************************************/
521 #ifdef SBA_HINT_SUPPORT
522 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
525 typedef unsigned long space_t;
526 #define KERNEL_SPACE 0
529 * sba_io_pdir_entry - fill in one IO PDIR entry
530 * @pdir_ptr: pointer to IO PDIR entry
531 * @sid: process Space ID - currently only support KERNEL_SPACE
532 * @vba: Virtual CPU address of buffer to map
533 * @hint: DMA hint set to use for this mapping
535 * SBA Mapping Routine
537 * Given a virtual address (vba, arg2) and space id, (sid, arg1)
538 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
540 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
541 * for Astro/Ike looks like:
545 * +-+---------------------+----------------------------------+----+--------+
546 * |V| U | PPN[43:12] | U | VI |
547 * +-+---------------------+----------------------------------+----+--------+
549 * Pluto is basically identical, supports fewer physical address bits:
552 * +-+------------------------+-------------------------------+----+--------+
553 * |V| U | PPN[39:12] | U | VI |
554 * +-+------------------------+-------------------------------+----+--------+
556 * V == Valid Bit (Most Significant Bit is bit 0)
558 * PPN == Physical Page Number
559 * VI == Virtual Index (aka Coherent Index)
561 * LPA instruction output is put into PPN field.
562 * LCI (Load Coherence Index) instruction provides the "VI" bits.
564 * We pre-swap the bytes since PCX-W is Big Endian and the
565 * IOMMU uses little endian for the pdir.
568 static void SBA_INLINE
569 sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
572 u64 pa; /* physical address */
573 register unsigned ci; /* coherent index */
575 pa = virt_to_phys(vba);
578 asm("lci 0(%1), %0" : "=r" (ci) : "r" (vba));
579 pa |= (ci >> PAGE_SHIFT) & 0xff; /* move CI (8 bits) into lowest byte */
581 pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */
582 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
585 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
586 * (bit #61, big endian), we have to flush and sync every time
587 * IO-PDIR is changed in Ike/Astro.
589 asm_io_fdc(pdir_ptr);
594 * sba_mark_invalid - invalidate one or more IO PDIR entries
595 * @ioc: IO MMU structure which owns the pdir we are interested in.
596 * @iova: IO Virtual Address mapped earlier
597 * @byte_cnt: number of bytes this mapping covers.
599 * Marking the IO PDIR entry(ies) as Invalid and invalidate
600 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
601 * is to purge stale entries in the IO TLB when unmapping entries.
603 * The PCOM register supports purging of multiple pages, with a minium
604 * of 1 page and a maximum of 2GB. Hardware requires the address be
605 * aligned to the size of the range being purged. The size of the range
606 * must be a power of 2. The "Cool perf optimization" in the
607 * allocation routine helps keep that true.
609 static SBA_INLINE void
610 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
612 u32 iovp = (u32) SBA_IOVP(ioc,iova);
613 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
615 #ifdef ASSERT_PDIR_SANITY
616 /* Assert first pdir entry is set.
618 ** Even though this is a big-endian machine, the entries
619 ** in the iopdir are little endian. That's why we look at
620 ** the byte at +7 instead of at +0.
622 if (0x80 != (((u8 *) pdir_ptr)[7])) {
623 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
627 if (byte_cnt > IOVP_SIZE)
630 unsigned long entries_per_cacheline = ioc_needs_fdc ?
631 L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
632 - (unsigned long) pdir_ptr;
636 /* set "size" field for PCOM */
637 iovp |= get_order(byte_cnt) + PAGE_SHIFT;
640 /* clear I/O Pdir entry "valid" bit first */
641 ((u8 *) pdir_ptr)[7] = 0;
642 asm_io_fdc(pdir_ptr);
645 entries_per_cacheline = L1_CACHE_SHIFT - 3;
649 byte_cnt -= IOVP_SIZE;
650 } while (byte_cnt > IOVP_SIZE);
652 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
655 ** clear I/O PDIR entry "valid" bit.
656 ** We have to R/M/W the cacheline regardless how much of the
657 ** pdir entry that we clobber.
658 ** The rest of the entry would be useful for debugging if we
659 ** could dump core on HPMC.
661 ((u8 *) pdir_ptr)[7] = 0;
662 asm_io_fdc(pdir_ptr);
664 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
668 * sba_dma_supported - PCI driver can query DMA support
669 * @dev: instance of PCI owned by the driver that's asking
670 * @mask: number of address bits this PCI device can handle
672 * See Documentation/DMA-API-HOWTO.txt
674 static int sba_dma_supported( struct device *dev, u64 mask)
679 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
684 /* Documentation/DMA-API-HOWTO.txt tells drivers to try 64-bit
685 * first, then fall back to 32-bit if that fails.
686 * We are just "encouraging" 32-bit DMA masks here since we can
687 * never allow IOMMU bypass unless we add special support for ZX1.
697 * check if mask is >= than the current max IO Virt Address
698 * The max IO Virt address will *always* < 30 bits.
700 return((int)(mask >= (ioc->ibase - 1 +
701 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
706 * sba_map_single - map one buffer and return IOVA for DMA
707 * @dev: instance of PCI owned by the driver that's asking.
708 * @addr: driver buffer to map.
709 * @size: number of bytes to map in driver buffer.
710 * @direction: R/W or both.
712 * See Documentation/DMA-API-HOWTO.txt
715 sba_map_single(struct device *dev, void *addr, size_t size,
716 enum dma_data_direction direction)
727 return DMA_MAPPING_ERROR;
729 /* save offset bits */
730 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
732 /* round up to nearest IOVP_SIZE */
733 size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
735 spin_lock_irqsave(&ioc->res_lock, flags);
736 #ifdef ASSERT_PDIR_SANITY
737 sba_check_pdir(ioc,"Check before sba_map_single()");
740 #ifdef SBA_COLLECT_STATS
741 ioc->msingle_calls++;
742 ioc->msingle_pages += size >> IOVP_SHIFT;
744 pide = sba_alloc_range(ioc, dev, size);
745 iovp = (dma_addr_t) pide << IOVP_SHIFT;
747 DBG_RUN("%s() 0x%p -> 0x%lx\n",
748 __func__, addr, (long) iovp | offset);
750 pdir_start = &(ioc->pdir_base[pide]);
753 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
755 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
757 (u8) (((u8 *) pdir_start)[7]),
758 (u8) (((u8 *) pdir_start)[6]),
759 (u8) (((u8 *) pdir_start)[5]),
760 (u8) (((u8 *) pdir_start)[4]),
761 (u8) (((u8 *) pdir_start)[3]),
762 (u8) (((u8 *) pdir_start)[2]),
763 (u8) (((u8 *) pdir_start)[1]),
764 (u8) (((u8 *) pdir_start)[0])
772 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
775 #ifdef ASSERT_PDIR_SANITY
776 sba_check_pdir(ioc,"Check after sba_map_single()");
778 spin_unlock_irqrestore(&ioc->res_lock, flags);
780 /* form complete address */
781 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
786 sba_map_page(struct device *dev, struct page *page, unsigned long offset,
787 size_t size, enum dma_data_direction direction,
790 return sba_map_single(dev, page_address(page) + offset, size,
796 * sba_unmap_page - unmap one IOVA and free resources
797 * @dev: instance of PCI owned by the driver that's asking.
798 * @iova: IOVA of driver buffer previously mapped.
799 * @size: number of bytes mapped in driver buffer.
800 * @direction: R/W or both.
802 * See Documentation/DMA-API-HOWTO.txt
805 sba_unmap_page(struct device *dev, dma_addr_t iova, size_t size,
806 enum dma_data_direction direction, unsigned long attrs)
809 #if DELAYED_RESOURCE_CNT > 0
810 struct sba_dma_pair *d;
815 DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size);
822 offset = iova & ~IOVP_MASK;
823 iova ^= offset; /* clear offset bits */
825 size = ALIGN(size, IOVP_SIZE);
827 spin_lock_irqsave(&ioc->res_lock, flags);
829 #ifdef SBA_COLLECT_STATS
830 ioc->usingle_calls++;
831 ioc->usingle_pages += size >> IOVP_SHIFT;
834 sba_mark_invalid(ioc, iova, size);
836 #if DELAYED_RESOURCE_CNT > 0
837 /* Delaying when we re-use a IO Pdir entry reduces the number
838 * of MMIO reads needed to flush writes to the PCOM register.
840 d = &(ioc->saved[ioc->saved_cnt]);
843 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
844 int cnt = ioc->saved_cnt;
846 sba_free_range(ioc, d->iova, d->size);
851 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
853 #else /* DELAYED_RESOURCE_CNT == 0 */
854 sba_free_range(ioc, iova, size);
856 /* If fdc's were issued, force fdc's to be visible now */
859 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
860 #endif /* DELAYED_RESOURCE_CNT == 0 */
862 spin_unlock_irqrestore(&ioc->res_lock, flags);
864 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
865 ** For Astro based systems this isn't a big deal WRT performance.
866 ** As long as 2.4 kernels copyin/copyout data from/to userspace,
867 ** we don't need the syncdma. The issue here is I/O MMU cachelines
868 ** are *not* coherent in all cases. May be hwrev dependent.
869 ** Need to investigate more.
870 asm volatile("syncdma");
876 * sba_alloc - allocate/map shared mem for DMA
877 * @hwdev: instance of PCI owned by the driver that's asking.
878 * @size: number of bytes mapped in driver buffer.
879 * @dma_handle: IOVA of new buffer.
881 * See Documentation/DMA-API-HOWTO.txt
883 static void *sba_alloc(struct device *hwdev, size_t size, dma_addr_t *dma_handle,
884 gfp_t gfp, unsigned long attrs)
889 /* only support PCI */
894 ret = (void *) __get_free_pages(gfp, get_order(size));
897 memset(ret, 0, size);
898 *dma_handle = sba_map_single(hwdev, ret, size, 0);
906 * sba_free - free/unmap shared mem for DMA
907 * @hwdev: instance of PCI owned by the driver that's asking.
908 * @size: number of bytes mapped in driver buffer.
909 * @vaddr: virtual address IOVA of "consistent" buffer.
910 * @dma_handler: IO virtual address of "consistent" buffer.
912 * See Documentation/DMA-API-HOWTO.txt
915 sba_free(struct device *hwdev, size_t size, void *vaddr,
916 dma_addr_t dma_handle, unsigned long attrs)
918 sba_unmap_page(hwdev, dma_handle, size, 0, 0);
919 free_pages((unsigned long) vaddr, get_order(size));
924 ** Since 0 is a valid pdir_base index value, can't use that
925 ** to determine if a value is valid or not. Use a flag to indicate
926 ** the SG list entry contains a valid pdir index.
928 #define PIDE_FLAG 0x80000000UL
930 #ifdef SBA_COLLECT_STATS
931 #define IOMMU_MAP_STATS
933 #include "iommu-helpers.h"
935 #ifdef DEBUG_LARGE_SG_ENTRIES
941 * sba_map_sg - map Scatter/Gather list
942 * @dev: instance of PCI owned by the driver that's asking.
943 * @sglist: array of buffer/length pairs
944 * @nents: number of entries in list
945 * @direction: R/W or both.
947 * See Documentation/DMA-API-HOWTO.txt
950 sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
951 enum dma_data_direction direction, unsigned long attrs)
954 int coalesced, filled = 0;
957 DBG_RUN_SG("%s() START %d entries\n", __func__, nents);
963 /* Fast path single entry scatterlists. */
965 sg_dma_address(sglist) = sba_map_single(dev, sg_virt(sglist),
966 sglist->length, direction);
967 sg_dma_len(sglist) = sglist->length;
971 spin_lock_irqsave(&ioc->res_lock, flags);
973 #ifdef ASSERT_PDIR_SANITY
974 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
976 sba_dump_sg(ioc, sglist, nents);
977 panic("Check before sba_map_sg()");
981 #ifdef SBA_COLLECT_STATS
986 ** First coalesce the chunks and allocate I/O pdir space
988 ** If this is one DMA stream, we can properly map using the
989 ** correct virtual address associated with each DMA page.
990 ** w/o this association, we wouldn't have coherent DMA!
991 ** Access to the virtual address is what forces a two pass algorithm.
993 coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, sba_alloc_range);
996 ** Program the I/O Pdir
998 ** map the virtual addresses to the I/O Pdir
999 ** o dma_address will contain the pdir index
1000 ** o dma_len will contain the number of bytes to map
1001 ** o address contains the virtual address.
1003 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
1005 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
1008 #ifdef ASSERT_PDIR_SANITY
1009 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
1011 sba_dump_sg(ioc, sglist, nents);
1012 panic("Check after sba_map_sg()\n");
1016 spin_unlock_irqrestore(&ioc->res_lock, flags);
1018 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled);
1025 * sba_unmap_sg - unmap Scatter/Gather list
1026 * @dev: instance of PCI owned by the driver that's asking.
1027 * @sglist: array of buffer/length pairs
1028 * @nents: number of entries in list
1029 * @direction: R/W or both.
1031 * See Documentation/DMA-API-HOWTO.txt
1034 sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
1035 enum dma_data_direction direction, unsigned long attrs)
1038 #ifdef ASSERT_PDIR_SANITY
1039 unsigned long flags;
1042 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1043 __func__, nents, sg_virt(sglist), sglist->length);
1051 #ifdef SBA_COLLECT_STATS
1055 #ifdef ASSERT_PDIR_SANITY
1056 spin_lock_irqsave(&ioc->res_lock, flags);
1057 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1058 spin_unlock_irqrestore(&ioc->res_lock, flags);
1061 while (sg_dma_len(sglist) && nents--) {
1063 sba_unmap_page(dev, sg_dma_address(sglist), sg_dma_len(sglist),
1065 #ifdef SBA_COLLECT_STATS
1066 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
1067 ioc->usingle_calls--; /* kluge since call is unmap_sg() */
1072 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents);
1074 #ifdef ASSERT_PDIR_SANITY
1075 spin_lock_irqsave(&ioc->res_lock, flags);
1076 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1077 spin_unlock_irqrestore(&ioc->res_lock, flags);
1082 static const struct dma_map_ops sba_ops = {
1083 .dma_supported = sba_dma_supported,
1086 .map_page = sba_map_page,
1087 .unmap_page = sba_unmap_page,
1088 .map_sg = sba_map_sg,
1089 .unmap_sg = sba_unmap_sg,
1093 /**************************************************************************
1095 ** SBA PAT PDC support
1097 ** o call pdc_pat_cell_module()
1098 ** o store ranges in PCI "resource" structures
1100 **************************************************************************/
1103 sba_get_pat_resources(struct sba_device *sba_dev)
1107 ** TODO/REVISIT/FIXME: support for directed ranges requires calls to
1108 ** PAT PDC to program the SBA/LBA directed range registers...this
1109 ** burden may fall on the LBA code since it directly supports the
1110 ** PCI subsystem. It's not clear yet. - ggg
1112 PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
1114 PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
1115 Tells where the dvi bits are located in the address.
1116 PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
1122 /**************************************************************
1124 * Initialization and claim
1126 ***************************************************************/
1127 #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
1128 #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
1130 sba_alloc_pdir(unsigned int pdir_size)
1132 unsigned long pdir_base;
1133 unsigned long pdir_order = get_order(pdir_size);
1135 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
1136 if (NULL == (void *) pdir_base) {
1137 panic("%s() could not allocate I/O Page Table\n",
1141 /* If this is not PA8700 (PCX-W2)
1142 ** OR newer than ver 2.2
1143 ** OR in a system that doesn't need VINDEX bits from SBA,
1145 ** then we aren't exposed to the HW bug.
1147 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
1148 || (boot_cpu_data.pdc.versions > 0x202)
1149 || (boot_cpu_data.pdc.capabilities & 0x08L) )
1150 return (void *) pdir_base;
1153 * PA8700 (PCX-W2, aka piranha) silent data corruption fix
1155 * An interaction between PA8700 CPU (Ver 2.2 or older) and
1156 * Ike/Astro can cause silent data corruption. This is only
1157 * a problem if the I/O PDIR is located in memory such that
1158 * (little-endian) bits 17 and 18 are on and bit 20 is off.
1160 * Since the max IO Pdir size is 2MB, by cleverly allocating the
1161 * right physical address, we can either avoid (IOPDIR <= 1MB)
1162 * or minimize (2MB IO Pdir) the problem if we restrict the
1163 * IO Pdir to a maximum size of 2MB-128K (1902K).
1165 * Because we always allocate 2^N sized IO pdirs, either of the
1166 * "bad" regions will be the last 128K if at all. That's easy
1170 if (pdir_order <= (19-12)) {
1171 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
1172 /* allocate a new one on 512k alignment */
1173 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
1174 /* release original */
1175 free_pages(pdir_base, pdir_order);
1177 pdir_base = new_pdir;
1179 /* release excess */
1180 while (pdir_order < (19-12)) {
1181 new_pdir += pdir_size;
1182 free_pages(new_pdir, pdir_order);
1190 ** Needs to be aligned on an "odd" 1MB boundary.
1192 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
1194 /* release original */
1195 free_pages( pdir_base, pdir_order);
1197 /* release first 1MB */
1198 free_pages(new_pdir, 20-12);
1200 pdir_base = new_pdir + 1024*1024;
1202 if (pdir_order > (20-12)) {
1206 ** Flag tells init_bitmap() to mark bad 128k as used
1207 ** and to reduce the size by 128k.
1209 piranha_bad_128k = 1;
1211 new_pdir += 3*1024*1024;
1212 /* release last 1MB */
1213 free_pages(new_pdir, 20-12);
1215 /* release unusable 128KB */
1216 free_pages(new_pdir - 128*1024 , 17-12);
1218 pdir_size -= 128*1024;
1222 memset((void *) pdir_base, 0, pdir_size);
1223 return (void *) pdir_base;
1226 struct ibase_data_struct {
1231 static int setup_ibase_imask_callback(struct device *dev, void *data)
1233 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
1234 extern void lba_set_iregs(struct parisc_device *, u32, u32);
1235 struct parisc_device *lba = to_parisc_device(dev);
1236 struct ibase_data_struct *ibd = data;
1237 int rope_num = (lba->hpa.start >> 13) & 0xf;
1238 if (rope_num >> 3 == ibd->ioc_num)
1239 lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask);
1243 /* setup Mercury or Elroy IBASE/IMASK registers. */
1245 setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1247 struct ibase_data_struct ibase_data = {
1252 device_for_each_child(&sba->dev, &ibase_data,
1253 setup_ibase_imask_callback);
1256 #ifdef SBA_AGP_SUPPORT
1258 sba_ioc_find_quicksilver(struct device *dev, void *data)
1260 int *agp_found = data;
1261 struct parisc_device *lba = to_parisc_device(dev);
1263 if (IS_QUICKSILVER(lba))
1270 sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1272 u32 iova_space_mask;
1273 u32 iova_space_size;
1274 int iov_order, tcnfg;
1275 #ifdef SBA_AGP_SUPPORT
1279 ** Firmware programs the base and size of a "safe IOVA space"
1280 ** (one that doesn't overlap memory or LMMIO space) in the
1281 ** IBASE and IMASK registers.
1283 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE);
1284 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
1286 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
1287 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
1288 iova_space_size /= 2;
1292 ** iov_order is always based on a 1GB IOVA space since we want to
1293 ** turn on the other half for AGP GART.
1295 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
1296 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
1298 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n",
1299 __func__, ioc->ioc_hpa, iova_space_size >> 20,
1300 iov_order + PAGE_SHIFT);
1302 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
1303 get_order(ioc->pdir_size));
1304 if (!ioc->pdir_base)
1305 panic("Couldn't allocate I/O Page Table\n");
1307 memset(ioc->pdir_base, 0, ioc->pdir_size);
1309 DBG_INIT("%s() pdir %p size %x\n",
1310 __func__, ioc->pdir_base, ioc->pdir_size);
1312 #ifdef SBA_HINT_SUPPORT
1313 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1314 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1316 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1317 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1320 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
1321 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1323 /* build IMASK for IOC and Elroy */
1324 iova_space_mask = 0xffffffff;
1325 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1326 ioc->imask = iova_space_mask;
1328 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1330 sba_dump_tlb(ioc->ioc_hpa);
1332 setup_ibase_imask(sba, ioc, ioc_num);
1334 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
1338 ** Setting the upper bits makes checking for bypass addresses
1339 ** a little faster later on.
1341 ioc->imask |= 0xFFFFFFFF00000000UL;
1344 /* Set I/O PDIR Page size to system page size */
1345 switch (PAGE_SHIFT) {
1346 case 12: tcnfg = 0; break; /* 4K */
1347 case 13: tcnfg = 1; break; /* 8K */
1348 case 14: tcnfg = 2; break; /* 16K */
1349 case 16: tcnfg = 3; break; /* 64K */
1351 panic(__FILE__ "Unsupported system page size %d",
1355 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
1358 ** Program the IOC's ibase and enable IOVA translation
1359 ** Bit zero == enable bit.
1361 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
1364 ** Clear I/O TLB of any possible entries.
1365 ** (Yes. This is a bit paranoid...but so what)
1367 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
1369 #ifdef SBA_AGP_SUPPORT
1372 ** If an AGP device is present, only use half of the IOV space
1373 ** for PCI DMA. Unfortunately we can't know ahead of time
1374 ** whether GART support will actually be used, for now we
1375 ** can just key on any AGP device found in the system.
1376 ** We program the next pdir index after we stop w/ a key for
1377 ** the GART code to handshake on.
1379 device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver);
1381 if (agp_found && sba_reserve_agpgart) {
1382 printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n",
1383 __func__, (iova_space_size/2) >> 20);
1384 ioc->pdir_size /= 2;
1385 ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE;
1387 #endif /*SBA_AGP_SUPPORT*/
1391 sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1393 u32 iova_space_size, iova_space_mask;
1394 unsigned int pdir_size, iov_order, tcnfg;
1397 ** Determine IOVA Space size from memory size.
1399 ** Ideally, PCI drivers would register the maximum number
1400 ** of DMA they can have outstanding for each device they
1401 ** own. Next best thing would be to guess how much DMA
1402 ** can be outstanding based on PCI Class/sub-class. Both
1403 ** methods still require some "extra" to support PCI
1404 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
1406 ** While we have 32-bits "IOVA" space, top two 2 bits are used
1407 ** for DMA hints - ergo only 30 bits max.
1410 iova_space_size = (u32) (totalram_pages()/global_ioc_cnt);
1412 /* limit IOVA space size to 1MB-1GB */
1413 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
1414 iova_space_size = 1 << (20 - PAGE_SHIFT);
1416 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
1417 iova_space_size = 1 << (30 - PAGE_SHIFT);
1421 ** iova space must be log2() in size.
1422 ** thus, pdir/res_map will also be log2().
1423 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
1425 iov_order = get_order(iova_space_size << PAGE_SHIFT);
1427 /* iova_space_size is now bytes, not pages */
1428 iova_space_size = 1 << (iov_order + PAGE_SHIFT);
1430 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
1432 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
1435 (unsigned long) totalram_pages() >> (20 - PAGE_SHIFT),
1436 iova_space_size>>20,
1437 iov_order + PAGE_SHIFT);
1439 ioc->pdir_base = sba_alloc_pdir(pdir_size);
1441 DBG_INIT("%s() pdir %p size %x\n",
1442 __func__, ioc->pdir_base, pdir_size);
1444 #ifdef SBA_HINT_SUPPORT
1445 /* FIXME : DMA HINTs not used */
1446 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1447 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1449 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1450 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1453 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1455 /* build IMASK for IOC and Elroy */
1456 iova_space_mask = 0xffffffff;
1457 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1460 ** On C3000 w/512MB mem, HP-UX 10.20 reports:
1461 ** ibase=0, imask=0xFE000000, size=0x2000000.
1464 ioc->imask = iova_space_mask; /* save it */
1466 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1469 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
1470 __func__, ioc->ibase, ioc->imask);
1473 ** FIXME: Hint registers are programmed with default hint
1474 ** values during boot, so hints should be sane even if we
1475 ** can't reprogram them the way drivers want.
1478 setup_ibase_imask(sba, ioc, ioc_num);
1481 ** Program the IOC's ibase and enable IOVA translation
1483 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
1484 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
1486 /* Set I/O PDIR Page size to system page size */
1487 switch (PAGE_SHIFT) {
1488 case 12: tcnfg = 0; break; /* 4K */
1489 case 13: tcnfg = 1; break; /* 8K */
1490 case 14: tcnfg = 2; break; /* 16K */
1491 case 16: tcnfg = 3; break; /* 64K */
1493 panic(__FILE__ "Unsupported system page size %d",
1497 /* Set I/O PDIR Page size to PAGE_SIZE (4k/16k/...) */
1498 WRITE_REG(tcnfg, ioc->ioc_hpa+IOC_TCNFG);
1501 ** Clear I/O TLB of any possible entries.
1502 ** (Yes. This is a bit paranoid...but so what)
1504 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
1506 ioc->ibase = 0; /* used by SBA_IOVA and related macros */
1508 DBG_INIT("%s() DONE\n", __func__);
1513 /**************************************************************************
1515 ** SBA initialization code (HW and SW)
1517 ** o identify SBA chip itself
1518 ** o initialize SBA chip modes (HardFail)
1519 ** o initialize SBA chip modes (HardFail)
1520 ** o FIXME: initialize DMA hints for reasonable defaults
1522 **************************************************************************/
1524 static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset)
1526 return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE);
1529 static void sba_hw_init(struct sba_device *sba_dev)
1535 if (!is_pdc_pat()) {
1536 /* Shutdown the USB controller on Astro-based workstations.
1537 ** Once we reprogram the IOMMU, the next DMA performed by
1538 ** USB will HPMC the box. USB is only enabled if a
1539 ** keyboard is present and found.
1541 ** With serial console, j6k v5.0 firmware says:
1542 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
1544 ** FIXME: Using GFX+USB console at power up but direct
1545 ** linux to serial console is still broken.
1546 ** USB could generate DMA so we must reset USB.
1547 ** The proper sequence would be:
1548 ** o block console output
1549 ** o reset USB device
1550 ** o reprogram serial port
1551 ** o unblock console output
1553 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
1554 pdc_io_reset_devices();
1561 printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
1562 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
1565 ** Need to deal with DMA from LAN.
1566 ** Maybe use page zero boot device as a handle to talk
1567 ** to PDC about which device to shutdown.
1569 ** Netbooting, j6k v5.0 firmware says:
1570 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
1571 ** ARGH! invalid class.
1573 if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
1574 && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
1579 if (!IS_PLUTO(sba_dev->dev)) {
1580 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
1581 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
1582 __func__, sba_dev->sba_hpa, ioc_ctl);
1583 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
1584 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
1585 /* j6700 v1.6 firmware sets 0x294f */
1586 /* A500 firmware sets 0x4d */
1588 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
1590 #ifdef DEBUG_SBA_INIT
1591 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
1592 DBG_INIT(" 0x%Lx\n", ioc_ctl);
1596 if (IS_ASTRO(sba_dev->dev)) {
1598 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
1601 sba_dev->chip_resv.name = "Astro Intr Ack";
1602 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
1603 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
1604 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1607 } else if (IS_PLUTO(sba_dev->dev)) {
1610 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
1613 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
1614 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
1615 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
1616 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1619 sba_dev->iommu_resv.name = "IOVA Space";
1620 sba_dev->iommu_resv.start = 0x40000000UL;
1621 sba_dev->iommu_resv.end = 0x50000000UL - 1;
1622 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
1626 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
1627 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
1630 /* TODO - LOOKUP Ike/Stretch chipset mem map */
1632 /* XXX: What about Reo Grande? */
1634 sba_dev->num_ioc = num_ioc;
1635 for (i = 0; i < num_ioc; i++) {
1636 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa;
1639 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) {
1642 * Clear ROPE(N)_CONFIG AO bit.
1643 * Disables "NT Ordering" (~= !"Relaxed Ordering")
1644 * Overrides bit 1 in DMA Hint Sets.
1645 * Improves netperf UDP_STREAM by ~10% for bcm5701.
1647 if (IS_PLUTO(sba_dev->dev)) {
1648 void __iomem *rope_cfg;
1649 unsigned long cfg_val;
1651 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j;
1652 cfg_val = READ_REG(rope_cfg);
1653 cfg_val &= ~IOC_ROPE_AO;
1654 WRITE_REG(cfg_val, rope_cfg);
1658 ** Make sure the box crashes on rope errors.
1660 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j);
1663 /* flush out the last writes */
1664 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1666 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
1668 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
1669 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
1671 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
1672 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
1673 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
1676 if (IS_PLUTO(sba_dev->dev)) {
1677 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
1679 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
1685 sba_common_init(struct sba_device *sba_dev)
1689 /* add this one to the head of the list (order doesn't matter)
1690 ** This will be useful for debugging - especially if we get coredumps
1692 sba_dev->next = sba_list;
1695 for(i=0; i< sba_dev->num_ioc; i++) {
1697 #ifdef DEBUG_DMB_TRAP
1698 extern void iterate_pages(unsigned long , unsigned long ,
1699 void (*)(pte_t * , unsigned long),
1701 void set_data_memory_break(pte_t * , unsigned long);
1703 /* resource map size dictated by pdir_size */
1704 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
1706 /* Second part of PIRANHA BUG */
1707 if (piranha_bad_128k) {
1708 res_size -= (128*1024)/sizeof(u64);
1711 res_size >>= 3; /* convert bit count to byte count */
1712 DBG_INIT("%s() res_size 0x%x\n",
1713 __func__, res_size);
1715 sba_dev->ioc[i].res_size = res_size;
1716 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
1718 #ifdef DEBUG_DMB_TRAP
1719 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1720 set_data_memory_break, 0);
1723 if (NULL == sba_dev->ioc[i].res_map)
1725 panic("%s:%s() could not allocate resource map\n",
1726 __FILE__, __func__ );
1729 memset(sba_dev->ioc[i].res_map, 0, res_size);
1730 /* next available IOVP - circular search */
1731 sba_dev->ioc[i].res_hint = (unsigned long *)
1732 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
1734 #ifdef ASSERT_PDIR_SANITY
1735 /* Mark first bit busy - ie no IOVA 0 */
1736 sba_dev->ioc[i].res_map[0] = 0x80;
1737 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
1740 /* Third (and last) part of PIRANHA BUG */
1741 if (piranha_bad_128k) {
1742 /* region from +1408K to +1536 is un-usable. */
1744 int idx_start = (1408*1024/sizeof(u64)) >> 3;
1745 int idx_end = (1536*1024/sizeof(u64)) >> 3;
1746 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
1747 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
1749 /* mark that part of the io pdir busy */
1750 while (p_start < p_end)
1755 #ifdef DEBUG_DMB_TRAP
1756 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1757 set_data_memory_break, 0);
1758 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
1759 set_data_memory_break, 0);
1762 DBG_INIT("%s() %d res_map %x %p\n",
1763 __func__, i, res_size, sba_dev->ioc[i].res_map);
1766 spin_lock_init(&sba_dev->sba_lock);
1767 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
1769 #ifdef DEBUG_SBA_INIT
1771 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
1772 * (bit #61, big endian), we have to flush and sync every time
1773 * IO-PDIR is changed in Ike/Astro.
1775 if (ioc_needs_fdc) {
1776 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
1778 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
1783 #ifdef CONFIG_PROC_FS
1784 static int sba_proc_info(struct seq_file *m, void *p)
1786 struct sba_device *sba_dev = sba_list;
1787 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1788 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
1789 #ifdef SBA_COLLECT_STATS
1790 unsigned long avg = 0, min, max;
1794 seq_printf(m, "%s rev %d.%d\n",
1796 (sba_dev->hw_rev & 0x7) + 1,
1797 (sba_dev->hw_rev & 0x18) >> 3);
1798 seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
1799 (int)((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
1802 seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
1803 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
1805 seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
1806 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
1807 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
1808 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE));
1811 seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n",
1813 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
1814 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
1815 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18));
1817 #ifdef SBA_COLLECT_STATS
1818 seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
1819 total_pages - ioc->used_pages, ioc->used_pages,
1820 (int)(ioc->used_pages * 100 / total_pages));
1822 min = max = ioc->avg_search[0];
1823 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1824 avg += ioc->avg_search[i];
1825 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1826 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1828 avg /= SBA_SEARCH_SAMPLE;
1829 seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1832 seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
1833 ioc->msingle_calls, ioc->msingle_pages,
1834 (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls));
1836 /* KLUGE - unmap_sg calls unmap_single for each mapped page */
1837 min = ioc->usingle_calls;
1838 max = ioc->usingle_pages - ioc->usg_pages;
1839 seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
1840 min, max, (int)((max * 1000)/min));
1842 seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1843 ioc->msg_calls, ioc->msg_pages,
1844 (int)((ioc->msg_pages * 1000)/ioc->msg_calls));
1846 seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1847 ioc->usg_calls, ioc->usg_pages,
1848 (int)((ioc->usg_pages * 1000)/ioc->usg_calls));
1855 sba_proc_bitmap_info(struct seq_file *m, void *p)
1857 struct sba_device *sba_dev = sba_list;
1858 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1860 seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map,
1861 ioc->res_size, false);
1866 #endif /* CONFIG_PROC_FS */
1868 static const struct parisc_device_id sba_tbl[] __initconst = {
1869 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
1870 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
1871 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
1872 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
1873 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
1877 static int sba_driver_callback(struct parisc_device *);
1879 static struct parisc_driver sba_driver __refdata = {
1880 .name = MODULE_NAME,
1881 .id_table = sba_tbl,
1882 .probe = sba_driver_callback,
1886 ** Determine if sba should claim this chip (return 0) or not (return 1).
1887 ** If so, initialize the chip and tell other partners in crime they
1890 static int __init sba_driver_callback(struct parisc_device *dev)
1892 struct sba_device *sba_dev;
1896 void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE);
1897 #ifdef CONFIG_PROC_FS
1898 struct proc_dir_entry *root;
1901 sba_dump_ranges(sba_addr);
1903 /* Read HW Rev First */
1904 func_class = READ_REG(sba_addr + SBA_FCLASS);
1906 if (IS_ASTRO(dev)) {
1907 unsigned long fclass;
1908 static char astro_rev[]="Astro ?.?";
1910 /* Astro is broken...Read HW Rev First */
1911 fclass = READ_REG(sba_addr);
1913 astro_rev[6] = '1' + (char) (fclass & 0x7);
1914 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
1915 version = astro_rev;
1917 } else if (IS_IKE(dev)) {
1918 static char ike_rev[] = "Ike rev ?";
1919 ike_rev[8] = '0' + (char) (func_class & 0xff);
1921 } else if (IS_PLUTO(dev)) {
1922 static char pluto_rev[]="Pluto ?.?";
1923 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
1924 pluto_rev[8] = '0' + (char) (func_class & 0x0f);
1925 version = pluto_rev;
1927 static char reo_rev[] = "REO rev ?";
1928 reo_rev[8] = '0' + (char) (func_class & 0xff);
1932 if (!global_ioc_cnt) {
1933 global_ioc_cnt = count_parisc_driver(&sba_driver);
1935 /* Astro and Pluto have one IOC per SBA */
1936 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev)))
1937 global_ioc_cnt *= 2;
1940 printk(KERN_INFO "%s found %s at 0x%llx\n",
1941 MODULE_NAME, version, (unsigned long long)dev->hpa.start);
1943 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL);
1945 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
1949 parisc_set_drvdata(dev, sba_dev);
1951 for(i=0; i<MAX_IOC; i++)
1952 spin_lock_init(&(sba_dev->ioc[i].res_lock));
1955 sba_dev->hw_rev = func_class;
1956 sba_dev->name = dev->name;
1957 sba_dev->sba_hpa = sba_addr;
1959 sba_get_pat_resources(sba_dev);
1960 sba_hw_init(sba_dev);
1961 sba_common_init(sba_dev);
1963 hppa_dma_ops = &sba_ops;
1965 #ifdef CONFIG_PROC_FS
1966 switch (dev->id.hversion) {
1967 case PLUTO_MCKINLEY_PORT:
1968 root = proc_mckinley_root;
1970 case ASTRO_RUNWAY_PORT:
1971 case IKE_MERCED_PORT:
1973 root = proc_runway_root;
1977 proc_create_single("sba_iommu", 0, root, sba_proc_info);
1978 proc_create_single("sba_iommu-bitmap", 0, root, sba_proc_bitmap_info);
1984 ** One time initialization to let the world know the SBA was found.
1985 ** This is the only routine which is NOT static.
1986 ** Must be called exactly once before pci_init().
1988 void __init sba_init(void)
1990 register_parisc_driver(&sba_driver);
1995 * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
1996 * @dev: The parisc device.
1998 * Returns the appropriate IOMMU data for the given parisc PCI controller.
1999 * This is cached and used later for PCI DMA Mapping.
2001 void * sba_get_iommu(struct parisc_device *pci_hba)
2003 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2004 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2005 char t = sba_dev->id.hw_type;
2006 int iocnum = (pci_hba->hw_path >> 3); /* rope # */
2008 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
2010 return &(sba->ioc[iocnum]);
2015 * sba_directed_lmmio - return first directed LMMIO range routed to rope
2016 * @pa_dev: The parisc device.
2017 * @r: resource PCI host controller wants start/end fields assigned.
2019 * For the given parisc PCI controller, determine if any direct ranges
2020 * are routed down the corresponding rope.
2022 void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
2024 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2025 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2026 char t = sba_dev->id.hw_type;
2028 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2030 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
2032 r->start = r->end = 0;
2034 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
2035 for (i=0; i<4; i++) {
2037 void __iomem *reg = sba->sba_hpa + i*0x18;
2039 base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
2040 if ((base & 1) == 0)
2041 continue; /* not enabled */
2043 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
2045 if ((size & (ROPES_PER_IOC-1)) != rope)
2046 continue; /* directed down different rope */
2048 r->start = (base & ~1UL) | PCI_F_EXTEND;
2049 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
2050 r->end = r->start + size;
2051 r->flags = IORESOURCE_MEM;
2057 * sba_distributed_lmmio - return portion of distributed LMMIO range
2058 * @pa_dev: The parisc device.
2059 * @r: resource PCI host controller wants start/end fields assigned.
2061 * For the given parisc PCI controller, return portion of distributed LMMIO
2062 * range. The distributed LMMIO is always present and it's just a question
2063 * of the base address and size of the range.
2065 void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
2067 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2068 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2069 char t = sba_dev->id.hw_type;
2071 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2073 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
2075 r->start = r->end = 0;
2077 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
2078 if ((base & 1) == 0) {
2079 BUG(); /* Gah! Distr Range wasn't enabled! */
2083 r->start = (base & ~1UL) | PCI_F_EXTEND;
2085 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
2086 r->start += rope * (size + 1); /* adjust base for this rope */
2087 r->end = r->start + size;
2088 r->flags = IORESOURCE_MEM;