1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** System Bus Adapter (SBA) I/O MMU manager
5 ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
6 ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
7 ** (c) Copyright 2000-2004 Hewlett-Packard Company
9 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
13 ** This module initializes the IOC (I/O Controller) found on B1000/C3000/
14 ** J5000/J7000/N-class/L-class machines and their successors.
16 ** FIXME: add DMA hint support programming in both sba and lba modules.
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/spinlock.h>
22 #include <linux/slab.h>
23 #include <linux/init.h>
26 #include <linux/string.h>
27 #include <linux/pci.h>
28 #include <linux/scatterlist.h>
29 #include <linux/iommu-helper.h>
31 #include <asm/byteorder.h>
33 #include <asm/dma.h> /* for DMA_CHUNK_SIZE */
35 #include <asm/hardware.h> /* for register_parisc_driver() stuff */
37 #include <linux/proc_fs.h>
38 #include <linux/seq_file.h>
39 #include <linux/module.h>
41 #include <asm/ropes.h>
42 #include <asm/mckinley.h> /* for proc_mckinley_root */
43 #include <asm/runway.h> /* for proc_runway_root */
44 #include <asm/page.h> /* for PAGE0 */
45 #include <asm/pdc.h> /* for PDC_MODEL_* */
46 #include <asm/pdcpat.h> /* for is_pdc_pat() */
47 #include <asm/parisc-device.h>
51 #define MODULE_NAME "SBA"
54 ** The number of debug flags is a clue - this code is fragile.
55 ** Don't even think about messing with it unless you have
56 ** plenty of 710's to sacrifice to the computer gods. :^)
60 #undef DEBUG_SBA_RUN_SG
61 #undef DEBUG_SBA_RESOURCE
62 #undef ASSERT_PDIR_SANITY
63 #undef DEBUG_LARGE_SG_ENTRIES
67 #define DBG_INIT(x...) printk(x)
69 #define DBG_INIT(x...)
73 #define DBG_RUN(x...) printk(x)
78 #ifdef DEBUG_SBA_RUN_SG
79 #define DBG_RUN_SG(x...) printk(x)
81 #define DBG_RUN_SG(x...)
85 #ifdef DEBUG_SBA_RESOURCE
86 #define DBG_RES(x...) printk(x)
91 #define SBA_INLINE __inline__
93 #define DEFAULT_DMA_HINT_REG 0
95 struct sba_device *sba_list;
96 EXPORT_SYMBOL_GPL(sba_list);
98 static unsigned long ioc_needs_fdc = 0;
100 /* global count of IOMMUs in the system */
101 static unsigned int global_ioc_cnt = 0;
103 /* PA8700 (Piranha 2.2) bug workaround */
104 static unsigned long piranha_bad_128k = 0;
106 /* Looks nice and keeps the compiler happy */
107 #define SBA_DEV(d) ((struct sba_device *) (d))
109 #ifdef CONFIG_AGP_PARISC
110 #define SBA_AGP_SUPPORT
111 #endif /*CONFIG_AGP_PARISC*/
113 #ifdef SBA_AGP_SUPPORT
114 static int sba_reserve_agpgart = 1;
115 module_param(sba_reserve_agpgart, int, 0444);
116 MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART");
120 /************************************
121 ** SBA register read and write support
123 ** BE WARNED: register writes are posted.
124 ** (ie follow writes which must reach HW with a read)
126 ** Superdome (in particular, REO) allows only 64-bit CSR accesses.
128 #define READ_REG32(addr) readl(addr)
129 #define READ_REG64(addr) readq(addr)
130 #define WRITE_REG32(val, addr) writel((val), (addr))
131 #define WRITE_REG64(val, addr) writeq((val), (addr))
134 #define READ_REG(addr) READ_REG64(addr)
135 #define WRITE_REG(value, addr) WRITE_REG64(value, addr)
137 #define READ_REG(addr) READ_REG32(addr)
138 #define WRITE_REG(value, addr) WRITE_REG32(value, addr)
141 #ifdef DEBUG_SBA_INIT
143 /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
146 * sba_dump_ranges - debugging only - print ranges assigned to this IOA
147 * @hpa: base address of the sba
149 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
150 * IO Adapter (aka Bus Converter).
153 sba_dump_ranges(void __iomem *hpa)
155 DBG_INIT("SBA at 0x%p\n", hpa);
156 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
157 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
158 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
160 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
161 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
162 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
166 * sba_dump_tlb - debugging only - print IOMMU operating parameters
167 * @hpa: base address of the IOMMU
169 * Print the size/location of the IO MMU PDIR.
171 static void sba_dump_tlb(void __iomem *hpa)
173 DBG_INIT("IO TLB at 0x%p\n", hpa);
174 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
175 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
176 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
177 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
181 #define sba_dump_ranges(x)
182 #define sba_dump_tlb(x)
183 #endif /* DEBUG_SBA_INIT */
186 #ifdef ASSERT_PDIR_SANITY
189 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
190 * @ioc: IO MMU structure which owns the pdir we are interested in.
191 * @msg: text to print ont the output line.
194 * Print one entry of the IO MMU PDIR in human readable form.
197 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
199 /* start printing from lowest pde in rval */
200 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
201 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
204 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
206 rptr, pide & (BITS_PER_LONG - 1), *rptr);
209 while (rcnt < BITS_PER_LONG) {
210 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
211 (rcnt == (pide & (BITS_PER_LONG - 1)))
217 printk(KERN_DEBUG "%s", msg);
222 * sba_check_pdir - debugging only - consistency checker
223 * @ioc: IO MMU structure which owns the pdir we are interested in.
224 * @msg: text to print ont the output line.
226 * Verify the resource map and pdir state is consistent
229 sba_check_pdir(struct ioc *ioc, char *msg)
231 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
232 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
233 u64 *pptr = ioc->pdir_base; /* pdir ptr */
236 while (rptr < rptr_end) {
238 int rcnt = 32; /* number of bits we might check */
241 /* Get last byte and highest bit from that */
242 u32 pde = ((u32) (((char *)pptr)[7])) << 24;
243 if ((rval ^ pde) & 0x80000000)
246 ** BUMMER! -- res_map != pdir --
247 ** Dump rval and matching pdir entries
249 sba_dump_pdir_entry(ioc, msg, pide);
253 rval <<= 1; /* try the next bit */
257 rptr++; /* look at next word of res_map */
259 /* It'd be nice if we always got here :^) */
265 * sba_dump_sg - debugging only - print Scatter-Gather list
266 * @ioc: IO MMU structure which owns the pdir we are interested in.
267 * @startsg: head of the SG list
268 * @nents: number of entries in SG list
270 * print the SG list so we can verify it's correct by hand.
273 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
275 while (nents-- > 0) {
276 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
278 (unsigned long) sg_dma_address(startsg),
280 sg_virt(startsg), startsg->length);
285 #endif /* ASSERT_PDIR_SANITY */
290 /**************************************************************
292 * I/O Pdir Resource Management
294 * Bits set in the resource map are in use.
295 * Each bit can represent a number of pages.
296 * LSbs represent lower addresses (IOVA's).
298 ***************************************************************/
299 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
301 /* Convert from IOVP to IOVA and vice versa. */
304 /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
305 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
306 #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
308 /* only support Astro and ancestors. Saves a few cycles in key places */
309 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
310 #define SBA_IOVP(ioc,iova) (iova)
313 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
315 #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
316 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
318 static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr,
319 unsigned int bitshiftcnt)
321 return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3)
326 * sba_search_bitmap - find free space in IO PDIR resource bitmap
327 * @ioc: IO MMU structure which owns the pdir we are interested in.
328 * @bits_wanted: number of entries we need.
330 * Find consecutive free bits in resource bitmap.
331 * Each bit represents one entry in the IO Pdir.
332 * Cool perf optimization: search for log2(size) bits at a time.
334 static SBA_INLINE unsigned long
335 sba_search_bitmap(struct ioc *ioc, struct device *dev,
336 unsigned long bits_wanted)
338 unsigned long *res_ptr = ioc->res_hint;
339 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
340 unsigned long pide = ~0UL, tpide;
341 unsigned long boundary_size;
345 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1,
346 1ULL << IOVP_SHIFT) >> IOVP_SHIFT;
348 #if defined(ZX1_SUPPORT)
349 BUG_ON(ioc->ibase & ~IOVP_MASK);
350 shift = ioc->ibase >> IOVP_SHIFT;
355 if (bits_wanted > (BITS_PER_LONG/2)) {
356 /* Search word at a time - no mask needed */
357 for(; res_ptr < res_end; ++res_ptr) {
358 tpide = ptr_to_pide(ioc, res_ptr, 0);
359 ret = iommu_is_span_boundary(tpide, bits_wanted,
362 if ((*res_ptr == 0) && !ret) {
363 *res_ptr = RESMAP_MASK(bits_wanted);
368 /* point to the next word on next pass */
370 ioc->res_bitshift = 0;
373 ** Search the resource bit map on well-aligned values.
374 ** "o" is the alignment.
375 ** We need the alignment to invalidate I/O TLB using
376 ** SBA HW features in the unmap path.
378 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
379 uint bitshiftcnt = ALIGN(ioc->res_bitshift, o);
382 if (bitshiftcnt >= BITS_PER_LONG) {
386 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
388 DBG_RES("%s() o %ld %p", __func__, o, res_ptr);
389 while(res_ptr < res_end)
391 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
393 tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt);
394 ret = iommu_is_span_boundary(tpide, bits_wanted,
397 if ((((*res_ptr) & mask) == 0) && !ret) {
398 *res_ptr |= mask; /* mark resources busy! */
405 mask = RESMAP_MASK(bits_wanted);
410 /* look in the same word on the next pass */
411 ioc->res_bitshift = bitshiftcnt + bits_wanted;
415 if (res_end <= res_ptr) {
416 ioc->res_hint = (unsigned long *) ioc->res_map;
417 ioc->res_bitshift = 0;
419 ioc->res_hint = res_ptr;
426 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
427 * @ioc: IO MMU structure which owns the pdir we are interested in.
428 * @size: number of bytes to create a mapping for
430 * Given a size, find consecutive unmarked and then mark those bits in the
434 sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size)
436 unsigned int pages_needed = size >> IOVP_SHIFT;
437 #ifdef SBA_COLLECT_STATS
438 unsigned long cr_start = mfctl(16);
442 pide = sba_search_bitmap(ioc, dev, pages_needed);
443 if (pide >= (ioc->res_size << 3)) {
444 pide = sba_search_bitmap(ioc, dev, pages_needed);
445 if (pide >= (ioc->res_size << 3))
446 panic("%s: I/O MMU @ %p is out of mapping resources\n",
447 __FILE__, ioc->ioc_hpa);
450 #ifdef ASSERT_PDIR_SANITY
451 /* verify the first enable bit is clear */
452 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
453 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
457 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
458 __func__, size, pages_needed, pide,
459 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
462 #ifdef SBA_COLLECT_STATS
464 unsigned long cr_end = mfctl(16);
465 unsigned long tmp = cr_end - cr_start;
466 /* check for roll over */
467 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
469 ioc->avg_search[ioc->avg_idx++] = cr_start;
470 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
472 ioc->used_pages += pages_needed;
480 * sba_free_range - unmark bits in IO PDIR resource bitmap
481 * @ioc: IO MMU structure which owns the pdir we are interested in.
482 * @iova: IO virtual address which was previously allocated.
483 * @size: number of bytes to create a mapping for
485 * clear bits in the ioc's resource map
487 static SBA_INLINE void
488 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
490 unsigned long iovp = SBA_IOVP(ioc, iova);
491 unsigned int pide = PDIR_INDEX(iovp);
492 unsigned int ridx = pide >> 3; /* convert bit to byte address */
493 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
495 int bits_not_wanted = size >> IOVP_SHIFT;
497 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
498 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
500 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
501 __func__, (uint) iova, size,
502 bits_not_wanted, m, pide, res_ptr, *res_ptr);
504 #ifdef SBA_COLLECT_STATS
505 ioc->used_pages -= bits_not_wanted;
512 /**************************************************************
514 * "Dynamic DMA Mapping" support (aka "Coherent I/O")
516 ***************************************************************/
518 #ifdef SBA_HINT_SUPPORT
519 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
522 typedef unsigned long space_t;
523 #define KERNEL_SPACE 0
526 * sba_io_pdir_entry - fill in one IO PDIR entry
527 * @pdir_ptr: pointer to IO PDIR entry
528 * @sid: process Space ID - currently only support KERNEL_SPACE
529 * @vba: Virtual CPU address of buffer to map
530 * @hint: DMA hint set to use for this mapping
532 * SBA Mapping Routine
534 * Given a virtual address (vba, arg2) and space id, (sid, arg1)
535 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
537 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
538 * for Astro/Ike looks like:
542 * +-+---------------------+----------------------------------+----+--------+
543 * |V| U | PPN[43:12] | U | VI |
544 * +-+---------------------+----------------------------------+----+--------+
546 * Pluto is basically identical, supports fewer physical address bits:
549 * +-+------------------------+-------------------------------+----+--------+
550 * |V| U | PPN[39:12] | U | VI |
551 * +-+------------------------+-------------------------------+----+--------+
553 * V == Valid Bit (Most Significant Bit is bit 0)
555 * PPN == Physical Page Number
556 * VI == Virtual Index (aka Coherent Index)
558 * LPA instruction output is put into PPN field.
559 * LCI (Load Coherence Index) instruction provides the "VI" bits.
561 * We pre-swap the bytes since PCX-W is Big Endian and the
562 * IOMMU uses little endian for the pdir.
565 static void SBA_INLINE
566 sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
569 u64 pa; /* physical address */
570 register unsigned ci; /* coherent index */
575 asm("lci 0(%1), %0" : "=r" (ci) : "r" (vba));
576 pa |= (ci >> PAGE_SHIFT) & 0xff; /* move CI (8 bits) into lowest byte */
578 pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */
579 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
582 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
583 * (bit #61, big endian), we have to flush and sync every time
584 * IO-PDIR is changed in Ike/Astro.
586 asm_io_fdc(pdir_ptr);
591 * sba_mark_invalid - invalidate one or more IO PDIR entries
592 * @ioc: IO MMU structure which owns the pdir we are interested in.
593 * @iova: IO Virtual Address mapped earlier
594 * @byte_cnt: number of bytes this mapping covers.
596 * Marking the IO PDIR entry(ies) as Invalid and invalidate
597 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
598 * is to purge stale entries in the IO TLB when unmapping entries.
600 * The PCOM register supports purging of multiple pages, with a minium
601 * of 1 page and a maximum of 2GB. Hardware requires the address be
602 * aligned to the size of the range being purged. The size of the range
603 * must be a power of 2. The "Cool perf optimization" in the
604 * allocation routine helps keep that true.
606 static SBA_INLINE void
607 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
609 u32 iovp = (u32) SBA_IOVP(ioc,iova);
610 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
612 #ifdef ASSERT_PDIR_SANITY
613 /* Assert first pdir entry is set.
615 ** Even though this is a big-endian machine, the entries
616 ** in the iopdir are little endian. That's why we look at
617 ** the byte at +7 instead of at +0.
619 if (0x80 != (((u8 *) pdir_ptr)[7])) {
620 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
624 if (byte_cnt > IOVP_SIZE)
627 unsigned long entries_per_cacheline = ioc_needs_fdc ?
628 L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
629 - (unsigned long) pdir_ptr;
633 /* set "size" field for PCOM */
634 iovp |= get_order(byte_cnt) + PAGE_SHIFT;
637 /* clear I/O Pdir entry "valid" bit first */
638 ((u8 *) pdir_ptr)[7] = 0;
639 asm_io_fdc(pdir_ptr);
642 entries_per_cacheline = L1_CACHE_SHIFT - 3;
646 byte_cnt -= IOVP_SIZE;
647 } while (byte_cnt > IOVP_SIZE);
649 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
652 ** clear I/O PDIR entry "valid" bit.
653 ** We have to R/M/W the cacheline regardless how much of the
654 ** pdir entry that we clobber.
655 ** The rest of the entry would be useful for debugging if we
656 ** could dump core on HPMC.
658 ((u8 *) pdir_ptr)[7] = 0;
659 asm_io_fdc(pdir_ptr);
661 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
665 * sba_dma_supported - PCI driver can query DMA support
666 * @dev: instance of PCI owned by the driver that's asking
667 * @mask: number of address bits this PCI device can handle
669 * See Documentation/DMA-API-HOWTO.txt
671 static int sba_dma_supported( struct device *dev, u64 mask)
676 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
681 /* Documentation/DMA-API-HOWTO.txt tells drivers to try 64-bit
682 * first, then fall back to 32-bit if that fails.
683 * We are just "encouraging" 32-bit DMA masks here since we can
684 * never allow IOMMU bypass unless we add special support for ZX1.
694 * check if mask is >= than the current max IO Virt Address
695 * The max IO Virt address will *always* < 30 bits.
697 return((int)(mask >= (ioc->ibase - 1 +
698 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
703 * sba_map_single - map one buffer and return IOVA for DMA
704 * @dev: instance of PCI owned by the driver that's asking.
705 * @addr: driver buffer to map.
706 * @size: number of bytes to map in driver buffer.
707 * @direction: R/W or both.
709 * See Documentation/DMA-API-HOWTO.txt
712 sba_map_single(struct device *dev, void *addr, size_t size,
713 enum dma_data_direction direction)
724 return DMA_MAPPING_ERROR;
726 /* save offset bits */
727 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
729 /* round up to nearest IOVP_SIZE */
730 size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
732 spin_lock_irqsave(&ioc->res_lock, flags);
733 #ifdef ASSERT_PDIR_SANITY
734 sba_check_pdir(ioc,"Check before sba_map_single()");
737 #ifdef SBA_COLLECT_STATS
738 ioc->msingle_calls++;
739 ioc->msingle_pages += size >> IOVP_SHIFT;
741 pide = sba_alloc_range(ioc, dev, size);
742 iovp = (dma_addr_t) pide << IOVP_SHIFT;
744 DBG_RUN("%s() 0x%p -> 0x%lx\n",
745 __func__, addr, (long) iovp | offset);
747 pdir_start = &(ioc->pdir_base[pide]);
750 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
752 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
754 (u8) (((u8 *) pdir_start)[7]),
755 (u8) (((u8 *) pdir_start)[6]),
756 (u8) (((u8 *) pdir_start)[5]),
757 (u8) (((u8 *) pdir_start)[4]),
758 (u8) (((u8 *) pdir_start)[3]),
759 (u8) (((u8 *) pdir_start)[2]),
760 (u8) (((u8 *) pdir_start)[1]),
761 (u8) (((u8 *) pdir_start)[0])
769 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
772 #ifdef ASSERT_PDIR_SANITY
773 sba_check_pdir(ioc,"Check after sba_map_single()");
775 spin_unlock_irqrestore(&ioc->res_lock, flags);
777 /* form complete address */
778 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
783 sba_map_page(struct device *dev, struct page *page, unsigned long offset,
784 size_t size, enum dma_data_direction direction,
787 return sba_map_single(dev, page_address(page) + offset, size,
793 * sba_unmap_page - unmap one IOVA and free resources
794 * @dev: instance of PCI owned by the driver that's asking.
795 * @iova: IOVA of driver buffer previously mapped.
796 * @size: number of bytes mapped in driver buffer.
797 * @direction: R/W or both.
799 * See Documentation/DMA-API-HOWTO.txt
802 sba_unmap_page(struct device *dev, dma_addr_t iova, size_t size,
803 enum dma_data_direction direction, unsigned long attrs)
806 #if DELAYED_RESOURCE_CNT > 0
807 struct sba_dma_pair *d;
812 DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size);
819 offset = iova & ~IOVP_MASK;
820 iova ^= offset; /* clear offset bits */
822 size = ALIGN(size, IOVP_SIZE);
824 spin_lock_irqsave(&ioc->res_lock, flags);
826 #ifdef SBA_COLLECT_STATS
827 ioc->usingle_calls++;
828 ioc->usingle_pages += size >> IOVP_SHIFT;
831 sba_mark_invalid(ioc, iova, size);
833 #if DELAYED_RESOURCE_CNT > 0
834 /* Delaying when we re-use a IO Pdir entry reduces the number
835 * of MMIO reads needed to flush writes to the PCOM register.
837 d = &(ioc->saved[ioc->saved_cnt]);
840 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
841 int cnt = ioc->saved_cnt;
843 sba_free_range(ioc, d->iova, d->size);
848 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
850 #else /* DELAYED_RESOURCE_CNT == 0 */
851 sba_free_range(ioc, iova, size);
853 /* If fdc's were issued, force fdc's to be visible now */
856 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
857 #endif /* DELAYED_RESOURCE_CNT == 0 */
859 spin_unlock_irqrestore(&ioc->res_lock, flags);
861 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
862 ** For Astro based systems this isn't a big deal WRT performance.
863 ** As long as 2.4 kernels copyin/copyout data from/to userspace,
864 ** we don't need the syncdma. The issue here is I/O MMU cachelines
865 ** are *not* coherent in all cases. May be hwrev dependent.
866 ** Need to investigate more.
867 asm volatile("syncdma");
873 * sba_alloc - allocate/map shared mem for DMA
874 * @hwdev: instance of PCI owned by the driver that's asking.
875 * @size: number of bytes mapped in driver buffer.
876 * @dma_handle: IOVA of new buffer.
878 * See Documentation/DMA-API-HOWTO.txt
880 static void *sba_alloc(struct device *hwdev, size_t size, dma_addr_t *dma_handle,
881 gfp_t gfp, unsigned long attrs)
886 /* only support PCI */
891 ret = (void *) __get_free_pages(gfp, get_order(size));
894 memset(ret, 0, size);
895 *dma_handle = sba_map_single(hwdev, ret, size, 0);
903 * sba_free - free/unmap shared mem for DMA
904 * @hwdev: instance of PCI owned by the driver that's asking.
905 * @size: number of bytes mapped in driver buffer.
906 * @vaddr: virtual address IOVA of "consistent" buffer.
907 * @dma_handler: IO virtual address of "consistent" buffer.
909 * See Documentation/DMA-API-HOWTO.txt
912 sba_free(struct device *hwdev, size_t size, void *vaddr,
913 dma_addr_t dma_handle, unsigned long attrs)
915 sba_unmap_page(hwdev, dma_handle, size, 0, 0);
916 free_pages((unsigned long) vaddr, get_order(size));
921 ** Since 0 is a valid pdir_base index value, can't use that
922 ** to determine if a value is valid or not. Use a flag to indicate
923 ** the SG list entry contains a valid pdir index.
925 #define PIDE_FLAG 0x80000000UL
927 #ifdef SBA_COLLECT_STATS
928 #define IOMMU_MAP_STATS
930 #include "iommu-helpers.h"
932 #ifdef DEBUG_LARGE_SG_ENTRIES
938 * sba_map_sg - map Scatter/Gather list
939 * @dev: instance of PCI owned by the driver that's asking.
940 * @sglist: array of buffer/length pairs
941 * @nents: number of entries in list
942 * @direction: R/W or both.
944 * See Documentation/DMA-API-HOWTO.txt
947 sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
948 enum dma_data_direction direction, unsigned long attrs)
951 int coalesced, filled = 0;
954 DBG_RUN_SG("%s() START %d entries\n", __func__, nents);
960 /* Fast path single entry scatterlists. */
962 sg_dma_address(sglist) = sba_map_single(dev, sg_virt(sglist),
963 sglist->length, direction);
964 sg_dma_len(sglist) = sglist->length;
968 spin_lock_irqsave(&ioc->res_lock, flags);
970 #ifdef ASSERT_PDIR_SANITY
971 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
973 sba_dump_sg(ioc, sglist, nents);
974 panic("Check before sba_map_sg()");
978 #ifdef SBA_COLLECT_STATS
983 ** First coalesce the chunks and allocate I/O pdir space
985 ** If this is one DMA stream, we can properly map using the
986 ** correct virtual address associated with each DMA page.
987 ** w/o this association, we wouldn't have coherent DMA!
988 ** Access to the virtual address is what forces a two pass algorithm.
990 coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, sba_alloc_range);
993 ** Program the I/O Pdir
995 ** map the virtual addresses to the I/O Pdir
996 ** o dma_address will contain the pdir index
997 ** o dma_len will contain the number of bytes to map
998 ** o address contains the virtual address.
1000 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
1002 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
1005 #ifdef ASSERT_PDIR_SANITY
1006 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
1008 sba_dump_sg(ioc, sglist, nents);
1009 panic("Check after sba_map_sg()\n");
1013 spin_unlock_irqrestore(&ioc->res_lock, flags);
1015 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled);
1022 * sba_unmap_sg - unmap Scatter/Gather list
1023 * @dev: instance of PCI owned by the driver that's asking.
1024 * @sglist: array of buffer/length pairs
1025 * @nents: number of entries in list
1026 * @direction: R/W or both.
1028 * See Documentation/DMA-API-HOWTO.txt
1031 sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
1032 enum dma_data_direction direction, unsigned long attrs)
1035 #ifdef ASSERT_PDIR_SANITY
1036 unsigned long flags;
1039 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1040 __func__, nents, sg_virt(sglist), sglist->length);
1048 #ifdef SBA_COLLECT_STATS
1052 #ifdef ASSERT_PDIR_SANITY
1053 spin_lock_irqsave(&ioc->res_lock, flags);
1054 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1055 spin_unlock_irqrestore(&ioc->res_lock, flags);
1058 while (sg_dma_len(sglist) && nents--) {
1060 sba_unmap_page(dev, sg_dma_address(sglist), sg_dma_len(sglist),
1062 #ifdef SBA_COLLECT_STATS
1063 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
1064 ioc->usingle_calls--; /* kluge since call is unmap_sg() */
1069 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents);
1071 #ifdef ASSERT_PDIR_SANITY
1072 spin_lock_irqsave(&ioc->res_lock, flags);
1073 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1074 spin_unlock_irqrestore(&ioc->res_lock, flags);
1079 static const struct dma_map_ops sba_ops = {
1080 .dma_supported = sba_dma_supported,
1083 .map_page = sba_map_page,
1084 .unmap_page = sba_unmap_page,
1085 .map_sg = sba_map_sg,
1086 .unmap_sg = sba_unmap_sg,
1087 .get_sgtable = dma_common_get_sgtable,
1091 /**************************************************************************
1093 ** SBA PAT PDC support
1095 ** o call pdc_pat_cell_module()
1096 ** o store ranges in PCI "resource" structures
1098 **************************************************************************/
1101 sba_get_pat_resources(struct sba_device *sba_dev)
1105 ** TODO/REVISIT/FIXME: support for directed ranges requires calls to
1106 ** PAT PDC to program the SBA/LBA directed range registers...this
1107 ** burden may fall on the LBA code since it directly supports the
1108 ** PCI subsystem. It's not clear yet. - ggg
1110 PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
1112 PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
1113 Tells where the dvi bits are located in the address.
1114 PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
1120 /**************************************************************
1122 * Initialization and claim
1124 ***************************************************************/
1125 #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
1126 #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
1128 sba_alloc_pdir(unsigned int pdir_size)
1130 unsigned long pdir_base;
1131 unsigned long pdir_order = get_order(pdir_size);
1133 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
1134 if (NULL == (void *) pdir_base) {
1135 panic("%s() could not allocate I/O Page Table\n",
1139 /* If this is not PA8700 (PCX-W2)
1140 ** OR newer than ver 2.2
1141 ** OR in a system that doesn't need VINDEX bits from SBA,
1143 ** then we aren't exposed to the HW bug.
1145 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
1146 || (boot_cpu_data.pdc.versions > 0x202)
1147 || (boot_cpu_data.pdc.capabilities & 0x08L) )
1148 return (void *) pdir_base;
1151 * PA8700 (PCX-W2, aka piranha) silent data corruption fix
1153 * An interaction between PA8700 CPU (Ver 2.2 or older) and
1154 * Ike/Astro can cause silent data corruption. This is only
1155 * a problem if the I/O PDIR is located in memory such that
1156 * (little-endian) bits 17 and 18 are on and bit 20 is off.
1158 * Since the max IO Pdir size is 2MB, by cleverly allocating the
1159 * right physical address, we can either avoid (IOPDIR <= 1MB)
1160 * or minimize (2MB IO Pdir) the problem if we restrict the
1161 * IO Pdir to a maximum size of 2MB-128K (1902K).
1163 * Because we always allocate 2^N sized IO pdirs, either of the
1164 * "bad" regions will be the last 128K if at all. That's easy
1168 if (pdir_order <= (19-12)) {
1169 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
1170 /* allocate a new one on 512k alignment */
1171 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
1172 /* release original */
1173 free_pages(pdir_base, pdir_order);
1175 pdir_base = new_pdir;
1177 /* release excess */
1178 while (pdir_order < (19-12)) {
1179 new_pdir += pdir_size;
1180 free_pages(new_pdir, pdir_order);
1188 ** Needs to be aligned on an "odd" 1MB boundary.
1190 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
1192 /* release original */
1193 free_pages( pdir_base, pdir_order);
1195 /* release first 1MB */
1196 free_pages(new_pdir, 20-12);
1198 pdir_base = new_pdir + 1024*1024;
1200 if (pdir_order > (20-12)) {
1204 ** Flag tells init_bitmap() to mark bad 128k as used
1205 ** and to reduce the size by 128k.
1207 piranha_bad_128k = 1;
1209 new_pdir += 3*1024*1024;
1210 /* release last 1MB */
1211 free_pages(new_pdir, 20-12);
1213 /* release unusable 128KB */
1214 free_pages(new_pdir - 128*1024 , 17-12);
1216 pdir_size -= 128*1024;
1220 memset((void *) pdir_base, 0, pdir_size);
1221 return (void *) pdir_base;
1224 struct ibase_data_struct {
1229 static int setup_ibase_imask_callback(struct device *dev, void *data)
1231 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
1232 extern void lba_set_iregs(struct parisc_device *, u32, u32);
1233 struct parisc_device *lba = to_parisc_device(dev);
1234 struct ibase_data_struct *ibd = data;
1235 int rope_num = (lba->hpa.start >> 13) & 0xf;
1236 if (rope_num >> 3 == ibd->ioc_num)
1237 lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask);
1241 /* setup Mercury or Elroy IBASE/IMASK registers. */
1243 setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1245 struct ibase_data_struct ibase_data = {
1250 device_for_each_child(&sba->dev, &ibase_data,
1251 setup_ibase_imask_callback);
1254 #ifdef SBA_AGP_SUPPORT
1256 sba_ioc_find_quicksilver(struct device *dev, void *data)
1258 int *agp_found = data;
1259 struct parisc_device *lba = to_parisc_device(dev);
1261 if (IS_QUICKSILVER(lba))
1268 sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1270 u32 iova_space_mask;
1271 u32 iova_space_size;
1272 int iov_order, tcnfg;
1273 #ifdef SBA_AGP_SUPPORT
1277 ** Firmware programs the base and size of a "safe IOVA space"
1278 ** (one that doesn't overlap memory or LMMIO space) in the
1279 ** IBASE and IMASK registers.
1281 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE);
1282 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
1284 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
1285 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
1286 iova_space_size /= 2;
1290 ** iov_order is always based on a 1GB IOVA space since we want to
1291 ** turn on the other half for AGP GART.
1293 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
1294 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
1296 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n",
1297 __func__, ioc->ioc_hpa, iova_space_size >> 20,
1298 iov_order + PAGE_SHIFT);
1300 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
1301 get_order(ioc->pdir_size));
1302 if (!ioc->pdir_base)
1303 panic("Couldn't allocate I/O Page Table\n");
1305 memset(ioc->pdir_base, 0, ioc->pdir_size);
1307 DBG_INIT("%s() pdir %p size %x\n",
1308 __func__, ioc->pdir_base, ioc->pdir_size);
1310 #ifdef SBA_HINT_SUPPORT
1311 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1312 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1314 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1315 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1318 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
1319 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1321 /* build IMASK for IOC and Elroy */
1322 iova_space_mask = 0xffffffff;
1323 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1324 ioc->imask = iova_space_mask;
1326 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1328 sba_dump_tlb(ioc->ioc_hpa);
1330 setup_ibase_imask(sba, ioc, ioc_num);
1332 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
1336 ** Setting the upper bits makes checking for bypass addresses
1337 ** a little faster later on.
1339 ioc->imask |= 0xFFFFFFFF00000000UL;
1342 /* Set I/O PDIR Page size to system page size */
1343 switch (PAGE_SHIFT) {
1344 case 12: tcnfg = 0; break; /* 4K */
1345 case 13: tcnfg = 1; break; /* 8K */
1346 case 14: tcnfg = 2; break; /* 16K */
1347 case 16: tcnfg = 3; break; /* 64K */
1349 panic(__FILE__ "Unsupported system page size %d",
1353 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
1356 ** Program the IOC's ibase and enable IOVA translation
1357 ** Bit zero == enable bit.
1359 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
1362 ** Clear I/O TLB of any possible entries.
1363 ** (Yes. This is a bit paranoid...but so what)
1365 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
1367 #ifdef SBA_AGP_SUPPORT
1370 ** If an AGP device is present, only use half of the IOV space
1371 ** for PCI DMA. Unfortunately we can't know ahead of time
1372 ** whether GART support will actually be used, for now we
1373 ** can just key on any AGP device found in the system.
1374 ** We program the next pdir index after we stop w/ a key for
1375 ** the GART code to handshake on.
1377 device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver);
1379 if (agp_found && sba_reserve_agpgart) {
1380 printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n",
1381 __func__, (iova_space_size/2) >> 20);
1382 ioc->pdir_size /= 2;
1383 ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE;
1385 #endif /*SBA_AGP_SUPPORT*/
1389 sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1391 u32 iova_space_size, iova_space_mask;
1392 unsigned int pdir_size, iov_order, tcnfg;
1395 ** Determine IOVA Space size from memory size.
1397 ** Ideally, PCI drivers would register the maximum number
1398 ** of DMA they can have outstanding for each device they
1399 ** own. Next best thing would be to guess how much DMA
1400 ** can be outstanding based on PCI Class/sub-class. Both
1401 ** methods still require some "extra" to support PCI
1402 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
1404 ** While we have 32-bits "IOVA" space, top two 2 bits are used
1405 ** for DMA hints - ergo only 30 bits max.
1408 iova_space_size = (u32) (totalram_pages()/global_ioc_cnt);
1410 /* limit IOVA space size to 1MB-1GB */
1411 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
1412 iova_space_size = 1 << (20 - PAGE_SHIFT);
1414 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
1415 iova_space_size = 1 << (30 - PAGE_SHIFT);
1419 ** iova space must be log2() in size.
1420 ** thus, pdir/res_map will also be log2().
1421 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
1423 iov_order = get_order(iova_space_size << PAGE_SHIFT);
1425 /* iova_space_size is now bytes, not pages */
1426 iova_space_size = 1 << (iov_order + PAGE_SHIFT);
1428 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
1430 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
1433 (unsigned long) totalram_pages() >> (20 - PAGE_SHIFT),
1434 iova_space_size>>20,
1435 iov_order + PAGE_SHIFT);
1437 ioc->pdir_base = sba_alloc_pdir(pdir_size);
1439 DBG_INIT("%s() pdir %p size %x\n",
1440 __func__, ioc->pdir_base, pdir_size);
1442 #ifdef SBA_HINT_SUPPORT
1443 /* FIXME : DMA HINTs not used */
1444 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1445 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1447 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1448 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1451 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1453 /* build IMASK for IOC and Elroy */
1454 iova_space_mask = 0xffffffff;
1455 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1458 ** On C3000 w/512MB mem, HP-UX 10.20 reports:
1459 ** ibase=0, imask=0xFE000000, size=0x2000000.
1462 ioc->imask = iova_space_mask; /* save it */
1464 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1467 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
1468 __func__, ioc->ibase, ioc->imask);
1471 ** FIXME: Hint registers are programmed with default hint
1472 ** values during boot, so hints should be sane even if we
1473 ** can't reprogram them the way drivers want.
1476 setup_ibase_imask(sba, ioc, ioc_num);
1479 ** Program the IOC's ibase and enable IOVA translation
1481 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
1482 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
1484 /* Set I/O PDIR Page size to system page size */
1485 switch (PAGE_SHIFT) {
1486 case 12: tcnfg = 0; break; /* 4K */
1487 case 13: tcnfg = 1; break; /* 8K */
1488 case 14: tcnfg = 2; break; /* 16K */
1489 case 16: tcnfg = 3; break; /* 64K */
1491 panic(__FILE__ "Unsupported system page size %d",
1495 /* Set I/O PDIR Page size to PAGE_SIZE (4k/16k/...) */
1496 WRITE_REG(tcnfg, ioc->ioc_hpa+IOC_TCNFG);
1499 ** Clear I/O TLB of any possible entries.
1500 ** (Yes. This is a bit paranoid...but so what)
1502 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
1504 ioc->ibase = 0; /* used by SBA_IOVA and related macros */
1506 DBG_INIT("%s() DONE\n", __func__);
1511 /**************************************************************************
1513 ** SBA initialization code (HW and SW)
1515 ** o identify SBA chip itself
1516 ** o initialize SBA chip modes (HardFail)
1517 ** o initialize SBA chip modes (HardFail)
1518 ** o FIXME: initialize DMA hints for reasonable defaults
1520 **************************************************************************/
1522 static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset)
1524 return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE);
1527 static void sba_hw_init(struct sba_device *sba_dev)
1533 if (!is_pdc_pat()) {
1534 /* Shutdown the USB controller on Astro-based workstations.
1535 ** Once we reprogram the IOMMU, the next DMA performed by
1536 ** USB will HPMC the box. USB is only enabled if a
1537 ** keyboard is present and found.
1539 ** With serial console, j6k v5.0 firmware says:
1540 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
1542 ** FIXME: Using GFX+USB console at power up but direct
1543 ** linux to serial console is still broken.
1544 ** USB could generate DMA so we must reset USB.
1545 ** The proper sequence would be:
1546 ** o block console output
1547 ** o reset USB device
1548 ** o reprogram serial port
1549 ** o unblock console output
1551 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
1552 pdc_io_reset_devices();
1559 printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
1560 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
1563 ** Need to deal with DMA from LAN.
1564 ** Maybe use page zero boot device as a handle to talk
1565 ** to PDC about which device to shutdown.
1567 ** Netbooting, j6k v5.0 firmware says:
1568 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
1569 ** ARGH! invalid class.
1571 if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
1572 && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
1577 if (!IS_PLUTO(sba_dev->dev)) {
1578 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
1579 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
1580 __func__, sba_dev->sba_hpa, ioc_ctl);
1581 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
1582 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
1583 /* j6700 v1.6 firmware sets 0x294f */
1584 /* A500 firmware sets 0x4d */
1586 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
1588 #ifdef DEBUG_SBA_INIT
1589 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
1590 DBG_INIT(" 0x%Lx\n", ioc_ctl);
1594 if (IS_ASTRO(sba_dev->dev)) {
1596 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
1599 sba_dev->chip_resv.name = "Astro Intr Ack";
1600 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
1601 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
1602 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1605 } else if (IS_PLUTO(sba_dev->dev)) {
1608 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
1611 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
1612 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
1613 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
1614 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1617 sba_dev->iommu_resv.name = "IOVA Space";
1618 sba_dev->iommu_resv.start = 0x40000000UL;
1619 sba_dev->iommu_resv.end = 0x50000000UL - 1;
1620 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
1624 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
1625 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
1628 /* TODO - LOOKUP Ike/Stretch chipset mem map */
1630 /* XXX: What about Reo Grande? */
1632 sba_dev->num_ioc = num_ioc;
1633 for (i = 0; i < num_ioc; i++) {
1634 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa;
1637 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) {
1640 * Clear ROPE(N)_CONFIG AO bit.
1641 * Disables "NT Ordering" (~= !"Relaxed Ordering")
1642 * Overrides bit 1 in DMA Hint Sets.
1643 * Improves netperf UDP_STREAM by ~10% for bcm5701.
1645 if (IS_PLUTO(sba_dev->dev)) {
1646 void __iomem *rope_cfg;
1647 unsigned long cfg_val;
1649 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j;
1650 cfg_val = READ_REG(rope_cfg);
1651 cfg_val &= ~IOC_ROPE_AO;
1652 WRITE_REG(cfg_val, rope_cfg);
1656 ** Make sure the box crashes on rope errors.
1658 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j);
1661 /* flush out the last writes */
1662 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1664 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
1666 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
1667 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
1669 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
1670 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
1671 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
1674 if (IS_PLUTO(sba_dev->dev)) {
1675 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
1677 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
1683 sba_common_init(struct sba_device *sba_dev)
1687 /* add this one to the head of the list (order doesn't matter)
1688 ** This will be useful for debugging - especially if we get coredumps
1690 sba_dev->next = sba_list;
1693 for(i=0; i< sba_dev->num_ioc; i++) {
1695 #ifdef DEBUG_DMB_TRAP
1696 extern void iterate_pages(unsigned long , unsigned long ,
1697 void (*)(pte_t * , unsigned long),
1699 void set_data_memory_break(pte_t * , unsigned long);
1701 /* resource map size dictated by pdir_size */
1702 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
1704 /* Second part of PIRANHA BUG */
1705 if (piranha_bad_128k) {
1706 res_size -= (128*1024)/sizeof(u64);
1709 res_size >>= 3; /* convert bit count to byte count */
1710 DBG_INIT("%s() res_size 0x%x\n",
1711 __func__, res_size);
1713 sba_dev->ioc[i].res_size = res_size;
1714 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
1716 #ifdef DEBUG_DMB_TRAP
1717 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1718 set_data_memory_break, 0);
1721 if (NULL == sba_dev->ioc[i].res_map)
1723 panic("%s:%s() could not allocate resource map\n",
1724 __FILE__, __func__ );
1727 memset(sba_dev->ioc[i].res_map, 0, res_size);
1728 /* next available IOVP - circular search */
1729 sba_dev->ioc[i].res_hint = (unsigned long *)
1730 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
1732 #ifdef ASSERT_PDIR_SANITY
1733 /* Mark first bit busy - ie no IOVA 0 */
1734 sba_dev->ioc[i].res_map[0] = 0x80;
1735 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
1738 /* Third (and last) part of PIRANHA BUG */
1739 if (piranha_bad_128k) {
1740 /* region from +1408K to +1536 is un-usable. */
1742 int idx_start = (1408*1024/sizeof(u64)) >> 3;
1743 int idx_end = (1536*1024/sizeof(u64)) >> 3;
1744 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
1745 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
1747 /* mark that part of the io pdir busy */
1748 while (p_start < p_end)
1753 #ifdef DEBUG_DMB_TRAP
1754 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1755 set_data_memory_break, 0);
1756 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
1757 set_data_memory_break, 0);
1760 DBG_INIT("%s() %d res_map %x %p\n",
1761 __func__, i, res_size, sba_dev->ioc[i].res_map);
1764 spin_lock_init(&sba_dev->sba_lock);
1765 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
1767 #ifdef DEBUG_SBA_INIT
1769 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
1770 * (bit #61, big endian), we have to flush and sync every time
1771 * IO-PDIR is changed in Ike/Astro.
1773 if (ioc_needs_fdc) {
1774 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
1776 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
1781 #ifdef CONFIG_PROC_FS
1782 static int sba_proc_info(struct seq_file *m, void *p)
1784 struct sba_device *sba_dev = sba_list;
1785 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1786 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
1787 #ifdef SBA_COLLECT_STATS
1788 unsigned long avg = 0, min, max;
1792 seq_printf(m, "%s rev %d.%d\n",
1794 (sba_dev->hw_rev & 0x7) + 1,
1795 (sba_dev->hw_rev & 0x18) >> 3);
1796 seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
1797 (int)((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
1800 seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
1801 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
1803 seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
1804 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
1805 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
1806 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE));
1809 seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n",
1811 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
1812 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
1813 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18));
1815 #ifdef SBA_COLLECT_STATS
1816 seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
1817 total_pages - ioc->used_pages, ioc->used_pages,
1818 (int)(ioc->used_pages * 100 / total_pages));
1820 min = max = ioc->avg_search[0];
1821 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1822 avg += ioc->avg_search[i];
1823 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1824 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1826 avg /= SBA_SEARCH_SAMPLE;
1827 seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1830 seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
1831 ioc->msingle_calls, ioc->msingle_pages,
1832 (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls));
1834 /* KLUGE - unmap_sg calls unmap_single for each mapped page */
1835 min = ioc->usingle_calls;
1836 max = ioc->usingle_pages - ioc->usg_pages;
1837 seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
1838 min, max, (int)((max * 1000)/min));
1840 seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1841 ioc->msg_calls, ioc->msg_pages,
1842 (int)((ioc->msg_pages * 1000)/ioc->msg_calls));
1844 seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1845 ioc->usg_calls, ioc->usg_pages,
1846 (int)((ioc->usg_pages * 1000)/ioc->usg_calls));
1853 sba_proc_bitmap_info(struct seq_file *m, void *p)
1855 struct sba_device *sba_dev = sba_list;
1856 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1858 seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map,
1859 ioc->res_size, false);
1864 #endif /* CONFIG_PROC_FS */
1866 static const struct parisc_device_id sba_tbl[] __initconst = {
1867 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
1868 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
1869 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
1870 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
1871 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
1875 static int sba_driver_callback(struct parisc_device *);
1877 static struct parisc_driver sba_driver __refdata = {
1878 .name = MODULE_NAME,
1879 .id_table = sba_tbl,
1880 .probe = sba_driver_callback,
1884 ** Determine if sba should claim this chip (return 0) or not (return 1).
1885 ** If so, initialize the chip and tell other partners in crime they
1888 static int __init sba_driver_callback(struct parisc_device *dev)
1890 struct sba_device *sba_dev;
1894 void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE);
1895 #ifdef CONFIG_PROC_FS
1896 struct proc_dir_entry *root;
1899 sba_dump_ranges(sba_addr);
1901 /* Read HW Rev First */
1902 func_class = READ_REG(sba_addr + SBA_FCLASS);
1904 if (IS_ASTRO(dev)) {
1905 unsigned long fclass;
1906 static char astro_rev[]="Astro ?.?";
1908 /* Astro is broken...Read HW Rev First */
1909 fclass = READ_REG(sba_addr);
1911 astro_rev[6] = '1' + (char) (fclass & 0x7);
1912 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
1913 version = astro_rev;
1915 } else if (IS_IKE(dev)) {
1916 static char ike_rev[] = "Ike rev ?";
1917 ike_rev[8] = '0' + (char) (func_class & 0xff);
1919 } else if (IS_PLUTO(dev)) {
1920 static char pluto_rev[]="Pluto ?.?";
1921 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
1922 pluto_rev[8] = '0' + (char) (func_class & 0x0f);
1923 version = pluto_rev;
1925 static char reo_rev[] = "REO rev ?";
1926 reo_rev[8] = '0' + (char) (func_class & 0xff);
1930 if (!global_ioc_cnt) {
1931 global_ioc_cnt = count_parisc_driver(&sba_driver);
1933 /* Astro and Pluto have one IOC per SBA */
1934 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev)))
1935 global_ioc_cnt *= 2;
1938 printk(KERN_INFO "%s found %s at 0x%llx\n",
1939 MODULE_NAME, version, (unsigned long long)dev->hpa.start);
1941 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL);
1943 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
1947 parisc_set_drvdata(dev, sba_dev);
1949 for(i=0; i<MAX_IOC; i++)
1950 spin_lock_init(&(sba_dev->ioc[i].res_lock));
1953 sba_dev->hw_rev = func_class;
1954 sba_dev->name = dev->name;
1955 sba_dev->sba_hpa = sba_addr;
1957 sba_get_pat_resources(sba_dev);
1958 sba_hw_init(sba_dev);
1959 sba_common_init(sba_dev);
1961 hppa_dma_ops = &sba_ops;
1963 #ifdef CONFIG_PROC_FS
1964 switch (dev->id.hversion) {
1965 case PLUTO_MCKINLEY_PORT:
1966 root = proc_mckinley_root;
1968 case ASTRO_RUNWAY_PORT:
1969 case IKE_MERCED_PORT:
1971 root = proc_runway_root;
1975 proc_create_single("sba_iommu", 0, root, sba_proc_info);
1976 proc_create_single("sba_iommu-bitmap", 0, root, sba_proc_bitmap_info);
1982 ** One time initialization to let the world know the SBA was found.
1983 ** This is the only routine which is NOT static.
1984 ** Must be called exactly once before pci_init().
1986 void __init sba_init(void)
1988 register_parisc_driver(&sba_driver);
1993 * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
1994 * @dev: The parisc device.
1996 * Returns the appropriate IOMMU data for the given parisc PCI controller.
1997 * This is cached and used later for PCI DMA Mapping.
1999 void * sba_get_iommu(struct parisc_device *pci_hba)
2001 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2002 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2003 char t = sba_dev->id.hw_type;
2004 int iocnum = (pci_hba->hw_path >> 3); /* rope # */
2006 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
2008 return &(sba->ioc[iocnum]);
2013 * sba_directed_lmmio - return first directed LMMIO range routed to rope
2014 * @pa_dev: The parisc device.
2015 * @r: resource PCI host controller wants start/end fields assigned.
2017 * For the given parisc PCI controller, determine if any direct ranges
2018 * are routed down the corresponding rope.
2020 void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
2022 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2023 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2024 char t = sba_dev->id.hw_type;
2026 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2028 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
2030 r->start = r->end = 0;
2032 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
2033 for (i=0; i<4; i++) {
2035 void __iomem *reg = sba->sba_hpa + i*0x18;
2037 base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
2038 if ((base & 1) == 0)
2039 continue; /* not enabled */
2041 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
2043 if ((size & (ROPES_PER_IOC-1)) != rope)
2044 continue; /* directed down different rope */
2046 r->start = (base & ~1UL) | PCI_F_EXTEND;
2047 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
2048 r->end = r->start + size;
2049 r->flags = IORESOURCE_MEM;
2055 * sba_distributed_lmmio - return portion of distributed LMMIO range
2056 * @pa_dev: The parisc device.
2057 * @r: resource PCI host controller wants start/end fields assigned.
2059 * For the given parisc PCI controller, return portion of distributed LMMIO
2060 * range. The distributed LMMIO is always present and it's just a question
2061 * of the base address and size of the range.
2063 void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
2065 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2066 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2067 char t = sba_dev->id.hw_type;
2069 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2071 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
2073 r->start = r->end = 0;
2075 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
2076 if ((base & 1) == 0) {
2077 BUG(); /* Gah! Distr Range wasn't enabled! */
2081 r->start = (base & ~1UL) | PCI_F_EXTEND;
2083 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
2084 r->start += rope * (size + 1); /* adjust base for this rope */
2085 r->end = r->start + size;
2086 r->flags = IORESOURCE_MEM;