1 // SPDX-License-Identifier: GPL-2.0
3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Kishon Vijay Abraham I <kishon@ti.com>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/of_device.h>
19 #include <linux/of_gpio.h>
20 #include <linux/of_pci.h>
21 #include <linux/pci.h>
22 #include <linux/phy/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/resource.h>
26 #include <linux/types.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/regmap.h>
30 #include "../../pci.h"
31 #include "pcie-designware.h"
33 /* PCIe controller wrapper DRA7XX configuration registers */
35 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024
36 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028
37 #define ERR_SYS BIT(0)
38 #define ERR_FATAL BIT(1)
39 #define ERR_NONFATAL BIT(2)
40 #define ERR_COR BIT(3)
41 #define ERR_AXI BIT(4)
42 #define ERR_ECRC BIT(5)
43 #define PME_TURN_OFF BIT(8)
44 #define PME_TO_ACK BIT(9)
45 #define PM_PME BIT(10)
46 #define LINK_REQ_RST BIT(11)
47 #define LINK_UP_EVT BIT(12)
48 #define CFG_BME_EVT BIT(13)
49 #define CFG_MSE_EVT BIT(14)
50 #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
51 ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
52 LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
54 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034
55 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038
61 #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
63 #define PCIECTRL_TI_CONF_DEVICE_TYPE 0x0100
64 #define DEVICE_TYPE_EP 0x0
65 #define DEVICE_TYPE_LEG_EP 0x1
66 #define DEVICE_TYPE_RC 0x4
68 #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
71 #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
72 #define LINK_UP BIT(16)
73 #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
75 #define EXP_CAP_ID_OFFSET 0x70
77 #define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124
78 #define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128
80 #define PCIECTRL_TI_CONF_MSI_XMT 0x012c
81 #define MSI_REQ_GRANT BIT(0)
82 #define MSI_VECTOR_SHIFT 7
84 #define PCIE_1LANE_2LANE_SELECTION BIT(13)
85 #define PCIE_B1C0_MODE_SEL BIT(2)
86 #define PCIE_B0_B1_TSYNCEN BIT(0)
90 void __iomem *base; /* DT ti_conf */
91 int phy_count; /* DT phy-names count */
94 struct irq_domain *irq_domain;
95 enum dw_pcie_device_mode mode;
98 struct dra7xx_pcie_of_data {
99 enum dw_pcie_device_mode mode;
100 u32 b1co_mode_sel_mask;
103 #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
105 static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
107 return readl(pcie->base + offset);
110 static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
113 writel(value, pcie->base + offset);
116 static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
118 return pci_addr & DRA7XX_CPU_TO_BUS_ADDR;
121 static int dra7xx_pcie_link_up(struct dw_pcie *pci)
123 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
124 u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
126 return !!(reg & LINK_UP);
129 static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
131 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
134 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
136 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
139 static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
141 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
142 struct device *dev = pci->dev;
144 u32 exp_cap_off = EXP_CAP_ID_OFFSET;
146 if (dw_pcie_link_up(pci)) {
147 dev_err(dev, "link is already up\n");
151 if (dra7xx->link_gen == 1) {
152 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
154 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
155 reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
156 reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
157 dw_pcie_write(pci->dbi_base + exp_cap_off +
158 PCI_EXP_LNKCAP, 4, reg);
161 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
163 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
164 reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
165 reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
166 dw_pcie_write(pci->dbi_base + exp_cap_off +
167 PCI_EXP_LNKCTL2, 2, reg);
171 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
173 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
178 static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
180 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
181 LEG_EP_INTERRUPTS | MSI);
183 dra7xx_pcie_writel(dra7xx,
184 PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
185 MSI | LEG_EP_INTERRUPTS);
188 static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
190 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
192 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
196 static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
198 dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
199 dra7xx_pcie_enable_msi_interrupts(dra7xx);
202 static int dra7xx_pcie_host_init(struct pcie_port *pp)
204 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
205 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
207 dw_pcie_setup_rc(pp);
209 dra7xx_pcie_establish_link(pci);
210 dw_pcie_wait_for_link(pci);
211 dw_pcie_msi_init(pp);
212 dra7xx_pcie_enable_interrupts(dra7xx);
217 static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
218 .host_init = dra7xx_pcie_host_init,
221 static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
222 irq_hw_number_t hwirq)
224 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
225 irq_set_chip_data(irq, domain->host_data);
230 static const struct irq_domain_ops intx_domain_ops = {
231 .map = dra7xx_pcie_intx_map,
232 .xlate = pci_irqd_intx_xlate,
235 static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
237 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
238 struct device *dev = pci->dev;
239 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
240 struct device_node *node = dev->of_node;
241 struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
243 if (!pcie_intc_node) {
244 dev_err(dev, "No PCIe Intc node found\n");
248 dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
249 &intx_domain_ops, pp);
250 if (!dra7xx->irq_domain) {
251 dev_err(dev, "Failed to get a INTx IRQ domain\n");
258 static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
260 struct dra7xx_pcie *dra7xx = arg;
261 struct dw_pcie *pci = dra7xx->pci;
262 struct pcie_port *pp = &pci->pp;
266 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
270 dw_handle_msi_irq(pp);
276 for_each_set_bit(bit, ®, PCI_NUM_INTX) {
277 virq = irq_find_mapping(dra7xx->irq_domain, bit);
279 generic_handle_irq(virq);
284 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
289 static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
291 struct dra7xx_pcie *dra7xx = arg;
292 struct dw_pcie *pci = dra7xx->pci;
293 struct device *dev = pci->dev;
294 struct dw_pcie_ep *ep = &pci->ep;
297 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
300 dev_dbg(dev, "System Error\n");
303 dev_dbg(dev, "Fatal Error\n");
305 if (reg & ERR_NONFATAL)
306 dev_dbg(dev, "Non Fatal Error\n");
309 dev_dbg(dev, "Correctable Error\n");
312 dev_dbg(dev, "AXI tag lookup fatal Error\n");
315 dev_dbg(dev, "ECRC Error\n");
317 if (reg & PME_TURN_OFF)
319 "Power Management Event Turn-Off message received\n");
321 if (reg & PME_TO_ACK)
323 "Power Management Turn-Off Ack message received\n");
326 dev_dbg(dev, "PM Power Management Event message received\n");
328 if (reg & LINK_REQ_RST)
329 dev_dbg(dev, "Link Request Reset\n");
331 if (reg & LINK_UP_EVT) {
332 if (dra7xx->mode == DW_PCIE_EP_TYPE)
333 dw_pcie_ep_linkup(ep);
334 dev_dbg(dev, "Link-up state change\n");
337 if (reg & CFG_BME_EVT)
338 dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
340 if (reg & CFG_MSE_EVT)
341 dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
343 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
348 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
350 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
351 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
354 for (bar = BAR_0; bar <= BAR_5; bar++)
355 dw_pcie_ep_reset_bar(pci, bar);
357 dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
360 static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx)
362 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1);
364 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1);
367 static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
372 reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT;
373 reg |= MSI_REQ_GRANT;
374 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg);
377 static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
378 enum pci_epc_irq_type type, u16 interrupt_num)
380 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
381 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
384 case PCI_EPC_IRQ_LEGACY:
385 dra7xx_pcie_raise_legacy_irq(dra7xx);
387 case PCI_EPC_IRQ_MSI:
388 dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
391 dev_err(pci->dev, "UNKNOWN IRQ type\n");
397 static struct dw_pcie_ep_ops pcie_ep_ops = {
398 .ep_init = dra7xx_pcie_ep_init,
399 .raise_irq = dra7xx_pcie_raise_irq,
402 static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
403 struct platform_device *pdev)
406 struct dw_pcie_ep *ep;
407 struct resource *res;
408 struct device *dev = &pdev->dev;
409 struct dw_pcie *pci = dra7xx->pci;
412 ep->ops = &pcie_ep_ops;
414 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics");
415 pci->dbi_base = devm_ioremap_resource(dev, res);
416 if (IS_ERR(pci->dbi_base))
417 return PTR_ERR(pci->dbi_base);
419 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics2");
420 pci->dbi_base2 = devm_ioremap_resource(dev, res);
421 if (IS_ERR(pci->dbi_base2))
422 return PTR_ERR(pci->dbi_base2);
424 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
428 ep->phys_base = res->start;
429 ep->addr_size = resource_size(res);
431 ret = dw_pcie_ep_init(ep);
433 dev_err(dev, "failed to initialize endpoint\n");
440 static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
441 struct platform_device *pdev)
444 struct dw_pcie *pci = dra7xx->pci;
445 struct pcie_port *pp = &pci->pp;
446 struct device *dev = pci->dev;
447 struct resource *res;
449 pp->irq = platform_get_irq(pdev, 1);
451 dev_err(dev, "missing IRQ resource\n");
455 ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
456 IRQF_SHARED | IRQF_NO_THREAD,
457 "dra7-pcie-msi", dra7xx);
459 dev_err(dev, "failed to request irq\n");
463 ret = dra7xx_pcie_init_irq_domain(pp);
467 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
468 pci->dbi_base = devm_ioremap_resource(dev, res);
469 if (IS_ERR(pci->dbi_base))
470 return PTR_ERR(pci->dbi_base);
472 pp->ops = &dra7xx_pcie_host_ops;
474 ret = dw_pcie_host_init(pp);
476 dev_err(dev, "failed to initialize host\n");
483 static const struct dw_pcie_ops dw_pcie_ops = {
484 .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup,
485 .start_link = dra7xx_pcie_establish_link,
486 .stop_link = dra7xx_pcie_stop_link,
487 .link_up = dra7xx_pcie_link_up,
490 static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx)
492 int phy_count = dra7xx->phy_count;
494 while (phy_count--) {
495 phy_power_off(dra7xx->phy[phy_count]);
496 phy_exit(dra7xx->phy[phy_count]);
500 static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
502 int phy_count = dra7xx->phy_count;
506 for (i = 0; i < phy_count; i++) {
507 ret = phy_init(dra7xx->phy[i]);
511 ret = phy_power_on(dra7xx->phy[i]);
513 phy_exit(dra7xx->phy[i]);
522 phy_power_off(dra7xx->phy[i]);
523 phy_exit(dra7xx->phy[i]);
529 static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = {
530 .mode = DW_PCIE_RC_TYPE,
533 static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
534 .mode = DW_PCIE_EP_TYPE,
537 static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = {
538 .b1co_mode_sel_mask = BIT(2),
539 .mode = DW_PCIE_RC_TYPE,
542 static const struct dra7xx_pcie_of_data dra726_pcie_rc_of_data = {
543 .b1co_mode_sel_mask = GENMASK(3, 2),
544 .mode = DW_PCIE_RC_TYPE,
547 static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = {
548 .b1co_mode_sel_mask = BIT(2),
549 .mode = DW_PCIE_EP_TYPE,
552 static const struct dra7xx_pcie_of_data dra726_pcie_ep_of_data = {
553 .b1co_mode_sel_mask = GENMASK(3, 2),
554 .mode = DW_PCIE_EP_TYPE,
557 static const struct of_device_id of_dra7xx_pcie_match[] = {
559 .compatible = "ti,dra7-pcie",
560 .data = &dra7xx_pcie_rc_of_data,
563 .compatible = "ti,dra7-pcie-ep",
564 .data = &dra7xx_pcie_ep_of_data,
567 .compatible = "ti,dra746-pcie-rc",
568 .data = &dra746_pcie_rc_of_data,
571 .compatible = "ti,dra726-pcie-rc",
572 .data = &dra726_pcie_rc_of_data,
575 .compatible = "ti,dra746-pcie-ep",
576 .data = &dra746_pcie_ep_of_data,
579 .compatible = "ti,dra726-pcie-ep",
580 .data = &dra726_pcie_ep_of_data,
586 * dra7xx_pcie_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
587 * @dra7xx: the dra7xx device where the workaround should be applied
589 * Access to the PCIe slave port that are not 32-bit aligned will result
590 * in incorrect mapping to TLP Address and Byte enable fields. Therefore,
591 * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
594 * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
596 static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
599 struct device_node *np = dev->of_node;
600 struct of_phandle_args args;
601 struct regmap *regmap;
603 regmap = syscon_regmap_lookup_by_phandle(np,
604 "ti,syscon-unaligned-access");
605 if (IS_ERR(regmap)) {
606 dev_dbg(dev, "can't get ti,syscon-unaligned-access\n");
610 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-unaligned-access",
613 dev_err(dev, "failed to parse ti,syscon-unaligned-access\n");
617 ret = regmap_update_bits(regmap, args.args[0], args.args[1],
620 dev_err(dev, "failed to enable unaligned access\n");
622 of_node_put(args.np);
627 static int dra7xx_pcie_configure_two_lane(struct device *dev,
628 u32 b1co_mode_sel_mask)
630 struct device_node *np = dev->of_node;
631 struct regmap *pcie_syscon;
632 unsigned int pcie_reg;
636 pcie_syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-lane-sel");
637 if (IS_ERR(pcie_syscon)) {
638 dev_err(dev, "unable to get ti,syscon-lane-sel\n");
642 if (of_property_read_u32_index(np, "ti,syscon-lane-sel", 1,
644 dev_err(dev, "couldn't get lane selection reg offset\n");
648 mask = b1co_mode_sel_mask | PCIE_B0_B1_TSYNCEN;
649 val = PCIE_B1C0_MODE_SEL | PCIE_B0_B1_TSYNCEN;
650 regmap_update_bits(pcie_syscon, pcie_reg, mask, val);
655 static int __init dra7xx_pcie_probe(struct platform_device *pdev)
663 struct device_link **link;
665 struct resource *res;
667 struct dra7xx_pcie *dra7xx;
668 struct device *dev = &pdev->dev;
669 struct device_node *np = dev->of_node;
671 struct gpio_desc *reset;
672 const struct of_device_id *match;
673 const struct dra7xx_pcie_of_data *data;
674 enum dw_pcie_device_mode mode;
675 u32 b1co_mode_sel_mask;
677 match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
681 data = (struct dra7xx_pcie_of_data *)match->data;
682 mode = (enum dw_pcie_device_mode)data->mode;
683 b1co_mode_sel_mask = data->b1co_mode_sel_mask;
685 dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
689 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
694 pci->ops = &dw_pcie_ops;
696 irq = platform_get_irq(pdev, 0);
698 dev_err(dev, "missing IRQ resource: %d\n", irq);
702 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
703 base = devm_ioremap_nocache(dev, res->start, resource_size(res));
707 phy_count = of_property_count_strings(np, "phy-names");
709 dev_err(dev, "unable to find the strings\n");
713 phy = devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL);
717 link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL);
721 for (i = 0; i < phy_count; i++) {
722 snprintf(name, sizeof(name), "pcie-phy%d", i);
723 phy[i] = devm_phy_get(dev, name);
725 return PTR_ERR(phy[i]);
727 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
737 dra7xx->phy_count = phy_count;
739 if (phy_count == 2) {
740 ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask);
742 dra7xx->phy_count = 1; /* Fallback to x1 lane mode */
745 ret = dra7xx_pcie_enable_phy(dra7xx);
747 dev_err(dev, "failed to enable phy\n");
751 platform_set_drvdata(pdev, dra7xx);
753 pm_runtime_enable(dev);
754 ret = pm_runtime_get_sync(dev);
756 dev_err(dev, "pm_runtime_get_sync failed\n");
760 reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
762 ret = PTR_ERR(reset);
763 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
767 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
769 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
771 dra7xx->link_gen = of_pci_get_max_link_speed(np);
772 if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
773 dra7xx->link_gen = 2;
776 case DW_PCIE_RC_TYPE:
777 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
782 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
785 ret = dra7xx_pcie_unaligned_memaccess(dev);
787 dev_err(dev, "WA for Errata i870 not applied\n");
789 ret = dra7xx_add_pcie_port(dra7xx, pdev);
793 case DW_PCIE_EP_TYPE:
794 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) {
799 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
802 ret = dra7xx_pcie_unaligned_memaccess(dev);
806 ret = dra7xx_add_pcie_ep(dra7xx, pdev);
811 dev_err(dev, "INVALID device type %d\n", mode);
815 ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
816 IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
818 dev_err(dev, "failed to request irq\n");
828 pm_runtime_disable(dev);
829 dra7xx_pcie_disable_phy(dra7xx);
833 device_link_del(link[i]);
838 #ifdef CONFIG_PM_SLEEP
839 static int dra7xx_pcie_suspend(struct device *dev)
841 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
842 struct dw_pcie *pci = dra7xx->pci;
845 if (dra7xx->mode != DW_PCIE_RC_TYPE)
849 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
850 val &= ~PCI_COMMAND_MEMORY;
851 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
856 static int dra7xx_pcie_resume(struct device *dev)
858 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
859 struct dw_pcie *pci = dra7xx->pci;
862 if (dra7xx->mode != DW_PCIE_RC_TYPE)
866 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
867 val |= PCI_COMMAND_MEMORY;
868 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
873 static int dra7xx_pcie_suspend_noirq(struct device *dev)
875 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
877 dra7xx_pcie_disable_phy(dra7xx);
882 static int dra7xx_pcie_resume_noirq(struct device *dev)
884 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
887 ret = dra7xx_pcie_enable_phy(dra7xx);
889 dev_err(dev, "failed to enable phy\n");
897 static void dra7xx_pcie_shutdown(struct platform_device *pdev)
899 struct device *dev = &pdev->dev;
900 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
903 dra7xx_pcie_stop_link(dra7xx->pci);
905 ret = pm_runtime_put_sync(dev);
907 dev_dbg(dev, "pm_runtime_put_sync failed\n");
909 pm_runtime_disable(dev);
910 dra7xx_pcie_disable_phy(dra7xx);
913 static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
914 SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
915 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
916 dra7xx_pcie_resume_noirq)
919 static struct platform_driver dra7xx_pcie_driver = {
922 .of_match_table = of_dra7xx_pcie_match,
923 .suppress_bind_attrs = true,
924 .pm = &dra7xx_pcie_pm_ops,
926 .shutdown = dra7xx_pcie_shutdown,
928 builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);