1 // SPDX-License-Identifier: GPL-2.0
3 * Synopsys DesignWare PCIe Endpoint controller driver
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
11 #include "pcie-designware.h"
12 #include <linux/pci-epc.h>
13 #include <linux/pci-epf.h>
15 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
17 struct pci_epc *epc = ep->epc;
22 static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar,
27 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
28 dw_pcie_dbi_ro_wr_en(pci);
29 dw_pcie_writel_dbi2(pci, reg, 0x0);
30 dw_pcie_writel_dbi(pci, reg, 0x0);
31 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
32 dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
33 dw_pcie_writel_dbi(pci, reg + 4, 0x0);
35 dw_pcie_dbi_ro_wr_dis(pci);
38 void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
40 __dw_pcie_ep_reset_bar(pci, bar, 0);
43 static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
46 u8 cap_id, next_cap_ptr;
49 reg = dw_pcie_readw_dbi(pci, cap_ptr);
50 next_cap_ptr = (reg & 0xff00) >> 8;
51 cap_id = (reg & 0x00ff);
53 if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX)
59 return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
62 static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap)
67 reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
68 next_cap_ptr = (reg & 0x00ff);
73 return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
76 static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
77 struct pci_epf_header *hdr)
79 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
80 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
82 dw_pcie_dbi_ro_wr_en(pci);
83 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid);
84 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid);
85 dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid);
86 dw_pcie_writeb_dbi(pci, PCI_CLASS_PROG, hdr->progif_code);
87 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE,
88 hdr->subclass_code | hdr->baseclass_code << 8);
89 dw_pcie_writeb_dbi(pci, PCI_CACHE_LINE_SIZE,
90 hdr->cache_line_size);
91 dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_VENDOR_ID,
92 hdr->subsys_vendor_id);
93 dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id);
94 dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN,
96 dw_pcie_dbi_ro_wr_dis(pci);
101 static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
103 enum dw_pcie_as_type as_type)
107 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
109 free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
110 if (free_win >= ep->num_ib_windows) {
111 dev_err(pci->dev, "No free inbound window\n");
115 ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
118 dev_err(pci->dev, "Failed to program IB window\n");
122 ep->bar_to_atu[bar] = free_win;
123 set_bit(free_win, ep->ib_window_map);
128 static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
129 u64 pci_addr, size_t size)
132 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
134 free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
135 if (free_win >= ep->num_ob_windows) {
136 dev_err(pci->dev, "No free outbound window\n");
140 dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
141 phys_addr, pci_addr, size);
143 set_bit(free_win, ep->ob_window_map);
144 ep->outbound_addr[free_win] = phys_addr;
149 static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
150 struct pci_epf_bar *epf_bar)
152 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
153 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
154 enum pci_barno bar = epf_bar->barno;
155 u32 atu_index = ep->bar_to_atu[bar];
157 __dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags);
159 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
160 clear_bit(atu_index, ep->ib_window_map);
163 static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
164 struct pci_epf_bar *epf_bar)
167 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
168 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
169 enum pci_barno bar = epf_bar->barno;
170 size_t size = epf_bar->size;
171 int flags = epf_bar->flags;
172 enum dw_pcie_as_type as_type;
173 u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
175 if (!(flags & PCI_BASE_ADDRESS_SPACE))
176 as_type = DW_PCIE_AS_MEM;
178 as_type = DW_PCIE_AS_IO;
180 ret = dw_pcie_ep_inbound_atu(ep, bar, epf_bar->phys_addr, as_type);
184 dw_pcie_dbi_ro_wr_en(pci);
186 dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
187 dw_pcie_writel_dbi(pci, reg, flags);
189 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
190 dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
191 dw_pcie_writel_dbi(pci, reg + 4, 0);
194 dw_pcie_dbi_ro_wr_dis(pci);
199 static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr,
204 for (index = 0; index < ep->num_ob_windows; index++) {
205 if (ep->outbound_addr[index] != addr)
214 static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
219 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
220 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
222 ret = dw_pcie_find_index(ep, addr, &atu_index);
226 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
227 clear_bit(atu_index, ep->ob_window_map);
230 static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
232 u64 pci_addr, size_t size)
235 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
236 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
238 ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size);
240 dev_err(pci->dev, "Failed to enable address\n");
247 static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
249 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
250 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
256 reg = ep->msi_cap + PCI_MSI_FLAGS;
257 val = dw_pcie_readw_dbi(pci, reg);
258 if (!(val & PCI_MSI_FLAGS_ENABLE))
261 val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
266 static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
268 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
269 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
275 reg = ep->msi_cap + PCI_MSI_FLAGS;
276 val = dw_pcie_readw_dbi(pci, reg);
277 val &= ~PCI_MSI_FLAGS_QMASK;
278 val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
279 dw_pcie_dbi_ro_wr_en(pci);
280 dw_pcie_writew_dbi(pci, reg, val);
281 dw_pcie_dbi_ro_wr_dis(pci);
286 static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
288 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
289 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
295 reg = ep->msix_cap + PCI_MSIX_FLAGS;
296 val = dw_pcie_readw_dbi(pci, reg);
297 if (!(val & PCI_MSIX_FLAGS_ENABLE))
300 val &= PCI_MSIX_FLAGS_QSIZE;
305 static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
307 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
308 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
314 reg = ep->msix_cap + PCI_MSIX_FLAGS;
315 val = dw_pcie_readw_dbi(pci, reg);
316 val &= ~PCI_MSIX_FLAGS_QSIZE;
318 dw_pcie_dbi_ro_wr_en(pci);
319 dw_pcie_writew_dbi(pci, reg, val);
320 dw_pcie_dbi_ro_wr_dis(pci);
325 static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
326 enum pci_epc_irq_type type, u16 interrupt_num)
328 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
330 if (!ep->ops->raise_irq)
333 return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
336 static void dw_pcie_ep_stop(struct pci_epc *epc)
338 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
339 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
341 if (!pci->ops->stop_link)
344 pci->ops->stop_link(pci);
347 static int dw_pcie_ep_start(struct pci_epc *epc)
349 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
350 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
352 if (!pci->ops->start_link)
355 return pci->ops->start_link(pci);
358 static const struct pci_epc_ops epc_ops = {
359 .write_header = dw_pcie_ep_write_header,
360 .set_bar = dw_pcie_ep_set_bar,
361 .clear_bar = dw_pcie_ep_clear_bar,
362 .map_addr = dw_pcie_ep_map_addr,
363 .unmap_addr = dw_pcie_ep_unmap_addr,
364 .set_msi = dw_pcie_ep_set_msi,
365 .get_msi = dw_pcie_ep_get_msi,
366 .set_msix = dw_pcie_ep_set_msix,
367 .get_msix = dw_pcie_ep_get_msix,
368 .raise_irq = dw_pcie_ep_raise_irq,
369 .start = dw_pcie_ep_start,
370 .stop = dw_pcie_ep_stop,
373 int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
375 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
376 struct device *dev = pci->dev;
378 dev_err(dev, "EP cannot trigger legacy IRQs\n");
383 int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
386 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
387 struct pci_epc *epc = ep->epc;
388 u16 msg_ctrl, msg_data;
389 u32 msg_addr_lower, msg_addr_upper, reg;
397 /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
398 reg = ep->msi_cap + PCI_MSI_FLAGS;
399 msg_ctrl = dw_pcie_readw_dbi(pci, reg);
400 has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
401 reg = ep->msi_cap + PCI_MSI_ADDRESS_LO;
402 msg_addr_lower = dw_pcie_readl_dbi(pci, reg);
404 reg = ep->msi_cap + PCI_MSI_ADDRESS_HI;
405 msg_addr_upper = dw_pcie_readl_dbi(pci, reg);
406 reg = ep->msi_cap + PCI_MSI_DATA_64;
407 msg_data = dw_pcie_readw_dbi(pci, reg);
410 reg = ep->msi_cap + PCI_MSI_DATA_32;
411 msg_data = dw_pcie_readw_dbi(pci, reg);
413 msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
414 ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
415 epc->mem->page_size);
419 writel(msg_data | (interrupt_num - 1), ep->msi_mem);
421 dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
426 int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
429 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
430 struct pci_epc *epc = ep->epc;
432 u32 bar_addr_upper, bar_addr_lower;
433 u32 msg_addr_upper, msg_addr_lower;
434 u32 reg, msg_data, vec_ctrl;
435 u64 tbl_addr, msg_addr, reg_u64;
436 void __iomem *msix_tbl;
439 reg = ep->msix_cap + PCI_MSIX_TABLE;
440 tbl_offset = dw_pcie_readl_dbi(pci, reg);
441 bir = (tbl_offset & PCI_MSIX_TABLE_BIR);
442 tbl_offset &= PCI_MSIX_TABLE_OFFSET;
444 reg = PCI_BASE_ADDRESS_0 + (4 * bir);
446 bar_addr_lower = dw_pcie_readl_dbi(pci, reg);
447 reg_u64 = (bar_addr_lower & PCI_BASE_ADDRESS_MEM_TYPE_MASK);
448 if (reg_u64 == PCI_BASE_ADDRESS_MEM_TYPE_64)
449 bar_addr_upper = dw_pcie_readl_dbi(pci, reg + 4);
451 tbl_addr = ((u64) bar_addr_upper) << 32 | bar_addr_lower;
452 tbl_addr += (tbl_offset + ((interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE));
453 tbl_addr &= PCI_BASE_ADDRESS_MEM_MASK;
455 msix_tbl = ioremap_nocache(ep->phys_base + tbl_addr,
456 PCI_MSIX_ENTRY_SIZE);
460 msg_addr_lower = readl(msix_tbl + PCI_MSIX_ENTRY_LOWER_ADDR);
461 msg_addr_upper = readl(msix_tbl + PCI_MSIX_ENTRY_UPPER_ADDR);
462 msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
463 msg_data = readl(msix_tbl + PCI_MSIX_ENTRY_DATA);
464 vec_ctrl = readl(msix_tbl + PCI_MSIX_ENTRY_VECTOR_CTRL);
468 if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT)
471 ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
472 epc->mem->page_size);
476 writel(msg_data, ep->msi_mem);
478 dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
483 void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
485 struct pci_epc *epc = ep->epc;
487 pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
488 epc->mem->page_size);
490 pci_epc_mem_exit(epc);
493 int dw_pcie_ep_init(struct dw_pcie_ep *ep)
498 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
499 struct device *dev = pci->dev;
500 struct device_node *np = dev->of_node;
502 if (!pci->dbi_base || !pci->dbi_base2) {
503 dev_err(dev, "dbi_base/dbi_base2 is not populated\n");
507 ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
509 dev_err(dev, "Unable to read *num-ib-windows* property\n");
512 if (ep->num_ib_windows > MAX_IATU_IN) {
513 dev_err(dev, "Invalid *num-ib-windows*\n");
517 ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
519 dev_err(dev, "Unable to read *num-ob-windows* property\n");
522 if (ep->num_ob_windows > MAX_IATU_OUT) {
523 dev_err(dev, "Invalid *num-ob-windows*\n");
527 ep->ib_window_map = devm_kcalloc(dev,
528 BITS_TO_LONGS(ep->num_ib_windows),
531 if (!ep->ib_window_map)
534 ep->ob_window_map = devm_kcalloc(dev,
535 BITS_TO_LONGS(ep->num_ob_windows),
538 if (!ep->ob_window_map)
541 addr = devm_kcalloc(dev, ep->num_ob_windows, sizeof(phys_addr_t),
545 ep->outbound_addr = addr;
547 epc = devm_pci_epc_create(dev, &epc_ops);
549 dev_err(dev, "Failed to create epc device\n");
554 epc_set_drvdata(epc, ep);
556 if (ep->ops->ep_init)
557 ep->ops->ep_init(ep);
559 ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
561 epc->max_functions = 1;
563 ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
566 dev_err(dev, "Failed to initialize address space\n");
570 ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
571 epc->mem->page_size);
573 dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
576 ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI);
578 ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX);