1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
11 * Author: Phil Edworthy <phil.edworthy@renesas.com>
14 #include <linux/bitops.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/phy/phy.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/slab.h>
33 #define PCIECAR 0x000010
34 #define PCIECCTLR 0x000018
35 #define CONFIG_SEND_ENABLE BIT(31)
36 #define TYPE0 (0 << 8)
38 #define PCIECDR 0x000020
39 #define PCIEMSR 0x000028
40 #define PCIEINTXR 0x000400
41 #define PCIEPHYSR 0x0007f0
43 #define PCIEMSITXR 0x000840
45 /* Transfer control */
46 #define PCIETCTLR 0x02000
47 #define DL_DOWN BIT(3)
49 #define PCIETSTR 0x02004
50 #define DATA_LINK_ACTIVE BIT(0)
51 #define PCIEERRFR 0x02020
52 #define UNSUPPORTED_REQUEST BIT(4)
53 #define PCIEMSIFR 0x02044
54 #define PCIEMSIALR 0x02048
56 #define PCIEMSIAUR 0x0204c
57 #define PCIEMSIIER 0x02050
59 /* root port address */
60 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
62 /* local address reg & mask */
63 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
64 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
65 #define LAM_PREFETCH BIT(3)
66 #define LAM_64BIT BIT(2)
67 #define LAR_ENABLE BIT(1)
69 /* PCIe address reg & mask */
70 #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
71 #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
72 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
73 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
74 #define PAR_ENABLE BIT(31)
75 #define IO_SPACE BIT(8)
78 #define PCICONF(x) (0x010000 + ((x) * 0x4))
79 #define PMCAP(x) (0x010040 + ((x) * 0x4))
80 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
81 #define VCCAP(x) (0x010100 + ((x) * 0x4))
84 #define IDSETR1 0x011004
85 #define TLCTLR 0x011048
86 #define MACSR 0x011054
87 #define SPCHGFIN BIT(4)
88 #define SPCHGFAIL BIT(6)
89 #define SPCHGSUC BIT(7)
90 #define LINK_SPEED (0xf << 16)
91 #define LINK_SPEED_2_5GTS (1 << 16)
92 #define LINK_SPEED_5_0GTS (2 << 16)
93 #define MACCTLR 0x011058
94 #define SPEED_CHANGE BIT(24)
95 #define SCRAMBLE_DISABLE BIT(27)
97 #define MACS2R 0x011078
98 #define MACCGSPSETR 0x011084
99 #define SPCNGRSN BIT(31)
102 #define H1_PCIEPHYADRR 0x04000c
103 #define WRITE_CMD BIT(16)
104 #define PHY_ACK BIT(24)
108 #define H1_PCIEPHYDOUTR 0x040014
111 #define GEN2_PCIEPHYADDR 0x780
112 #define GEN2_PCIEPHYDATA 0x784
113 #define GEN2_PCIEPHYCTRL 0x78c
115 #define INT_PCI_MSI_NR 32
117 #define RCONF(x) (PCICONF(0) + (x))
118 #define RPMCAP(x) (PMCAP(0) + (x))
119 #define REXPCAP(x) (EXPCAP(0) + (x))
120 #define RVCCAP(x) (VCCAP(0) + (x))
122 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
123 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
124 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
126 #define RCAR_PCI_MAX_RESOURCES 4
127 #define MAX_NR_INBOUND_MAPS 6
130 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
131 struct irq_domain *domain;
132 struct msi_controller chip;
139 static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
141 return container_of(chip, struct rcar_msi, chip);
144 /* Structure representing the PCIe interface */
149 struct list_head resources;
155 static void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val,
158 writel(val, pcie->base + reg);
161 static u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg)
163 return readl(pcie->base + reg);
167 RCAR_PCI_ACCESS_READ,
168 RCAR_PCI_ACCESS_WRITE,
171 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
173 unsigned int shift = BITS_PER_BYTE * (where & 3);
174 u32 val = rcar_pci_read_reg(pcie, where & ~3);
176 val &= ~(mask << shift);
177 val |= data << shift;
178 rcar_pci_write_reg(pcie, val, where & ~3);
181 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
183 unsigned int shift = BITS_PER_BYTE * (where & 3);
184 u32 val = rcar_pci_read_reg(pcie, where & ~3);
189 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
190 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
191 unsigned char access_type, struct pci_bus *bus,
192 unsigned int devfn, int where, u32 *data)
194 unsigned int dev, func, reg, index;
196 dev = PCI_SLOT(devfn);
197 func = PCI_FUNC(devfn);
202 * While each channel has its own memory-mapped extended config
203 * space, it's generally only accessible when in endpoint mode.
204 * When in root complex mode, the controller is unable to target
205 * itself with either type 0 or type 1 accesses, and indeed, any
206 * controller initiated target transfer to its own config space
207 * result in a completer abort.
209 * Each channel effectively only supports a single device, but as
210 * the same channel <-> device access works for any PCI_SLOT()
211 * value, we cheat a bit here and bind the controller's config
212 * space to devfn 0 in order to enable self-enumeration. In this
213 * case the regular ECAR/ECDR path is sidelined and the mangled
214 * config access itself is initiated as an internal bus transaction.
216 if (pci_is_root_bus(bus)) {
218 return PCIBIOS_DEVICE_NOT_FOUND;
220 if (access_type == RCAR_PCI_ACCESS_READ) {
221 *data = rcar_pci_read_reg(pcie, PCICONF(index));
223 /* Keep an eye out for changes to the root bus number */
224 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
225 pcie->root_bus_nr = *data & 0xff;
227 rcar_pci_write_reg(pcie, *data, PCICONF(index));
230 return PCIBIOS_SUCCESSFUL;
233 if (pcie->root_bus_nr < 0)
234 return PCIBIOS_DEVICE_NOT_FOUND;
237 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
239 /* Set the PIO address */
240 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
241 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
243 /* Enable the configuration access */
244 if (bus->parent->number == pcie->root_bus_nr)
245 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
247 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
249 /* Check for errors */
250 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
251 return PCIBIOS_DEVICE_NOT_FOUND;
253 /* Check for master and target aborts */
254 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
255 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
256 return PCIBIOS_DEVICE_NOT_FOUND;
258 if (access_type == RCAR_PCI_ACCESS_READ)
259 *data = rcar_pci_read_reg(pcie, PCIECDR);
261 rcar_pci_write_reg(pcie, *data, PCIECDR);
263 /* Disable the configuration access */
264 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
266 return PCIBIOS_SUCCESSFUL;
269 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
270 int where, int size, u32 *val)
272 struct rcar_pcie *pcie = bus->sysdata;
275 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
276 bus, devfn, where, val);
277 if (ret != PCIBIOS_SUCCESSFUL) {
283 *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff;
285 *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff;
287 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
288 bus->number, devfn, where, size, *val);
293 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
294 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
295 int where, int size, u32 val)
297 struct rcar_pcie *pcie = bus->sysdata;
302 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
303 bus, devfn, where, &data);
304 if (ret != PCIBIOS_SUCCESSFUL)
307 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
308 bus->number, devfn, where, size, val);
311 shift = BITS_PER_BYTE * (where & 3);
312 data &= ~(0xff << shift);
313 data |= ((val & 0xff) << shift);
314 } else if (size == 2) {
315 shift = BITS_PER_BYTE * (where & 2);
316 data &= ~(0xffff << shift);
317 data |= ((val & 0xffff) << shift);
321 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
322 bus, devfn, where, &data);
327 static struct pci_ops rcar_pcie_ops = {
328 .read = rcar_pcie_read_conf,
329 .write = rcar_pcie_write_conf,
332 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie,
333 struct resource *res)
335 /* Setup PCIe address space mappings for each resource */
336 resource_size_t size;
337 resource_size_t res_start;
340 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
343 * The PAMR mask is calculated in units of 128Bytes, which
344 * keeps things pretty simple.
346 size = resource_size(res);
347 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
348 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
350 if (res->flags & IORESOURCE_IO)
351 res_start = pci_pio_to_address(res->start);
353 res_start = res->start;
355 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
356 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
359 /* First resource is for IO */
361 if (res->flags & IORESOURCE_IO)
364 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
367 static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci)
369 struct resource_entry *win;
372 /* Setup PCI resources */
373 resource_list_for_each_entry(win, &pci->resources) {
374 struct resource *res = win->res;
379 switch (resource_type(res)) {
382 rcar_pcie_setup_window(i, pci, res);
386 pci->root_bus_nr = res->start;
392 pci_add_resource(resource, res);
398 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie)
400 struct device *dev = pcie->dev;
401 unsigned int timeout = 1000;
404 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS)
407 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) {
408 dev_err(dev, "Speed change already in progress\n");
412 macsr = rcar_pci_read_reg(pcie, MACSR);
413 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS)
416 /* Set target link speed to 5.0 GT/s */
417 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
418 PCI_EXP_LNKSTA_CLS_5_0GB);
420 /* Set speed change reason as intentional factor */
421 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0);
423 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */
424 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL))
425 rcar_pci_write_reg(pcie, macsr, MACSR);
427 /* Start link speed change */
428 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE);
431 macsr = rcar_pci_read_reg(pcie, MACSR);
432 if (macsr & SPCHGFIN) {
433 /* Clear the interrupt bits */
434 rcar_pci_write_reg(pcie, macsr, MACSR);
436 if (macsr & SPCHGFAIL)
437 dev_err(dev, "Speed change failed\n");
445 dev_err(dev, "Speed change timed out\n");
448 dev_info(dev, "Current link speed is %s GT/s\n",
449 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5");
452 static int rcar_pcie_enable(struct rcar_pcie *pcie)
454 struct device *dev = pcie->dev;
455 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
456 struct pci_bus *bus, *child;
459 /* Try setting 5 GT/s link speed */
460 rcar_pcie_force_speedup(pcie);
462 rcar_pcie_setup(&bridge->windows, pcie);
464 pci_add_flags(PCI_REASSIGN_ALL_BUS);
466 bridge->dev.parent = dev;
467 bridge->sysdata = pcie;
468 bridge->busnr = pcie->root_bus_nr;
469 bridge->ops = &rcar_pcie_ops;
470 bridge->map_irq = of_irq_parse_and_map_pci;
471 bridge->swizzle_irq = pci_common_swizzle;
472 if (IS_ENABLED(CONFIG_PCI_MSI))
473 bridge->msi = &pcie->msi.chip;
475 ret = pci_scan_root_bus_bridge(bridge);
481 pci_bus_size_bridges(bus);
482 pci_bus_assign_resources(bus);
484 list_for_each_entry(child, &bus->children, node)
485 pcie_bus_configure_settings(child);
487 pci_bus_add_devices(bus);
492 static int phy_wait_for_ack(struct rcar_pcie *pcie)
494 struct device *dev = pcie->dev;
495 unsigned int timeout = 100;
498 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
504 dev_err(dev, "Access to PCIe phy timed out\n");
509 static void phy_write_reg(struct rcar_pcie *pcie,
510 unsigned int rate, u32 addr,
511 unsigned int lane, u32 data)
515 phyaddr = WRITE_CMD |
516 ((rate & 1) << RATE_POS) |
517 ((lane & 0xf) << LANE_POS) |
518 ((addr & 0xff) << ADR_POS);
521 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
522 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
524 /* Ignore errors as they will be dealt with if the data link is down */
525 phy_wait_for_ack(pcie);
528 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
529 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
531 /* Ignore errors as they will be dealt with if the data link is down */
532 phy_wait_for_ack(pcie);
535 static int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie)
537 unsigned int timeout = 10;
540 if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY)
549 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
551 unsigned int timeout = 10000;
554 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
564 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
568 /* Begin initialization */
569 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
572 rcar_pci_write_reg(pcie, 1, PCIEMSR);
574 err = rcar_pcie_wait_for_phyrdy(pcie);
579 * Initial header for port config space is type 1, set the device
580 * class to match. Hardware takes care of propagating the IDSETR
581 * settings, so there is no need to bother with a quirk.
583 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
586 * Setup Secondary Bus Number & Subordinate Bus Number, even though
587 * they aren't used, to avoid bridge being detected as broken.
589 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
590 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
592 /* Initialize default capabilities. */
593 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
594 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
595 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
596 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
597 PCI_HEADER_TYPE_BRIDGE);
599 /* Enable data link layer active state reporting */
600 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
601 PCI_EXP_LNKCAP_DLLLARC);
603 /* Write out the physical slot number = 0 */
604 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
606 /* Set the completion timer timeout to the maximum 50ms. */
607 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
609 /* Terminate list of capabilities (Next Capability Offset=0) */
610 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
613 if (IS_ENABLED(CONFIG_PCI_MSI))
614 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
616 /* Finish initialization - establish a PCI Express link */
617 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
619 /* This will timeout if we don't have a link. */
620 err = rcar_pcie_wait_for_dl(pcie);
624 /* Enable INTx interrupts */
625 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
632 static int rcar_pcie_phy_init_h1(struct rcar_pcie *pcie)
634 /* Initialize the phy */
635 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
636 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
637 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
638 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
639 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
640 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
641 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
642 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
643 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
644 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
645 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
646 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
648 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
649 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
650 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
655 static int rcar_pcie_phy_init_gen2(struct rcar_pcie *pcie)
658 * These settings come from the R-Car Series, 2nd Generation User's
659 * Manual, section 50.3.1 (2) Initialization of the physical layer.
661 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
662 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
663 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
664 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
666 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
667 /* The following value is for DC connection, no termination resistor */
668 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
669 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
670 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
675 static int rcar_pcie_phy_init_gen3(struct rcar_pcie *pcie)
679 err = phy_init(pcie->phy);
683 err = phy_power_on(pcie->phy);
690 static int rcar_msi_alloc(struct rcar_msi *chip)
694 mutex_lock(&chip->lock);
696 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
697 if (msi < INT_PCI_MSI_NR)
698 set_bit(msi, chip->used);
702 mutex_unlock(&chip->lock);
707 static int rcar_msi_alloc_region(struct rcar_msi *chip, int no_irqs)
711 mutex_lock(&chip->lock);
712 msi = bitmap_find_free_region(chip->used, INT_PCI_MSI_NR,
713 order_base_2(no_irqs));
714 mutex_unlock(&chip->lock);
719 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
721 mutex_lock(&chip->lock);
722 clear_bit(irq, chip->used);
723 mutex_unlock(&chip->lock);
726 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
728 struct rcar_pcie *pcie = data;
729 struct rcar_msi *msi = &pcie->msi;
730 struct device *dev = pcie->dev;
733 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
735 /* MSI & INTx share an interrupt - we only handle MSI here */
740 unsigned int index = find_first_bit(®, 32);
741 unsigned int msi_irq;
743 /* clear the interrupt */
744 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
746 msi_irq = irq_find_mapping(msi->domain, index);
748 if (test_bit(index, msi->used))
749 generic_handle_irq(msi_irq);
751 dev_info(dev, "unhandled MSI\n");
753 /* Unknown MSI, just clear it */
754 dev_dbg(dev, "unexpected MSI\n");
757 /* see if there's any more pending in this vector */
758 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
764 static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
765 struct msi_desc *desc)
767 struct rcar_msi *msi = to_rcar_msi(chip);
768 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
773 hwirq = rcar_msi_alloc(msi);
777 irq = irq_find_mapping(msi->domain, hwirq);
779 rcar_msi_free(msi, hwirq);
783 irq_set_msi_desc(irq, desc);
785 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
786 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
789 pci_write_msi_msg(irq, &msg);
794 static int rcar_msi_setup_irqs(struct msi_controller *chip,
795 struct pci_dev *pdev, int nvec, int type)
797 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
798 struct rcar_msi *msi = to_rcar_msi(chip);
799 struct msi_desc *desc;
805 /* MSI-X interrupts are not supported */
806 if (type == PCI_CAP_ID_MSIX)
809 WARN_ON(!list_is_singular(&pdev->dev.msi_list));
810 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
812 hwirq = rcar_msi_alloc_region(msi, nvec);
816 irq = irq_find_mapping(msi->domain, hwirq);
820 for (i = 0; i < nvec; i++) {
822 * irq_create_mapping() called from rcar_pcie_probe() pre-
823 * allocates descs, so there is no need to allocate descs here.
824 * We can therefore assume that if irq_find_mapping() above
825 * returns non-zero, then the descs are also successfully
828 if (irq_set_msi_desc_off(irq, i, desc)) {
834 desc->nvec_used = nvec;
835 desc->msi_attrib.multiple = order_base_2(nvec);
837 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
838 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
841 pci_write_msi_msg(irq, &msg);
846 static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
848 struct rcar_msi *msi = to_rcar_msi(chip);
849 struct irq_data *d = irq_get_irq_data(irq);
851 rcar_msi_free(msi, d->hwirq);
854 static struct irq_chip rcar_msi_irq_chip = {
855 .name = "R-Car PCIe MSI",
856 .irq_enable = pci_msi_unmask_irq,
857 .irq_disable = pci_msi_mask_irq,
858 .irq_mask = pci_msi_mask_irq,
859 .irq_unmask = pci_msi_unmask_irq,
862 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
863 irq_hw_number_t hwirq)
865 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
866 irq_set_chip_data(irq, domain->host_data);
871 static const struct irq_domain_ops msi_domain_ops = {
875 static void rcar_pcie_unmap_msi(struct rcar_pcie *pcie)
877 struct rcar_msi *msi = &pcie->msi;
880 for (i = 0; i < INT_PCI_MSI_NR; i++) {
881 irq = irq_find_mapping(msi->domain, i);
883 irq_dispose_mapping(irq);
886 irq_domain_remove(msi->domain);
889 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
891 struct device *dev = pcie->dev;
892 struct rcar_msi *msi = &pcie->msi;
896 mutex_init(&msi->lock);
899 msi->chip.setup_irq = rcar_msi_setup_irq;
900 msi->chip.setup_irqs = rcar_msi_setup_irqs;
901 msi->chip.teardown_irq = rcar_msi_teardown_irq;
903 msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR,
904 &msi_domain_ops, &msi->chip);
906 dev_err(dev, "failed to create IRQ domain\n");
910 for (i = 0; i < INT_PCI_MSI_NR; i++)
911 irq_create_mapping(msi->domain, i);
913 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
914 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq,
915 IRQF_SHARED | IRQF_NO_THREAD,
916 rcar_msi_irq_chip.name, pcie);
918 dev_err(dev, "failed to request IRQ: %d\n", err);
922 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq,
923 IRQF_SHARED | IRQF_NO_THREAD,
924 rcar_msi_irq_chip.name, pcie);
926 dev_err(dev, "failed to request IRQ: %d\n", err);
930 /* setup MSI data target */
931 msi->pages = __get_free_pages(GFP_KERNEL, 0);
936 base = virt_to_phys((void *)msi->pages);
938 rcar_pci_write_reg(pcie, lower_32_bits(base) | MSIFE, PCIEMSIALR);
939 rcar_pci_write_reg(pcie, upper_32_bits(base), PCIEMSIAUR);
941 /* enable all MSI interrupts */
942 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
947 rcar_pcie_unmap_msi(pcie);
951 static void rcar_pcie_teardown_msi(struct rcar_pcie *pcie)
953 struct rcar_msi *msi = &pcie->msi;
955 /* Disable all MSI interrupts */
956 rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
958 /* Disable address decoding of the MSI interrupt, MSIFE */
959 rcar_pci_write_reg(pcie, 0, PCIEMSIALR);
961 free_pages(msi->pages, 0);
963 rcar_pcie_unmap_msi(pcie);
966 static int rcar_pcie_get_resources(struct rcar_pcie *pcie)
968 struct device *dev = pcie->dev;
972 pcie->phy = devm_phy_optional_get(dev, "pcie");
973 if (IS_ERR(pcie->phy))
974 return PTR_ERR(pcie->phy);
976 err = of_address_to_resource(dev->of_node, 0, &res);
980 pcie->base = devm_ioremap_resource(dev, &res);
981 if (IS_ERR(pcie->base))
982 return PTR_ERR(pcie->base);
984 pcie->bus_clk = devm_clk_get(dev, "pcie_bus");
985 if (IS_ERR(pcie->bus_clk)) {
986 dev_err(dev, "cannot get pcie bus clock\n");
987 return PTR_ERR(pcie->bus_clk);
990 i = irq_of_parse_and_map(dev->of_node, 0);
992 dev_err(dev, "cannot get platform resources for msi interrupt\n");
998 i = irq_of_parse_and_map(dev->of_node, 1);
1000 dev_err(dev, "cannot get platform resources for msi interrupt\n");
1009 irq_dispose_mapping(pcie->msi.irq1);
1014 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
1015 struct of_pci_range *range,
1018 u64 restype = range->flags;
1019 u64 cpu_addr = range->cpu_addr;
1020 u64 cpu_end = range->cpu_addr + range->size;
1021 u64 pci_addr = range->pci_addr;
1022 u32 flags = LAM_64BIT | LAR_ENABLE;
1027 if (restype & IORESOURCE_PREFETCH)
1028 flags |= LAM_PREFETCH;
1031 * If the size of the range is larger than the alignment of the start
1032 * address, we have to use multiple entries to perform the mapping.
1035 unsigned long nr_zeros = __ffs64(cpu_addr);
1036 u64 alignment = 1ULL << nr_zeros;
1038 size = min(range->size, alignment);
1042 /* Hardware supports max 4GiB inbound region */
1043 size = min(size, 1ULL << 32);
1045 mask = roundup_pow_of_two(size) - 1;
1048 while (cpu_addr < cpu_end) {
1049 if (idx >= MAX_NR_INBOUND_MAPS - 1) {
1050 dev_err(pcie->dev, "Failed to map inbound regions!\n");
1054 * Set up 64-bit inbound regions as the range parser doesn't
1055 * distinguish between 32 and 64-bit types.
1057 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr),
1059 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
1060 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags,
1063 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr),
1065 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr),
1067 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
1078 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
1079 struct device_node *np)
1081 struct of_pci_range range;
1082 struct of_pci_range_parser parser;
1086 if (of_pci_dma_range_parser_init(&parser, np))
1089 /* Get the dma-ranges from DT */
1090 for_each_of_pci_range(&parser, &range) {
1091 u64 end = range.cpu_addr + range.size - 1;
1093 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
1094 range.flags, range.cpu_addr, end, range.pci_addr);
1096 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
1104 static const struct of_device_id rcar_pcie_of_match[] = {
1105 { .compatible = "renesas,pcie-r8a7779",
1106 .data = rcar_pcie_phy_init_h1 },
1107 { .compatible = "renesas,pcie-r8a7790",
1108 .data = rcar_pcie_phy_init_gen2 },
1109 { .compatible = "renesas,pcie-r8a7791",
1110 .data = rcar_pcie_phy_init_gen2 },
1111 { .compatible = "renesas,pcie-rcar-gen2",
1112 .data = rcar_pcie_phy_init_gen2 },
1113 { .compatible = "renesas,pcie-r8a7795",
1114 .data = rcar_pcie_phy_init_gen3 },
1115 { .compatible = "renesas,pcie-rcar-gen3",
1116 .data = rcar_pcie_phy_init_gen3 },
1120 static int rcar_pcie_probe(struct platform_device *pdev)
1122 struct device *dev = &pdev->dev;
1123 struct rcar_pcie *pcie;
1126 int (*phy_init_fn)(struct rcar_pcie *);
1127 struct pci_host_bridge *bridge;
1129 bridge = pci_alloc_host_bridge(sizeof(*pcie));
1133 pcie = pci_host_bridge_priv(bridge);
1136 platform_set_drvdata(pdev, pcie);
1138 err = pci_parse_request_of_pci_ranges(dev, &pcie->resources, NULL);
1140 goto err_free_bridge;
1142 pm_runtime_enable(pcie->dev);
1143 err = pm_runtime_get_sync(pcie->dev);
1145 dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
1146 goto err_pm_disable;
1149 err = rcar_pcie_get_resources(pcie);
1151 dev_err(dev, "failed to request resources: %d\n", err);
1155 err = clk_prepare_enable(pcie->bus_clk);
1157 dev_err(dev, "failed to enable bus clock: %d\n", err);
1158 goto err_unmap_msi_irqs;
1161 err = rcar_pcie_parse_map_dma_ranges(pcie, dev->of_node);
1163 goto err_clk_disable;
1165 phy_init_fn = of_device_get_match_data(dev);
1166 err = phy_init_fn(pcie);
1168 dev_err(dev, "failed to init PCIe PHY\n");
1169 goto err_clk_disable;
1172 /* Failure to get a link might just be that no cards are inserted */
1173 if (rcar_pcie_hw_init(pcie)) {
1174 dev_info(dev, "PCIe link down\n");
1176 goto err_phy_shutdown;
1179 data = rcar_pci_read_reg(pcie, MACSR);
1180 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1182 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1183 err = rcar_pcie_enable_msi(pcie);
1186 "failed to enable MSI support: %d\n",
1188 goto err_phy_shutdown;
1192 err = rcar_pcie_enable(pcie);
1194 goto err_msi_teardown;
1199 if (IS_ENABLED(CONFIG_PCI_MSI))
1200 rcar_pcie_teardown_msi(pcie);
1204 phy_power_off(pcie->phy);
1205 phy_exit(pcie->phy);
1209 clk_disable_unprepare(pcie->bus_clk);
1212 irq_dispose_mapping(pcie->msi.irq2);
1213 irq_dispose_mapping(pcie->msi.irq1);
1216 pm_runtime_put(dev);
1219 pm_runtime_disable(dev);
1220 pci_free_resource_list(&pcie->resources);
1223 pci_free_host_bridge(bridge);
1228 static int rcar_pcie_resume_noirq(struct device *dev)
1230 struct rcar_pcie *pcie = dev_get_drvdata(dev);
1232 if (rcar_pci_read_reg(pcie, PMSR) &&
1233 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN))
1236 /* Re-establish the PCIe link */
1237 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
1238 return rcar_pcie_wait_for_dl(pcie);
1241 static const struct dev_pm_ops rcar_pcie_pm_ops = {
1242 .resume_noirq = rcar_pcie_resume_noirq,
1245 static struct platform_driver rcar_pcie_driver = {
1247 .name = "rcar-pcie",
1248 .of_match_table = rcar_pcie_of_match,
1249 .pm = &rcar_pcie_pm_ops,
1250 .suppress_bind_attrs = true,
1252 .probe = rcar_pcie_probe,
1254 builtin_platform_driver(rcar_pcie_driver);