1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 * Copyright 2015 Linaro Limited.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/interrupt.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/of_device.h>
20 #include <linux/of_gpio.h>
21 #include <linux/pci.h>
22 #include <linux/platform_device.h>
23 #include <linux/phy/phy.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/reset.h>
26 #include <linux/slab.h>
27 #include <linux/types.h>
29 #include "pcie-designware.h"
31 #define PCIE20_PARF_SYS_CTRL 0x00
32 #define MST_WAKEUP_EN BIT(13)
33 #define SLV_WAKEUP_EN BIT(12)
34 #define MSTR_ACLK_CGC_DIS BIT(10)
35 #define SLV_ACLK_CGC_DIS BIT(9)
36 #define CORE_CLK_CGC_DIS BIT(6)
37 #define AUX_PWR_DET BIT(4)
38 #define L23_CLK_RMV_DIS BIT(2)
39 #define L1_CLK_RMV_DIS BIT(1)
41 #define PCIE20_COMMAND_STATUS 0x04
42 #define CMD_BME_VAL 0x4
43 #define PCIE20_DEVICE_CONTROL2_STATUS2 0x98
44 #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
46 #define PCIE20_PARF_PHY_CTRL 0x40
47 #define PCIE20_PARF_PHY_REFCLK 0x4C
48 #define PCIE20_PARF_DBI_BASE_ADDR 0x168
49 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
50 #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
51 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
52 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
53 #define PCIE20_PARF_LTSSM 0x1B0
54 #define PCIE20_PARF_SID_OFFSET 0x234
55 #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
57 #define PCIE20_ELBI_SYS_CTRL 0x04
58 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
60 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
61 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
62 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
63 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
64 #define CFG_BRIDGE_SB_INIT BIT(0)
66 #define PCIE20_CAP 0x70
67 #define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + 0xC)
68 #define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) | BIT(11))
69 #define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
70 #define PCIE_CAP_LINK1_VAL 0x2FD7F
72 #define PCIE20_PARF_Q2A_FLUSH 0x1AC
74 #define PCIE20_MISC_CONTROL_1_REG 0x8BC
75 #define DBI_RO_WR_EN 1
77 #define PERST_DELAY_US 1000
79 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
80 #define SLV_ADDR_SPACE_SZ 0x10000000
82 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
83 struct qcom_pcie_resources_2_1_0 {
84 struct clk *iface_clk;
87 struct reset_control *pci_reset;
88 struct reset_control *axi_reset;
89 struct reset_control *ahb_reset;
90 struct reset_control *por_reset;
91 struct reset_control *phy_reset;
92 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
95 struct qcom_pcie_resources_1_0_0 {
98 struct clk *master_bus;
99 struct clk *slave_bus;
100 struct reset_control *core;
101 struct regulator *vdda;
104 #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2
105 struct qcom_pcie_resources_2_3_2 {
107 struct clk *master_clk;
108 struct clk *slave_clk;
110 struct clk *pipe_clk;
111 struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
114 struct qcom_pcie_resources_2_4_0 {
116 struct clk *master_clk;
117 struct clk *slave_clk;
118 struct reset_control *axi_m_reset;
119 struct reset_control *axi_s_reset;
120 struct reset_control *pipe_reset;
121 struct reset_control *axi_m_vmid_reset;
122 struct reset_control *axi_s_xpu_reset;
123 struct reset_control *parf_reset;
124 struct reset_control *phy_reset;
125 struct reset_control *axi_m_sticky_reset;
126 struct reset_control *pipe_sticky_reset;
127 struct reset_control *pwr_reset;
128 struct reset_control *ahb_reset;
129 struct reset_control *phy_ahb_reset;
132 struct qcom_pcie_resources_2_3_3 {
134 struct clk *axi_m_clk;
135 struct clk *axi_s_clk;
138 struct reset_control *rst[7];
141 union qcom_pcie_resources {
142 struct qcom_pcie_resources_1_0_0 v1_0_0;
143 struct qcom_pcie_resources_2_1_0 v2_1_0;
144 struct qcom_pcie_resources_2_3_2 v2_3_2;
145 struct qcom_pcie_resources_2_3_3 v2_3_3;
146 struct qcom_pcie_resources_2_4_0 v2_4_0;
151 struct qcom_pcie_ops {
152 int (*get_resources)(struct qcom_pcie *pcie);
153 int (*init)(struct qcom_pcie *pcie);
154 int (*post_init)(struct qcom_pcie *pcie);
155 void (*deinit)(struct qcom_pcie *pcie);
156 void (*post_deinit)(struct qcom_pcie *pcie);
157 void (*ltssm_enable)(struct qcom_pcie *pcie);
162 void __iomem *parf; /* DT parf */
163 void __iomem *elbi; /* DT elbi */
164 union qcom_pcie_resources res;
166 struct gpio_desc *reset;
167 const struct qcom_pcie_ops *ops;
170 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
172 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
174 gpiod_set_value_cansleep(pcie->reset, 1);
175 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
178 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
180 gpiod_set_value_cansleep(pcie->reset, 0);
181 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
184 static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
186 struct dw_pcie *pci = pcie->pci;
188 if (dw_pcie_link_up(pci))
191 /* Enable Link Training state machine */
192 if (pcie->ops->ltssm_enable)
193 pcie->ops->ltssm_enable(pcie);
195 return dw_pcie_wait_for_link(pci);
198 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
202 /* enable link training */
203 val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
204 val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
205 writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
208 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
210 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
211 struct dw_pcie *pci = pcie->pci;
212 struct device *dev = pci->dev;
215 res->supplies[0].supply = "vdda";
216 res->supplies[1].supply = "vdda_phy";
217 res->supplies[2].supply = "vdda_refclk";
218 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
223 res->iface_clk = devm_clk_get(dev, "iface");
224 if (IS_ERR(res->iface_clk))
225 return PTR_ERR(res->iface_clk);
227 res->core_clk = devm_clk_get(dev, "core");
228 if (IS_ERR(res->core_clk))
229 return PTR_ERR(res->core_clk);
231 res->phy_clk = devm_clk_get(dev, "phy");
232 if (IS_ERR(res->phy_clk))
233 return PTR_ERR(res->phy_clk);
235 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
236 if (IS_ERR(res->pci_reset))
237 return PTR_ERR(res->pci_reset);
239 res->axi_reset = devm_reset_control_get_exclusive(dev, "axi");
240 if (IS_ERR(res->axi_reset))
241 return PTR_ERR(res->axi_reset);
243 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
244 if (IS_ERR(res->ahb_reset))
245 return PTR_ERR(res->ahb_reset);
247 res->por_reset = devm_reset_control_get_exclusive(dev, "por");
248 if (IS_ERR(res->por_reset))
249 return PTR_ERR(res->por_reset);
251 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
252 return PTR_ERR_OR_ZERO(res->phy_reset);
255 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
257 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
259 reset_control_assert(res->pci_reset);
260 reset_control_assert(res->axi_reset);
261 reset_control_assert(res->ahb_reset);
262 reset_control_assert(res->por_reset);
263 reset_control_assert(res->pci_reset);
264 clk_disable_unprepare(res->iface_clk);
265 clk_disable_unprepare(res->core_clk);
266 clk_disable_unprepare(res->phy_clk);
267 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
270 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
272 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
273 struct dw_pcie *pci = pcie->pci;
274 struct device *dev = pci->dev;
278 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
280 dev_err(dev, "cannot enable regulators\n");
284 ret = reset_control_assert(res->ahb_reset);
286 dev_err(dev, "cannot assert ahb reset\n");
290 ret = clk_prepare_enable(res->iface_clk);
292 dev_err(dev, "cannot prepare/enable iface clock\n");
296 ret = clk_prepare_enable(res->phy_clk);
298 dev_err(dev, "cannot prepare/enable phy clock\n");
302 ret = clk_prepare_enable(res->core_clk);
304 dev_err(dev, "cannot prepare/enable core clock\n");
308 ret = reset_control_deassert(res->ahb_reset);
310 dev_err(dev, "cannot deassert ahb reset\n");
311 goto err_deassert_ahb;
314 /* enable PCIe clocks and resets */
315 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
317 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
319 /* enable external reference clock */
320 val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
322 writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
324 ret = reset_control_deassert(res->phy_reset);
326 dev_err(dev, "cannot deassert phy reset\n");
330 ret = reset_control_deassert(res->pci_reset);
332 dev_err(dev, "cannot deassert pci reset\n");
336 ret = reset_control_deassert(res->por_reset);
338 dev_err(dev, "cannot deassert por reset\n");
342 ret = reset_control_deassert(res->axi_reset);
344 dev_err(dev, "cannot deassert axi reset\n");
348 /* wait for clock acquisition */
349 usleep_range(1000, 1500);
352 /* Set the Max TLP size to 2K, instead of using default of 4K */
353 writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
354 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
355 writel(CFG_BRIDGE_SB_INIT,
356 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
361 clk_disable_unprepare(res->core_clk);
363 clk_disable_unprepare(res->phy_clk);
365 clk_disable_unprepare(res->iface_clk);
367 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
372 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
374 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
375 struct dw_pcie *pci = pcie->pci;
376 struct device *dev = pci->dev;
378 res->vdda = devm_regulator_get(dev, "vdda");
379 if (IS_ERR(res->vdda))
380 return PTR_ERR(res->vdda);
382 res->iface = devm_clk_get(dev, "iface");
383 if (IS_ERR(res->iface))
384 return PTR_ERR(res->iface);
386 res->aux = devm_clk_get(dev, "aux");
387 if (IS_ERR(res->aux))
388 return PTR_ERR(res->aux);
390 res->master_bus = devm_clk_get(dev, "master_bus");
391 if (IS_ERR(res->master_bus))
392 return PTR_ERR(res->master_bus);
394 res->slave_bus = devm_clk_get(dev, "slave_bus");
395 if (IS_ERR(res->slave_bus))
396 return PTR_ERR(res->slave_bus);
398 res->core = devm_reset_control_get_exclusive(dev, "core");
399 return PTR_ERR_OR_ZERO(res->core);
402 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
404 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
406 reset_control_assert(res->core);
407 clk_disable_unprepare(res->slave_bus);
408 clk_disable_unprepare(res->master_bus);
409 clk_disable_unprepare(res->iface);
410 clk_disable_unprepare(res->aux);
411 regulator_disable(res->vdda);
414 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
416 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
417 struct dw_pcie *pci = pcie->pci;
418 struct device *dev = pci->dev;
421 ret = reset_control_deassert(res->core);
423 dev_err(dev, "cannot deassert core reset\n");
427 ret = clk_prepare_enable(res->aux);
429 dev_err(dev, "cannot prepare/enable aux clock\n");
433 ret = clk_prepare_enable(res->iface);
435 dev_err(dev, "cannot prepare/enable iface clock\n");
439 ret = clk_prepare_enable(res->master_bus);
441 dev_err(dev, "cannot prepare/enable master_bus clock\n");
445 ret = clk_prepare_enable(res->slave_bus);
447 dev_err(dev, "cannot prepare/enable slave_bus clock\n");
451 ret = regulator_enable(res->vdda);
453 dev_err(dev, "cannot enable vdda regulator\n");
457 /* change DBI base address */
458 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
460 if (IS_ENABLED(CONFIG_PCI_MSI)) {
461 u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
464 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
469 clk_disable_unprepare(res->slave_bus);
471 clk_disable_unprepare(res->master_bus);
473 clk_disable_unprepare(res->iface);
475 clk_disable_unprepare(res->aux);
477 reset_control_assert(res->core);
482 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
486 /* enable link training */
487 val = readl(pcie->parf + PCIE20_PARF_LTSSM);
489 writel(val, pcie->parf + PCIE20_PARF_LTSSM);
492 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
494 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
495 struct dw_pcie *pci = pcie->pci;
496 struct device *dev = pci->dev;
499 res->supplies[0].supply = "vdda";
500 res->supplies[1].supply = "vddpe-3v3";
501 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
506 res->aux_clk = devm_clk_get(dev, "aux");
507 if (IS_ERR(res->aux_clk))
508 return PTR_ERR(res->aux_clk);
510 res->cfg_clk = devm_clk_get(dev, "cfg");
511 if (IS_ERR(res->cfg_clk))
512 return PTR_ERR(res->cfg_clk);
514 res->master_clk = devm_clk_get(dev, "bus_master");
515 if (IS_ERR(res->master_clk))
516 return PTR_ERR(res->master_clk);
518 res->slave_clk = devm_clk_get(dev, "bus_slave");
519 if (IS_ERR(res->slave_clk))
520 return PTR_ERR(res->slave_clk);
522 res->pipe_clk = devm_clk_get(dev, "pipe");
523 return PTR_ERR_OR_ZERO(res->pipe_clk);
526 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
528 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
530 clk_disable_unprepare(res->slave_clk);
531 clk_disable_unprepare(res->master_clk);
532 clk_disable_unprepare(res->cfg_clk);
533 clk_disable_unprepare(res->aux_clk);
535 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
538 static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie)
540 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
542 clk_disable_unprepare(res->pipe_clk);
545 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
547 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
548 struct dw_pcie *pci = pcie->pci;
549 struct device *dev = pci->dev;
553 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
555 dev_err(dev, "cannot enable regulators\n");
559 ret = clk_prepare_enable(res->aux_clk);
561 dev_err(dev, "cannot prepare/enable aux clock\n");
565 ret = clk_prepare_enable(res->cfg_clk);
567 dev_err(dev, "cannot prepare/enable cfg clock\n");
571 ret = clk_prepare_enable(res->master_clk);
573 dev_err(dev, "cannot prepare/enable master clock\n");
577 ret = clk_prepare_enable(res->slave_clk);
579 dev_err(dev, "cannot prepare/enable slave clock\n");
583 /* enable PCIe clocks and resets */
584 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
586 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
588 /* change DBI base address */
589 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
591 /* MAC PHY_POWERDOWN MUX DISABLE */
592 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
594 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
596 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
598 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
600 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
602 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
607 clk_disable_unprepare(res->master_clk);
609 clk_disable_unprepare(res->cfg_clk);
611 clk_disable_unprepare(res->aux_clk);
614 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
619 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
621 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
622 struct dw_pcie *pci = pcie->pci;
623 struct device *dev = pci->dev;
626 ret = clk_prepare_enable(res->pipe_clk);
628 dev_err(dev, "cannot prepare/enable pipe clock\n");
635 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
637 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
638 struct dw_pcie *pci = pcie->pci;
639 struct device *dev = pci->dev;
641 res->aux_clk = devm_clk_get(dev, "aux");
642 if (IS_ERR(res->aux_clk))
643 return PTR_ERR(res->aux_clk);
645 res->master_clk = devm_clk_get(dev, "master_bus");
646 if (IS_ERR(res->master_clk))
647 return PTR_ERR(res->master_clk);
649 res->slave_clk = devm_clk_get(dev, "slave_bus");
650 if (IS_ERR(res->slave_clk))
651 return PTR_ERR(res->slave_clk);
653 res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m");
654 if (IS_ERR(res->axi_m_reset))
655 return PTR_ERR(res->axi_m_reset);
657 res->axi_s_reset = devm_reset_control_get_exclusive(dev, "axi_s");
658 if (IS_ERR(res->axi_s_reset))
659 return PTR_ERR(res->axi_s_reset);
661 res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
662 if (IS_ERR(res->pipe_reset))
663 return PTR_ERR(res->pipe_reset);
665 res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,
667 if (IS_ERR(res->axi_m_vmid_reset))
668 return PTR_ERR(res->axi_m_vmid_reset);
670 res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,
672 if (IS_ERR(res->axi_s_xpu_reset))
673 return PTR_ERR(res->axi_s_xpu_reset);
675 res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");
676 if (IS_ERR(res->parf_reset))
677 return PTR_ERR(res->parf_reset);
679 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
680 if (IS_ERR(res->phy_reset))
681 return PTR_ERR(res->phy_reset);
683 res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev,
685 if (IS_ERR(res->axi_m_sticky_reset))
686 return PTR_ERR(res->axi_m_sticky_reset);
688 res->pipe_sticky_reset = devm_reset_control_get_exclusive(dev,
690 if (IS_ERR(res->pipe_sticky_reset))
691 return PTR_ERR(res->pipe_sticky_reset);
693 res->pwr_reset = devm_reset_control_get_exclusive(dev, "pwr");
694 if (IS_ERR(res->pwr_reset))
695 return PTR_ERR(res->pwr_reset);
697 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
698 if (IS_ERR(res->ahb_reset))
699 return PTR_ERR(res->ahb_reset);
701 res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");
702 if (IS_ERR(res->phy_ahb_reset))
703 return PTR_ERR(res->phy_ahb_reset);
708 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
710 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
712 reset_control_assert(res->axi_m_reset);
713 reset_control_assert(res->axi_s_reset);
714 reset_control_assert(res->pipe_reset);
715 reset_control_assert(res->pipe_sticky_reset);
716 reset_control_assert(res->phy_reset);
717 reset_control_assert(res->phy_ahb_reset);
718 reset_control_assert(res->axi_m_sticky_reset);
719 reset_control_assert(res->pwr_reset);
720 reset_control_assert(res->ahb_reset);
721 clk_disable_unprepare(res->aux_clk);
722 clk_disable_unprepare(res->master_clk);
723 clk_disable_unprepare(res->slave_clk);
726 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
728 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
729 struct dw_pcie *pci = pcie->pci;
730 struct device *dev = pci->dev;
734 ret = reset_control_assert(res->axi_m_reset);
736 dev_err(dev, "cannot assert axi master reset\n");
740 ret = reset_control_assert(res->axi_s_reset);
742 dev_err(dev, "cannot assert axi slave reset\n");
746 usleep_range(10000, 12000);
748 ret = reset_control_assert(res->pipe_reset);
750 dev_err(dev, "cannot assert pipe reset\n");
754 ret = reset_control_assert(res->pipe_sticky_reset);
756 dev_err(dev, "cannot assert pipe sticky reset\n");
760 ret = reset_control_assert(res->phy_reset);
762 dev_err(dev, "cannot assert phy reset\n");
766 ret = reset_control_assert(res->phy_ahb_reset);
768 dev_err(dev, "cannot assert phy ahb reset\n");
772 usleep_range(10000, 12000);
774 ret = reset_control_assert(res->axi_m_sticky_reset);
776 dev_err(dev, "cannot assert axi master sticky reset\n");
780 ret = reset_control_assert(res->pwr_reset);
782 dev_err(dev, "cannot assert power reset\n");
786 ret = reset_control_assert(res->ahb_reset);
788 dev_err(dev, "cannot assert ahb reset\n");
792 usleep_range(10000, 12000);
794 ret = reset_control_deassert(res->phy_ahb_reset);
796 dev_err(dev, "cannot deassert phy ahb reset\n");
800 ret = reset_control_deassert(res->phy_reset);
802 dev_err(dev, "cannot deassert phy reset\n");
806 ret = reset_control_deassert(res->pipe_reset);
808 dev_err(dev, "cannot deassert pipe reset\n");
812 ret = reset_control_deassert(res->pipe_sticky_reset);
814 dev_err(dev, "cannot deassert pipe sticky reset\n");
815 goto err_rst_pipe_sticky;
818 usleep_range(10000, 12000);
820 ret = reset_control_deassert(res->axi_m_reset);
822 dev_err(dev, "cannot deassert axi master reset\n");
826 ret = reset_control_deassert(res->axi_m_sticky_reset);
828 dev_err(dev, "cannot deassert axi master sticky reset\n");
829 goto err_rst_axi_m_sticky;
832 ret = reset_control_deassert(res->axi_s_reset);
834 dev_err(dev, "cannot deassert axi slave reset\n");
838 ret = reset_control_deassert(res->pwr_reset);
840 dev_err(dev, "cannot deassert power reset\n");
844 ret = reset_control_deassert(res->ahb_reset);
846 dev_err(dev, "cannot deassert ahb reset\n");
850 usleep_range(10000, 12000);
852 ret = clk_prepare_enable(res->aux_clk);
854 dev_err(dev, "cannot prepare/enable iface clock\n");
858 ret = clk_prepare_enable(res->master_clk);
860 dev_err(dev, "cannot prepare/enable core clock\n");
864 ret = clk_prepare_enable(res->slave_clk);
866 dev_err(dev, "cannot prepare/enable phy clock\n");
870 /* enable PCIe clocks and resets */
871 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
873 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
875 /* change DBI base address */
876 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
878 /* MAC PHY_POWERDOWN MUX DISABLE */
879 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
881 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
883 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
885 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
887 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
889 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
894 clk_disable_unprepare(res->master_clk);
896 clk_disable_unprepare(res->aux_clk);
898 reset_control_assert(res->ahb_reset);
900 reset_control_assert(res->pwr_reset);
902 reset_control_assert(res->axi_s_reset);
904 reset_control_assert(res->axi_m_sticky_reset);
905 err_rst_axi_m_sticky:
906 reset_control_assert(res->axi_m_reset);
908 reset_control_assert(res->pipe_sticky_reset);
910 reset_control_assert(res->pipe_reset);
912 reset_control_assert(res->phy_reset);
914 reset_control_assert(res->phy_ahb_reset);
918 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
920 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
921 struct dw_pcie *pci = pcie->pci;
922 struct device *dev = pci->dev;
924 const char *rst_names[] = { "axi_m", "axi_s", "pipe",
925 "axi_m_sticky", "sticky",
928 res->iface = devm_clk_get(dev, "iface");
929 if (IS_ERR(res->iface))
930 return PTR_ERR(res->iface);
932 res->axi_m_clk = devm_clk_get(dev, "axi_m");
933 if (IS_ERR(res->axi_m_clk))
934 return PTR_ERR(res->axi_m_clk);
936 res->axi_s_clk = devm_clk_get(dev, "axi_s");
937 if (IS_ERR(res->axi_s_clk))
938 return PTR_ERR(res->axi_s_clk);
940 res->ahb_clk = devm_clk_get(dev, "ahb");
941 if (IS_ERR(res->ahb_clk))
942 return PTR_ERR(res->ahb_clk);
944 res->aux_clk = devm_clk_get(dev, "aux");
945 if (IS_ERR(res->aux_clk))
946 return PTR_ERR(res->aux_clk);
948 for (i = 0; i < ARRAY_SIZE(rst_names); i++) {
949 res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
950 if (IS_ERR(res->rst[i]))
951 return PTR_ERR(res->rst[i]);
957 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
959 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
961 clk_disable_unprepare(res->iface);
962 clk_disable_unprepare(res->axi_m_clk);
963 clk_disable_unprepare(res->axi_s_clk);
964 clk_disable_unprepare(res->ahb_clk);
965 clk_disable_unprepare(res->aux_clk);
968 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
970 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
971 struct dw_pcie *pci = pcie->pci;
972 struct device *dev = pci->dev;
976 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
977 ret = reset_control_assert(res->rst[i]);
979 dev_err(dev, "reset #%d assert failed (%d)\n", i, ret);
984 usleep_range(2000, 2500);
986 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
987 ret = reset_control_deassert(res->rst[i]);
989 dev_err(dev, "reset #%d deassert failed (%d)\n", i,
996 * Don't have a way to see if the reset has completed.
997 * Wait for some time.
999 usleep_range(2000, 2500);
1001 ret = clk_prepare_enable(res->iface);
1003 dev_err(dev, "cannot prepare/enable core clock\n");
1007 ret = clk_prepare_enable(res->axi_m_clk);
1009 dev_err(dev, "cannot prepare/enable core clock\n");
1013 ret = clk_prepare_enable(res->axi_s_clk);
1015 dev_err(dev, "cannot prepare/enable axi slave clock\n");
1019 ret = clk_prepare_enable(res->ahb_clk);
1021 dev_err(dev, "cannot prepare/enable ahb clock\n");
1025 ret = clk_prepare_enable(res->aux_clk);
1027 dev_err(dev, "cannot prepare/enable aux clock\n");
1031 writel(SLV_ADDR_SPACE_SZ,
1032 pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
1034 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1036 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1038 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1040 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
1041 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
1042 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
1043 pcie->parf + PCIE20_PARF_SYS_CTRL);
1044 writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
1046 writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS);
1047 writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
1048 writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1);
1050 val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
1051 val &= ~PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT;
1052 writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
1054 writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base +
1055 PCIE20_DEVICE_CONTROL2_STATUS2);
1060 clk_disable_unprepare(res->ahb_clk);
1062 clk_disable_unprepare(res->axi_s_clk);
1064 clk_disable_unprepare(res->axi_m_clk);
1066 clk_disable_unprepare(res->iface);
1069 * Not checking for failure, will anyway return
1070 * the original failure in 'ret'.
1072 for (i = 0; i < ARRAY_SIZE(res->rst); i++)
1073 reset_control_assert(res->rst[i]);
1078 static int qcom_pcie_link_up(struct dw_pcie *pci)
1080 u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA);
1082 return !!(val & PCI_EXP_LNKSTA_DLLLA);
1085 static int qcom_pcie_host_init(struct pcie_port *pp)
1087 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1088 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1091 qcom_ep_reset_assert(pcie);
1093 ret = pcie->ops->init(pcie);
1097 ret = phy_power_on(pcie->phy);
1101 if (pcie->ops->post_init) {
1102 ret = pcie->ops->post_init(pcie);
1104 goto err_disable_phy;
1107 dw_pcie_setup_rc(pp);
1109 if (IS_ENABLED(CONFIG_PCI_MSI))
1110 dw_pcie_msi_init(pp);
1112 qcom_ep_reset_deassert(pcie);
1114 ret = qcom_pcie_establish_link(pcie);
1120 qcom_ep_reset_assert(pcie);
1121 if (pcie->ops->post_deinit)
1122 pcie->ops->post_deinit(pcie);
1124 phy_power_off(pcie->phy);
1126 pcie->ops->deinit(pcie);
1131 static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
1134 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1136 /* the device class is not reported correctly from the register */
1137 if (where == PCI_CLASS_REVISION && size == 4) {
1138 *val = readl(pci->dbi_base + PCI_CLASS_REVISION);
1139 *val &= 0xff; /* keep revision id */
1140 *val |= PCI_CLASS_BRIDGE_PCI << 16;
1141 return PCIBIOS_SUCCESSFUL;
1144 return dw_pcie_read(pci->dbi_base + where, size, val);
1147 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1148 .host_init = qcom_pcie_host_init,
1149 .rd_own_conf = qcom_pcie_rd_own_conf,
1152 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
1153 static const struct qcom_pcie_ops ops_2_1_0 = {
1154 .get_resources = qcom_pcie_get_resources_2_1_0,
1155 .init = qcom_pcie_init_2_1_0,
1156 .deinit = qcom_pcie_deinit_2_1_0,
1157 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1160 /* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */
1161 static const struct qcom_pcie_ops ops_1_0_0 = {
1162 .get_resources = qcom_pcie_get_resources_1_0_0,
1163 .init = qcom_pcie_init_1_0_0,
1164 .deinit = qcom_pcie_deinit_1_0_0,
1165 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1168 /* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */
1169 static const struct qcom_pcie_ops ops_2_3_2 = {
1170 .get_resources = qcom_pcie_get_resources_2_3_2,
1171 .init = qcom_pcie_init_2_3_2,
1172 .post_init = qcom_pcie_post_init_2_3_2,
1173 .deinit = qcom_pcie_deinit_2_3_2,
1174 .post_deinit = qcom_pcie_post_deinit_2_3_2,
1175 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1178 /* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */
1179 static const struct qcom_pcie_ops ops_2_4_0 = {
1180 .get_resources = qcom_pcie_get_resources_2_4_0,
1181 .init = qcom_pcie_init_2_4_0,
1182 .deinit = qcom_pcie_deinit_2_4_0,
1183 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1186 /* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */
1187 static const struct qcom_pcie_ops ops_2_3_3 = {
1188 .get_resources = qcom_pcie_get_resources_2_3_3,
1189 .init = qcom_pcie_init_2_3_3,
1190 .deinit = qcom_pcie_deinit_2_3_3,
1191 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1194 static const struct dw_pcie_ops dw_pcie_ops = {
1195 .link_up = qcom_pcie_link_up,
1198 static int qcom_pcie_probe(struct platform_device *pdev)
1200 struct device *dev = &pdev->dev;
1201 struct resource *res;
1202 struct pcie_port *pp;
1203 struct dw_pcie *pci;
1204 struct qcom_pcie *pcie;
1207 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1211 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1216 pci->ops = &dw_pcie_ops;
1221 pcie->ops = of_device_get_match_data(dev);
1223 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW);
1224 if (IS_ERR(pcie->reset))
1225 return PTR_ERR(pcie->reset);
1227 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
1228 pcie->parf = devm_ioremap_resource(dev, res);
1229 if (IS_ERR(pcie->parf))
1230 return PTR_ERR(pcie->parf);
1232 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
1233 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
1234 if (IS_ERR(pci->dbi_base))
1235 return PTR_ERR(pci->dbi_base);
1237 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
1238 pcie->elbi = devm_ioremap_resource(dev, res);
1239 if (IS_ERR(pcie->elbi))
1240 return PTR_ERR(pcie->elbi);
1242 pcie->phy = devm_phy_optional_get(dev, "pciephy");
1243 if (IS_ERR(pcie->phy))
1244 return PTR_ERR(pcie->phy);
1246 ret = pcie->ops->get_resources(pcie);
1250 pp->root_bus_nr = -1;
1251 pp->ops = &qcom_pcie_dw_ops;
1253 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1254 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
1255 if (pp->msi_irq < 0)
1259 ret = phy_init(pcie->phy);
1263 platform_set_drvdata(pdev, pcie);
1265 ret = dw_pcie_host_init(pp);
1267 dev_err(dev, "cannot initialize host\n");
1274 static const struct of_device_id qcom_pcie_match[] = {
1275 { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
1276 { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
1277 { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
1278 { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
1279 { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
1280 { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
1284 static struct platform_driver qcom_pcie_driver = {
1285 .probe = qcom_pcie_probe,
1287 .name = "qcom-pcie",
1288 .suppress_bind_attrs = true,
1289 .of_match_table = qcom_pcie_match,
1292 builtin_platform_driver(qcom_pcie_driver);