1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
17 #include <linux/of_pci.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pci-aspm.h>
27 #include <linux/pm_wakeup.h>
28 #include <linux/interrupt.h>
29 #include <linux/device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/pci_hotplug.h>
32 #include <linux/vmalloc.h>
33 #include <linux/pci-ats.h>
34 #include <asm/setup.h>
36 #include <linux/aer.h>
39 const char *pci_power_names[] = {
40 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
42 EXPORT_SYMBOL_GPL(pci_power_names);
44 int isa_dma_bridge_buggy;
45 EXPORT_SYMBOL(isa_dma_bridge_buggy);
48 EXPORT_SYMBOL(pci_pci_problems);
50 unsigned int pci_pm_d3_delay;
52 static void pci_pme_list_scan(struct work_struct *work);
54 static LIST_HEAD(pci_pme_list);
55 static DEFINE_MUTEX(pci_pme_list_mutex);
56 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
58 struct pci_pme_device {
59 struct list_head list;
63 #define PME_TIMEOUT 1000 /* How long between PME checks */
65 static void pci_dev_d3_sleep(struct pci_dev *dev)
67 unsigned int delay = dev->d3_delay;
69 if (delay < pci_pm_d3_delay)
70 delay = pci_pm_d3_delay;
76 #ifdef CONFIG_PCI_DOMAINS
77 int pci_domains_supported = 1;
80 #define DEFAULT_CARDBUS_IO_SIZE (256)
81 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
82 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
83 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
84 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
86 #define DEFAULT_HOTPLUG_IO_SIZE (256)
87 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
88 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
89 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
90 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
92 #define DEFAULT_HOTPLUG_BUS_SIZE 1
93 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
95 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
98 * The default CLS is used if arch didn't set CLS explicitly and not
99 * all pci devices agree on the same value. Arch can override either
100 * the dfl or actual value as it sees fit. Don't forget this is
101 * measured in 32-bit words, not bytes.
103 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
104 u8 pci_cache_line_size;
107 * If we set up a device for bus mastering, we need to check the latency
108 * timer as certain BIOSes forget to set it properly.
110 unsigned int pcibios_max_latency = 255;
112 /* If set, the PCIe ARI capability will not be used. */
113 static bool pcie_ari_disabled;
115 /* If set, the PCIe ATS capability will not be used. */
116 static bool pcie_ats_disabled;
118 bool pci_ats_disabled(void)
120 return pcie_ats_disabled;
123 /* Disable bridge_d3 for all PCIe ports */
124 static bool pci_bridge_d3_disable;
125 /* Force bridge_d3 for all PCIe ports */
126 static bool pci_bridge_d3_force;
128 static int __init pcie_port_pm_setup(char *str)
130 if (!strcmp(str, "off"))
131 pci_bridge_d3_disable = true;
132 else if (!strcmp(str, "force"))
133 pci_bridge_d3_force = true;
136 __setup("pcie_port_pm=", pcie_port_pm_setup);
138 /* Time to wait after a reset for device to become responsive */
139 #define PCIE_RESET_READY_POLL_MS 60000
142 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
143 * @bus: pointer to PCI bus structure to search
145 * Given a PCI bus, returns the highest PCI bus number present in the set
146 * including the given PCI bus and its list of child PCI buses.
148 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
151 unsigned char max, n;
153 max = bus->busn_res.end;
154 list_for_each_entry(tmp, &bus->children, node) {
155 n = pci_bus_max_busnr(tmp);
161 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
163 #ifdef CONFIG_HAS_IOMEM
164 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
166 struct resource *res = &pdev->resource[bar];
169 * Make sure the BAR is actually a memory resource, not an IO resource
171 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
172 pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
175 return ioremap_nocache(res->start, resource_size(res));
177 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
179 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
182 * Make sure the BAR is actually a memory resource, not an IO resource
184 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
188 return ioremap_wc(pci_resource_start(pdev, bar),
189 pci_resource_len(pdev, bar));
191 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
195 * pci_dev_str_match - test if a string matches a device
196 * @dev: the PCI device to test
197 * @p: string to match the device against
198 * @endptr: pointer to the string after the match
200 * Test if a string (typically from a kernel parameter) matches a specified
201 * PCI device. The string may be of one of the following formats:
203 * [<domain>:]<bus>:<device>.<func>
204 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
206 * The first format specifies a PCI bus/device/function address which
207 * may change if new hardware is inserted, if motherboard firmware changes,
208 * or due to changes caused in kernel parameters. If the domain is
209 * left unspecified, it is taken to be 0.
211 * The second format matches devices using IDs in the configuration
212 * space which may match multiple devices in the system. A value of 0
213 * for any field will match all devices. (Note: this differs from
214 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
215 * legacy reasons and convenience so users don't have to specify
216 * FFFFFFFFs on the command line.)
218 * Returns 1 if the string matches the device, 0 if it does not and
219 * a negative error code if the string cannot be parsed.
221 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
225 int seg, bus, slot, func, count;
226 unsigned short vendor, device, subsystem_vendor, subsystem_device;
228 if (strncmp(p, "pci:", 4) == 0) {
229 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
231 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
232 &subsystem_vendor, &subsystem_device, &count);
234 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
238 subsystem_vendor = 0;
239 subsystem_device = 0;
244 if ((!vendor || vendor == dev->vendor) &&
245 (!device || device == dev->device) &&
246 (!subsystem_vendor ||
247 subsystem_vendor == dev->subsystem_vendor) &&
248 (!subsystem_device ||
249 subsystem_device == dev->subsystem_device))
253 /* PCI Bus, Device, Function IDs are specified */
254 ret = sscanf(p, "%x:%x:%x.%x%n", &seg, &bus, &slot,
258 ret = sscanf(p, "%x:%x.%x%n", &bus, &slot,
266 if (seg == pci_domain_nr(dev->bus) &&
267 bus == dev->bus->number &&
268 slot == PCI_SLOT(dev->devfn) &&
269 func == PCI_FUNC(dev->devfn))
281 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
282 u8 pos, int cap, int *ttl)
287 pci_bus_read_config_byte(bus, devfn, pos, &pos);
293 pci_bus_read_config_word(bus, devfn, pos, &ent);
305 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
308 int ttl = PCI_FIND_CAP_TTL;
310 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
313 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
315 return __pci_find_next_cap(dev->bus, dev->devfn,
316 pos + PCI_CAP_LIST_NEXT, cap);
318 EXPORT_SYMBOL_GPL(pci_find_next_capability);
320 static int __pci_bus_find_cap_start(struct pci_bus *bus,
321 unsigned int devfn, u8 hdr_type)
325 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
326 if (!(status & PCI_STATUS_CAP_LIST))
330 case PCI_HEADER_TYPE_NORMAL:
331 case PCI_HEADER_TYPE_BRIDGE:
332 return PCI_CAPABILITY_LIST;
333 case PCI_HEADER_TYPE_CARDBUS:
334 return PCI_CB_CAPABILITY_LIST;
341 * pci_find_capability - query for devices' capabilities
342 * @dev: PCI device to query
343 * @cap: capability code
345 * Tell if a device supports a given PCI capability.
346 * Returns the address of the requested capability structure within the
347 * device's PCI configuration space or 0 in case the device does not
348 * support it. Possible values for @cap:
350 * %PCI_CAP_ID_PM Power Management
351 * %PCI_CAP_ID_AGP Accelerated Graphics Port
352 * %PCI_CAP_ID_VPD Vital Product Data
353 * %PCI_CAP_ID_SLOTID Slot Identification
354 * %PCI_CAP_ID_MSI Message Signalled Interrupts
355 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
356 * %PCI_CAP_ID_PCIX PCI-X
357 * %PCI_CAP_ID_EXP PCI Express
359 int pci_find_capability(struct pci_dev *dev, int cap)
363 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
365 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
369 EXPORT_SYMBOL(pci_find_capability);
372 * pci_bus_find_capability - query for devices' capabilities
373 * @bus: the PCI bus to query
374 * @devfn: PCI device to query
375 * @cap: capability code
377 * Like pci_find_capability() but works for pci devices that do not have a
378 * pci_dev structure set up yet.
380 * Returns the address of the requested capability structure within the
381 * device's PCI configuration space or 0 in case the device does not
384 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
389 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
391 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
393 pos = __pci_find_next_cap(bus, devfn, pos, cap);
397 EXPORT_SYMBOL(pci_bus_find_capability);
400 * pci_find_next_ext_capability - Find an extended capability
401 * @dev: PCI device to query
402 * @start: address at which to start looking (0 to start at beginning of list)
403 * @cap: capability code
405 * Returns the address of the next matching extended capability structure
406 * within the device's PCI configuration space or 0 if the device does
407 * not support it. Some capabilities can occur several times, e.g., the
408 * vendor-specific capability, and this provides a way to find them all.
410 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
414 int pos = PCI_CFG_SPACE_SIZE;
416 /* minimum 8 bytes per capability */
417 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
419 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
425 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
429 * If we have no capabilities, this is indicated by cap ID,
430 * cap version and next pointer all being 0.
436 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
439 pos = PCI_EXT_CAP_NEXT(header);
440 if (pos < PCI_CFG_SPACE_SIZE)
443 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
449 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
452 * pci_find_ext_capability - Find an extended capability
453 * @dev: PCI device to query
454 * @cap: capability code
456 * Returns the address of the requested extended capability structure
457 * within the device's PCI configuration space or 0 if the device does
458 * not support it. Possible values for @cap:
460 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
461 * %PCI_EXT_CAP_ID_VC Virtual Channel
462 * %PCI_EXT_CAP_ID_DSN Device Serial Number
463 * %PCI_EXT_CAP_ID_PWR Power Budgeting
465 int pci_find_ext_capability(struct pci_dev *dev, int cap)
467 return pci_find_next_ext_capability(dev, 0, cap);
469 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
471 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
473 int rc, ttl = PCI_FIND_CAP_TTL;
476 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
477 mask = HT_3BIT_CAP_MASK;
479 mask = HT_5BIT_CAP_MASK;
481 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
482 PCI_CAP_ID_HT, &ttl);
484 rc = pci_read_config_byte(dev, pos + 3, &cap);
485 if (rc != PCIBIOS_SUCCESSFUL)
488 if ((cap & mask) == ht_cap)
491 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
492 pos + PCI_CAP_LIST_NEXT,
493 PCI_CAP_ID_HT, &ttl);
499 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
500 * @dev: PCI device to query
501 * @pos: Position from which to continue searching
502 * @ht_cap: Hypertransport capability code
504 * To be used in conjunction with pci_find_ht_capability() to search for
505 * all capabilities matching @ht_cap. @pos should always be a value returned
506 * from pci_find_ht_capability().
508 * NB. To be 100% safe against broken PCI devices, the caller should take
509 * steps to avoid an infinite loop.
511 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
513 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
515 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
518 * pci_find_ht_capability - query a device's Hypertransport capabilities
519 * @dev: PCI device to query
520 * @ht_cap: Hypertransport capability code
522 * Tell if a device supports a given Hypertransport capability.
523 * Returns an address within the device's PCI configuration space
524 * or 0 in case the device does not support the request capability.
525 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
526 * which has a Hypertransport capability matching @ht_cap.
528 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
532 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
534 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
538 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
541 * pci_find_parent_resource - return resource region of parent bus of given region
542 * @dev: PCI device structure contains resources to be searched
543 * @res: child resource record for which parent is sought
545 * For given resource region of given device, return the resource
546 * region of parent bus the given region is contained in.
548 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
549 struct resource *res)
551 const struct pci_bus *bus = dev->bus;
555 pci_bus_for_each_resource(bus, r, i) {
558 if (resource_contains(r, res)) {
561 * If the window is prefetchable but the BAR is
562 * not, the allocator made a mistake.
564 if (r->flags & IORESOURCE_PREFETCH &&
565 !(res->flags & IORESOURCE_PREFETCH))
569 * If we're below a transparent bridge, there may
570 * be both a positively-decoded aperture and a
571 * subtractively-decoded region that contain the BAR.
572 * We want the positively-decoded one, so this depends
573 * on pci_bus_for_each_resource() giving us those
581 EXPORT_SYMBOL(pci_find_parent_resource);
584 * pci_find_resource - Return matching PCI device resource
585 * @dev: PCI device to query
586 * @res: Resource to look for
588 * Goes over standard PCI resources (BARs) and checks if the given resource
589 * is partially or fully contained in any of them. In that case the
590 * matching resource is returned, %NULL otherwise.
592 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
596 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
597 struct resource *r = &dev->resource[i];
599 if (r->start && resource_contains(r, res))
605 EXPORT_SYMBOL(pci_find_resource);
608 * pci_find_pcie_root_port - return PCIe Root Port
609 * @dev: PCI device to query
611 * Traverse up the parent chain and return the PCIe Root Port PCI Device
612 * for a given PCI Device.
614 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
616 struct pci_dev *bridge, *highest_pcie_bridge = dev;
618 bridge = pci_upstream_bridge(dev);
619 while (bridge && pci_is_pcie(bridge)) {
620 highest_pcie_bridge = bridge;
621 bridge = pci_upstream_bridge(bridge);
624 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
627 return highest_pcie_bridge;
629 EXPORT_SYMBOL(pci_find_pcie_root_port);
632 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
633 * @dev: the PCI device to operate on
634 * @pos: config space offset of status word
635 * @mask: mask of bit(s) to care about in status word
637 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
639 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
643 /* Wait for Transaction Pending bit clean */
644 for (i = 0; i < 4; i++) {
647 msleep((1 << (i - 1)) * 100);
649 pci_read_config_word(dev, pos, &status);
650 if (!(status & mask))
658 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
659 * @dev: PCI device to have its BARs restored
661 * Restore the BAR values for a given device, so as to make it
662 * accessible by its driver.
664 static void pci_restore_bars(struct pci_dev *dev)
668 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
669 pci_update_resource(dev, i);
672 static const struct pci_platform_pm_ops *pci_platform_pm;
674 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
676 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
677 !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
679 pci_platform_pm = ops;
683 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
685 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
688 static inline int platform_pci_set_power_state(struct pci_dev *dev,
691 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
694 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
696 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
699 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
701 return pci_platform_pm ?
702 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
705 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
707 return pci_platform_pm ?
708 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
711 static inline bool platform_pci_need_resume(struct pci_dev *dev)
713 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
717 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
719 * @dev: PCI device to handle.
720 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
723 * -EINVAL if the requested state is invalid.
724 * -EIO if device does not support PCI PM or its PM capabilities register has a
725 * wrong version, or device doesn't support the requested state.
726 * 0 if device already is in the requested state.
727 * 0 if device's power state has been successfully changed.
729 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
732 bool need_restore = false;
734 /* Check if we're already there */
735 if (dev->current_state == state)
741 if (state < PCI_D0 || state > PCI_D3hot)
744 /* Validate current state:
745 * Can enter D0 from any state, but if we can only go deeper
746 * to sleep if we're already in a low power state
748 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
749 && dev->current_state > state) {
750 pci_err(dev, "invalid power transition (from state %d to %d)\n",
751 dev->current_state, state);
755 /* check if this device supports the desired state */
756 if ((state == PCI_D1 && !dev->d1_support)
757 || (state == PCI_D2 && !dev->d2_support))
760 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
762 /* If we're (effectively) in D3, force entire word to 0.
763 * This doesn't affect PME_Status, disables PME_En, and
764 * sets PowerState to 0.
766 switch (dev->current_state) {
770 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
775 case PCI_UNKNOWN: /* Boot-up */
776 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
777 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
779 /* Fall-through: force to D0 */
785 /* enter specified state */
786 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
788 /* Mandatory power management transition delays */
789 /* see PCI PM 1.1 5.6.1 table 18 */
790 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
791 pci_dev_d3_sleep(dev);
792 else if (state == PCI_D2 || dev->current_state == PCI_D2)
793 udelay(PCI_PM_D2_DELAY);
795 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
796 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
797 if (dev->current_state != state && printk_ratelimit())
798 pci_info(dev, "Refused to change power state, currently in D%d\n",
802 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
803 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
804 * from D3hot to D0 _may_ perform an internal reset, thereby
805 * going to "D0 Uninitialized" rather than "D0 Initialized".
806 * For example, at least some versions of the 3c905B and the
807 * 3c556B exhibit this behaviour.
809 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
810 * devices in a D3hot state at boot. Consequently, we need to
811 * restore at least the BARs so that the device will be
812 * accessible to its driver.
815 pci_restore_bars(dev);
818 pcie_aspm_pm_state_change(dev->bus->self);
824 * pci_update_current_state - Read power state of given device and cache it
825 * @dev: PCI device to handle.
826 * @state: State to cache in case the device doesn't have the PM capability
828 * The power state is read from the PMCSR register, which however is
829 * inaccessible in D3cold. The platform firmware is therefore queried first
830 * to detect accessibility of the register. In case the platform firmware
831 * reports an incorrect state or the device isn't power manageable by the
832 * platform at all, we try to detect D3cold by testing accessibility of the
833 * vendor ID in config space.
835 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
837 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
838 !pci_device_is_present(dev)) {
839 dev->current_state = PCI_D3cold;
840 } else if (dev->pm_cap) {
843 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
844 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
846 dev->current_state = state;
851 * pci_power_up - Put the given device into D0 forcibly
852 * @dev: PCI device to power up
854 void pci_power_up(struct pci_dev *dev)
856 if (platform_pci_power_manageable(dev))
857 platform_pci_set_power_state(dev, PCI_D0);
859 pci_raw_set_power_state(dev, PCI_D0);
860 pci_update_current_state(dev, PCI_D0);
864 * pci_platform_power_transition - Use platform to change device power state
865 * @dev: PCI device to handle.
866 * @state: State to put the device into.
868 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
872 if (platform_pci_power_manageable(dev)) {
873 error = platform_pci_set_power_state(dev, state);
875 pci_update_current_state(dev, state);
879 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
880 dev->current_state = PCI_D0;
886 * pci_wakeup - Wake up a PCI device
887 * @pci_dev: Device to handle.
888 * @ign: ignored parameter
890 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
892 pci_wakeup_event(pci_dev);
893 pm_request_resume(&pci_dev->dev);
898 * pci_wakeup_bus - Walk given bus and wake up devices on it
899 * @bus: Top bus of the subtree to walk.
901 void pci_wakeup_bus(struct pci_bus *bus)
904 pci_walk_bus(bus, pci_wakeup, NULL);
908 * __pci_start_power_transition - Start power transition of a PCI device
909 * @dev: PCI device to handle.
910 * @state: State to put the device into.
912 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
914 if (state == PCI_D0) {
915 pci_platform_power_transition(dev, PCI_D0);
917 * Mandatory power management transition delays, see
918 * PCI Express Base Specification Revision 2.0 Section
919 * 6.6.1: Conventional Reset. Do not delay for
920 * devices powered on/off by corresponding bridge,
921 * because have already delayed for the bridge.
923 if (dev->runtime_d3cold) {
924 if (dev->d3cold_delay)
925 msleep(dev->d3cold_delay);
927 * When powering on a bridge from D3cold, the
928 * whole hierarchy may be powered on into
929 * D0uninitialized state, resume them to give
930 * them a chance to suspend again
932 pci_wakeup_bus(dev->subordinate);
938 * __pci_dev_set_current_state - Set current state of a PCI device
939 * @dev: Device to handle
940 * @data: pointer to state to be set
942 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
944 pci_power_t state = *(pci_power_t *)data;
946 dev->current_state = state;
951 * pci_bus_set_current_state - Walk given bus and set current state of devices
952 * @bus: Top bus of the subtree to walk.
953 * @state: state to be set
955 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
958 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
962 * __pci_complete_power_transition - Complete power transition of a PCI device
963 * @dev: PCI device to handle.
964 * @state: State to put the device into.
966 * This function should not be called directly by device drivers.
968 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
974 ret = pci_platform_power_transition(dev, state);
975 /* Power off the bridge may power off the whole hierarchy */
976 if (!ret && state == PCI_D3cold)
977 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
980 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
983 * pci_set_power_state - Set the power state of a PCI device
984 * @dev: PCI device to handle.
985 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
987 * Transition a device to a new power state, using the platform firmware and/or
988 * the device's PCI PM registers.
991 * -EINVAL if the requested state is invalid.
992 * -EIO if device does not support PCI PM or its PM capabilities register has a
993 * wrong version, or device doesn't support the requested state.
994 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
995 * 0 if device already is in the requested state.
996 * 0 if the transition is to D3 but D3 is not supported.
997 * 0 if device's power state has been successfully changed.
999 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1003 /* bound the state we're entering */
1004 if (state > PCI_D3cold)
1006 else if (state < PCI_D0)
1008 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1010 * If the device or the parent bridge do not support PCI PM,
1011 * ignore the request if we're doing anything other than putting
1012 * it into D0 (which would only happen on boot).
1016 /* Check if we're already there */
1017 if (dev->current_state == state)
1020 __pci_start_power_transition(dev, state);
1022 /* This device is quirked not to be put into D3, so
1023 don't put it in D3 */
1024 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1028 * To put device in D3cold, we put device into D3hot in native
1029 * way, then put device into D3cold with platform ops
1031 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
1034 if (!__pci_complete_power_transition(dev, state))
1039 EXPORT_SYMBOL(pci_set_power_state);
1042 * pci_choose_state - Choose the power state of a PCI device
1043 * @dev: PCI device to be suspended
1044 * @state: target sleep state for the whole system. This is the value
1045 * that is passed to suspend() function.
1047 * Returns PCI power state suitable for given device and given system
1051 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
1058 ret = platform_pci_choose_state(dev);
1059 if (ret != PCI_POWER_ERROR)
1062 switch (state.event) {
1065 case PM_EVENT_FREEZE:
1066 case PM_EVENT_PRETHAW:
1067 /* REVISIT both freeze and pre-thaw "should" use D0 */
1068 case PM_EVENT_SUSPEND:
1069 case PM_EVENT_HIBERNATE:
1072 pci_info(dev, "unrecognized suspend event %d\n",
1078 EXPORT_SYMBOL(pci_choose_state);
1080 #define PCI_EXP_SAVE_REGS 7
1082 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1083 u16 cap, bool extended)
1085 struct pci_cap_saved_state *tmp;
1087 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1088 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1094 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1096 return _pci_find_saved_cap(dev, cap, false);
1099 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1101 return _pci_find_saved_cap(dev, cap, true);
1104 static int pci_save_pcie_state(struct pci_dev *dev)
1107 struct pci_cap_saved_state *save_state;
1110 if (!pci_is_pcie(dev))
1113 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1115 pci_err(dev, "buffer not found in %s\n", __func__);
1119 cap = (u16 *)&save_state->cap.data[0];
1120 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1121 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1122 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1123 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1124 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1125 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1126 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1131 static void pci_restore_pcie_state(struct pci_dev *dev)
1134 struct pci_cap_saved_state *save_state;
1137 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1141 cap = (u16 *)&save_state->cap.data[0];
1142 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1143 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1144 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1145 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1146 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1147 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1148 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1152 static int pci_save_pcix_state(struct pci_dev *dev)
1155 struct pci_cap_saved_state *save_state;
1157 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1161 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1163 pci_err(dev, "buffer not found in %s\n", __func__);
1167 pci_read_config_word(dev, pos + PCI_X_CMD,
1168 (u16 *)save_state->cap.data);
1173 static void pci_restore_pcix_state(struct pci_dev *dev)
1176 struct pci_cap_saved_state *save_state;
1179 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1180 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1181 if (!save_state || !pos)
1183 cap = (u16 *)&save_state->cap.data[0];
1185 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1190 * pci_save_state - save the PCI configuration space of a device before suspending
1191 * @dev: - PCI device that we're dealing with
1193 int pci_save_state(struct pci_dev *dev)
1196 /* XXX: 100% dword access ok here? */
1197 for (i = 0; i < 16; i++)
1198 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1199 dev->state_saved = true;
1201 i = pci_save_pcie_state(dev);
1205 i = pci_save_pcix_state(dev);
1209 return pci_save_vc_state(dev);
1211 EXPORT_SYMBOL(pci_save_state);
1213 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1214 u32 saved_val, int retry)
1218 pci_read_config_dword(pdev, offset, &val);
1219 if (val == saved_val)
1223 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1224 offset, val, saved_val);
1225 pci_write_config_dword(pdev, offset, saved_val);
1229 pci_read_config_dword(pdev, offset, &val);
1230 if (val == saved_val)
1237 static void pci_restore_config_space_range(struct pci_dev *pdev,
1238 int start, int end, int retry)
1242 for (index = end; index >= start; index--)
1243 pci_restore_config_dword(pdev, 4 * index,
1244 pdev->saved_config_space[index],
1248 static void pci_restore_config_space(struct pci_dev *pdev)
1250 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1251 pci_restore_config_space_range(pdev, 10, 15, 0);
1252 /* Restore BARs before the command register. */
1253 pci_restore_config_space_range(pdev, 4, 9, 10);
1254 pci_restore_config_space_range(pdev, 0, 3, 0);
1256 pci_restore_config_space_range(pdev, 0, 15, 0);
1261 * pci_restore_state - Restore the saved state of a PCI device
1262 * @dev: - PCI device that we're dealing with
1264 void pci_restore_state(struct pci_dev *dev)
1266 if (!dev->state_saved)
1269 /* PCI Express register must be restored first */
1270 pci_restore_pcie_state(dev);
1271 pci_restore_pasid_state(dev);
1272 pci_restore_pri_state(dev);
1273 pci_restore_ats_state(dev);
1274 pci_restore_vc_state(dev);
1276 pci_cleanup_aer_error_status_regs(dev);
1278 pci_restore_config_space(dev);
1280 pci_restore_pcix_state(dev);
1281 pci_restore_msi_state(dev);
1283 /* Restore ACS and IOV configuration state */
1284 pci_enable_acs(dev);
1285 pci_restore_iov_state(dev);
1287 dev->state_saved = false;
1289 EXPORT_SYMBOL(pci_restore_state);
1291 struct pci_saved_state {
1292 u32 config_space[16];
1293 struct pci_cap_saved_data cap[0];
1297 * pci_store_saved_state - Allocate and return an opaque struct containing
1298 * the device saved state.
1299 * @dev: PCI device that we're dealing with
1301 * Return NULL if no state or error.
1303 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1305 struct pci_saved_state *state;
1306 struct pci_cap_saved_state *tmp;
1307 struct pci_cap_saved_data *cap;
1310 if (!dev->state_saved)
1313 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1315 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1316 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1318 state = kzalloc(size, GFP_KERNEL);
1322 memcpy(state->config_space, dev->saved_config_space,
1323 sizeof(state->config_space));
1326 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1327 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1328 memcpy(cap, &tmp->cap, len);
1329 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1331 /* Empty cap_save terminates list */
1335 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1338 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1339 * @dev: PCI device that we're dealing with
1340 * @state: Saved state returned from pci_store_saved_state()
1342 int pci_load_saved_state(struct pci_dev *dev,
1343 struct pci_saved_state *state)
1345 struct pci_cap_saved_data *cap;
1347 dev->state_saved = false;
1352 memcpy(dev->saved_config_space, state->config_space,
1353 sizeof(state->config_space));
1357 struct pci_cap_saved_state *tmp;
1359 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1360 if (!tmp || tmp->cap.size != cap->size)
1363 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1364 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1365 sizeof(struct pci_cap_saved_data) + cap->size);
1368 dev->state_saved = true;
1371 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1374 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1375 * and free the memory allocated for it.
1376 * @dev: PCI device that we're dealing with
1377 * @state: Pointer to saved state returned from pci_store_saved_state()
1379 int pci_load_and_free_saved_state(struct pci_dev *dev,
1380 struct pci_saved_state **state)
1382 int ret = pci_load_saved_state(dev, *state);
1387 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1389 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1391 return pci_enable_resources(dev, bars);
1394 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1397 struct pci_dev *bridge;
1401 err = pci_set_power_state(dev, PCI_D0);
1402 if (err < 0 && err != -EIO)
1405 bridge = pci_upstream_bridge(dev);
1407 pcie_aspm_powersave_config_link(bridge);
1409 err = pcibios_enable_device(dev, bars);
1412 pci_fixup_device(pci_fixup_enable, dev);
1414 if (dev->msi_enabled || dev->msix_enabled)
1417 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1419 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1420 if (cmd & PCI_COMMAND_INTX_DISABLE)
1421 pci_write_config_word(dev, PCI_COMMAND,
1422 cmd & ~PCI_COMMAND_INTX_DISABLE);
1429 * pci_reenable_device - Resume abandoned device
1430 * @dev: PCI device to be resumed
1432 * Note this function is a backend of pci_default_resume and is not supposed
1433 * to be called by normal code, write proper resume handler and use it instead.
1435 int pci_reenable_device(struct pci_dev *dev)
1437 if (pci_is_enabled(dev))
1438 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1441 EXPORT_SYMBOL(pci_reenable_device);
1443 static void pci_enable_bridge(struct pci_dev *dev)
1445 struct pci_dev *bridge;
1448 bridge = pci_upstream_bridge(dev);
1450 pci_enable_bridge(bridge);
1452 if (pci_is_enabled(dev)) {
1453 if (!dev->is_busmaster)
1454 pci_set_master(dev);
1458 retval = pci_enable_device(dev);
1460 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1462 pci_set_master(dev);
1465 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1467 struct pci_dev *bridge;
1472 * Power state could be unknown at this point, either due to a fresh
1473 * boot or a device removal call. So get the current power state
1474 * so that things like MSI message writing will behave as expected
1475 * (e.g. if the device really is in D0 at enable time).
1479 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1480 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1483 if (atomic_inc_return(&dev->enable_cnt) > 1)
1484 return 0; /* already enabled */
1486 bridge = pci_upstream_bridge(dev);
1488 pci_enable_bridge(bridge);
1490 /* only skip sriov related */
1491 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1492 if (dev->resource[i].flags & flags)
1494 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1495 if (dev->resource[i].flags & flags)
1498 err = do_pci_enable_device(dev, bars);
1500 atomic_dec(&dev->enable_cnt);
1505 * pci_enable_device_io - Initialize a device for use with IO space
1506 * @dev: PCI device to be initialized
1508 * Initialize device before it's used by a driver. Ask low-level code
1509 * to enable I/O resources. Wake up the device if it was suspended.
1510 * Beware, this function can fail.
1512 int pci_enable_device_io(struct pci_dev *dev)
1514 return pci_enable_device_flags(dev, IORESOURCE_IO);
1516 EXPORT_SYMBOL(pci_enable_device_io);
1519 * pci_enable_device_mem - Initialize a device for use with Memory space
1520 * @dev: PCI device to be initialized
1522 * Initialize device before it's used by a driver. Ask low-level code
1523 * to enable Memory resources. Wake up the device if it was suspended.
1524 * Beware, this function can fail.
1526 int pci_enable_device_mem(struct pci_dev *dev)
1528 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1530 EXPORT_SYMBOL(pci_enable_device_mem);
1533 * pci_enable_device - Initialize device before it's used by a driver.
1534 * @dev: PCI device to be initialized
1536 * Initialize device before it's used by a driver. Ask low-level code
1537 * to enable I/O and memory. Wake up the device if it was suspended.
1538 * Beware, this function can fail.
1540 * Note we don't actually enable the device many times if we call
1541 * this function repeatedly (we just increment the count).
1543 int pci_enable_device(struct pci_dev *dev)
1545 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1547 EXPORT_SYMBOL(pci_enable_device);
1550 * Managed PCI resources. This manages device on/off, intx/msi/msix
1551 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1552 * there's no need to track it separately. pci_devres is initialized
1553 * when a device is enabled using managed PCI device enable interface.
1556 unsigned int enabled:1;
1557 unsigned int pinned:1;
1558 unsigned int orig_intx:1;
1559 unsigned int restore_intx:1;
1564 static void pcim_release(struct device *gendev, void *res)
1566 struct pci_dev *dev = to_pci_dev(gendev);
1567 struct pci_devres *this = res;
1570 if (dev->msi_enabled)
1571 pci_disable_msi(dev);
1572 if (dev->msix_enabled)
1573 pci_disable_msix(dev);
1575 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1576 if (this->region_mask & (1 << i))
1577 pci_release_region(dev, i);
1582 if (this->restore_intx)
1583 pci_intx(dev, this->orig_intx);
1585 if (this->enabled && !this->pinned)
1586 pci_disable_device(dev);
1589 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1591 struct pci_devres *dr, *new_dr;
1593 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1597 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1600 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1603 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1605 if (pci_is_managed(pdev))
1606 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1611 * pcim_enable_device - Managed pci_enable_device()
1612 * @pdev: PCI device to be initialized
1614 * Managed pci_enable_device().
1616 int pcim_enable_device(struct pci_dev *pdev)
1618 struct pci_devres *dr;
1621 dr = get_pci_dr(pdev);
1627 rc = pci_enable_device(pdev);
1629 pdev->is_managed = 1;
1634 EXPORT_SYMBOL(pcim_enable_device);
1637 * pcim_pin_device - Pin managed PCI device
1638 * @pdev: PCI device to pin
1640 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1641 * driver detach. @pdev must have been enabled with
1642 * pcim_enable_device().
1644 void pcim_pin_device(struct pci_dev *pdev)
1646 struct pci_devres *dr;
1648 dr = find_pci_dr(pdev);
1649 WARN_ON(!dr || !dr->enabled);
1653 EXPORT_SYMBOL(pcim_pin_device);
1656 * pcibios_add_device - provide arch specific hooks when adding device dev
1657 * @dev: the PCI device being added
1659 * Permits the platform to provide architecture specific functionality when
1660 * devices are added. This is the default implementation. Architecture
1661 * implementations can override this.
1663 int __weak pcibios_add_device(struct pci_dev *dev)
1669 * pcibios_release_device - provide arch specific hooks when releasing device dev
1670 * @dev: the PCI device being released
1672 * Permits the platform to provide architecture specific functionality when
1673 * devices are released. This is the default implementation. Architecture
1674 * implementations can override this.
1676 void __weak pcibios_release_device(struct pci_dev *dev) {}
1679 * pcibios_disable_device - disable arch specific PCI resources for device dev
1680 * @dev: the PCI device to disable
1682 * Disables architecture specific PCI resources for the device. This
1683 * is the default implementation. Architecture implementations can
1686 void __weak pcibios_disable_device(struct pci_dev *dev) {}
1689 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1690 * @irq: ISA IRQ to penalize
1691 * @active: IRQ active or not
1693 * Permits the platform to provide architecture-specific functionality when
1694 * penalizing ISA IRQs. This is the default implementation. Architecture
1695 * implementations can override this.
1697 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1699 static void do_pci_disable_device(struct pci_dev *dev)
1703 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1704 if (pci_command & PCI_COMMAND_MASTER) {
1705 pci_command &= ~PCI_COMMAND_MASTER;
1706 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1709 pcibios_disable_device(dev);
1713 * pci_disable_enabled_device - Disable device without updating enable_cnt
1714 * @dev: PCI device to disable
1716 * NOTE: This function is a backend of PCI power management routines and is
1717 * not supposed to be called drivers.
1719 void pci_disable_enabled_device(struct pci_dev *dev)
1721 if (pci_is_enabled(dev))
1722 do_pci_disable_device(dev);
1726 * pci_disable_device - Disable PCI device after use
1727 * @dev: PCI device to be disabled
1729 * Signal to the system that the PCI device is not in use by the system
1730 * anymore. This only involves disabling PCI bus-mastering, if active.
1732 * Note we don't actually disable the device until all callers of
1733 * pci_enable_device() have called pci_disable_device().
1735 void pci_disable_device(struct pci_dev *dev)
1737 struct pci_devres *dr;
1739 dr = find_pci_dr(dev);
1743 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1744 "disabling already-disabled device");
1746 if (atomic_dec_return(&dev->enable_cnt) != 0)
1749 do_pci_disable_device(dev);
1751 dev->is_busmaster = 0;
1753 EXPORT_SYMBOL(pci_disable_device);
1756 * pcibios_set_pcie_reset_state - set reset state for device dev
1757 * @dev: the PCIe device reset
1758 * @state: Reset state to enter into
1761 * Sets the PCIe reset state for the device. This is the default
1762 * implementation. Architecture implementations can override this.
1764 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1765 enum pcie_reset_state state)
1771 * pci_set_pcie_reset_state - set reset state for device dev
1772 * @dev: the PCIe device reset
1773 * @state: Reset state to enter into
1776 * Sets the PCI reset state for the device.
1778 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1780 return pcibios_set_pcie_reset_state(dev, state);
1782 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1785 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
1786 * @dev: PCIe root port or event collector.
1788 void pcie_clear_root_pme_status(struct pci_dev *dev)
1790 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
1794 * pci_check_pme_status - Check if given device has generated PME.
1795 * @dev: Device to check.
1797 * Check the PME status of the device and if set, clear it and clear PME enable
1798 * (if set). Return 'true' if PME status and PME enable were both set or
1799 * 'false' otherwise.
1801 bool pci_check_pme_status(struct pci_dev *dev)
1810 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1811 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1812 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1815 /* Clear PME status. */
1816 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1817 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1818 /* Disable PME to avoid interrupt flood. */
1819 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1823 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1829 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1830 * @dev: Device to handle.
1831 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1833 * Check if @dev has generated PME and queue a resume request for it in that
1836 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1838 if (pme_poll_reset && dev->pme_poll)
1839 dev->pme_poll = false;
1841 if (pci_check_pme_status(dev)) {
1842 pci_wakeup_event(dev);
1843 pm_request_resume(&dev->dev);
1849 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1850 * @bus: Top bus of the subtree to walk.
1852 void pci_pme_wakeup_bus(struct pci_bus *bus)
1855 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1860 * pci_pme_capable - check the capability of PCI device to generate PME#
1861 * @dev: PCI device to handle.
1862 * @state: PCI state from which device will issue PME#.
1864 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1869 return !!(dev->pme_support & (1 << state));
1871 EXPORT_SYMBOL(pci_pme_capable);
1873 static void pci_pme_list_scan(struct work_struct *work)
1875 struct pci_pme_device *pme_dev, *n;
1877 mutex_lock(&pci_pme_list_mutex);
1878 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1879 if (pme_dev->dev->pme_poll) {
1880 struct pci_dev *bridge;
1882 bridge = pme_dev->dev->bus->self;
1884 * If bridge is in low power state, the
1885 * configuration space of subordinate devices
1886 * may be not accessible
1888 if (bridge && bridge->current_state != PCI_D0)
1890 pci_pme_wakeup(pme_dev->dev, NULL);
1892 list_del(&pme_dev->list);
1896 if (!list_empty(&pci_pme_list))
1897 queue_delayed_work(system_freezable_wq, &pci_pme_work,
1898 msecs_to_jiffies(PME_TIMEOUT));
1899 mutex_unlock(&pci_pme_list_mutex);
1902 static void __pci_pme_active(struct pci_dev *dev, bool enable)
1906 if (!dev->pme_support)
1909 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1910 /* Clear PME_Status by writing 1 to it and enable PME# */
1911 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1913 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1915 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1919 * pci_pme_restore - Restore PME configuration after config space restore.
1920 * @dev: PCI device to update.
1922 void pci_pme_restore(struct pci_dev *dev)
1926 if (!dev->pme_support)
1929 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1930 if (dev->wakeup_prepared) {
1931 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
1932 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
1934 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1935 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1937 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1941 * pci_pme_active - enable or disable PCI device's PME# function
1942 * @dev: PCI device to handle.
1943 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1945 * The caller must verify that the device is capable of generating PME# before
1946 * calling this function with @enable equal to 'true'.
1948 void pci_pme_active(struct pci_dev *dev, bool enable)
1950 __pci_pme_active(dev, enable);
1953 * PCI (as opposed to PCIe) PME requires that the device have
1954 * its PME# line hooked up correctly. Not all hardware vendors
1955 * do this, so the PME never gets delivered and the device
1956 * remains asleep. The easiest way around this is to
1957 * periodically walk the list of suspended devices and check
1958 * whether any have their PME flag set. The assumption is that
1959 * we'll wake up often enough anyway that this won't be a huge
1960 * hit, and the power savings from the devices will still be a
1963 * Although PCIe uses in-band PME message instead of PME# line
1964 * to report PME, PME does not work for some PCIe devices in
1965 * reality. For example, there are devices that set their PME
1966 * status bits, but don't really bother to send a PME message;
1967 * there are PCI Express Root Ports that don't bother to
1968 * trigger interrupts when they receive PME messages from the
1969 * devices below. So PME poll is used for PCIe devices too.
1972 if (dev->pme_poll) {
1973 struct pci_pme_device *pme_dev;
1975 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1978 pci_warn(dev, "can't enable PME#\n");
1982 mutex_lock(&pci_pme_list_mutex);
1983 list_add(&pme_dev->list, &pci_pme_list);
1984 if (list_is_singular(&pci_pme_list))
1985 queue_delayed_work(system_freezable_wq,
1987 msecs_to_jiffies(PME_TIMEOUT));
1988 mutex_unlock(&pci_pme_list_mutex);
1990 mutex_lock(&pci_pme_list_mutex);
1991 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1992 if (pme_dev->dev == dev) {
1993 list_del(&pme_dev->list);
1998 mutex_unlock(&pci_pme_list_mutex);
2002 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2004 EXPORT_SYMBOL(pci_pme_active);
2007 * __pci_enable_wake - enable PCI device as wakeup event source
2008 * @dev: PCI device affected
2009 * @state: PCI state from which device will issue wakeup events
2010 * @enable: True to enable event generation; false to disable
2012 * This enables the device as a wakeup event source, or disables it.
2013 * When such events involves platform-specific hooks, those hooks are
2014 * called automatically by this routine.
2016 * Devices with legacy power management (no standard PCI PM capabilities)
2017 * always require such platform hooks.
2020 * 0 is returned on success
2021 * -EINVAL is returned if device is not supposed to wake up the system
2022 * Error code depending on the platform is returned if both the platform and
2023 * the native mechanism fail to enable the generation of wake-up events
2025 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2030 * Bridges can only signal wakeup on behalf of subordinate devices,
2031 * but that is set up elsewhere, so skip them.
2033 if (pci_has_subordinate(dev))
2036 /* Don't do the same thing twice in a row for one device. */
2037 if (!!enable == !!dev->wakeup_prepared)
2041 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2042 * Anderson we should be doing PME# wake enable followed by ACPI wake
2043 * enable. To disable wake-up we call the platform first, for symmetry.
2049 if (pci_pme_capable(dev, state))
2050 pci_pme_active(dev, true);
2053 error = platform_pci_set_wakeup(dev, true);
2057 dev->wakeup_prepared = true;
2059 platform_pci_set_wakeup(dev, false);
2060 pci_pme_active(dev, false);
2061 dev->wakeup_prepared = false;
2068 * pci_enable_wake - change wakeup settings for a PCI device
2069 * @pci_dev: Target device
2070 * @state: PCI state from which device will issue wakeup events
2071 * @enable: Whether or not to enable event generation
2073 * If @enable is set, check device_may_wakeup() for the device before calling
2074 * __pci_enable_wake() for it.
2076 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2078 if (enable && !device_may_wakeup(&pci_dev->dev))
2081 return __pci_enable_wake(pci_dev, state, enable);
2083 EXPORT_SYMBOL(pci_enable_wake);
2086 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2087 * @dev: PCI device to prepare
2088 * @enable: True to enable wake-up event generation; false to disable
2090 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2091 * and this function allows them to set that up cleanly - pci_enable_wake()
2092 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2093 * ordering constraints.
2095 * This function only returns error code if the device is not allowed to wake
2096 * up the system from sleep or it is not capable of generating PME# from both
2097 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2099 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2101 return pci_pme_capable(dev, PCI_D3cold) ?
2102 pci_enable_wake(dev, PCI_D3cold, enable) :
2103 pci_enable_wake(dev, PCI_D3hot, enable);
2105 EXPORT_SYMBOL(pci_wake_from_d3);
2108 * pci_target_state - find an appropriate low power state for a given PCI dev
2110 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2112 * Use underlying platform code to find a supported low power state for @dev.
2113 * If the platform can't manage @dev, return the deepest state from which it
2114 * can generate wake events, based on any available PME info.
2116 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2118 pci_power_t target_state = PCI_D3hot;
2120 if (platform_pci_power_manageable(dev)) {
2122 * Call the platform to find the target state for the device.
2124 pci_power_t state = platform_pci_choose_state(dev);
2127 case PCI_POWER_ERROR:
2132 if (pci_no_d1d2(dev))
2135 target_state = state;
2138 return target_state;
2142 target_state = PCI_D0;
2145 * If the device is in D3cold even though it's not power-manageable by
2146 * the platform, it may have been powered down by non-standard means.
2147 * Best to let it slumber.
2149 if (dev->current_state == PCI_D3cold)
2150 target_state = PCI_D3cold;
2154 * Find the deepest state from which the device can generate
2157 if (dev->pme_support) {
2159 && !(dev->pme_support & (1 << target_state)))
2164 return target_state;
2168 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2169 * @dev: Device to handle.
2171 * Choose the power state appropriate for the device depending on whether
2172 * it can wake up the system and/or is power manageable by the platform
2173 * (PCI_D3hot is the default) and put the device into that state.
2175 int pci_prepare_to_sleep(struct pci_dev *dev)
2177 bool wakeup = device_may_wakeup(&dev->dev);
2178 pci_power_t target_state = pci_target_state(dev, wakeup);
2181 if (target_state == PCI_POWER_ERROR)
2184 pci_enable_wake(dev, target_state, wakeup);
2186 error = pci_set_power_state(dev, target_state);
2189 pci_enable_wake(dev, target_state, false);
2193 EXPORT_SYMBOL(pci_prepare_to_sleep);
2196 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2197 * @dev: Device to handle.
2199 * Disable device's system wake-up capability and put it into D0.
2201 int pci_back_from_sleep(struct pci_dev *dev)
2203 pci_enable_wake(dev, PCI_D0, false);
2204 return pci_set_power_state(dev, PCI_D0);
2206 EXPORT_SYMBOL(pci_back_from_sleep);
2209 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2210 * @dev: PCI device being suspended.
2212 * Prepare @dev to generate wake-up events at run time and put it into a low
2215 int pci_finish_runtime_suspend(struct pci_dev *dev)
2217 pci_power_t target_state;
2220 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2221 if (target_state == PCI_POWER_ERROR)
2224 dev->runtime_d3cold = target_state == PCI_D3cold;
2226 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2228 error = pci_set_power_state(dev, target_state);
2231 pci_enable_wake(dev, target_state, false);
2232 dev->runtime_d3cold = false;
2239 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2240 * @dev: Device to check.
2242 * Return true if the device itself is capable of generating wake-up events
2243 * (through the platform or using the native PCIe PME) or if the device supports
2244 * PME and one of its upstream bridges can generate wake-up events.
2246 bool pci_dev_run_wake(struct pci_dev *dev)
2248 struct pci_bus *bus = dev->bus;
2250 if (!dev->pme_support)
2253 /* PME-capable in principle, but not from the target power state */
2254 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2257 if (device_can_wakeup(&dev->dev))
2260 while (bus->parent) {
2261 struct pci_dev *bridge = bus->self;
2263 if (device_can_wakeup(&bridge->dev))
2269 /* We have reached the root bus. */
2271 return device_can_wakeup(bus->bridge);
2275 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2278 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2279 * @pci_dev: Device to check.
2281 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2282 * reconfigured due to wakeup settings difference between system and runtime
2283 * suspend and the current power state of it is suitable for the upcoming
2284 * (system) transition.
2286 * If the device is not configured for system wakeup, disable PME for it before
2287 * returning 'true' to prevent it from waking up the system unnecessarily.
2289 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2291 struct device *dev = &pci_dev->dev;
2292 bool wakeup = device_may_wakeup(dev);
2294 if (!pm_runtime_suspended(dev)
2295 || pci_target_state(pci_dev, wakeup) != pci_dev->current_state
2296 || platform_pci_need_resume(pci_dev))
2300 * At this point the device is good to go unless it's been configured
2301 * to generate PME at the runtime suspend time, but it is not supposed
2302 * to wake up the system. In that case, simply disable PME for it
2303 * (it will have to be re-enabled on exit from system resume).
2305 * If the device's power state is D3cold and the platform check above
2306 * hasn't triggered, the device's configuration is suitable and we don't
2307 * need to manipulate it at all.
2309 spin_lock_irq(&dev->power.lock);
2311 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2313 __pci_pme_active(pci_dev, false);
2315 spin_unlock_irq(&dev->power.lock);
2320 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2321 * @pci_dev: Device to handle.
2323 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2324 * it might have been disabled during the prepare phase of system suspend if
2325 * the device was not configured for system wakeup.
2327 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2329 struct device *dev = &pci_dev->dev;
2331 if (!pci_dev_run_wake(pci_dev))
2334 spin_lock_irq(&dev->power.lock);
2336 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2337 __pci_pme_active(pci_dev, true);
2339 spin_unlock_irq(&dev->power.lock);
2342 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2344 struct device *dev = &pdev->dev;
2345 struct device *parent = dev->parent;
2348 pm_runtime_get_sync(parent);
2349 pm_runtime_get_noresume(dev);
2351 * pdev->current_state is set to PCI_D3cold during suspending,
2352 * so wait until suspending completes
2354 pm_runtime_barrier(dev);
2356 * Only need to resume devices in D3cold, because config
2357 * registers are still accessible for devices suspended but
2360 if (pdev->current_state == PCI_D3cold)
2361 pm_runtime_resume(dev);
2364 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2366 struct device *dev = &pdev->dev;
2367 struct device *parent = dev->parent;
2369 pm_runtime_put(dev);
2371 pm_runtime_put_sync(parent);
2375 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2376 * @bridge: Bridge to check
2378 * This function checks if it is possible to move the bridge to D3.
2379 * Currently we only allow D3 for recent enough PCIe ports.
2381 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2383 if (!pci_is_pcie(bridge))
2386 switch (pci_pcie_type(bridge)) {
2387 case PCI_EXP_TYPE_ROOT_PORT:
2388 case PCI_EXP_TYPE_UPSTREAM:
2389 case PCI_EXP_TYPE_DOWNSTREAM:
2390 if (pci_bridge_d3_disable)
2394 * Hotplug interrupts cannot be delivered if the link is down,
2395 * so parents of a hotplug port must stay awake. In addition,
2396 * hotplug ports handled by firmware in System Management Mode
2397 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2398 * For simplicity, disallow in general for now.
2400 if (bridge->is_hotplug_bridge)
2403 if (pci_bridge_d3_force)
2407 * It should be safe to put PCIe ports from 2015 or newer
2410 if (dmi_get_bios_year() >= 2015)
2418 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2420 bool *d3cold_ok = data;
2422 if (/* The device needs to be allowed to go D3cold ... */
2423 dev->no_d3cold || !dev->d3cold_allowed ||
2425 /* ... and if it is wakeup capable to do so from D3cold. */
2426 (device_may_wakeup(&dev->dev) &&
2427 !pci_pme_capable(dev, PCI_D3cold)) ||
2429 /* If it is a bridge it must be allowed to go to D3. */
2430 !pci_power_manageable(dev))
2438 * pci_bridge_d3_update - Update bridge D3 capabilities
2439 * @dev: PCI device which is changed
2441 * Update upstream bridge PM capabilities accordingly depending on if the
2442 * device PM configuration was changed or the device is being removed. The
2443 * change is also propagated upstream.
2445 void pci_bridge_d3_update(struct pci_dev *dev)
2447 bool remove = !device_is_registered(&dev->dev);
2448 struct pci_dev *bridge;
2449 bool d3cold_ok = true;
2451 bridge = pci_upstream_bridge(dev);
2452 if (!bridge || !pci_bridge_d3_possible(bridge))
2456 * If D3 is currently allowed for the bridge, removing one of its
2457 * children won't change that.
2459 if (remove && bridge->bridge_d3)
2463 * If D3 is currently allowed for the bridge and a child is added or
2464 * changed, disallowance of D3 can only be caused by that child, so
2465 * we only need to check that single device, not any of its siblings.
2467 * If D3 is currently not allowed for the bridge, checking the device
2468 * first may allow us to skip checking its siblings.
2471 pci_dev_check_d3cold(dev, &d3cold_ok);
2474 * If D3 is currently not allowed for the bridge, this may be caused
2475 * either by the device being changed/removed or any of its siblings,
2476 * so we need to go through all children to find out if one of them
2477 * continues to block D3.
2479 if (d3cold_ok && !bridge->bridge_d3)
2480 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2483 if (bridge->bridge_d3 != d3cold_ok) {
2484 bridge->bridge_d3 = d3cold_ok;
2485 /* Propagate change to upstream bridges */
2486 pci_bridge_d3_update(bridge);
2491 * pci_d3cold_enable - Enable D3cold for device
2492 * @dev: PCI device to handle
2494 * This function can be used in drivers to enable D3cold from the device
2495 * they handle. It also updates upstream PCI bridge PM capabilities
2498 void pci_d3cold_enable(struct pci_dev *dev)
2500 if (dev->no_d3cold) {
2501 dev->no_d3cold = false;
2502 pci_bridge_d3_update(dev);
2505 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2508 * pci_d3cold_disable - Disable D3cold for device
2509 * @dev: PCI device to handle
2511 * This function can be used in drivers to disable D3cold from the device
2512 * they handle. It also updates upstream PCI bridge PM capabilities
2515 void pci_d3cold_disable(struct pci_dev *dev)
2517 if (!dev->no_d3cold) {
2518 dev->no_d3cold = true;
2519 pci_bridge_d3_update(dev);
2522 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2525 * pci_pm_init - Initialize PM functions of given PCI device
2526 * @dev: PCI device to handle.
2528 void pci_pm_init(struct pci_dev *dev)
2533 pm_runtime_forbid(&dev->dev);
2534 pm_runtime_set_active(&dev->dev);
2535 pm_runtime_enable(&dev->dev);
2536 device_enable_async_suspend(&dev->dev);
2537 dev->wakeup_prepared = false;
2540 dev->pme_support = 0;
2542 /* find PCI PM capability in list */
2543 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2546 /* Check device's ability to generate PME# */
2547 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2549 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2550 pci_err(dev, "unsupported PM cap regs version (%u)\n",
2551 pmc & PCI_PM_CAP_VER_MASK);
2556 dev->d3_delay = PCI_PM_D3_WAIT;
2557 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2558 dev->bridge_d3 = pci_bridge_d3_possible(dev);
2559 dev->d3cold_allowed = true;
2561 dev->d1_support = false;
2562 dev->d2_support = false;
2563 if (!pci_no_d1d2(dev)) {
2564 if (pmc & PCI_PM_CAP_D1)
2565 dev->d1_support = true;
2566 if (pmc & PCI_PM_CAP_D2)
2567 dev->d2_support = true;
2569 if (dev->d1_support || dev->d2_support)
2570 pci_printk(KERN_DEBUG, dev, "supports%s%s\n",
2571 dev->d1_support ? " D1" : "",
2572 dev->d2_support ? " D2" : "");
2575 pmc &= PCI_PM_CAP_PME_MASK;
2577 pci_printk(KERN_DEBUG, dev, "PME# supported from%s%s%s%s%s\n",
2578 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2579 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2580 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2581 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2582 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2583 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2584 dev->pme_poll = true;
2586 * Make device's PM flags reflect the wake-up capability, but
2587 * let the user space enable it to wake up the system as needed.
2589 device_set_wakeup_capable(&dev->dev, true);
2590 /* Disable the PME# generation functionality */
2591 pci_pme_active(dev, false);
2595 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2597 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
2601 case PCI_EA_P_VF_MEM:
2602 flags |= IORESOURCE_MEM;
2604 case PCI_EA_P_MEM_PREFETCH:
2605 case PCI_EA_P_VF_MEM_PREFETCH:
2606 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2609 flags |= IORESOURCE_IO;
2618 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2621 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2622 return &dev->resource[bei];
2623 #ifdef CONFIG_PCI_IOV
2624 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2625 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2626 return &dev->resource[PCI_IOV_RESOURCES +
2627 bei - PCI_EA_BEI_VF_BAR0];
2629 else if (bei == PCI_EA_BEI_ROM)
2630 return &dev->resource[PCI_ROM_RESOURCE];
2635 /* Read an Enhanced Allocation (EA) entry */
2636 static int pci_ea_read(struct pci_dev *dev, int offset)
2638 struct resource *res;
2639 int ent_size, ent_offset = offset;
2640 resource_size_t start, end;
2641 unsigned long flags;
2642 u32 dw0, bei, base, max_offset;
2644 bool support_64 = (sizeof(resource_size_t) >= 8);
2646 pci_read_config_dword(dev, ent_offset, &dw0);
2649 /* Entry size field indicates DWORDs after 1st */
2650 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2652 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2655 bei = (dw0 & PCI_EA_BEI) >> 4;
2656 prop = (dw0 & PCI_EA_PP) >> 8;
2659 * If the Property is in the reserved range, try the Secondary
2662 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2663 prop = (dw0 & PCI_EA_SP) >> 16;
2664 if (prop > PCI_EA_P_BRIDGE_IO)
2667 res = pci_ea_get_resource(dev, bei, prop);
2669 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
2673 flags = pci_ea_flags(dev, prop);
2675 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
2680 pci_read_config_dword(dev, ent_offset, &base);
2681 start = (base & PCI_EA_FIELD_MASK);
2684 /* Read MaxOffset */
2685 pci_read_config_dword(dev, ent_offset, &max_offset);
2688 /* Read Base MSBs (if 64-bit entry) */
2689 if (base & PCI_EA_IS_64) {
2692 pci_read_config_dword(dev, ent_offset, &base_upper);
2695 flags |= IORESOURCE_MEM_64;
2697 /* entry starts above 32-bit boundary, can't use */
2698 if (!support_64 && base_upper)
2702 start |= ((u64)base_upper << 32);
2705 end = start + (max_offset | 0x03);
2707 /* Read MaxOffset MSBs (if 64-bit entry) */
2708 if (max_offset & PCI_EA_IS_64) {
2709 u32 max_offset_upper;
2711 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2714 flags |= IORESOURCE_MEM_64;
2716 /* entry too big, can't use */
2717 if (!support_64 && max_offset_upper)
2721 end += ((u64)max_offset_upper << 32);
2725 pci_err(dev, "EA Entry crosses address boundary\n");
2729 if (ent_size != ent_offset - offset) {
2730 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
2731 ent_size, ent_offset - offset);
2735 res->name = pci_name(dev);
2740 if (bei <= PCI_EA_BEI_BAR5)
2741 pci_printk(KERN_DEBUG, dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2743 else if (bei == PCI_EA_BEI_ROM)
2744 pci_printk(KERN_DEBUG, dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2746 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2747 pci_printk(KERN_DEBUG, dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2748 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2750 pci_printk(KERN_DEBUG, dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2754 return offset + ent_size;
2757 /* Enhanced Allocation Initialization */
2758 void pci_ea_init(struct pci_dev *dev)
2765 /* find PCI EA capability in list */
2766 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2770 /* determine the number of entries */
2771 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2773 num_ent &= PCI_EA_NUM_ENT_MASK;
2775 offset = ea + PCI_EA_FIRST_ENT;
2777 /* Skip DWORD 2 for type 1 functions */
2778 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2781 /* parse each EA entry */
2782 for (i = 0; i < num_ent; ++i)
2783 offset = pci_ea_read(dev, offset);
2786 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2787 struct pci_cap_saved_state *new_cap)
2789 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2793 * _pci_add_cap_save_buffer - allocate buffer for saving given
2794 * capability registers
2795 * @dev: the PCI device
2796 * @cap: the capability to allocate the buffer for
2797 * @extended: Standard or Extended capability ID
2798 * @size: requested size of the buffer
2800 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2801 bool extended, unsigned int size)
2804 struct pci_cap_saved_state *save_state;
2807 pos = pci_find_ext_capability(dev, cap);
2809 pos = pci_find_capability(dev, cap);
2814 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2818 save_state->cap.cap_nr = cap;
2819 save_state->cap.cap_extended = extended;
2820 save_state->cap.size = size;
2821 pci_add_saved_cap(dev, save_state);
2826 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2828 return _pci_add_cap_save_buffer(dev, cap, false, size);
2831 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2833 return _pci_add_cap_save_buffer(dev, cap, true, size);
2837 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2838 * @dev: the PCI device
2840 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2844 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2845 PCI_EXP_SAVE_REGS * sizeof(u16));
2847 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
2849 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2851 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
2853 pci_allocate_vc_save_buffers(dev);
2856 void pci_free_cap_save_buffers(struct pci_dev *dev)
2858 struct pci_cap_saved_state *tmp;
2859 struct hlist_node *n;
2861 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2866 * pci_configure_ari - enable or disable ARI forwarding
2867 * @dev: the PCI device
2869 * If @dev and its upstream bridge both support ARI, enable ARI in the
2870 * bridge. Otherwise, disable ARI in the bridge.
2872 void pci_configure_ari(struct pci_dev *dev)
2875 struct pci_dev *bridge;
2877 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2880 bridge = dev->bus->self;
2884 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2885 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2888 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2889 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2890 PCI_EXP_DEVCTL2_ARI);
2891 bridge->ari_enabled = 1;
2893 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2894 PCI_EXP_DEVCTL2_ARI);
2895 bridge->ari_enabled = 0;
2899 static int pci_acs_enable;
2902 * pci_request_acs - ask for ACS to be enabled if supported
2904 void pci_request_acs(void)
2910 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2911 * @dev: the PCI device
2913 static void pci_std_enable_acs(struct pci_dev *dev)
2919 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2923 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2924 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2926 /* Source Validation */
2927 ctrl |= (cap & PCI_ACS_SV);
2929 /* P2P Request Redirect */
2930 ctrl |= (cap & PCI_ACS_RR);
2932 /* P2P Completion Redirect */
2933 ctrl |= (cap & PCI_ACS_CR);
2935 /* Upstream Forwarding */
2936 ctrl |= (cap & PCI_ACS_UF);
2938 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2942 * pci_enable_acs - enable ACS if hardware support it
2943 * @dev: the PCI device
2945 void pci_enable_acs(struct pci_dev *dev)
2947 if (!pci_acs_enable)
2950 if (!pci_dev_specific_enable_acs(dev))
2953 pci_std_enable_acs(dev);
2956 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2961 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2966 * Except for egress control, capabilities are either required
2967 * or only required if controllable. Features missing from the
2968 * capability field can therefore be assumed as hard-wired enabled.
2970 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2971 acs_flags &= (cap | PCI_ACS_EC);
2973 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2974 return (ctrl & acs_flags) == acs_flags;
2978 * pci_acs_enabled - test ACS against required flags for a given device
2979 * @pdev: device to test
2980 * @acs_flags: required PCI ACS flags
2982 * Return true if the device supports the provided flags. Automatically
2983 * filters out flags that are not implemented on multifunction devices.
2985 * Note that this interface checks the effective ACS capabilities of the
2986 * device rather than the actual capabilities. For instance, most single
2987 * function endpoints are not required to support ACS because they have no
2988 * opportunity for peer-to-peer access. We therefore return 'true'
2989 * regardless of whether the device exposes an ACS capability. This makes
2990 * it much easier for callers of this function to ignore the actual type
2991 * or topology of the device when testing ACS support.
2993 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2997 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3002 * Conventional PCI and PCI-X devices never support ACS, either
3003 * effectively or actually. The shared bus topology implies that
3004 * any device on the bus can receive or snoop DMA.
3006 if (!pci_is_pcie(pdev))
3009 switch (pci_pcie_type(pdev)) {
3011 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3012 * but since their primary interface is PCI/X, we conservatively
3013 * handle them as we would a non-PCIe device.
3015 case PCI_EXP_TYPE_PCIE_BRIDGE:
3017 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3018 * applicable... must never implement an ACS Extended Capability...".
3019 * This seems arbitrary, but we take a conservative interpretation
3020 * of this statement.
3022 case PCI_EXP_TYPE_PCI_BRIDGE:
3023 case PCI_EXP_TYPE_RC_EC:
3026 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3027 * implement ACS in order to indicate their peer-to-peer capabilities,
3028 * regardless of whether they are single- or multi-function devices.
3030 case PCI_EXP_TYPE_DOWNSTREAM:
3031 case PCI_EXP_TYPE_ROOT_PORT:
3032 return pci_acs_flags_enabled(pdev, acs_flags);
3034 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3035 * implemented by the remaining PCIe types to indicate peer-to-peer
3036 * capabilities, but only when they are part of a multifunction
3037 * device. The footnote for section 6.12 indicates the specific
3038 * PCIe types included here.
3040 case PCI_EXP_TYPE_ENDPOINT:
3041 case PCI_EXP_TYPE_UPSTREAM:
3042 case PCI_EXP_TYPE_LEG_END:
3043 case PCI_EXP_TYPE_RC_END:
3044 if (!pdev->multifunction)
3047 return pci_acs_flags_enabled(pdev, acs_flags);
3051 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3052 * to single function devices with the exception of downstream ports.
3058 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
3059 * @start: starting downstream device
3060 * @end: ending upstream device or NULL to search to the root bus
3061 * @acs_flags: required flags
3063 * Walk up a device tree from start to end testing PCI ACS support. If
3064 * any step along the way does not support the required flags, return false.
3066 bool pci_acs_path_enabled(struct pci_dev *start,
3067 struct pci_dev *end, u16 acs_flags)
3069 struct pci_dev *pdev, *parent = start;
3074 if (!pci_acs_enabled(pdev, acs_flags))
3077 if (pci_is_root_bus(pdev->bus))
3078 return (end == NULL);
3080 parent = pdev->bus->self;
3081 } while (pdev != end);
3087 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3091 * Helper to find the position of the ctrl register for a BAR.
3092 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3093 * Returns -ENOENT if no ctrl register for the BAR could be found.
3095 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3097 unsigned int pos, nbars, i;
3100 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3104 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3105 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3106 PCI_REBAR_CTRL_NBAR_SHIFT;
3108 for (i = 0; i < nbars; i++, pos += 8) {
3111 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3112 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3121 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3123 * @bar: BAR to query
3125 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3126 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3128 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3133 pos = pci_rebar_find_pos(pdev, bar);
3137 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3138 return (cap & PCI_REBAR_CAP_SIZES) >> 4;
3142 * pci_rebar_get_current_size - get the current size of a BAR
3144 * @bar: BAR to set size to
3146 * Read the size of a BAR from the resizable BAR config.
3147 * Returns size if found or negative error code.
3149 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3154 pos = pci_rebar_find_pos(pdev, bar);
3158 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3159 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> 8;
3163 * pci_rebar_set_size - set a new size for a BAR
3165 * @bar: BAR to set size to
3166 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3168 * Set the new size of a BAR as defined in the spec.
3169 * Returns zero if resizing was successful, error code otherwise.
3171 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3176 pos = pci_rebar_find_pos(pdev, bar);
3180 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3181 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3183 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3188 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3189 * @dev: the PCI device
3190 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3191 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3192 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3193 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3195 * Return 0 if all upstream bridges support AtomicOp routing, egress
3196 * blocking is disabled on all upstream ports, and the root port supports
3197 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3198 * AtomicOp completion), or negative otherwise.
3200 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3202 struct pci_bus *bus = dev->bus;
3203 struct pci_dev *bridge;
3206 if (!pci_is_pcie(dev))
3210 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3211 * AtomicOp requesters. For now, we only support endpoints as
3212 * requesters and root ports as completers. No endpoints as
3213 * completers, and no peer-to-peer.
3216 switch (pci_pcie_type(dev)) {
3217 case PCI_EXP_TYPE_ENDPOINT:
3218 case PCI_EXP_TYPE_LEG_END:
3219 case PCI_EXP_TYPE_RC_END:
3225 while (bus->parent) {
3228 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3230 switch (pci_pcie_type(bridge)) {
3231 /* Ensure switch ports support AtomicOp routing */
3232 case PCI_EXP_TYPE_UPSTREAM:
3233 case PCI_EXP_TYPE_DOWNSTREAM:
3234 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3238 /* Ensure root port supports all the sizes we care about */
3239 case PCI_EXP_TYPE_ROOT_PORT:
3240 if ((cap & cap_mask) != cap_mask)
3245 /* Ensure upstream ports don't block AtomicOps on egress */
3246 if (!bridge->has_secondary_link) {
3247 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3249 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3256 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3257 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3260 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3263 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3264 * @dev: the PCI device
3265 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3267 * Perform INTx swizzling for a device behind one level of bridge. This is
3268 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3269 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3270 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3271 * the PCI Express Base Specification, Revision 2.1)
3273 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3277 if (pci_ari_enabled(dev->bus))
3280 slot = PCI_SLOT(dev->devfn);
3282 return (((pin - 1) + slot) % 4) + 1;
3285 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3293 while (!pci_is_root_bus(dev->bus)) {
3294 pin = pci_swizzle_interrupt_pin(dev, pin);
3295 dev = dev->bus->self;
3302 * pci_common_swizzle - swizzle INTx all the way to root bridge
3303 * @dev: the PCI device
3304 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3306 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3307 * bridges all the way up to a PCI root bus.
3309 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3313 while (!pci_is_root_bus(dev->bus)) {
3314 pin = pci_swizzle_interrupt_pin(dev, pin);
3315 dev = dev->bus->self;
3318 return PCI_SLOT(dev->devfn);
3320 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3323 * pci_release_region - Release a PCI bar
3324 * @pdev: PCI device whose resources were previously reserved by pci_request_region
3325 * @bar: BAR to release
3327 * Releases the PCI I/O and memory resources previously reserved by a
3328 * successful call to pci_request_region. Call this function only
3329 * after all use of the PCI regions has ceased.
3331 void pci_release_region(struct pci_dev *pdev, int bar)
3333 struct pci_devres *dr;
3335 if (pci_resource_len(pdev, bar) == 0)
3337 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3338 release_region(pci_resource_start(pdev, bar),
3339 pci_resource_len(pdev, bar));
3340 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3341 release_mem_region(pci_resource_start(pdev, bar),
3342 pci_resource_len(pdev, bar));
3344 dr = find_pci_dr(pdev);
3346 dr->region_mask &= ~(1 << bar);
3348 EXPORT_SYMBOL(pci_release_region);
3351 * __pci_request_region - Reserved PCI I/O and memory resource
3352 * @pdev: PCI device whose resources are to be reserved
3353 * @bar: BAR to be reserved
3354 * @res_name: Name to be associated with resource.
3355 * @exclusive: whether the region access is exclusive or not
3357 * Mark the PCI region associated with PCI device @pdev BR @bar as
3358 * being reserved by owner @res_name. Do not access any
3359 * address inside the PCI regions unless this call returns
3362 * If @exclusive is set, then the region is marked so that userspace
3363 * is explicitly not allowed to map the resource via /dev/mem or
3364 * sysfs MMIO access.
3366 * Returns 0 on success, or %EBUSY on error. A warning
3367 * message is also printed on failure.
3369 static int __pci_request_region(struct pci_dev *pdev, int bar,
3370 const char *res_name, int exclusive)
3372 struct pci_devres *dr;
3374 if (pci_resource_len(pdev, bar) == 0)
3377 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3378 if (!request_region(pci_resource_start(pdev, bar),
3379 pci_resource_len(pdev, bar), res_name))
3381 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3382 if (!__request_mem_region(pci_resource_start(pdev, bar),
3383 pci_resource_len(pdev, bar), res_name,
3388 dr = find_pci_dr(pdev);
3390 dr->region_mask |= 1 << bar;
3395 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3396 &pdev->resource[bar]);
3401 * pci_request_region - Reserve PCI I/O and memory resource
3402 * @pdev: PCI device whose resources are to be reserved
3403 * @bar: BAR to be reserved
3404 * @res_name: Name to be associated with resource
3406 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3407 * being reserved by owner @res_name. Do not access any
3408 * address inside the PCI regions unless this call returns
3411 * Returns 0 on success, or %EBUSY on error. A warning
3412 * message is also printed on failure.
3414 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3416 return __pci_request_region(pdev, bar, res_name, 0);
3418 EXPORT_SYMBOL(pci_request_region);
3421 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3422 * @pdev: PCI device whose resources are to be reserved
3423 * @bar: BAR to be reserved
3424 * @res_name: Name to be associated with resource.
3426 * Mark the PCI region associated with PCI device @pdev BR @bar as
3427 * being reserved by owner @res_name. Do not access any
3428 * address inside the PCI regions unless this call returns
3431 * Returns 0 on success, or %EBUSY on error. A warning
3432 * message is also printed on failure.
3434 * The key difference that _exclusive makes it that userspace is
3435 * explicitly not allowed to map the resource via /dev/mem or
3438 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3439 const char *res_name)
3441 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3443 EXPORT_SYMBOL(pci_request_region_exclusive);
3446 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3447 * @pdev: PCI device whose resources were previously reserved
3448 * @bars: Bitmask of BARs to be released
3450 * Release selected PCI I/O and memory resources previously reserved.
3451 * Call this function only after all use of the PCI regions has ceased.
3453 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3457 for (i = 0; i < 6; i++)
3458 if (bars & (1 << i))
3459 pci_release_region(pdev, i);
3461 EXPORT_SYMBOL(pci_release_selected_regions);
3463 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3464 const char *res_name, int excl)
3468 for (i = 0; i < 6; i++)
3469 if (bars & (1 << i))
3470 if (__pci_request_region(pdev, i, res_name, excl))
3476 if (bars & (1 << i))
3477 pci_release_region(pdev, i);
3484 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3485 * @pdev: PCI device whose resources are to be reserved
3486 * @bars: Bitmask of BARs to be requested
3487 * @res_name: Name to be associated with resource
3489 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3490 const char *res_name)
3492 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3494 EXPORT_SYMBOL(pci_request_selected_regions);
3496 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3497 const char *res_name)
3499 return __pci_request_selected_regions(pdev, bars, res_name,
3500 IORESOURCE_EXCLUSIVE);
3502 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3505 * pci_release_regions - Release reserved PCI I/O and memory resources
3506 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3508 * Releases all PCI I/O and memory resources previously reserved by a
3509 * successful call to pci_request_regions. Call this function only
3510 * after all use of the PCI regions has ceased.
3513 void pci_release_regions(struct pci_dev *pdev)
3515 pci_release_selected_regions(pdev, (1 << 6) - 1);
3517 EXPORT_SYMBOL(pci_release_regions);
3520 * pci_request_regions - Reserved PCI I/O and memory resources
3521 * @pdev: PCI device whose resources are to be reserved
3522 * @res_name: Name to be associated with resource.
3524 * Mark all PCI regions associated with PCI device @pdev as
3525 * being reserved by owner @res_name. Do not access any
3526 * address inside the PCI regions unless this call returns
3529 * Returns 0 on success, or %EBUSY on error. A warning
3530 * message is also printed on failure.
3532 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3534 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3536 EXPORT_SYMBOL(pci_request_regions);
3539 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3540 * @pdev: PCI device whose resources are to be reserved
3541 * @res_name: Name to be associated with resource.
3543 * Mark all PCI regions associated with PCI device @pdev as
3544 * being reserved by owner @res_name. Do not access any
3545 * address inside the PCI regions unless this call returns
3548 * pci_request_regions_exclusive() will mark the region so that
3549 * /dev/mem and the sysfs MMIO access will not be allowed.
3551 * Returns 0 on success, or %EBUSY on error. A warning
3552 * message is also printed on failure.
3554 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3556 return pci_request_selected_regions_exclusive(pdev,
3557 ((1 << 6) - 1), res_name);
3559 EXPORT_SYMBOL(pci_request_regions_exclusive);
3562 * Record the PCI IO range (expressed as CPU physical address + size).
3563 * Return a negative value if an error has occured, zero otherwise
3565 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
3566 resource_size_t size)
3570 struct logic_pio_hwaddr *range;
3572 if (!size || addr + size < addr)
3575 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3579 range->fwnode = fwnode;
3581 range->hw_start = addr;
3582 range->flags = LOGIC_PIO_CPU_MMIO;
3584 ret = logic_pio_register_range(range);
3592 phys_addr_t pci_pio_to_address(unsigned long pio)
3594 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3597 if (pio >= MMIO_UPPER_LIMIT)
3600 address = logic_pio_to_hwaddr(pio);
3606 unsigned long __weak pci_address_to_pio(phys_addr_t address)
3609 return logic_pio_trans_cpuaddr(address);
3611 if (address > IO_SPACE_LIMIT)
3612 return (unsigned long)-1;
3614 return (unsigned long) address;
3619 * pci_remap_iospace - Remap the memory mapped I/O space
3620 * @res: Resource describing the I/O space
3621 * @phys_addr: physical address of range to be mapped
3623 * Remap the memory mapped I/O space described by the @res
3624 * and the CPU physical address @phys_addr into virtual address space.
3625 * Only architectures that have memory mapped IO functions defined
3626 * (and the PCI_IOBASE value defined) should call this function.
3628 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3630 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3631 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3633 if (!(res->flags & IORESOURCE_IO))
3636 if (res->end > IO_SPACE_LIMIT)
3639 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3640 pgprot_device(PAGE_KERNEL));
3642 /* this architecture does not have memory mapped I/O space,
3643 so this function should never be called */
3644 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3648 EXPORT_SYMBOL(pci_remap_iospace);
3651 * pci_unmap_iospace - Unmap the memory mapped I/O space
3652 * @res: resource to be unmapped
3654 * Unmap the CPU virtual address @res from virtual address space.
3655 * Only architectures that have memory mapped IO functions defined
3656 * (and the PCI_IOBASE value defined) should call this function.
3658 void pci_unmap_iospace(struct resource *res)
3660 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3661 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3663 unmap_kernel_range(vaddr, resource_size(res));
3666 EXPORT_SYMBOL(pci_unmap_iospace);
3669 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
3670 * @dev: Generic device to remap IO address for
3671 * @offset: Resource address to map
3672 * @size: Size of map
3674 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
3677 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
3678 resource_size_t offset,
3679 resource_size_t size)
3681 void __iomem **ptr, *addr;
3683 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
3687 addr = pci_remap_cfgspace(offset, size);
3690 devres_add(dev, ptr);
3696 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
3699 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
3700 * @dev: generic device to handle the resource for
3701 * @res: configuration space resource to be handled
3703 * Checks that a resource is a valid memory region, requests the memory
3704 * region and ioremaps with pci_remap_cfgspace() API that ensures the
3705 * proper PCI configuration space memory attributes are guaranteed.
3707 * All operations are managed and will be undone on driver detach.
3709 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
3710 * on failure. Usage example::
3712 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3713 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
3715 * return PTR_ERR(base);
3717 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
3718 struct resource *res)
3720 resource_size_t size;
3722 void __iomem *dest_ptr;
3726 if (!res || resource_type(res) != IORESOURCE_MEM) {
3727 dev_err(dev, "invalid resource\n");
3728 return IOMEM_ERR_PTR(-EINVAL);
3731 size = resource_size(res);
3732 name = res->name ?: dev_name(dev);
3734 if (!devm_request_mem_region(dev, res->start, size, name)) {
3735 dev_err(dev, "can't request region for resource %pR\n", res);
3736 return IOMEM_ERR_PTR(-EBUSY);
3739 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
3741 dev_err(dev, "ioremap failed for resource %pR\n", res);
3742 devm_release_mem_region(dev, res->start, size);
3743 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
3748 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
3750 static void __pci_set_master(struct pci_dev *dev, bool enable)
3754 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3756 cmd = old_cmd | PCI_COMMAND_MASTER;
3758 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3759 if (cmd != old_cmd) {
3760 pci_dbg(dev, "%s bus mastering\n",
3761 enable ? "enabling" : "disabling");
3762 pci_write_config_word(dev, PCI_COMMAND, cmd);
3764 dev->is_busmaster = enable;
3768 * pcibios_setup - process "pci=" kernel boot arguments
3769 * @str: string used to pass in "pci=" kernel boot arguments
3771 * Process kernel boot arguments. This is the default implementation.
3772 * Architecture specific implementations can override this as necessary.
3774 char * __weak __init pcibios_setup(char *str)
3780 * pcibios_set_master - enable PCI bus-mastering for device dev
3781 * @dev: the PCI device to enable
3783 * Enables PCI bus-mastering for the device. This is the default
3784 * implementation. Architecture specific implementations can override
3785 * this if necessary.
3787 void __weak pcibios_set_master(struct pci_dev *dev)
3791 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3792 if (pci_is_pcie(dev))
3795 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
3797 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
3798 else if (lat > pcibios_max_latency)
3799 lat = pcibios_max_latency;
3803 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
3807 * pci_set_master - enables bus-mastering for device dev
3808 * @dev: the PCI device to enable
3810 * Enables bus-mastering on the device and calls pcibios_set_master()
3811 * to do the needed arch specific settings.
3813 void pci_set_master(struct pci_dev *dev)
3815 __pci_set_master(dev, true);
3816 pcibios_set_master(dev);
3818 EXPORT_SYMBOL(pci_set_master);
3821 * pci_clear_master - disables bus-mastering for device dev
3822 * @dev: the PCI device to disable
3824 void pci_clear_master(struct pci_dev *dev)
3826 __pci_set_master(dev, false);
3828 EXPORT_SYMBOL(pci_clear_master);
3831 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3832 * @dev: the PCI device for which MWI is to be enabled
3834 * Helper function for pci_set_mwi.
3835 * Originally copied from drivers/net/acenic.c.
3836 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3838 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3840 int pci_set_cacheline_size(struct pci_dev *dev)
3844 if (!pci_cache_line_size)
3847 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3848 equal to or multiple of the right value. */
3849 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3850 if (cacheline_size >= pci_cache_line_size &&
3851 (cacheline_size % pci_cache_line_size) == 0)
3854 /* Write the correct value. */
3855 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
3857 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3858 if (cacheline_size == pci_cache_line_size)
3861 pci_printk(KERN_DEBUG, dev, "cache line size of %d is not supported\n",
3862 pci_cache_line_size << 2);
3866 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
3869 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3870 * @dev: the PCI device for which MWI is enabled
3872 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3874 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3876 int pci_set_mwi(struct pci_dev *dev)
3878 #ifdef PCI_DISABLE_MWI
3884 rc = pci_set_cacheline_size(dev);
3888 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3889 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
3890 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
3891 cmd |= PCI_COMMAND_INVALIDATE;
3892 pci_write_config_word(dev, PCI_COMMAND, cmd);
3897 EXPORT_SYMBOL(pci_set_mwi);
3900 * pcim_set_mwi - a device-managed pci_set_mwi()
3901 * @dev: the PCI device for which MWI is enabled
3903 * Managed pci_set_mwi().
3905 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3907 int pcim_set_mwi(struct pci_dev *dev)
3909 struct pci_devres *dr;
3911 dr = find_pci_dr(dev);
3916 return pci_set_mwi(dev);
3918 EXPORT_SYMBOL(pcim_set_mwi);
3921 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3922 * @dev: the PCI device for which MWI is enabled
3924 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3925 * Callers are not required to check the return value.
3927 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3929 int pci_try_set_mwi(struct pci_dev *dev)
3931 #ifdef PCI_DISABLE_MWI
3934 return pci_set_mwi(dev);
3937 EXPORT_SYMBOL(pci_try_set_mwi);
3940 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3941 * @dev: the PCI device to disable
3943 * Disables PCI Memory-Write-Invalidate transaction on the device
3945 void pci_clear_mwi(struct pci_dev *dev)
3947 #ifndef PCI_DISABLE_MWI
3950 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3951 if (cmd & PCI_COMMAND_INVALIDATE) {
3952 cmd &= ~PCI_COMMAND_INVALIDATE;
3953 pci_write_config_word(dev, PCI_COMMAND, cmd);
3957 EXPORT_SYMBOL(pci_clear_mwi);
3960 * pci_intx - enables/disables PCI INTx for device dev
3961 * @pdev: the PCI device to operate on
3962 * @enable: boolean: whether to enable or disable PCI INTx
3964 * Enables/disables PCI INTx for device dev
3966 void pci_intx(struct pci_dev *pdev, int enable)
3968 u16 pci_command, new;
3970 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3973 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3975 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3977 if (new != pci_command) {
3978 struct pci_devres *dr;
3980 pci_write_config_word(pdev, PCI_COMMAND, new);
3982 dr = find_pci_dr(pdev);
3983 if (dr && !dr->restore_intx) {
3984 dr->restore_intx = 1;
3985 dr->orig_intx = !enable;
3989 EXPORT_SYMBOL_GPL(pci_intx);
3991 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3993 struct pci_bus *bus = dev->bus;
3994 bool mask_updated = true;
3995 u32 cmd_status_dword;
3996 u16 origcmd, newcmd;
3997 unsigned long flags;
4001 * We do a single dword read to retrieve both command and status.
4002 * Document assumptions that make this possible.
4004 BUILD_BUG_ON(PCI_COMMAND % 4);
4005 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4007 raw_spin_lock_irqsave(&pci_lock, flags);
4009 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4011 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4014 * Check interrupt status register to see whether our device
4015 * triggered the interrupt (when masking) or the next IRQ is
4016 * already pending (when unmasking).
4018 if (mask != irq_pending) {
4019 mask_updated = false;
4023 origcmd = cmd_status_dword;
4024 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4026 newcmd |= PCI_COMMAND_INTX_DISABLE;
4027 if (newcmd != origcmd)
4028 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4031 raw_spin_unlock_irqrestore(&pci_lock, flags);
4033 return mask_updated;
4037 * pci_check_and_mask_intx - mask INTx on pending interrupt
4038 * @dev: the PCI device to operate on
4040 * Check if the device dev has its INTx line asserted, mask it and
4041 * return true in that case. False is returned if no interrupt was
4044 bool pci_check_and_mask_intx(struct pci_dev *dev)
4046 return pci_check_and_set_intx_mask(dev, true);
4048 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4051 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4052 * @dev: the PCI device to operate on
4054 * Check if the device dev has its INTx line asserted, unmask it if not
4055 * and return true. False is returned and the mask remains active if
4056 * there was still an interrupt pending.
4058 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4060 return pci_check_and_set_intx_mask(dev, false);
4062 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4065 * pci_wait_for_pending_transaction - waits for pending transaction
4066 * @dev: the PCI device to operate on
4068 * Return 0 if transaction is pending 1 otherwise.
4070 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4072 if (!pci_is_pcie(dev))
4075 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4076 PCI_EXP_DEVSTA_TRPND);
4078 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4080 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
4086 * After reset, the device should not silently discard config
4087 * requests, but it may still indicate that it needs more time by
4088 * responding to them with CRS completions. The Root Port will
4089 * generally synthesize ~0 data to complete the read (except when
4090 * CRS SV is enabled and the read was for the Vendor ID; in that
4091 * case it synthesizes 0x0001 data).
4093 * Wait for the device to return a non-CRS completion. Read the
4094 * Command register instead of Vendor ID so we don't have to
4095 * contend with the CRS SV value.
4097 pci_read_config_dword(dev, PCI_COMMAND, &id);
4099 if (delay > timeout) {
4100 pci_warn(dev, "not ready %dms after %s; giving up\n",
4101 delay - 1, reset_type);
4106 pci_info(dev, "not ready %dms after %s; waiting\n",
4107 delay - 1, reset_type);
4111 pci_read_config_dword(dev, PCI_COMMAND, &id);
4115 pci_info(dev, "ready %dms after %s\n", delay - 1,
4122 * pcie_has_flr - check if a device supports function level resets
4123 * @dev: device to check
4125 * Returns true if the device advertises support for PCIe function level
4128 static bool pcie_has_flr(struct pci_dev *dev)
4132 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4135 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
4136 return cap & PCI_EXP_DEVCAP_FLR;
4140 * pcie_flr - initiate a PCIe function level reset
4141 * @dev: device to reset
4143 * Initiate a function level reset on @dev. The caller should ensure the
4144 * device supports FLR before calling this function, e.g. by using the
4145 * pcie_has_flr() helper.
4147 int pcie_flr(struct pci_dev *dev)
4149 if (!pci_wait_for_pending_transaction(dev))
4150 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4152 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4155 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4156 * 100ms, but may silently discard requests while the FLR is in
4157 * progress. Wait 100ms before trying to access the device.
4161 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4163 EXPORT_SYMBOL_GPL(pcie_flr);
4165 static int pci_af_flr(struct pci_dev *dev, int probe)
4170 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4174 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4177 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4178 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4185 * Wait for Transaction Pending bit to clear. A word-aligned test
4186 * is used, so we use the conrol offset rather than status and shift
4187 * the test bit to match.
4189 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4190 PCI_AF_STATUS_TP << 8))
4191 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4193 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4196 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4197 * updated 27 July 2006; a device must complete an FLR within
4198 * 100ms, but may silently discard requests while the FLR is in
4199 * progress. Wait 100ms before trying to access the device.
4203 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4207 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4208 * @dev: Device to reset.
4209 * @probe: If set, only check if the device can be reset this way.
4211 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4212 * unset, it will be reinitialized internally when going from PCI_D3hot to
4213 * PCI_D0. If that's the case and the device is not in a low-power state
4214 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4216 * NOTE: This causes the caller to sleep for twice the device power transition
4217 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4218 * by default (i.e. unless the @dev's d3_delay field has a different value).
4219 * Moreover, only devices in D0 can be reset by this function.
4221 static int pci_pm_reset(struct pci_dev *dev, int probe)
4225 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4228 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4229 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4235 if (dev->current_state != PCI_D0)
4238 csr &= ~PCI_PM_CTRL_STATE_MASK;
4240 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4241 pci_dev_d3_sleep(dev);
4243 csr &= ~PCI_PM_CTRL_STATE_MASK;
4245 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4246 pci_dev_d3_sleep(dev);
4248 return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS);
4251 * pcie_wait_for_link - Wait until link is active or inactive
4252 * @pdev: Bridge device
4253 * @active: waiting for active or inactive?
4255 * Use this to wait till link becomes active or inactive.
4257 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4264 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4265 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4274 pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n",
4275 active ? "set" : "cleared");
4280 void pci_reset_secondary_bus(struct pci_dev *dev)
4284 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4285 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4286 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4289 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4290 * this to 2ms to ensure that we meet the minimum requirement.
4294 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
4295 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4298 * Trhfa for conventional PCI is 2^25 clock cycles.
4299 * Assuming a minimum 33MHz clock this results in a 1s
4300 * delay before we can consider subordinate devices to
4301 * be re-initialized. PCIe has some ways to shorten this,
4302 * but we don't make use of them yet.
4307 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4309 pci_reset_secondary_bus(dev);
4313 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
4314 * @dev: Bridge device
4316 * Use the bridge control register to assert reset on the secondary bus.
4317 * Devices on the secondary bus are left in power-on state.
4319 int pci_reset_bridge_secondary_bus(struct pci_dev *dev)
4321 pcibios_reset_secondary_bus(dev);
4323 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
4325 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
4327 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4329 struct pci_dev *pdev;
4331 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4332 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4335 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4342 pci_reset_bridge_secondary_bus(dev->bus->self);
4347 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
4351 if (!hotplug || !try_module_get(hotplug->ops->owner))
4354 if (hotplug->ops->reset_slot)
4355 rc = hotplug->ops->reset_slot(hotplug, probe);
4357 module_put(hotplug->ops->owner);
4362 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
4364 struct pci_dev *pdev;
4366 if (dev->subordinate || !dev->slot ||
4367 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4370 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4371 if (pdev != dev && pdev->slot == dev->slot)
4374 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
4377 static void pci_dev_lock(struct pci_dev *dev)
4379 pci_cfg_access_lock(dev);
4380 /* block PM suspend, driver probe, etc. */
4381 device_lock(&dev->dev);
4384 /* Return 1 on successful lock, 0 on contention */
4385 static int pci_dev_trylock(struct pci_dev *dev)
4387 if (pci_cfg_access_trylock(dev)) {
4388 if (device_trylock(&dev->dev))
4390 pci_cfg_access_unlock(dev);
4396 static void pci_dev_unlock(struct pci_dev *dev)
4398 device_unlock(&dev->dev);
4399 pci_cfg_access_unlock(dev);
4402 static void pci_dev_save_and_disable(struct pci_dev *dev)
4404 const struct pci_error_handlers *err_handler =
4405 dev->driver ? dev->driver->err_handler : NULL;
4408 * dev->driver->err_handler->reset_prepare() is protected against
4409 * races with ->remove() by the device lock, which must be held by
4412 if (err_handler && err_handler->reset_prepare)
4413 err_handler->reset_prepare(dev);
4416 * Wake-up device prior to save. PM registers default to D0 after
4417 * reset and a simple register restore doesn't reliably return
4418 * to a non-D0 state anyway.
4420 pci_set_power_state(dev, PCI_D0);
4422 pci_save_state(dev);
4424 * Disable the device by clearing the Command register, except for
4425 * INTx-disable which is set. This not only disables MMIO and I/O port
4426 * BARs, but also prevents the device from being Bus Master, preventing
4427 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4428 * compliant devices, INTx-disable prevents legacy interrupts.
4430 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4433 static void pci_dev_restore(struct pci_dev *dev)
4435 const struct pci_error_handlers *err_handler =
4436 dev->driver ? dev->driver->err_handler : NULL;
4438 pci_restore_state(dev);
4441 * dev->driver->err_handler->reset_done() is protected against
4442 * races with ->remove() by the device lock, which must be held by
4445 if (err_handler && err_handler->reset_done)
4446 err_handler->reset_done(dev);
4450 * __pci_reset_function_locked - reset a PCI device function while holding
4451 * the @dev mutex lock.
4452 * @dev: PCI device to reset
4454 * Some devices allow an individual function to be reset without affecting
4455 * other functions in the same device. The PCI device must be responsive
4456 * to PCI config space in order to use this function.
4458 * The device function is presumed to be unused and the caller is holding
4459 * the device mutex lock when this function is called.
4460 * Resetting the device will make the contents of PCI configuration space
4461 * random, so any caller of this must be prepared to reinitialise the
4462 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4465 * Returns 0 if the device function was successfully reset or negative if the
4466 * device doesn't support resetting a single function.
4468 int __pci_reset_function_locked(struct pci_dev *dev)
4475 * A reset method returns -ENOTTY if it doesn't support this device
4476 * and we should try the next method.
4478 * If it returns 0 (success), we're finished. If it returns any
4479 * other error, we're also finished: this indicates that further
4480 * reset mechanisms might be broken on the device.
4482 rc = pci_dev_specific_reset(dev, 0);
4485 if (pcie_has_flr(dev)) {
4490 rc = pci_af_flr(dev, 0);
4493 rc = pci_pm_reset(dev, 0);
4496 rc = pci_dev_reset_slot_function(dev, 0);
4499 return pci_parent_bus_reset(dev, 0);
4501 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4504 * pci_probe_reset_function - check whether the device can be safely reset
4505 * @dev: PCI device to reset
4507 * Some devices allow an individual function to be reset without affecting
4508 * other functions in the same device. The PCI device must be responsive
4509 * to PCI config space in order to use this function.
4511 * Returns 0 if the device function can be reset or negative if the
4512 * device doesn't support resetting a single function.
4514 int pci_probe_reset_function(struct pci_dev *dev)
4520 rc = pci_dev_specific_reset(dev, 1);
4523 if (pcie_has_flr(dev))
4525 rc = pci_af_flr(dev, 1);
4528 rc = pci_pm_reset(dev, 1);
4531 rc = pci_dev_reset_slot_function(dev, 1);
4535 return pci_parent_bus_reset(dev, 1);
4539 * pci_reset_function - quiesce and reset a PCI device function
4540 * @dev: PCI device to reset
4542 * Some devices allow an individual function to be reset without affecting
4543 * other functions in the same device. The PCI device must be responsive
4544 * to PCI config space in order to use this function.
4546 * This function does not just reset the PCI portion of a device, but
4547 * clears all the state associated with the device. This function differs
4548 * from __pci_reset_function_locked() in that it saves and restores device state
4549 * over the reset and takes the PCI device lock.
4551 * Returns 0 if the device function was successfully reset or negative if the
4552 * device doesn't support resetting a single function.
4554 int pci_reset_function(struct pci_dev *dev)
4562 pci_dev_save_and_disable(dev);
4564 rc = __pci_reset_function_locked(dev);
4566 pci_dev_restore(dev);
4567 pci_dev_unlock(dev);
4571 EXPORT_SYMBOL_GPL(pci_reset_function);
4574 * pci_reset_function_locked - quiesce and reset a PCI device function
4575 * @dev: PCI device to reset
4577 * Some devices allow an individual function to be reset without affecting
4578 * other functions in the same device. The PCI device must be responsive
4579 * to PCI config space in order to use this function.
4581 * This function does not just reset the PCI portion of a device, but
4582 * clears all the state associated with the device. This function differs
4583 * from __pci_reset_function_locked() in that it saves and restores device state
4584 * over the reset. It also differs from pci_reset_function() in that it
4585 * requires the PCI device lock to be held.
4587 * Returns 0 if the device function was successfully reset or negative if the
4588 * device doesn't support resetting a single function.
4590 int pci_reset_function_locked(struct pci_dev *dev)
4597 pci_dev_save_and_disable(dev);
4599 rc = __pci_reset_function_locked(dev);
4601 pci_dev_restore(dev);
4605 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
4608 * pci_try_reset_function - quiesce and reset a PCI device function
4609 * @dev: PCI device to reset
4611 * Same as above, except return -EAGAIN if unable to lock device.
4613 int pci_try_reset_function(struct pci_dev *dev)
4620 if (!pci_dev_trylock(dev))
4623 pci_dev_save_and_disable(dev);
4624 rc = __pci_reset_function_locked(dev);
4625 pci_dev_restore(dev);
4626 pci_dev_unlock(dev);
4630 EXPORT_SYMBOL_GPL(pci_try_reset_function);
4632 /* Do any devices on or below this bus prevent a bus reset? */
4633 static bool pci_bus_resetable(struct pci_bus *bus)
4635 struct pci_dev *dev;
4638 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4641 list_for_each_entry(dev, &bus->devices, bus_list) {
4642 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4643 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4650 /* Lock devices from the top of the tree down */
4651 static void pci_bus_lock(struct pci_bus *bus)
4653 struct pci_dev *dev;
4655 list_for_each_entry(dev, &bus->devices, bus_list) {
4657 if (dev->subordinate)
4658 pci_bus_lock(dev->subordinate);
4662 /* Unlock devices from the bottom of the tree up */
4663 static void pci_bus_unlock(struct pci_bus *bus)
4665 struct pci_dev *dev;
4667 list_for_each_entry(dev, &bus->devices, bus_list) {
4668 if (dev->subordinate)
4669 pci_bus_unlock(dev->subordinate);
4670 pci_dev_unlock(dev);
4674 /* Return 1 on successful lock, 0 on contention */
4675 static int pci_bus_trylock(struct pci_bus *bus)
4677 struct pci_dev *dev;
4679 list_for_each_entry(dev, &bus->devices, bus_list) {
4680 if (!pci_dev_trylock(dev))
4682 if (dev->subordinate) {
4683 if (!pci_bus_trylock(dev->subordinate)) {
4684 pci_dev_unlock(dev);
4692 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
4693 if (dev->subordinate)
4694 pci_bus_unlock(dev->subordinate);
4695 pci_dev_unlock(dev);
4700 /* Do any devices on or below this slot prevent a bus reset? */
4701 static bool pci_slot_resetable(struct pci_slot *slot)
4703 struct pci_dev *dev;
4705 if (slot->bus->self &&
4706 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4709 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4710 if (!dev->slot || dev->slot != slot)
4712 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4713 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4720 /* Lock devices from the top of the tree down */
4721 static void pci_slot_lock(struct pci_slot *slot)
4723 struct pci_dev *dev;
4725 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4726 if (!dev->slot || dev->slot != slot)
4729 if (dev->subordinate)
4730 pci_bus_lock(dev->subordinate);
4734 /* Unlock devices from the bottom of the tree up */
4735 static void pci_slot_unlock(struct pci_slot *slot)
4737 struct pci_dev *dev;
4739 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4740 if (!dev->slot || dev->slot != slot)
4742 if (dev->subordinate)
4743 pci_bus_unlock(dev->subordinate);
4744 pci_dev_unlock(dev);
4748 /* Return 1 on successful lock, 0 on contention */
4749 static int pci_slot_trylock(struct pci_slot *slot)
4751 struct pci_dev *dev;
4753 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4754 if (!dev->slot || dev->slot != slot)
4756 if (!pci_dev_trylock(dev))
4758 if (dev->subordinate) {
4759 if (!pci_bus_trylock(dev->subordinate)) {
4760 pci_dev_unlock(dev);
4768 list_for_each_entry_continue_reverse(dev,
4769 &slot->bus->devices, bus_list) {
4770 if (!dev->slot || dev->slot != slot)
4772 if (dev->subordinate)
4773 pci_bus_unlock(dev->subordinate);
4774 pci_dev_unlock(dev);
4779 /* Save and disable devices from the top of the tree down */
4780 static void pci_bus_save_and_disable(struct pci_bus *bus)
4782 struct pci_dev *dev;
4784 list_for_each_entry(dev, &bus->devices, bus_list) {
4786 pci_dev_save_and_disable(dev);
4787 pci_dev_unlock(dev);
4788 if (dev->subordinate)
4789 pci_bus_save_and_disable(dev->subordinate);
4794 * Restore devices from top of the tree down - parent bridges need to be
4795 * restored before we can get to subordinate devices.
4797 static void pci_bus_restore(struct pci_bus *bus)
4799 struct pci_dev *dev;
4801 list_for_each_entry(dev, &bus->devices, bus_list) {
4803 pci_dev_restore(dev);
4804 pci_dev_unlock(dev);
4805 if (dev->subordinate)
4806 pci_bus_restore(dev->subordinate);
4810 /* Save and disable devices from the top of the tree down */
4811 static void pci_slot_save_and_disable(struct pci_slot *slot)
4813 struct pci_dev *dev;
4815 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4816 if (!dev->slot || dev->slot != slot)
4818 pci_dev_save_and_disable(dev);
4819 if (dev->subordinate)
4820 pci_bus_save_and_disable(dev->subordinate);
4825 * Restore devices from top of the tree down - parent bridges need to be
4826 * restored before we can get to subordinate devices.
4828 static void pci_slot_restore(struct pci_slot *slot)
4830 struct pci_dev *dev;
4832 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4833 if (!dev->slot || dev->slot != slot)
4836 pci_dev_restore(dev);
4837 pci_dev_unlock(dev);
4838 if (dev->subordinate)
4839 pci_bus_restore(dev->subordinate);
4843 static int pci_slot_reset(struct pci_slot *slot, int probe)
4847 if (!slot || !pci_slot_resetable(slot))
4851 pci_slot_lock(slot);
4855 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
4858 pci_slot_unlock(slot);
4864 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4865 * @slot: PCI slot to probe
4867 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4869 int pci_probe_reset_slot(struct pci_slot *slot)
4871 return pci_slot_reset(slot, 1);
4873 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
4876 * pci_reset_slot - reset a PCI slot
4877 * @slot: PCI slot to reset
4879 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4880 * independent of other slots. For instance, some slots may support slot power
4881 * control. In the case of a 1:1 bus to slot architecture, this function may
4882 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4883 * Generally a slot reset should be attempted before a bus reset. All of the
4884 * function of the slot and any subordinate buses behind the slot are reset
4885 * through this function. PCI config space of all devices in the slot and
4886 * behind the slot is saved before and restored after reset.
4888 * Return 0 on success, non-zero on error.
4890 int pci_reset_slot(struct pci_slot *slot)
4894 rc = pci_slot_reset(slot, 1);
4898 pci_slot_save_and_disable(slot);
4900 rc = pci_slot_reset(slot, 0);
4902 pci_slot_restore(slot);
4906 EXPORT_SYMBOL_GPL(pci_reset_slot);
4909 * pci_try_reset_slot - Try to reset a PCI slot
4910 * @slot: PCI slot to reset
4912 * Same as above except return -EAGAIN if the slot cannot be locked
4914 int pci_try_reset_slot(struct pci_slot *slot)
4918 rc = pci_slot_reset(slot, 1);
4922 pci_slot_save_and_disable(slot);
4924 if (pci_slot_trylock(slot)) {
4926 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
4927 pci_slot_unlock(slot);
4931 pci_slot_restore(slot);
4935 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
4937 static int pci_bus_reset(struct pci_bus *bus, int probe)
4939 if (!bus->self || !pci_bus_resetable(bus))
4949 pci_reset_bridge_secondary_bus(bus->self);
4951 pci_bus_unlock(bus);
4957 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4958 * @bus: PCI bus to probe
4960 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4962 int pci_probe_reset_bus(struct pci_bus *bus)
4964 return pci_bus_reset(bus, 1);
4966 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
4969 * pci_reset_bus - reset a PCI bus
4970 * @bus: top level PCI bus to reset
4972 * Do a bus reset on the given bus and any subordinate buses, saving
4973 * and restoring state of all devices.
4975 * Return 0 on success, non-zero on error.
4977 int pci_reset_bus(struct pci_bus *bus)
4981 rc = pci_bus_reset(bus, 1);
4985 pci_bus_save_and_disable(bus);
4987 rc = pci_bus_reset(bus, 0);
4989 pci_bus_restore(bus);
4993 EXPORT_SYMBOL_GPL(pci_reset_bus);
4996 * pci_try_reset_bus - Try to reset a PCI bus
4997 * @bus: top level PCI bus to reset
4999 * Same as above except return -EAGAIN if the bus cannot be locked
5001 int pci_try_reset_bus(struct pci_bus *bus)
5005 rc = pci_bus_reset(bus, 1);
5009 pci_bus_save_and_disable(bus);
5011 if (pci_bus_trylock(bus)) {
5013 pci_reset_bridge_secondary_bus(bus->self);
5014 pci_bus_unlock(bus);
5018 pci_bus_restore(bus);
5022 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
5025 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5026 * @dev: PCI device to query
5028 * Returns mmrbc: maximum designed memory read count in bytes
5029 * or appropriate error value.
5031 int pcix_get_max_mmrbc(struct pci_dev *dev)
5036 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5040 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5043 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5045 EXPORT_SYMBOL(pcix_get_max_mmrbc);
5048 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5049 * @dev: PCI device to query
5051 * Returns mmrbc: maximum memory read count in bytes
5052 * or appropriate error value.
5054 int pcix_get_mmrbc(struct pci_dev *dev)
5059 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5063 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5066 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5068 EXPORT_SYMBOL(pcix_get_mmrbc);
5071 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5072 * @dev: PCI device to query
5073 * @mmrbc: maximum memory read count in bytes
5074 * valid values are 512, 1024, 2048, 4096
5076 * If possible sets maximum memory read byte count, some bridges have erratas
5077 * that prevent this.
5079 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5085 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5088 v = ffs(mmrbc) - 10;
5090 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5094 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5097 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5100 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5103 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5105 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5108 cmd &= ~PCI_X_CMD_MAX_READ;
5110 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5115 EXPORT_SYMBOL(pcix_set_mmrbc);
5118 * pcie_get_readrq - get PCI Express read request size
5119 * @dev: PCI device to query
5121 * Returns maximum memory read request in bytes
5122 * or appropriate error value.
5124 int pcie_get_readrq(struct pci_dev *dev)
5128 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5130 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5132 EXPORT_SYMBOL(pcie_get_readrq);
5135 * pcie_set_readrq - set PCI Express maximum memory read request
5136 * @dev: PCI device to query
5137 * @rq: maximum memory read count in bytes
5138 * valid values are 128, 256, 512, 1024, 2048, 4096
5140 * If possible sets maximum memory read request in bytes
5142 int pcie_set_readrq(struct pci_dev *dev, int rq)
5146 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5150 * If using the "performance" PCIe config, we clamp the
5151 * read rq size to the max packet size to prevent the
5152 * host bridge generating requests larger than we can
5155 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5156 int mps = pcie_get_mps(dev);
5162 v = (ffs(rq) - 8) << 12;
5164 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5165 PCI_EXP_DEVCTL_READRQ, v);
5167 EXPORT_SYMBOL(pcie_set_readrq);
5170 * pcie_get_mps - get PCI Express maximum payload size
5171 * @dev: PCI device to query
5173 * Returns maximum payload size in bytes
5175 int pcie_get_mps(struct pci_dev *dev)
5179 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5181 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5183 EXPORT_SYMBOL(pcie_get_mps);
5186 * pcie_set_mps - set PCI Express maximum payload size
5187 * @dev: PCI device to query
5188 * @mps: maximum payload size in bytes
5189 * valid values are 128, 256, 512, 1024, 2048, 4096
5191 * If possible sets maximum payload size
5193 int pcie_set_mps(struct pci_dev *dev, int mps)
5197 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
5201 if (v > dev->pcie_mpss)
5205 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5206 PCI_EXP_DEVCTL_PAYLOAD, v);
5208 EXPORT_SYMBOL(pcie_set_mps);
5211 * pcie_bandwidth_available - determine minimum link settings of a PCIe
5212 * device and its bandwidth limitation
5213 * @dev: PCI device to query
5214 * @limiting_dev: storage for device causing the bandwidth limitation
5215 * @speed: storage for speed of limiting device
5216 * @width: storage for width of limiting device
5218 * Walk up the PCI device chain and find the point where the minimum
5219 * bandwidth is available. Return the bandwidth available there and (if
5220 * limiting_dev, speed, and width pointers are supplied) information about
5221 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
5224 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
5225 enum pci_bus_speed *speed,
5226 enum pcie_link_width *width)
5229 enum pci_bus_speed next_speed;
5230 enum pcie_link_width next_width;
5234 *speed = PCI_SPEED_UNKNOWN;
5236 *width = PCIE_LNK_WIDTH_UNKNOWN;
5241 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
5243 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
5244 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
5245 PCI_EXP_LNKSTA_NLW_SHIFT;
5247 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
5249 /* Check if current device limits the total bandwidth */
5250 if (!bw || next_bw <= bw) {
5254 *limiting_dev = dev;
5256 *speed = next_speed;
5258 *width = next_width;
5261 dev = pci_upstream_bridge(dev);
5266 EXPORT_SYMBOL(pcie_bandwidth_available);
5269 * pcie_get_speed_cap - query for the PCI device's link speed capability
5270 * @dev: PCI device to query
5272 * Query the PCI device speed capability. Return the maximum link speed
5273 * supported by the device.
5275 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
5277 u32 lnkcap2, lnkcap;
5280 * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link
5281 * Speeds Vector in Link Capabilities 2 when supported, falling
5282 * back to Max Link Speed in Link Capabilities otherwise.
5284 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
5285 if (lnkcap2) { /* PCIe r3.0-compliant */
5286 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
5287 return PCIE_SPEED_16_0GT;
5288 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
5289 return PCIE_SPEED_8_0GT;
5290 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
5291 return PCIE_SPEED_5_0GT;
5292 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
5293 return PCIE_SPEED_2_5GT;
5294 return PCI_SPEED_UNKNOWN;
5297 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5299 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
5300 return PCIE_SPEED_16_0GT;
5301 else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
5302 return PCIE_SPEED_8_0GT;
5303 else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
5304 return PCIE_SPEED_5_0GT;
5305 else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
5306 return PCIE_SPEED_2_5GT;
5309 return PCI_SPEED_UNKNOWN;
5313 * pcie_get_width_cap - query for the PCI device's link width capability
5314 * @dev: PCI device to query
5316 * Query the PCI device width capability. Return the maximum link width
5317 * supported by the device.
5319 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
5323 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5325 return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
5327 return PCIE_LNK_WIDTH_UNKNOWN;
5331 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
5333 * @speed: storage for link speed
5334 * @width: storage for link width
5336 * Calculate a PCI device's link bandwidth by querying for its link speed
5337 * and width, multiplying them, and applying encoding overhead. The result
5338 * is in Mb/s, i.e., megabits/second of raw bandwidth.
5340 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
5341 enum pcie_link_width *width)
5343 *speed = pcie_get_speed_cap(dev);
5344 *width = pcie_get_width_cap(dev);
5346 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
5349 return *width * PCIE_SPEED2MBS_ENC(*speed);
5353 * pcie_print_link_status - Report the PCI device's link speed and width
5354 * @dev: PCI device to query
5356 * Report the available bandwidth at the device. If this is less than the
5357 * device is capable of, report the device's maximum possible bandwidth and
5358 * the upstream link that limits its performance to less than that.
5360 void pcie_print_link_status(struct pci_dev *dev)
5362 enum pcie_link_width width, width_cap;
5363 enum pci_bus_speed speed, speed_cap;
5364 struct pci_dev *limiting_dev = NULL;
5365 u32 bw_avail, bw_cap;
5367 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
5368 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
5370 if (bw_avail >= bw_cap)
5371 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
5372 bw_cap / 1000, bw_cap % 1000,
5373 PCIE_SPEED2STR(speed_cap), width_cap);
5375 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
5376 bw_avail / 1000, bw_avail % 1000,
5377 PCIE_SPEED2STR(speed), width,
5378 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
5379 bw_cap / 1000, bw_cap % 1000,
5380 PCIE_SPEED2STR(speed_cap), width_cap);
5382 EXPORT_SYMBOL(pcie_print_link_status);
5385 * pci_select_bars - Make BAR mask from the type of resource
5386 * @dev: the PCI device for which BAR mask is made
5387 * @flags: resource type mask to be selected
5389 * This helper routine makes bar mask from the type of resource.
5391 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
5394 for (i = 0; i < PCI_NUM_RESOURCES; i++)
5395 if (pci_resource_flags(dev, i) & flags)
5399 EXPORT_SYMBOL(pci_select_bars);
5401 /* Some architectures require additional programming to enable VGA */
5402 static arch_set_vga_state_t arch_set_vga_state;
5404 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
5406 arch_set_vga_state = func; /* NULL disables */
5409 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
5410 unsigned int command_bits, u32 flags)
5412 if (arch_set_vga_state)
5413 return arch_set_vga_state(dev, decode, command_bits,
5419 * pci_set_vga_state - set VGA decode state on device and parents if requested
5420 * @dev: the PCI device
5421 * @decode: true = enable decoding, false = disable decoding
5422 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
5423 * @flags: traverse ancestors and change bridges
5424 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
5426 int pci_set_vga_state(struct pci_dev *dev, bool decode,
5427 unsigned int command_bits, u32 flags)
5429 struct pci_bus *bus;
5430 struct pci_dev *bridge;
5434 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
5436 /* ARCH specific VGA enables */
5437 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
5441 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
5442 pci_read_config_word(dev, PCI_COMMAND, &cmd);
5444 cmd |= command_bits;
5446 cmd &= ~command_bits;
5447 pci_write_config_word(dev, PCI_COMMAND, cmd);
5450 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
5457 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
5460 cmd |= PCI_BRIDGE_CTL_VGA;
5462 cmd &= ~PCI_BRIDGE_CTL_VGA;
5463 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
5472 * pci_add_dma_alias - Add a DMA devfn alias for a device
5473 * @dev: the PCI device for which alias is added
5474 * @devfn: alias slot and function
5476 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
5477 * It should be called early, preferably as PCI fixup header quirk.
5479 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
5481 if (!dev->dma_alias_mask)
5482 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
5483 sizeof(long), GFP_KERNEL);
5484 if (!dev->dma_alias_mask) {
5485 pci_warn(dev, "Unable to allocate DMA alias mask\n");
5489 set_bit(devfn, dev->dma_alias_mask);
5490 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
5491 PCI_SLOT(devfn), PCI_FUNC(devfn));
5494 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
5496 return (dev1->dma_alias_mask &&
5497 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
5498 (dev2->dma_alias_mask &&
5499 test_bit(dev1->devfn, dev2->dma_alias_mask));
5502 bool pci_device_is_present(struct pci_dev *pdev)
5506 if (pci_dev_is_disconnected(pdev))
5508 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
5510 EXPORT_SYMBOL_GPL(pci_device_is_present);
5512 void pci_ignore_hotplug(struct pci_dev *dev)
5514 struct pci_dev *bridge = dev->bus->self;
5516 dev->ignore_hotplug = 1;
5517 /* Propagate the "ignore hotplug" setting to the parent bridge. */
5519 bridge->ignore_hotplug = 1;
5521 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
5523 resource_size_t __weak pcibios_default_alignment(void)
5528 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
5529 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
5530 static DEFINE_SPINLOCK(resource_alignment_lock);
5533 * pci_specified_resource_alignment - get resource alignment specified by user.
5534 * @dev: the PCI device to get
5535 * @resize: whether or not to change resources' size when reassigning alignment
5537 * RETURNS: Resource alignment if it is specified.
5538 * Zero if it is not specified.
5540 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
5543 int align_order, count;
5544 resource_size_t align = pcibios_default_alignment();
5548 spin_lock(&resource_alignment_lock);
5549 p = resource_alignment_param;
5552 if (pci_has_flag(PCI_PROBE_ONLY)) {
5554 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
5560 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
5567 ret = pci_dev_str_match(dev, p, &p);
5570 if (align_order == -1)
5573 align = 1 << align_order;
5575 } else if (ret < 0) {
5576 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
5581 if (*p != ';' && *p != ',') {
5582 /* End of param or invalid format */
5588 spin_unlock(&resource_alignment_lock);
5592 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
5593 resource_size_t align, bool resize)
5595 struct resource *r = &dev->resource[bar];
5596 resource_size_t size;
5598 if (!(r->flags & IORESOURCE_MEM))
5601 if (r->flags & IORESOURCE_PCI_FIXED) {
5602 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
5603 bar, r, (unsigned long long)align);
5607 size = resource_size(r);
5612 * Increase the alignment of the resource. There are two ways we
5615 * 1) Increase the size of the resource. BARs are aligned on their
5616 * size, so when we reallocate space for this resource, we'll
5617 * allocate it with the larger alignment. This also prevents
5618 * assignment of any other BARs inside the alignment region, so
5619 * if we're requesting page alignment, this means no other BARs
5620 * will share the page.
5622 * The disadvantage is that this makes the resource larger than
5623 * the hardware BAR, which may break drivers that compute things
5624 * based on the resource size, e.g., to find registers at a
5625 * fixed offset before the end of the BAR.
5627 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
5628 * set r->start to the desired alignment. By itself this
5629 * doesn't prevent other BARs being put inside the alignment
5630 * region, but if we realign *every* resource of every device in
5631 * the system, none of them will share an alignment region.
5633 * When the user has requested alignment for only some devices via
5634 * the "pci=resource_alignment" argument, "resize" is true and we
5635 * use the first method. Otherwise we assume we're aligning all
5636 * devices and we use the second.
5639 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
5640 bar, r, (unsigned long long)align);
5646 r->flags &= ~IORESOURCE_SIZEALIGN;
5647 r->flags |= IORESOURCE_STARTALIGN;
5649 r->end = r->start + size - 1;
5651 r->flags |= IORESOURCE_UNSET;
5655 * This function disables memory decoding and releases memory resources
5656 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5657 * It also rounds up size to specified alignment.
5658 * Later on, the kernel will assign page-aligned memory resource back
5661 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
5665 resource_size_t align;
5667 bool resize = false;
5670 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
5671 * 3.4.1.11. Their resources are allocated from the space
5672 * described by the VF BARx register in the PF's SR-IOV capability.
5673 * We can't influence their alignment here.
5678 /* check if specified PCI is target device to reassign */
5679 align = pci_specified_resource_alignment(dev, &resize);
5683 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
5684 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
5685 pci_warn(dev, "Can't reassign resources to host bridge\n");
5689 pci_read_config_word(dev, PCI_COMMAND, &command);
5690 command &= ~PCI_COMMAND_MEMORY;
5691 pci_write_config_word(dev, PCI_COMMAND, command);
5693 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
5694 pci_request_resource_alignment(dev, i, align, resize);
5697 * Need to disable bridge's resource window,
5698 * to enable the kernel to reassign new resource
5701 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
5702 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
5703 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
5704 r = &dev->resource[i];
5705 if (!(r->flags & IORESOURCE_MEM))
5707 r->flags |= IORESOURCE_UNSET;
5708 r->end = resource_size(r) - 1;
5711 pci_disable_bridge_window(dev);
5715 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
5717 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
5718 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
5719 spin_lock(&resource_alignment_lock);
5720 strncpy(resource_alignment_param, buf, count);
5721 resource_alignment_param[count] = '\0';
5722 spin_unlock(&resource_alignment_lock);
5726 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
5729 spin_lock(&resource_alignment_lock);
5730 count = snprintf(buf, size, "%s", resource_alignment_param);
5731 spin_unlock(&resource_alignment_lock);
5735 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
5737 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
5740 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
5741 const char *buf, size_t count)
5743 return pci_set_resource_alignment_param(buf, count);
5746 static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
5747 pci_resource_alignment_store);
5749 static int __init pci_resource_alignment_sysfs_init(void)
5751 return bus_create_file(&pci_bus_type,
5752 &bus_attr_resource_alignment);
5754 late_initcall(pci_resource_alignment_sysfs_init);
5756 static void pci_no_domains(void)
5758 #ifdef CONFIG_PCI_DOMAINS
5759 pci_domains_supported = 0;
5763 #ifdef CONFIG_PCI_DOMAINS_GENERIC
5764 static atomic_t __domain_nr = ATOMIC_INIT(-1);
5766 static int pci_get_new_domain_nr(void)
5768 return atomic_inc_return(&__domain_nr);
5771 static int of_pci_bus_find_domain_nr(struct device *parent)
5773 static int use_dt_domains = -1;
5777 domain = of_get_pci_domain_nr(parent->of_node);
5779 * Check DT domain and use_dt_domains values.
5781 * If DT domain property is valid (domain >= 0) and
5782 * use_dt_domains != 0, the DT assignment is valid since this means
5783 * we have not previously allocated a domain number by using
5784 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5785 * 1, to indicate that we have just assigned a domain number from
5788 * If DT domain property value is not valid (ie domain < 0), and we
5789 * have not previously assigned a domain number from DT
5790 * (use_dt_domains != 1) we should assign a domain number by
5793 * pci_get_new_domain_nr()
5795 * API and update the use_dt_domains value to keep track of method we
5796 * are using to assign domain numbers (use_dt_domains = 0).
5798 * All other combinations imply we have a platform that is trying
5799 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5800 * which is a recipe for domain mishandling and it is prevented by
5801 * invalidating the domain value (domain = -1) and printing a
5802 * corresponding error.
5804 if (domain >= 0 && use_dt_domains) {
5806 } else if (domain < 0 && use_dt_domains != 1) {
5808 domain = pci_get_new_domain_nr();
5811 pr_err("Node %pOF has ", parent->of_node);
5812 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
5819 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
5821 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
5822 acpi_pci_bus_find_domain_nr(bus);
5827 * pci_ext_cfg_avail - can we access extended PCI config space?
5829 * Returns 1 if we can access PCI extended config space (offsets
5830 * greater than 0xff). This is the default implementation. Architecture
5831 * implementations can override this.
5833 int __weak pci_ext_cfg_avail(void)
5838 void __weak pci_fixup_cardbus(struct pci_bus *bus)
5841 EXPORT_SYMBOL(pci_fixup_cardbus);
5843 static int __init pci_setup(char *str)
5846 char *k = strchr(str, ',');
5849 if (*str && (str = pcibios_setup(str)) && *str) {
5850 if (!strcmp(str, "nomsi")) {
5852 } else if (!strncmp(str, "noats", 5)) {
5853 pr_info("PCIe: ATS is disabled\n");
5854 pcie_ats_disabled = true;
5855 } else if (!strcmp(str, "noaer")) {
5857 } else if (!strncmp(str, "realloc=", 8)) {
5858 pci_realloc_get_opt(str + 8);
5859 } else if (!strncmp(str, "realloc", 7)) {
5860 pci_realloc_get_opt("on");
5861 } else if (!strcmp(str, "nodomains")) {
5863 } else if (!strncmp(str, "noari", 5)) {
5864 pcie_ari_disabled = true;
5865 } else if (!strncmp(str, "cbiosize=", 9)) {
5866 pci_cardbus_io_size = memparse(str + 9, &str);
5867 } else if (!strncmp(str, "cbmemsize=", 10)) {
5868 pci_cardbus_mem_size = memparse(str + 10, &str);
5869 } else if (!strncmp(str, "resource_alignment=", 19)) {
5870 pci_set_resource_alignment_param(str + 19,
5872 } else if (!strncmp(str, "ecrc=", 5)) {
5873 pcie_ecrc_get_policy(str + 5);
5874 } else if (!strncmp(str, "hpiosize=", 9)) {
5875 pci_hotplug_io_size = memparse(str + 9, &str);
5876 } else if (!strncmp(str, "hpmemsize=", 10)) {
5877 pci_hotplug_mem_size = memparse(str + 10, &str);
5878 } else if (!strncmp(str, "hpbussize=", 10)) {
5879 pci_hotplug_bus_size =
5880 simple_strtoul(str + 10, &str, 0);
5881 if (pci_hotplug_bus_size > 0xff)
5882 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
5883 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
5884 pcie_bus_config = PCIE_BUS_TUNE_OFF;
5885 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
5886 pcie_bus_config = PCIE_BUS_SAFE;
5887 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
5888 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5889 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
5890 pcie_bus_config = PCIE_BUS_PEER2PEER;
5891 } else if (!strncmp(str, "pcie_scan_all", 13)) {
5892 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
5894 printk(KERN_ERR "PCI: Unknown option `%s'\n",
5902 early_param("pci", pci_setup);