1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
17 #include <linux/of_pci.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pci-ats.h>
33 #include <asm/setup.h>
35 #include <linux/aer.h>
38 DEFINE_MUTEX(pci_slot_mutex);
40 const char *pci_power_names[] = {
41 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
43 EXPORT_SYMBOL_GPL(pci_power_names);
45 int isa_dma_bridge_buggy;
46 EXPORT_SYMBOL(isa_dma_bridge_buggy);
49 EXPORT_SYMBOL(pci_pci_problems);
51 unsigned int pci_pm_d3_delay;
53 static void pci_pme_list_scan(struct work_struct *work);
55 static LIST_HEAD(pci_pme_list);
56 static DEFINE_MUTEX(pci_pme_list_mutex);
57 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
59 struct pci_pme_device {
60 struct list_head list;
64 #define PME_TIMEOUT 1000 /* How long between PME checks */
66 static void pci_dev_d3_sleep(struct pci_dev *dev)
68 unsigned int delay = dev->d3_delay;
70 if (delay < pci_pm_d3_delay)
71 delay = pci_pm_d3_delay;
77 #ifdef CONFIG_PCI_DOMAINS
78 int pci_domains_supported = 1;
81 #define DEFAULT_CARDBUS_IO_SIZE (256)
82 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
83 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
84 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
85 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
87 #define DEFAULT_HOTPLUG_IO_SIZE (256)
88 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
89 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
90 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
91 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
93 #define DEFAULT_HOTPLUG_BUS_SIZE 1
94 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
96 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
99 * The default CLS is used if arch didn't set CLS explicitly and not
100 * all pci devices agree on the same value. Arch can override either
101 * the dfl or actual value as it sees fit. Don't forget this is
102 * measured in 32-bit words, not bytes.
104 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
105 u8 pci_cache_line_size;
108 * If we set up a device for bus mastering, we need to check the latency
109 * timer as certain BIOSes forget to set it properly.
111 unsigned int pcibios_max_latency = 255;
113 /* If set, the PCIe ARI capability will not be used. */
114 static bool pcie_ari_disabled;
116 /* If set, the PCIe ATS capability will not be used. */
117 static bool pcie_ats_disabled;
119 /* If set, the PCI config space of each device is printed during boot. */
122 bool pci_ats_disabled(void)
124 return pcie_ats_disabled;
127 /* Disable bridge_d3 for all PCIe ports */
128 static bool pci_bridge_d3_disable;
129 /* Force bridge_d3 for all PCIe ports */
130 static bool pci_bridge_d3_force;
132 static int __init pcie_port_pm_setup(char *str)
134 if (!strcmp(str, "off"))
135 pci_bridge_d3_disable = true;
136 else if (!strcmp(str, "force"))
137 pci_bridge_d3_force = true;
140 __setup("pcie_port_pm=", pcie_port_pm_setup);
142 /* Time to wait after a reset for device to become responsive */
143 #define PCIE_RESET_READY_POLL_MS 60000
146 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
147 * @bus: pointer to PCI bus structure to search
149 * Given a PCI bus, returns the highest PCI bus number present in the set
150 * including the given PCI bus and its list of child PCI buses.
152 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
155 unsigned char max, n;
157 max = bus->busn_res.end;
158 list_for_each_entry(tmp, &bus->children, node) {
159 n = pci_bus_max_busnr(tmp);
165 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
167 #ifdef CONFIG_HAS_IOMEM
168 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
170 struct resource *res = &pdev->resource[bar];
173 * Make sure the BAR is actually a memory resource, not an IO resource
175 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
176 pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
179 return ioremap_nocache(res->start, resource_size(res));
181 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
183 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
186 * Make sure the BAR is actually a memory resource, not an IO resource
188 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
192 return ioremap_wc(pci_resource_start(pdev, bar),
193 pci_resource_len(pdev, bar));
195 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
199 * pci_dev_str_match_path - test if a path string matches a device
200 * @dev: the PCI device to test
201 * @p: string to match the device against
202 * @endptr: pointer to the string after the match
204 * Test if a string (typically from a kernel parameter) formatted as a
205 * path of device/function addresses matches a PCI device. The string must
208 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
210 * A path for a device can be obtained using 'lspci -t'. Using a path
211 * is more robust against bus renumbering than using only a single bus,
212 * device and function address.
214 * Returns 1 if the string matches the device, 0 if it does not and
215 * a negative error code if it fails to parse the string.
217 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
221 int seg, bus, slot, func;
225 *endptr = strchrnul(path, ';');
227 wpath = kmemdup_nul(path, *endptr - path, GFP_KERNEL);
232 p = strrchr(wpath, '/');
235 ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
241 if (dev->devfn != PCI_DEVFN(slot, func)) {
247 * Note: we don't need to get a reference to the upstream
248 * bridge because we hold a reference to the top level
249 * device which should hold a reference to the bridge,
252 dev = pci_upstream_bridge(dev);
261 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
265 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
272 ret = (seg == pci_domain_nr(dev->bus) &&
273 bus == dev->bus->number &&
274 dev->devfn == PCI_DEVFN(slot, func));
282 * pci_dev_str_match - test if a string matches a device
283 * @dev: the PCI device to test
284 * @p: string to match the device against
285 * @endptr: pointer to the string after the match
287 * Test if a string (typically from a kernel parameter) matches a specified
288 * PCI device. The string may be of one of the following formats:
290 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
291 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
293 * The first format specifies a PCI bus/device/function address which
294 * may change if new hardware is inserted, if motherboard firmware changes,
295 * or due to changes caused in kernel parameters. If the domain is
296 * left unspecified, it is taken to be 0. In order to be robust against
297 * bus renumbering issues, a path of PCI device/function numbers may be used
298 * to address the specific device. The path for a device can be determined
299 * through the use of 'lspci -t'.
301 * The second format matches devices using IDs in the configuration
302 * space which may match multiple devices in the system. A value of 0
303 * for any field will match all devices. (Note: this differs from
304 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
305 * legacy reasons and convenience so users don't have to specify
306 * FFFFFFFFs on the command line.)
308 * Returns 1 if the string matches the device, 0 if it does not and
309 * a negative error code if the string cannot be parsed.
311 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
316 unsigned short vendor, device, subsystem_vendor, subsystem_device;
318 if (strncmp(p, "pci:", 4) == 0) {
319 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
321 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
322 &subsystem_vendor, &subsystem_device, &count);
324 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
328 subsystem_vendor = 0;
329 subsystem_device = 0;
334 if ((!vendor || vendor == dev->vendor) &&
335 (!device || device == dev->device) &&
336 (!subsystem_vendor ||
337 subsystem_vendor == dev->subsystem_vendor) &&
338 (!subsystem_device ||
339 subsystem_device == dev->subsystem_device))
343 * PCI Bus, Device, Function IDs are specified
344 * (optionally, may include a path of devfns following it)
346 ret = pci_dev_str_match_path(dev, p, &p);
361 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
362 u8 pos, int cap, int *ttl)
367 pci_bus_read_config_byte(bus, devfn, pos, &pos);
373 pci_bus_read_config_word(bus, devfn, pos, &ent);
385 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
388 int ttl = PCI_FIND_CAP_TTL;
390 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
393 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
395 return __pci_find_next_cap(dev->bus, dev->devfn,
396 pos + PCI_CAP_LIST_NEXT, cap);
398 EXPORT_SYMBOL_GPL(pci_find_next_capability);
400 static int __pci_bus_find_cap_start(struct pci_bus *bus,
401 unsigned int devfn, u8 hdr_type)
405 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
406 if (!(status & PCI_STATUS_CAP_LIST))
410 case PCI_HEADER_TYPE_NORMAL:
411 case PCI_HEADER_TYPE_BRIDGE:
412 return PCI_CAPABILITY_LIST;
413 case PCI_HEADER_TYPE_CARDBUS:
414 return PCI_CB_CAPABILITY_LIST;
421 * pci_find_capability - query for devices' capabilities
422 * @dev: PCI device to query
423 * @cap: capability code
425 * Tell if a device supports a given PCI capability.
426 * Returns the address of the requested capability structure within the
427 * device's PCI configuration space or 0 in case the device does not
428 * support it. Possible values for @cap:
430 * %PCI_CAP_ID_PM Power Management
431 * %PCI_CAP_ID_AGP Accelerated Graphics Port
432 * %PCI_CAP_ID_VPD Vital Product Data
433 * %PCI_CAP_ID_SLOTID Slot Identification
434 * %PCI_CAP_ID_MSI Message Signalled Interrupts
435 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
436 * %PCI_CAP_ID_PCIX PCI-X
437 * %PCI_CAP_ID_EXP PCI Express
439 int pci_find_capability(struct pci_dev *dev, int cap)
443 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
445 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
449 EXPORT_SYMBOL(pci_find_capability);
452 * pci_bus_find_capability - query for devices' capabilities
453 * @bus: the PCI bus to query
454 * @devfn: PCI device to query
455 * @cap: capability code
457 * Like pci_find_capability() but works for pci devices that do not have a
458 * pci_dev structure set up yet.
460 * Returns the address of the requested capability structure within the
461 * device's PCI configuration space or 0 in case the device does not
464 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
469 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
471 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
473 pos = __pci_find_next_cap(bus, devfn, pos, cap);
477 EXPORT_SYMBOL(pci_bus_find_capability);
480 * pci_find_next_ext_capability - Find an extended capability
481 * @dev: PCI device to query
482 * @start: address at which to start looking (0 to start at beginning of list)
483 * @cap: capability code
485 * Returns the address of the next matching extended capability structure
486 * within the device's PCI configuration space or 0 if the device does
487 * not support it. Some capabilities can occur several times, e.g., the
488 * vendor-specific capability, and this provides a way to find them all.
490 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
494 int pos = PCI_CFG_SPACE_SIZE;
496 /* minimum 8 bytes per capability */
497 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
499 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
505 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
509 * If we have no capabilities, this is indicated by cap ID,
510 * cap version and next pointer all being 0.
516 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
519 pos = PCI_EXT_CAP_NEXT(header);
520 if (pos < PCI_CFG_SPACE_SIZE)
523 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
529 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
532 * pci_find_ext_capability - Find an extended capability
533 * @dev: PCI device to query
534 * @cap: capability code
536 * Returns the address of the requested extended capability structure
537 * within the device's PCI configuration space or 0 if the device does
538 * not support it. Possible values for @cap:
540 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
541 * %PCI_EXT_CAP_ID_VC Virtual Channel
542 * %PCI_EXT_CAP_ID_DSN Device Serial Number
543 * %PCI_EXT_CAP_ID_PWR Power Budgeting
545 int pci_find_ext_capability(struct pci_dev *dev, int cap)
547 return pci_find_next_ext_capability(dev, 0, cap);
549 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
551 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
553 int rc, ttl = PCI_FIND_CAP_TTL;
556 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
557 mask = HT_3BIT_CAP_MASK;
559 mask = HT_5BIT_CAP_MASK;
561 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
562 PCI_CAP_ID_HT, &ttl);
564 rc = pci_read_config_byte(dev, pos + 3, &cap);
565 if (rc != PCIBIOS_SUCCESSFUL)
568 if ((cap & mask) == ht_cap)
571 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
572 pos + PCI_CAP_LIST_NEXT,
573 PCI_CAP_ID_HT, &ttl);
579 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
580 * @dev: PCI device to query
581 * @pos: Position from which to continue searching
582 * @ht_cap: Hypertransport capability code
584 * To be used in conjunction with pci_find_ht_capability() to search for
585 * all capabilities matching @ht_cap. @pos should always be a value returned
586 * from pci_find_ht_capability().
588 * NB. To be 100% safe against broken PCI devices, the caller should take
589 * steps to avoid an infinite loop.
591 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
593 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
595 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
598 * pci_find_ht_capability - query a device's Hypertransport capabilities
599 * @dev: PCI device to query
600 * @ht_cap: Hypertransport capability code
602 * Tell if a device supports a given Hypertransport capability.
603 * Returns an address within the device's PCI configuration space
604 * or 0 in case the device does not support the request capability.
605 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
606 * which has a Hypertransport capability matching @ht_cap.
608 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
612 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
614 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
618 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
621 * pci_find_parent_resource - return resource region of parent bus of given region
622 * @dev: PCI device structure contains resources to be searched
623 * @res: child resource record for which parent is sought
625 * For given resource region of given device, return the resource
626 * region of parent bus the given region is contained in.
628 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
629 struct resource *res)
631 const struct pci_bus *bus = dev->bus;
635 pci_bus_for_each_resource(bus, r, i) {
638 if (resource_contains(r, res)) {
641 * If the window is prefetchable but the BAR is
642 * not, the allocator made a mistake.
644 if (r->flags & IORESOURCE_PREFETCH &&
645 !(res->flags & IORESOURCE_PREFETCH))
649 * If we're below a transparent bridge, there may
650 * be both a positively-decoded aperture and a
651 * subtractively-decoded region that contain the BAR.
652 * We want the positively-decoded one, so this depends
653 * on pci_bus_for_each_resource() giving us those
661 EXPORT_SYMBOL(pci_find_parent_resource);
664 * pci_find_resource - Return matching PCI device resource
665 * @dev: PCI device to query
666 * @res: Resource to look for
668 * Goes over standard PCI resources (BARs) and checks if the given resource
669 * is partially or fully contained in any of them. In that case the
670 * matching resource is returned, %NULL otherwise.
672 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
676 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
677 struct resource *r = &dev->resource[i];
679 if (r->start && resource_contains(r, res))
685 EXPORT_SYMBOL(pci_find_resource);
688 * pci_find_pcie_root_port - return PCIe Root Port
689 * @dev: PCI device to query
691 * Traverse up the parent chain and return the PCIe Root Port PCI Device
692 * for a given PCI Device.
694 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
696 struct pci_dev *bridge, *highest_pcie_bridge = dev;
698 bridge = pci_upstream_bridge(dev);
699 while (bridge && pci_is_pcie(bridge)) {
700 highest_pcie_bridge = bridge;
701 bridge = pci_upstream_bridge(bridge);
704 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
707 return highest_pcie_bridge;
709 EXPORT_SYMBOL(pci_find_pcie_root_port);
712 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
713 * @dev: the PCI device to operate on
714 * @pos: config space offset of status word
715 * @mask: mask of bit(s) to care about in status word
717 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
719 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
723 /* Wait for Transaction Pending bit clean */
724 for (i = 0; i < 4; i++) {
727 msleep((1 << (i - 1)) * 100);
729 pci_read_config_word(dev, pos, &status);
730 if (!(status & mask))
738 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
739 * @dev: PCI device to have its BARs restored
741 * Restore the BAR values for a given device, so as to make it
742 * accessible by its driver.
744 static void pci_restore_bars(struct pci_dev *dev)
748 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
749 pci_update_resource(dev, i);
752 static const struct pci_platform_pm_ops *pci_platform_pm;
754 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
756 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
757 !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
759 pci_platform_pm = ops;
763 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
765 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
768 static inline int platform_pci_set_power_state(struct pci_dev *dev,
771 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
774 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
776 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
779 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
781 return pci_platform_pm ?
782 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
785 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
787 return pci_platform_pm ?
788 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
791 static inline bool platform_pci_need_resume(struct pci_dev *dev)
793 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
797 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
799 * @dev: PCI device to handle.
800 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
803 * -EINVAL if the requested state is invalid.
804 * -EIO if device does not support PCI PM or its PM capabilities register has a
805 * wrong version, or device doesn't support the requested state.
806 * 0 if device already is in the requested state.
807 * 0 if device's power state has been successfully changed.
809 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
812 bool need_restore = false;
814 /* Check if we're already there */
815 if (dev->current_state == state)
821 if (state < PCI_D0 || state > PCI_D3hot)
824 /* Validate current state:
825 * Can enter D0 from any state, but if we can only go deeper
826 * to sleep if we're already in a low power state
828 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
829 && dev->current_state > state) {
830 pci_err(dev, "invalid power transition (from state %d to %d)\n",
831 dev->current_state, state);
835 /* check if this device supports the desired state */
836 if ((state == PCI_D1 && !dev->d1_support)
837 || (state == PCI_D2 && !dev->d2_support))
840 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
842 /* If we're (effectively) in D3, force entire word to 0.
843 * This doesn't affect PME_Status, disables PME_En, and
844 * sets PowerState to 0.
846 switch (dev->current_state) {
850 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
855 case PCI_UNKNOWN: /* Boot-up */
856 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
857 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
859 /* Fall-through: force to D0 */
865 /* enter specified state */
866 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
868 /* Mandatory power management transition delays */
869 /* see PCI PM 1.1 5.6.1 table 18 */
870 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
871 pci_dev_d3_sleep(dev);
872 else if (state == PCI_D2 || dev->current_state == PCI_D2)
873 udelay(PCI_PM_D2_DELAY);
875 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
876 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
877 if (dev->current_state != state && printk_ratelimit())
878 pci_info(dev, "Refused to change power state, currently in D%d\n",
882 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
883 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
884 * from D3hot to D0 _may_ perform an internal reset, thereby
885 * going to "D0 Uninitialized" rather than "D0 Initialized".
886 * For example, at least some versions of the 3c905B and the
887 * 3c556B exhibit this behaviour.
889 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
890 * devices in a D3hot state at boot. Consequently, we need to
891 * restore at least the BARs so that the device will be
892 * accessible to its driver.
895 pci_restore_bars(dev);
898 pcie_aspm_pm_state_change(dev->bus->self);
904 * pci_update_current_state - Read power state of given device and cache it
905 * @dev: PCI device to handle.
906 * @state: State to cache in case the device doesn't have the PM capability
908 * The power state is read from the PMCSR register, which however is
909 * inaccessible in D3cold. The platform firmware is therefore queried first
910 * to detect accessibility of the register. In case the platform firmware
911 * reports an incorrect state or the device isn't power manageable by the
912 * platform at all, we try to detect D3cold by testing accessibility of the
913 * vendor ID in config space.
915 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
917 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
918 !pci_device_is_present(dev)) {
919 dev->current_state = PCI_D3cold;
920 } else if (dev->pm_cap) {
923 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
924 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
926 dev->current_state = state;
931 * pci_power_up - Put the given device into D0 forcibly
932 * @dev: PCI device to power up
934 void pci_power_up(struct pci_dev *dev)
936 if (platform_pci_power_manageable(dev))
937 platform_pci_set_power_state(dev, PCI_D0);
939 pci_raw_set_power_state(dev, PCI_D0);
940 pci_update_current_state(dev, PCI_D0);
944 * pci_platform_power_transition - Use platform to change device power state
945 * @dev: PCI device to handle.
946 * @state: State to put the device into.
948 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
952 if (platform_pci_power_manageable(dev)) {
953 error = platform_pci_set_power_state(dev, state);
955 pci_update_current_state(dev, state);
959 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
960 dev->current_state = PCI_D0;
966 * pci_wakeup - Wake up a PCI device
967 * @pci_dev: Device to handle.
968 * @ign: ignored parameter
970 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
972 pci_wakeup_event(pci_dev);
973 pm_request_resume(&pci_dev->dev);
978 * pci_wakeup_bus - Walk given bus and wake up devices on it
979 * @bus: Top bus of the subtree to walk.
981 void pci_wakeup_bus(struct pci_bus *bus)
984 pci_walk_bus(bus, pci_wakeup, NULL);
988 * __pci_start_power_transition - Start power transition of a PCI device
989 * @dev: PCI device to handle.
990 * @state: State to put the device into.
992 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
994 if (state == PCI_D0) {
995 pci_platform_power_transition(dev, PCI_D0);
997 * Mandatory power management transition delays, see
998 * PCI Express Base Specification Revision 2.0 Section
999 * 6.6.1: Conventional Reset. Do not delay for
1000 * devices powered on/off by corresponding bridge,
1001 * because have already delayed for the bridge.
1003 if (dev->runtime_d3cold) {
1004 if (dev->d3cold_delay)
1005 msleep(dev->d3cold_delay);
1007 * When powering on a bridge from D3cold, the
1008 * whole hierarchy may be powered on into
1009 * D0uninitialized state, resume them to give
1010 * them a chance to suspend again
1012 pci_wakeup_bus(dev->subordinate);
1018 * __pci_dev_set_current_state - Set current state of a PCI device
1019 * @dev: Device to handle
1020 * @data: pointer to state to be set
1022 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1024 pci_power_t state = *(pci_power_t *)data;
1026 dev->current_state = state;
1031 * pci_bus_set_current_state - Walk given bus and set current state of devices
1032 * @bus: Top bus of the subtree to walk.
1033 * @state: state to be set
1035 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1038 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1042 * __pci_complete_power_transition - Complete power transition of a PCI device
1043 * @dev: PCI device to handle.
1044 * @state: State to put the device into.
1046 * This function should not be called directly by device drivers.
1048 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
1052 if (state <= PCI_D0)
1054 ret = pci_platform_power_transition(dev, state);
1055 /* Power off the bridge may power off the whole hierarchy */
1056 if (!ret && state == PCI_D3cold)
1057 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1060 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
1063 * pci_set_power_state - Set the power state of a PCI device
1064 * @dev: PCI device to handle.
1065 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1067 * Transition a device to a new power state, using the platform firmware and/or
1068 * the device's PCI PM registers.
1071 * -EINVAL if the requested state is invalid.
1072 * -EIO if device does not support PCI PM or its PM capabilities register has a
1073 * wrong version, or device doesn't support the requested state.
1074 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1075 * 0 if device already is in the requested state.
1076 * 0 if the transition is to D3 but D3 is not supported.
1077 * 0 if device's power state has been successfully changed.
1079 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1083 /* bound the state we're entering */
1084 if (state > PCI_D3cold)
1086 else if (state < PCI_D0)
1088 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1090 * If the device or the parent bridge do not support PCI PM,
1091 * ignore the request if we're doing anything other than putting
1092 * it into D0 (which would only happen on boot).
1096 /* Check if we're already there */
1097 if (dev->current_state == state)
1100 __pci_start_power_transition(dev, state);
1102 /* This device is quirked not to be put into D3, so
1103 don't put it in D3 */
1104 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1108 * To put device in D3cold, we put device into D3hot in native
1109 * way, then put device into D3cold with platform ops
1111 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
1114 if (!__pci_complete_power_transition(dev, state))
1119 EXPORT_SYMBOL(pci_set_power_state);
1122 * pci_choose_state - Choose the power state of a PCI device
1123 * @dev: PCI device to be suspended
1124 * @state: target sleep state for the whole system. This is the value
1125 * that is passed to suspend() function.
1127 * Returns PCI power state suitable for given device and given system
1131 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
1138 ret = platform_pci_choose_state(dev);
1139 if (ret != PCI_POWER_ERROR)
1142 switch (state.event) {
1145 case PM_EVENT_FREEZE:
1146 case PM_EVENT_PRETHAW:
1147 /* REVISIT both freeze and pre-thaw "should" use D0 */
1148 case PM_EVENT_SUSPEND:
1149 case PM_EVENT_HIBERNATE:
1152 pci_info(dev, "unrecognized suspend event %d\n",
1158 EXPORT_SYMBOL(pci_choose_state);
1160 #define PCI_EXP_SAVE_REGS 7
1162 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1163 u16 cap, bool extended)
1165 struct pci_cap_saved_state *tmp;
1167 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1168 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1174 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1176 return _pci_find_saved_cap(dev, cap, false);
1179 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1181 return _pci_find_saved_cap(dev, cap, true);
1184 static int pci_save_pcie_state(struct pci_dev *dev)
1187 struct pci_cap_saved_state *save_state;
1190 if (!pci_is_pcie(dev))
1193 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1195 pci_err(dev, "buffer not found in %s\n", __func__);
1199 cap = (u16 *)&save_state->cap.data[0];
1200 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1201 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1202 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1203 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1204 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1205 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1206 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1211 static void pci_restore_pcie_state(struct pci_dev *dev)
1214 struct pci_cap_saved_state *save_state;
1217 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1221 cap = (u16 *)&save_state->cap.data[0];
1222 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1223 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1224 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1225 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1226 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1227 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1228 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1232 static int pci_save_pcix_state(struct pci_dev *dev)
1235 struct pci_cap_saved_state *save_state;
1237 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1241 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1243 pci_err(dev, "buffer not found in %s\n", __func__);
1247 pci_read_config_word(dev, pos + PCI_X_CMD,
1248 (u16 *)save_state->cap.data);
1253 static void pci_restore_pcix_state(struct pci_dev *dev)
1256 struct pci_cap_saved_state *save_state;
1259 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1260 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1261 if (!save_state || !pos)
1263 cap = (u16 *)&save_state->cap.data[0];
1265 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1270 * pci_save_state - save the PCI configuration space of a device before suspending
1271 * @dev: - PCI device that we're dealing with
1273 int pci_save_state(struct pci_dev *dev)
1276 /* XXX: 100% dword access ok here? */
1277 for (i = 0; i < 16; i++)
1278 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1279 dev->state_saved = true;
1281 i = pci_save_pcie_state(dev);
1285 i = pci_save_pcix_state(dev);
1289 pci_save_dpc_state(dev);
1290 return pci_save_vc_state(dev);
1292 EXPORT_SYMBOL(pci_save_state);
1294 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1295 u32 saved_val, int retry)
1299 pci_read_config_dword(pdev, offset, &val);
1300 if (val == saved_val)
1304 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1305 offset, val, saved_val);
1306 pci_write_config_dword(pdev, offset, saved_val);
1310 pci_read_config_dword(pdev, offset, &val);
1311 if (val == saved_val)
1318 static void pci_restore_config_space_range(struct pci_dev *pdev,
1319 int start, int end, int retry)
1323 for (index = end; index >= start; index--)
1324 pci_restore_config_dword(pdev, 4 * index,
1325 pdev->saved_config_space[index],
1329 static void pci_restore_config_space(struct pci_dev *pdev)
1331 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1332 pci_restore_config_space_range(pdev, 10, 15, 0);
1333 /* Restore BARs before the command register. */
1334 pci_restore_config_space_range(pdev, 4, 9, 10);
1335 pci_restore_config_space_range(pdev, 0, 3, 0);
1337 pci_restore_config_space_range(pdev, 0, 15, 0);
1341 static void pci_restore_rebar_state(struct pci_dev *pdev)
1343 unsigned int pos, nbars, i;
1346 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1350 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1351 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
1352 PCI_REBAR_CTRL_NBAR_SHIFT;
1354 for (i = 0; i < nbars; i++, pos += 8) {
1355 struct resource *res;
1358 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1359 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1360 res = pdev->resource + bar_idx;
1361 size = order_base_2((resource_size(res) >> 20) | 1) - 1;
1362 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1363 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
1364 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1369 * pci_restore_state - Restore the saved state of a PCI device
1370 * @dev: - PCI device that we're dealing with
1372 void pci_restore_state(struct pci_dev *dev)
1374 if (!dev->state_saved)
1377 /* PCI Express register must be restored first */
1378 pci_restore_pcie_state(dev);
1379 pci_restore_pasid_state(dev);
1380 pci_restore_pri_state(dev);
1381 pci_restore_ats_state(dev);
1382 pci_restore_vc_state(dev);
1383 pci_restore_rebar_state(dev);
1384 pci_restore_dpc_state(dev);
1386 pci_cleanup_aer_error_status_regs(dev);
1388 pci_restore_config_space(dev);
1390 pci_restore_pcix_state(dev);
1391 pci_restore_msi_state(dev);
1393 /* Restore ACS and IOV configuration state */
1394 pci_enable_acs(dev);
1395 pci_restore_iov_state(dev);
1397 dev->state_saved = false;
1399 EXPORT_SYMBOL(pci_restore_state);
1401 struct pci_saved_state {
1402 u32 config_space[16];
1403 struct pci_cap_saved_data cap[0];
1407 * pci_store_saved_state - Allocate and return an opaque struct containing
1408 * the device saved state.
1409 * @dev: PCI device that we're dealing with
1411 * Return NULL if no state or error.
1413 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1415 struct pci_saved_state *state;
1416 struct pci_cap_saved_state *tmp;
1417 struct pci_cap_saved_data *cap;
1420 if (!dev->state_saved)
1423 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1425 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1426 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1428 state = kzalloc(size, GFP_KERNEL);
1432 memcpy(state->config_space, dev->saved_config_space,
1433 sizeof(state->config_space));
1436 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1437 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1438 memcpy(cap, &tmp->cap, len);
1439 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1441 /* Empty cap_save terminates list */
1445 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1448 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1449 * @dev: PCI device that we're dealing with
1450 * @state: Saved state returned from pci_store_saved_state()
1452 int pci_load_saved_state(struct pci_dev *dev,
1453 struct pci_saved_state *state)
1455 struct pci_cap_saved_data *cap;
1457 dev->state_saved = false;
1462 memcpy(dev->saved_config_space, state->config_space,
1463 sizeof(state->config_space));
1467 struct pci_cap_saved_state *tmp;
1469 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1470 if (!tmp || tmp->cap.size != cap->size)
1473 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1474 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1475 sizeof(struct pci_cap_saved_data) + cap->size);
1478 dev->state_saved = true;
1481 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1484 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1485 * and free the memory allocated for it.
1486 * @dev: PCI device that we're dealing with
1487 * @state: Pointer to saved state returned from pci_store_saved_state()
1489 int pci_load_and_free_saved_state(struct pci_dev *dev,
1490 struct pci_saved_state **state)
1492 int ret = pci_load_saved_state(dev, *state);
1497 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1499 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1501 return pci_enable_resources(dev, bars);
1504 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1507 struct pci_dev *bridge;
1511 err = pci_set_power_state(dev, PCI_D0);
1512 if (err < 0 && err != -EIO)
1515 bridge = pci_upstream_bridge(dev);
1517 pcie_aspm_powersave_config_link(bridge);
1519 err = pcibios_enable_device(dev, bars);
1522 pci_fixup_device(pci_fixup_enable, dev);
1524 if (dev->msi_enabled || dev->msix_enabled)
1527 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1529 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1530 if (cmd & PCI_COMMAND_INTX_DISABLE)
1531 pci_write_config_word(dev, PCI_COMMAND,
1532 cmd & ~PCI_COMMAND_INTX_DISABLE);
1539 * pci_reenable_device - Resume abandoned device
1540 * @dev: PCI device to be resumed
1542 * Note this function is a backend of pci_default_resume and is not supposed
1543 * to be called by normal code, write proper resume handler and use it instead.
1545 int pci_reenable_device(struct pci_dev *dev)
1547 if (pci_is_enabled(dev))
1548 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1551 EXPORT_SYMBOL(pci_reenable_device);
1553 static void pci_enable_bridge(struct pci_dev *dev)
1555 struct pci_dev *bridge;
1558 bridge = pci_upstream_bridge(dev);
1560 pci_enable_bridge(bridge);
1562 if (pci_is_enabled(dev)) {
1563 if (!dev->is_busmaster)
1564 pci_set_master(dev);
1568 retval = pci_enable_device(dev);
1570 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1572 pci_set_master(dev);
1575 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1577 struct pci_dev *bridge;
1582 * Power state could be unknown at this point, either due to a fresh
1583 * boot or a device removal call. So get the current power state
1584 * so that things like MSI message writing will behave as expected
1585 * (e.g. if the device really is in D0 at enable time).
1589 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1590 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1593 if (atomic_inc_return(&dev->enable_cnt) > 1)
1594 return 0; /* already enabled */
1596 bridge = pci_upstream_bridge(dev);
1598 pci_enable_bridge(bridge);
1600 /* only skip sriov related */
1601 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1602 if (dev->resource[i].flags & flags)
1604 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1605 if (dev->resource[i].flags & flags)
1608 err = do_pci_enable_device(dev, bars);
1610 atomic_dec(&dev->enable_cnt);
1615 * pci_enable_device_io - Initialize a device for use with IO space
1616 * @dev: PCI device to be initialized
1618 * Initialize device before it's used by a driver. Ask low-level code
1619 * to enable I/O resources. Wake up the device if it was suspended.
1620 * Beware, this function can fail.
1622 int pci_enable_device_io(struct pci_dev *dev)
1624 return pci_enable_device_flags(dev, IORESOURCE_IO);
1626 EXPORT_SYMBOL(pci_enable_device_io);
1629 * pci_enable_device_mem - Initialize a device for use with Memory space
1630 * @dev: PCI device to be initialized
1632 * Initialize device before it's used by a driver. Ask low-level code
1633 * to enable Memory resources. Wake up the device if it was suspended.
1634 * Beware, this function can fail.
1636 int pci_enable_device_mem(struct pci_dev *dev)
1638 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1640 EXPORT_SYMBOL(pci_enable_device_mem);
1643 * pci_enable_device - Initialize device before it's used by a driver.
1644 * @dev: PCI device to be initialized
1646 * Initialize device before it's used by a driver. Ask low-level code
1647 * to enable I/O and memory. Wake up the device if it was suspended.
1648 * Beware, this function can fail.
1650 * Note we don't actually enable the device many times if we call
1651 * this function repeatedly (we just increment the count).
1653 int pci_enable_device(struct pci_dev *dev)
1655 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1657 EXPORT_SYMBOL(pci_enable_device);
1660 * Managed PCI resources. This manages device on/off, intx/msi/msix
1661 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1662 * there's no need to track it separately. pci_devres is initialized
1663 * when a device is enabled using managed PCI device enable interface.
1666 unsigned int enabled:1;
1667 unsigned int pinned:1;
1668 unsigned int orig_intx:1;
1669 unsigned int restore_intx:1;
1674 static void pcim_release(struct device *gendev, void *res)
1676 struct pci_dev *dev = to_pci_dev(gendev);
1677 struct pci_devres *this = res;
1680 if (dev->msi_enabled)
1681 pci_disable_msi(dev);
1682 if (dev->msix_enabled)
1683 pci_disable_msix(dev);
1685 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1686 if (this->region_mask & (1 << i))
1687 pci_release_region(dev, i);
1692 if (this->restore_intx)
1693 pci_intx(dev, this->orig_intx);
1695 if (this->enabled && !this->pinned)
1696 pci_disable_device(dev);
1699 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1701 struct pci_devres *dr, *new_dr;
1703 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1707 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1710 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1713 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1715 if (pci_is_managed(pdev))
1716 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1721 * pcim_enable_device - Managed pci_enable_device()
1722 * @pdev: PCI device to be initialized
1724 * Managed pci_enable_device().
1726 int pcim_enable_device(struct pci_dev *pdev)
1728 struct pci_devres *dr;
1731 dr = get_pci_dr(pdev);
1737 rc = pci_enable_device(pdev);
1739 pdev->is_managed = 1;
1744 EXPORT_SYMBOL(pcim_enable_device);
1747 * pcim_pin_device - Pin managed PCI device
1748 * @pdev: PCI device to pin
1750 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1751 * driver detach. @pdev must have been enabled with
1752 * pcim_enable_device().
1754 void pcim_pin_device(struct pci_dev *pdev)
1756 struct pci_devres *dr;
1758 dr = find_pci_dr(pdev);
1759 WARN_ON(!dr || !dr->enabled);
1763 EXPORT_SYMBOL(pcim_pin_device);
1766 * pcibios_add_device - provide arch specific hooks when adding device dev
1767 * @dev: the PCI device being added
1769 * Permits the platform to provide architecture specific functionality when
1770 * devices are added. This is the default implementation. Architecture
1771 * implementations can override this.
1773 int __weak pcibios_add_device(struct pci_dev *dev)
1779 * pcibios_release_device - provide arch specific hooks when releasing device dev
1780 * @dev: the PCI device being released
1782 * Permits the platform to provide architecture specific functionality when
1783 * devices are released. This is the default implementation. Architecture
1784 * implementations can override this.
1786 void __weak pcibios_release_device(struct pci_dev *dev) {}
1789 * pcibios_disable_device - disable arch specific PCI resources for device dev
1790 * @dev: the PCI device to disable
1792 * Disables architecture specific PCI resources for the device. This
1793 * is the default implementation. Architecture implementations can
1796 void __weak pcibios_disable_device(struct pci_dev *dev) {}
1799 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1800 * @irq: ISA IRQ to penalize
1801 * @active: IRQ active or not
1803 * Permits the platform to provide architecture-specific functionality when
1804 * penalizing ISA IRQs. This is the default implementation. Architecture
1805 * implementations can override this.
1807 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1809 static void do_pci_disable_device(struct pci_dev *dev)
1813 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1814 if (pci_command & PCI_COMMAND_MASTER) {
1815 pci_command &= ~PCI_COMMAND_MASTER;
1816 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1819 pcibios_disable_device(dev);
1823 * pci_disable_enabled_device - Disable device without updating enable_cnt
1824 * @dev: PCI device to disable
1826 * NOTE: This function is a backend of PCI power management routines and is
1827 * not supposed to be called drivers.
1829 void pci_disable_enabled_device(struct pci_dev *dev)
1831 if (pci_is_enabled(dev))
1832 do_pci_disable_device(dev);
1836 * pci_disable_device - Disable PCI device after use
1837 * @dev: PCI device to be disabled
1839 * Signal to the system that the PCI device is not in use by the system
1840 * anymore. This only involves disabling PCI bus-mastering, if active.
1842 * Note we don't actually disable the device until all callers of
1843 * pci_enable_device() have called pci_disable_device().
1845 void pci_disable_device(struct pci_dev *dev)
1847 struct pci_devres *dr;
1849 dr = find_pci_dr(dev);
1853 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1854 "disabling already-disabled device");
1856 if (atomic_dec_return(&dev->enable_cnt) != 0)
1859 do_pci_disable_device(dev);
1861 dev->is_busmaster = 0;
1863 EXPORT_SYMBOL(pci_disable_device);
1866 * pcibios_set_pcie_reset_state - set reset state for device dev
1867 * @dev: the PCIe device reset
1868 * @state: Reset state to enter into
1871 * Sets the PCIe reset state for the device. This is the default
1872 * implementation. Architecture implementations can override this.
1874 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1875 enum pcie_reset_state state)
1881 * pci_set_pcie_reset_state - set reset state for device dev
1882 * @dev: the PCIe device reset
1883 * @state: Reset state to enter into
1886 * Sets the PCI reset state for the device.
1888 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1890 return pcibios_set_pcie_reset_state(dev, state);
1892 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1895 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
1896 * @dev: PCIe root port or event collector.
1898 void pcie_clear_root_pme_status(struct pci_dev *dev)
1900 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
1904 * pci_check_pme_status - Check if given device has generated PME.
1905 * @dev: Device to check.
1907 * Check the PME status of the device and if set, clear it and clear PME enable
1908 * (if set). Return 'true' if PME status and PME enable were both set or
1909 * 'false' otherwise.
1911 bool pci_check_pme_status(struct pci_dev *dev)
1920 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1921 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1922 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1925 /* Clear PME status. */
1926 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1927 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1928 /* Disable PME to avoid interrupt flood. */
1929 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1933 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1939 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1940 * @dev: Device to handle.
1941 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1943 * Check if @dev has generated PME and queue a resume request for it in that
1946 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1948 if (pme_poll_reset && dev->pme_poll)
1949 dev->pme_poll = false;
1951 if (pci_check_pme_status(dev)) {
1952 pci_wakeup_event(dev);
1953 pm_request_resume(&dev->dev);
1959 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1960 * @bus: Top bus of the subtree to walk.
1962 void pci_pme_wakeup_bus(struct pci_bus *bus)
1965 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1970 * pci_pme_capable - check the capability of PCI device to generate PME#
1971 * @dev: PCI device to handle.
1972 * @state: PCI state from which device will issue PME#.
1974 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1979 return !!(dev->pme_support & (1 << state));
1981 EXPORT_SYMBOL(pci_pme_capable);
1983 static void pci_pme_list_scan(struct work_struct *work)
1985 struct pci_pme_device *pme_dev, *n;
1987 mutex_lock(&pci_pme_list_mutex);
1988 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1989 if (pme_dev->dev->pme_poll) {
1990 struct pci_dev *bridge;
1992 bridge = pme_dev->dev->bus->self;
1994 * If bridge is in low power state, the
1995 * configuration space of subordinate devices
1996 * may be not accessible
1998 if (bridge && bridge->current_state != PCI_D0)
2000 pci_pme_wakeup(pme_dev->dev, NULL);
2002 list_del(&pme_dev->list);
2006 if (!list_empty(&pci_pme_list))
2007 queue_delayed_work(system_freezable_wq, &pci_pme_work,
2008 msecs_to_jiffies(PME_TIMEOUT));
2009 mutex_unlock(&pci_pme_list_mutex);
2012 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2016 if (!dev->pme_support)
2019 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2020 /* Clear PME_Status by writing 1 to it and enable PME# */
2021 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2023 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2025 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2029 * pci_pme_restore - Restore PME configuration after config space restore.
2030 * @dev: PCI device to update.
2032 void pci_pme_restore(struct pci_dev *dev)
2036 if (!dev->pme_support)
2039 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2040 if (dev->wakeup_prepared) {
2041 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2042 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2044 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2045 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2047 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2051 * pci_pme_active - enable or disable PCI device's PME# function
2052 * @dev: PCI device to handle.
2053 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2055 * The caller must verify that the device is capable of generating PME# before
2056 * calling this function with @enable equal to 'true'.
2058 void pci_pme_active(struct pci_dev *dev, bool enable)
2060 __pci_pme_active(dev, enable);
2063 * PCI (as opposed to PCIe) PME requires that the device have
2064 * its PME# line hooked up correctly. Not all hardware vendors
2065 * do this, so the PME never gets delivered and the device
2066 * remains asleep. The easiest way around this is to
2067 * periodically walk the list of suspended devices and check
2068 * whether any have their PME flag set. The assumption is that
2069 * we'll wake up often enough anyway that this won't be a huge
2070 * hit, and the power savings from the devices will still be a
2073 * Although PCIe uses in-band PME message instead of PME# line
2074 * to report PME, PME does not work for some PCIe devices in
2075 * reality. For example, there are devices that set their PME
2076 * status bits, but don't really bother to send a PME message;
2077 * there are PCI Express Root Ports that don't bother to
2078 * trigger interrupts when they receive PME messages from the
2079 * devices below. So PME poll is used for PCIe devices too.
2082 if (dev->pme_poll) {
2083 struct pci_pme_device *pme_dev;
2085 pme_dev = kmalloc(sizeof(struct pci_pme_device),
2088 pci_warn(dev, "can't enable PME#\n");
2092 mutex_lock(&pci_pme_list_mutex);
2093 list_add(&pme_dev->list, &pci_pme_list);
2094 if (list_is_singular(&pci_pme_list))
2095 queue_delayed_work(system_freezable_wq,
2097 msecs_to_jiffies(PME_TIMEOUT));
2098 mutex_unlock(&pci_pme_list_mutex);
2100 mutex_lock(&pci_pme_list_mutex);
2101 list_for_each_entry(pme_dev, &pci_pme_list, list) {
2102 if (pme_dev->dev == dev) {
2103 list_del(&pme_dev->list);
2108 mutex_unlock(&pci_pme_list_mutex);
2112 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2114 EXPORT_SYMBOL(pci_pme_active);
2117 * __pci_enable_wake - enable PCI device as wakeup event source
2118 * @dev: PCI device affected
2119 * @state: PCI state from which device will issue wakeup events
2120 * @enable: True to enable event generation; false to disable
2122 * This enables the device as a wakeup event source, or disables it.
2123 * When such events involves platform-specific hooks, those hooks are
2124 * called automatically by this routine.
2126 * Devices with legacy power management (no standard PCI PM capabilities)
2127 * always require such platform hooks.
2130 * 0 is returned on success
2131 * -EINVAL is returned if device is not supposed to wake up the system
2132 * Error code depending on the platform is returned if both the platform and
2133 * the native mechanism fail to enable the generation of wake-up events
2135 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2140 * Bridges that are not power-manageable directly only signal
2141 * wakeup on behalf of subordinate devices which is set up
2142 * elsewhere, so skip them. However, bridges that are
2143 * power-manageable may signal wakeup for themselves (for example,
2144 * on a hotplug event) and they need to be covered here.
2146 if (!pci_power_manageable(dev))
2149 /* Don't do the same thing twice in a row for one device. */
2150 if (!!enable == !!dev->wakeup_prepared)
2154 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2155 * Anderson we should be doing PME# wake enable followed by ACPI wake
2156 * enable. To disable wake-up we call the platform first, for symmetry.
2162 if (pci_pme_capable(dev, state))
2163 pci_pme_active(dev, true);
2166 error = platform_pci_set_wakeup(dev, true);
2170 dev->wakeup_prepared = true;
2172 platform_pci_set_wakeup(dev, false);
2173 pci_pme_active(dev, false);
2174 dev->wakeup_prepared = false;
2181 * pci_enable_wake - change wakeup settings for a PCI device
2182 * @pci_dev: Target device
2183 * @state: PCI state from which device will issue wakeup events
2184 * @enable: Whether or not to enable event generation
2186 * If @enable is set, check device_may_wakeup() for the device before calling
2187 * __pci_enable_wake() for it.
2189 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2191 if (enable && !device_may_wakeup(&pci_dev->dev))
2194 return __pci_enable_wake(pci_dev, state, enable);
2196 EXPORT_SYMBOL(pci_enable_wake);
2199 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2200 * @dev: PCI device to prepare
2201 * @enable: True to enable wake-up event generation; false to disable
2203 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2204 * and this function allows them to set that up cleanly - pci_enable_wake()
2205 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2206 * ordering constraints.
2208 * This function only returns error code if the device is not allowed to wake
2209 * up the system from sleep or it is not capable of generating PME# from both
2210 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2212 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2214 return pci_pme_capable(dev, PCI_D3cold) ?
2215 pci_enable_wake(dev, PCI_D3cold, enable) :
2216 pci_enable_wake(dev, PCI_D3hot, enable);
2218 EXPORT_SYMBOL(pci_wake_from_d3);
2221 * pci_target_state - find an appropriate low power state for a given PCI dev
2223 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2225 * Use underlying platform code to find a supported low power state for @dev.
2226 * If the platform can't manage @dev, return the deepest state from which it
2227 * can generate wake events, based on any available PME info.
2229 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2231 pci_power_t target_state = PCI_D3hot;
2233 if (platform_pci_power_manageable(dev)) {
2235 * Call the platform to find the target state for the device.
2237 pci_power_t state = platform_pci_choose_state(dev);
2240 case PCI_POWER_ERROR:
2245 if (pci_no_d1d2(dev))
2247 /* else: fall through */
2249 target_state = state;
2252 return target_state;
2256 target_state = PCI_D0;
2259 * If the device is in D3cold even though it's not power-manageable by
2260 * the platform, it may have been powered down by non-standard means.
2261 * Best to let it slumber.
2263 if (dev->current_state == PCI_D3cold)
2264 target_state = PCI_D3cold;
2268 * Find the deepest state from which the device can generate
2271 if (dev->pme_support) {
2273 && !(dev->pme_support & (1 << target_state)))
2278 return target_state;
2282 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2283 * @dev: Device to handle.
2285 * Choose the power state appropriate for the device depending on whether
2286 * it can wake up the system and/or is power manageable by the platform
2287 * (PCI_D3hot is the default) and put the device into that state.
2289 int pci_prepare_to_sleep(struct pci_dev *dev)
2291 bool wakeup = device_may_wakeup(&dev->dev);
2292 pci_power_t target_state = pci_target_state(dev, wakeup);
2295 if (target_state == PCI_POWER_ERROR)
2298 pci_enable_wake(dev, target_state, wakeup);
2300 error = pci_set_power_state(dev, target_state);
2303 pci_enable_wake(dev, target_state, false);
2307 EXPORT_SYMBOL(pci_prepare_to_sleep);
2310 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2311 * @dev: Device to handle.
2313 * Disable device's system wake-up capability and put it into D0.
2315 int pci_back_from_sleep(struct pci_dev *dev)
2317 pci_enable_wake(dev, PCI_D0, false);
2318 return pci_set_power_state(dev, PCI_D0);
2320 EXPORT_SYMBOL(pci_back_from_sleep);
2323 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2324 * @dev: PCI device being suspended.
2326 * Prepare @dev to generate wake-up events at run time and put it into a low
2329 int pci_finish_runtime_suspend(struct pci_dev *dev)
2331 pci_power_t target_state;
2334 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2335 if (target_state == PCI_POWER_ERROR)
2338 dev->runtime_d3cold = target_state == PCI_D3cold;
2340 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2342 error = pci_set_power_state(dev, target_state);
2345 pci_enable_wake(dev, target_state, false);
2346 dev->runtime_d3cold = false;
2353 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2354 * @dev: Device to check.
2356 * Return true if the device itself is capable of generating wake-up events
2357 * (through the platform or using the native PCIe PME) or if the device supports
2358 * PME and one of its upstream bridges can generate wake-up events.
2360 bool pci_dev_run_wake(struct pci_dev *dev)
2362 struct pci_bus *bus = dev->bus;
2364 if (!dev->pme_support)
2367 /* PME-capable in principle, but not from the target power state */
2368 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2371 if (device_can_wakeup(&dev->dev))
2374 while (bus->parent) {
2375 struct pci_dev *bridge = bus->self;
2377 if (device_can_wakeup(&bridge->dev))
2383 /* We have reached the root bus. */
2385 return device_can_wakeup(bus->bridge);
2389 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2392 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2393 * @pci_dev: Device to check.
2395 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2396 * reconfigured due to wakeup settings difference between system and runtime
2397 * suspend and the current power state of it is suitable for the upcoming
2398 * (system) transition.
2400 * If the device is not configured for system wakeup, disable PME for it before
2401 * returning 'true' to prevent it from waking up the system unnecessarily.
2403 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2405 struct device *dev = &pci_dev->dev;
2406 bool wakeup = device_may_wakeup(dev);
2408 if (!pm_runtime_suspended(dev)
2409 || pci_target_state(pci_dev, wakeup) != pci_dev->current_state
2410 || platform_pci_need_resume(pci_dev))
2414 * At this point the device is good to go unless it's been configured
2415 * to generate PME at the runtime suspend time, but it is not supposed
2416 * to wake up the system. In that case, simply disable PME for it
2417 * (it will have to be re-enabled on exit from system resume).
2419 * If the device's power state is D3cold and the platform check above
2420 * hasn't triggered, the device's configuration is suitable and we don't
2421 * need to manipulate it at all.
2423 spin_lock_irq(&dev->power.lock);
2425 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2427 __pci_pme_active(pci_dev, false);
2429 spin_unlock_irq(&dev->power.lock);
2434 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2435 * @pci_dev: Device to handle.
2437 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2438 * it might have been disabled during the prepare phase of system suspend if
2439 * the device was not configured for system wakeup.
2441 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2443 struct device *dev = &pci_dev->dev;
2445 if (!pci_dev_run_wake(pci_dev))
2448 spin_lock_irq(&dev->power.lock);
2450 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2451 __pci_pme_active(pci_dev, true);
2453 spin_unlock_irq(&dev->power.lock);
2456 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2458 struct device *dev = &pdev->dev;
2459 struct device *parent = dev->parent;
2462 pm_runtime_get_sync(parent);
2463 pm_runtime_get_noresume(dev);
2465 * pdev->current_state is set to PCI_D3cold during suspending,
2466 * so wait until suspending completes
2468 pm_runtime_barrier(dev);
2470 * Only need to resume devices in D3cold, because config
2471 * registers are still accessible for devices suspended but
2474 if (pdev->current_state == PCI_D3cold)
2475 pm_runtime_resume(dev);
2478 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2480 struct device *dev = &pdev->dev;
2481 struct device *parent = dev->parent;
2483 pm_runtime_put(dev);
2485 pm_runtime_put_sync(parent);
2489 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2490 * @bridge: Bridge to check
2492 * This function checks if it is possible to move the bridge to D3.
2493 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2495 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2497 if (!pci_is_pcie(bridge))
2500 switch (pci_pcie_type(bridge)) {
2501 case PCI_EXP_TYPE_ROOT_PORT:
2502 case PCI_EXP_TYPE_UPSTREAM:
2503 case PCI_EXP_TYPE_DOWNSTREAM:
2504 if (pci_bridge_d3_disable)
2508 * Hotplug ports handled by firmware in System Management Mode
2509 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2511 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
2514 if (pci_bridge_d3_force)
2517 /* Even the oldest 2010 Thunderbolt controller supports D3. */
2518 if (bridge->is_thunderbolt)
2522 * Hotplug ports handled natively by the OS were not validated
2523 * by vendors for runtime D3 at least until 2018 because there
2524 * was no OS support.
2526 if (bridge->is_hotplug_bridge)
2530 * It should be safe to put PCIe ports from 2015 or newer
2533 if (dmi_get_bios_year() >= 2015)
2541 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2543 bool *d3cold_ok = data;
2545 if (/* The device needs to be allowed to go D3cold ... */
2546 dev->no_d3cold || !dev->d3cold_allowed ||
2548 /* ... and if it is wakeup capable to do so from D3cold. */
2549 (device_may_wakeup(&dev->dev) &&
2550 !pci_pme_capable(dev, PCI_D3cold)) ||
2552 /* If it is a bridge it must be allowed to go to D3. */
2553 !pci_power_manageable(dev))
2561 * pci_bridge_d3_update - Update bridge D3 capabilities
2562 * @dev: PCI device which is changed
2564 * Update upstream bridge PM capabilities accordingly depending on if the
2565 * device PM configuration was changed or the device is being removed. The
2566 * change is also propagated upstream.
2568 void pci_bridge_d3_update(struct pci_dev *dev)
2570 bool remove = !device_is_registered(&dev->dev);
2571 struct pci_dev *bridge;
2572 bool d3cold_ok = true;
2574 bridge = pci_upstream_bridge(dev);
2575 if (!bridge || !pci_bridge_d3_possible(bridge))
2579 * If D3 is currently allowed for the bridge, removing one of its
2580 * children won't change that.
2582 if (remove && bridge->bridge_d3)
2586 * If D3 is currently allowed for the bridge and a child is added or
2587 * changed, disallowance of D3 can only be caused by that child, so
2588 * we only need to check that single device, not any of its siblings.
2590 * If D3 is currently not allowed for the bridge, checking the device
2591 * first may allow us to skip checking its siblings.
2594 pci_dev_check_d3cold(dev, &d3cold_ok);
2597 * If D3 is currently not allowed for the bridge, this may be caused
2598 * either by the device being changed/removed or any of its siblings,
2599 * so we need to go through all children to find out if one of them
2600 * continues to block D3.
2602 if (d3cold_ok && !bridge->bridge_d3)
2603 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2606 if (bridge->bridge_d3 != d3cold_ok) {
2607 bridge->bridge_d3 = d3cold_ok;
2608 /* Propagate change to upstream bridges */
2609 pci_bridge_d3_update(bridge);
2614 * pci_d3cold_enable - Enable D3cold for device
2615 * @dev: PCI device to handle
2617 * This function can be used in drivers to enable D3cold from the device
2618 * they handle. It also updates upstream PCI bridge PM capabilities
2621 void pci_d3cold_enable(struct pci_dev *dev)
2623 if (dev->no_d3cold) {
2624 dev->no_d3cold = false;
2625 pci_bridge_d3_update(dev);
2628 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2631 * pci_d3cold_disable - Disable D3cold for device
2632 * @dev: PCI device to handle
2634 * This function can be used in drivers to disable D3cold from the device
2635 * they handle. It also updates upstream PCI bridge PM capabilities
2638 void pci_d3cold_disable(struct pci_dev *dev)
2640 if (!dev->no_d3cold) {
2641 dev->no_d3cold = true;
2642 pci_bridge_d3_update(dev);
2645 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2648 * pci_pm_init - Initialize PM functions of given PCI device
2649 * @dev: PCI device to handle.
2651 void pci_pm_init(struct pci_dev *dev)
2656 pm_runtime_forbid(&dev->dev);
2657 pm_runtime_set_active(&dev->dev);
2658 pm_runtime_enable(&dev->dev);
2659 device_enable_async_suspend(&dev->dev);
2660 dev->wakeup_prepared = false;
2663 dev->pme_support = 0;
2665 /* find PCI PM capability in list */
2666 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2669 /* Check device's ability to generate PME# */
2670 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2672 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2673 pci_err(dev, "unsupported PM cap regs version (%u)\n",
2674 pmc & PCI_PM_CAP_VER_MASK);
2679 dev->d3_delay = PCI_PM_D3_WAIT;
2680 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2681 dev->bridge_d3 = pci_bridge_d3_possible(dev);
2682 dev->d3cold_allowed = true;
2684 dev->d1_support = false;
2685 dev->d2_support = false;
2686 if (!pci_no_d1d2(dev)) {
2687 if (pmc & PCI_PM_CAP_D1)
2688 dev->d1_support = true;
2689 if (pmc & PCI_PM_CAP_D2)
2690 dev->d2_support = true;
2692 if (dev->d1_support || dev->d2_support)
2693 pci_printk(KERN_DEBUG, dev, "supports%s%s\n",
2694 dev->d1_support ? " D1" : "",
2695 dev->d2_support ? " D2" : "");
2698 pmc &= PCI_PM_CAP_PME_MASK;
2700 pci_printk(KERN_DEBUG, dev, "PME# supported from%s%s%s%s%s\n",
2701 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2702 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2703 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2704 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2705 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2706 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2707 dev->pme_poll = true;
2709 * Make device's PM flags reflect the wake-up capability, but
2710 * let the user space enable it to wake up the system as needed.
2712 device_set_wakeup_capable(&dev->dev, true);
2713 /* Disable the PME# generation functionality */
2714 pci_pme_active(dev, false);
2718 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2720 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
2724 case PCI_EA_P_VF_MEM:
2725 flags |= IORESOURCE_MEM;
2727 case PCI_EA_P_MEM_PREFETCH:
2728 case PCI_EA_P_VF_MEM_PREFETCH:
2729 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2732 flags |= IORESOURCE_IO;
2741 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2744 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2745 return &dev->resource[bei];
2746 #ifdef CONFIG_PCI_IOV
2747 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2748 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2749 return &dev->resource[PCI_IOV_RESOURCES +
2750 bei - PCI_EA_BEI_VF_BAR0];
2752 else if (bei == PCI_EA_BEI_ROM)
2753 return &dev->resource[PCI_ROM_RESOURCE];
2758 /* Read an Enhanced Allocation (EA) entry */
2759 static int pci_ea_read(struct pci_dev *dev, int offset)
2761 struct resource *res;
2762 int ent_size, ent_offset = offset;
2763 resource_size_t start, end;
2764 unsigned long flags;
2765 u32 dw0, bei, base, max_offset;
2767 bool support_64 = (sizeof(resource_size_t) >= 8);
2769 pci_read_config_dword(dev, ent_offset, &dw0);
2772 /* Entry size field indicates DWORDs after 1st */
2773 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2775 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2778 bei = (dw0 & PCI_EA_BEI) >> 4;
2779 prop = (dw0 & PCI_EA_PP) >> 8;
2782 * If the Property is in the reserved range, try the Secondary
2785 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2786 prop = (dw0 & PCI_EA_SP) >> 16;
2787 if (prop > PCI_EA_P_BRIDGE_IO)
2790 res = pci_ea_get_resource(dev, bei, prop);
2792 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
2796 flags = pci_ea_flags(dev, prop);
2798 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
2803 pci_read_config_dword(dev, ent_offset, &base);
2804 start = (base & PCI_EA_FIELD_MASK);
2807 /* Read MaxOffset */
2808 pci_read_config_dword(dev, ent_offset, &max_offset);
2811 /* Read Base MSBs (if 64-bit entry) */
2812 if (base & PCI_EA_IS_64) {
2815 pci_read_config_dword(dev, ent_offset, &base_upper);
2818 flags |= IORESOURCE_MEM_64;
2820 /* entry starts above 32-bit boundary, can't use */
2821 if (!support_64 && base_upper)
2825 start |= ((u64)base_upper << 32);
2828 end = start + (max_offset | 0x03);
2830 /* Read MaxOffset MSBs (if 64-bit entry) */
2831 if (max_offset & PCI_EA_IS_64) {
2832 u32 max_offset_upper;
2834 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2837 flags |= IORESOURCE_MEM_64;
2839 /* entry too big, can't use */
2840 if (!support_64 && max_offset_upper)
2844 end += ((u64)max_offset_upper << 32);
2848 pci_err(dev, "EA Entry crosses address boundary\n");
2852 if (ent_size != ent_offset - offset) {
2853 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
2854 ent_size, ent_offset - offset);
2858 res->name = pci_name(dev);
2863 if (bei <= PCI_EA_BEI_BAR5)
2864 pci_printk(KERN_DEBUG, dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2866 else if (bei == PCI_EA_BEI_ROM)
2867 pci_printk(KERN_DEBUG, dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2869 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2870 pci_printk(KERN_DEBUG, dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2871 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2873 pci_printk(KERN_DEBUG, dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2877 return offset + ent_size;
2880 /* Enhanced Allocation Initialization */
2881 void pci_ea_init(struct pci_dev *dev)
2888 /* find PCI EA capability in list */
2889 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2893 /* determine the number of entries */
2894 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2896 num_ent &= PCI_EA_NUM_ENT_MASK;
2898 offset = ea + PCI_EA_FIRST_ENT;
2900 /* Skip DWORD 2 for type 1 functions */
2901 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2904 /* parse each EA entry */
2905 for (i = 0; i < num_ent; ++i)
2906 offset = pci_ea_read(dev, offset);
2909 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2910 struct pci_cap_saved_state *new_cap)
2912 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2916 * _pci_add_cap_save_buffer - allocate buffer for saving given
2917 * capability registers
2918 * @dev: the PCI device
2919 * @cap: the capability to allocate the buffer for
2920 * @extended: Standard or Extended capability ID
2921 * @size: requested size of the buffer
2923 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2924 bool extended, unsigned int size)
2927 struct pci_cap_saved_state *save_state;
2930 pos = pci_find_ext_capability(dev, cap);
2932 pos = pci_find_capability(dev, cap);
2937 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2941 save_state->cap.cap_nr = cap;
2942 save_state->cap.cap_extended = extended;
2943 save_state->cap.size = size;
2944 pci_add_saved_cap(dev, save_state);
2949 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2951 return _pci_add_cap_save_buffer(dev, cap, false, size);
2954 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2956 return _pci_add_cap_save_buffer(dev, cap, true, size);
2960 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2961 * @dev: the PCI device
2963 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2967 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2968 PCI_EXP_SAVE_REGS * sizeof(u16));
2970 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
2972 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2974 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
2976 pci_allocate_vc_save_buffers(dev);
2979 void pci_free_cap_save_buffers(struct pci_dev *dev)
2981 struct pci_cap_saved_state *tmp;
2982 struct hlist_node *n;
2984 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2989 * pci_configure_ari - enable or disable ARI forwarding
2990 * @dev: the PCI device
2992 * If @dev and its upstream bridge both support ARI, enable ARI in the
2993 * bridge. Otherwise, disable ARI in the bridge.
2995 void pci_configure_ari(struct pci_dev *dev)
2998 struct pci_dev *bridge;
3000 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3003 bridge = dev->bus->self;
3007 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3008 if (!(cap & PCI_EXP_DEVCAP2_ARI))
3011 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3012 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3013 PCI_EXP_DEVCTL2_ARI);
3014 bridge->ari_enabled = 1;
3016 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3017 PCI_EXP_DEVCTL2_ARI);
3018 bridge->ari_enabled = 0;
3022 static int pci_acs_enable;
3025 * pci_request_acs - ask for ACS to be enabled if supported
3027 void pci_request_acs(void)
3032 static const char *disable_acs_redir_param;
3035 * pci_disable_acs_redir - disable ACS redirect capabilities
3036 * @dev: the PCI device
3038 * For only devices specified in the disable_acs_redir parameter.
3040 static void pci_disable_acs_redir(struct pci_dev *dev)
3047 if (!disable_acs_redir_param)
3050 p = disable_acs_redir_param;
3052 ret = pci_dev_str_match(dev, p, &p);
3054 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
3055 disable_acs_redir_param);
3058 } else if (ret == 1) {
3063 if (*p != ';' && *p != ',') {
3064 /* End of param or invalid format */
3073 if (!pci_dev_specific_disable_acs_redir(dev))
3076 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3078 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
3082 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
3084 /* P2P Request & Completion Redirect */
3085 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
3087 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
3089 pci_info(dev, "disabled ACS redirect\n");
3093 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
3094 * @dev: the PCI device
3096 static void pci_std_enable_acs(struct pci_dev *dev)
3102 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3106 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
3107 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
3109 /* Source Validation */
3110 ctrl |= (cap & PCI_ACS_SV);
3112 /* P2P Request Redirect */
3113 ctrl |= (cap & PCI_ACS_RR);
3115 /* P2P Completion Redirect */
3116 ctrl |= (cap & PCI_ACS_CR);
3118 /* Upstream Forwarding */
3119 ctrl |= (cap & PCI_ACS_UF);
3121 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
3125 * pci_enable_acs - enable ACS if hardware support it
3126 * @dev: the PCI device
3128 void pci_enable_acs(struct pci_dev *dev)
3130 if (!pci_acs_enable)
3131 goto disable_acs_redir;
3133 if (!pci_dev_specific_enable_acs(dev))
3134 goto disable_acs_redir;
3136 pci_std_enable_acs(dev);
3140 * Note: pci_disable_acs_redir() must be called even if ACS was not
3141 * enabled by the kernel because it may have been enabled by
3142 * platform firmware. So if we are told to disable it, we should
3143 * always disable it after setting the kernel's default
3146 pci_disable_acs_redir(dev);
3149 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3154 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
3159 * Except for egress control, capabilities are either required
3160 * or only required if controllable. Features missing from the
3161 * capability field can therefore be assumed as hard-wired enabled.
3163 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3164 acs_flags &= (cap | PCI_ACS_EC);
3166 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3167 return (ctrl & acs_flags) == acs_flags;
3171 * pci_acs_enabled - test ACS against required flags for a given device
3172 * @pdev: device to test
3173 * @acs_flags: required PCI ACS flags
3175 * Return true if the device supports the provided flags. Automatically
3176 * filters out flags that are not implemented on multifunction devices.
3178 * Note that this interface checks the effective ACS capabilities of the
3179 * device rather than the actual capabilities. For instance, most single
3180 * function endpoints are not required to support ACS because they have no
3181 * opportunity for peer-to-peer access. We therefore return 'true'
3182 * regardless of whether the device exposes an ACS capability. This makes
3183 * it much easier for callers of this function to ignore the actual type
3184 * or topology of the device when testing ACS support.
3186 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3190 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3195 * Conventional PCI and PCI-X devices never support ACS, either
3196 * effectively or actually. The shared bus topology implies that
3197 * any device on the bus can receive or snoop DMA.
3199 if (!pci_is_pcie(pdev))
3202 switch (pci_pcie_type(pdev)) {
3204 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3205 * but since their primary interface is PCI/X, we conservatively
3206 * handle them as we would a non-PCIe device.
3208 case PCI_EXP_TYPE_PCIE_BRIDGE:
3210 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3211 * applicable... must never implement an ACS Extended Capability...".
3212 * This seems arbitrary, but we take a conservative interpretation
3213 * of this statement.
3215 case PCI_EXP_TYPE_PCI_BRIDGE:
3216 case PCI_EXP_TYPE_RC_EC:
3219 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3220 * implement ACS in order to indicate their peer-to-peer capabilities,
3221 * regardless of whether they are single- or multi-function devices.
3223 case PCI_EXP_TYPE_DOWNSTREAM:
3224 case PCI_EXP_TYPE_ROOT_PORT:
3225 return pci_acs_flags_enabled(pdev, acs_flags);
3227 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3228 * implemented by the remaining PCIe types to indicate peer-to-peer
3229 * capabilities, but only when they are part of a multifunction
3230 * device. The footnote for section 6.12 indicates the specific
3231 * PCIe types included here.
3233 case PCI_EXP_TYPE_ENDPOINT:
3234 case PCI_EXP_TYPE_UPSTREAM:
3235 case PCI_EXP_TYPE_LEG_END:
3236 case PCI_EXP_TYPE_RC_END:
3237 if (!pdev->multifunction)
3240 return pci_acs_flags_enabled(pdev, acs_flags);
3244 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3245 * to single function devices with the exception of downstream ports.
3251 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
3252 * @start: starting downstream device
3253 * @end: ending upstream device or NULL to search to the root bus
3254 * @acs_flags: required flags
3256 * Walk up a device tree from start to end testing PCI ACS support. If
3257 * any step along the way does not support the required flags, return false.
3259 bool pci_acs_path_enabled(struct pci_dev *start,
3260 struct pci_dev *end, u16 acs_flags)
3262 struct pci_dev *pdev, *parent = start;
3267 if (!pci_acs_enabled(pdev, acs_flags))
3270 if (pci_is_root_bus(pdev->bus))
3271 return (end == NULL);
3273 parent = pdev->bus->self;
3274 } while (pdev != end);
3280 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3284 * Helper to find the position of the ctrl register for a BAR.
3285 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3286 * Returns -ENOENT if no ctrl register for the BAR could be found.
3288 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3290 unsigned int pos, nbars, i;
3293 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3297 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3298 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3299 PCI_REBAR_CTRL_NBAR_SHIFT;
3301 for (i = 0; i < nbars; i++, pos += 8) {
3304 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3305 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3314 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3316 * @bar: BAR to query
3318 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3319 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3321 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3326 pos = pci_rebar_find_pos(pdev, bar);
3330 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3331 return (cap & PCI_REBAR_CAP_SIZES) >> 4;
3335 * pci_rebar_get_current_size - get the current size of a BAR
3337 * @bar: BAR to set size to
3339 * Read the size of a BAR from the resizable BAR config.
3340 * Returns size if found or negative error code.
3342 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3347 pos = pci_rebar_find_pos(pdev, bar);
3351 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3352 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
3356 * pci_rebar_set_size - set a new size for a BAR
3358 * @bar: BAR to set size to
3359 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3361 * Set the new size of a BAR as defined in the spec.
3362 * Returns zero if resizing was successful, error code otherwise.
3364 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3369 pos = pci_rebar_find_pos(pdev, bar);
3373 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3374 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3375 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
3376 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3381 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3382 * @dev: the PCI device
3383 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3384 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3385 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3386 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3388 * Return 0 if all upstream bridges support AtomicOp routing, egress
3389 * blocking is disabled on all upstream ports, and the root port supports
3390 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3391 * AtomicOp completion), or negative otherwise.
3393 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3395 struct pci_bus *bus = dev->bus;
3396 struct pci_dev *bridge;
3399 if (!pci_is_pcie(dev))
3403 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3404 * AtomicOp requesters. For now, we only support endpoints as
3405 * requesters and root ports as completers. No endpoints as
3406 * completers, and no peer-to-peer.
3409 switch (pci_pcie_type(dev)) {
3410 case PCI_EXP_TYPE_ENDPOINT:
3411 case PCI_EXP_TYPE_LEG_END:
3412 case PCI_EXP_TYPE_RC_END:
3418 while (bus->parent) {
3421 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3423 switch (pci_pcie_type(bridge)) {
3424 /* Ensure switch ports support AtomicOp routing */
3425 case PCI_EXP_TYPE_UPSTREAM:
3426 case PCI_EXP_TYPE_DOWNSTREAM:
3427 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3431 /* Ensure root port supports all the sizes we care about */
3432 case PCI_EXP_TYPE_ROOT_PORT:
3433 if ((cap & cap_mask) != cap_mask)
3438 /* Ensure upstream ports don't block AtomicOps on egress */
3439 if (!bridge->has_secondary_link) {
3440 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3442 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3449 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3450 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3453 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3456 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3457 * @dev: the PCI device
3458 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3460 * Perform INTx swizzling for a device behind one level of bridge. This is
3461 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3462 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3463 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3464 * the PCI Express Base Specification, Revision 2.1)
3466 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3470 if (pci_ari_enabled(dev->bus))
3473 slot = PCI_SLOT(dev->devfn);
3475 return (((pin - 1) + slot) % 4) + 1;
3478 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3486 while (!pci_is_root_bus(dev->bus)) {
3487 pin = pci_swizzle_interrupt_pin(dev, pin);
3488 dev = dev->bus->self;
3495 * pci_common_swizzle - swizzle INTx all the way to root bridge
3496 * @dev: the PCI device
3497 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3499 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3500 * bridges all the way up to a PCI root bus.
3502 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3506 while (!pci_is_root_bus(dev->bus)) {
3507 pin = pci_swizzle_interrupt_pin(dev, pin);
3508 dev = dev->bus->self;
3511 return PCI_SLOT(dev->devfn);
3513 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3516 * pci_release_region - Release a PCI bar
3517 * @pdev: PCI device whose resources were previously reserved by pci_request_region
3518 * @bar: BAR to release
3520 * Releases the PCI I/O and memory resources previously reserved by a
3521 * successful call to pci_request_region. Call this function only
3522 * after all use of the PCI regions has ceased.
3524 void pci_release_region(struct pci_dev *pdev, int bar)
3526 struct pci_devres *dr;
3528 if (pci_resource_len(pdev, bar) == 0)
3530 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3531 release_region(pci_resource_start(pdev, bar),
3532 pci_resource_len(pdev, bar));
3533 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3534 release_mem_region(pci_resource_start(pdev, bar),
3535 pci_resource_len(pdev, bar));
3537 dr = find_pci_dr(pdev);
3539 dr->region_mask &= ~(1 << bar);
3541 EXPORT_SYMBOL(pci_release_region);
3544 * __pci_request_region - Reserved PCI I/O and memory resource
3545 * @pdev: PCI device whose resources are to be reserved
3546 * @bar: BAR to be reserved
3547 * @res_name: Name to be associated with resource.
3548 * @exclusive: whether the region access is exclusive or not
3550 * Mark the PCI region associated with PCI device @pdev BR @bar as
3551 * being reserved by owner @res_name. Do not access any
3552 * address inside the PCI regions unless this call returns
3555 * If @exclusive is set, then the region is marked so that userspace
3556 * is explicitly not allowed to map the resource via /dev/mem or
3557 * sysfs MMIO access.
3559 * Returns 0 on success, or %EBUSY on error. A warning
3560 * message is also printed on failure.
3562 static int __pci_request_region(struct pci_dev *pdev, int bar,
3563 const char *res_name, int exclusive)
3565 struct pci_devres *dr;
3567 if (pci_resource_len(pdev, bar) == 0)
3570 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3571 if (!request_region(pci_resource_start(pdev, bar),
3572 pci_resource_len(pdev, bar), res_name))
3574 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3575 if (!__request_mem_region(pci_resource_start(pdev, bar),
3576 pci_resource_len(pdev, bar), res_name,
3581 dr = find_pci_dr(pdev);
3583 dr->region_mask |= 1 << bar;
3588 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3589 &pdev->resource[bar]);
3594 * pci_request_region - Reserve PCI I/O and memory resource
3595 * @pdev: PCI device whose resources are to be reserved
3596 * @bar: BAR to be reserved
3597 * @res_name: Name to be associated with resource
3599 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3600 * being reserved by owner @res_name. Do not access any
3601 * address inside the PCI regions unless this call returns
3604 * Returns 0 on success, or %EBUSY on error. A warning
3605 * message is also printed on failure.
3607 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3609 return __pci_request_region(pdev, bar, res_name, 0);
3611 EXPORT_SYMBOL(pci_request_region);
3614 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3615 * @pdev: PCI device whose resources are to be reserved
3616 * @bar: BAR to be reserved
3617 * @res_name: Name to be associated with resource.
3619 * Mark the PCI region associated with PCI device @pdev BR @bar as
3620 * being reserved by owner @res_name. Do not access any
3621 * address inside the PCI regions unless this call returns
3624 * Returns 0 on success, or %EBUSY on error. A warning
3625 * message is also printed on failure.
3627 * The key difference that _exclusive makes it that userspace is
3628 * explicitly not allowed to map the resource via /dev/mem or
3631 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3632 const char *res_name)
3634 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3636 EXPORT_SYMBOL(pci_request_region_exclusive);
3639 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3640 * @pdev: PCI device whose resources were previously reserved
3641 * @bars: Bitmask of BARs to be released
3643 * Release selected PCI I/O and memory resources previously reserved.
3644 * Call this function only after all use of the PCI regions has ceased.
3646 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3650 for (i = 0; i < 6; i++)
3651 if (bars & (1 << i))
3652 pci_release_region(pdev, i);
3654 EXPORT_SYMBOL(pci_release_selected_regions);
3656 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3657 const char *res_name, int excl)
3661 for (i = 0; i < 6; i++)
3662 if (bars & (1 << i))
3663 if (__pci_request_region(pdev, i, res_name, excl))
3669 if (bars & (1 << i))
3670 pci_release_region(pdev, i);
3677 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3678 * @pdev: PCI device whose resources are to be reserved
3679 * @bars: Bitmask of BARs to be requested
3680 * @res_name: Name to be associated with resource
3682 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3683 const char *res_name)
3685 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3687 EXPORT_SYMBOL(pci_request_selected_regions);
3689 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3690 const char *res_name)
3692 return __pci_request_selected_regions(pdev, bars, res_name,
3693 IORESOURCE_EXCLUSIVE);
3695 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3698 * pci_release_regions - Release reserved PCI I/O and memory resources
3699 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3701 * Releases all PCI I/O and memory resources previously reserved by a
3702 * successful call to pci_request_regions. Call this function only
3703 * after all use of the PCI regions has ceased.
3706 void pci_release_regions(struct pci_dev *pdev)
3708 pci_release_selected_regions(pdev, (1 << 6) - 1);
3710 EXPORT_SYMBOL(pci_release_regions);
3713 * pci_request_regions - Reserved PCI I/O and memory resources
3714 * @pdev: PCI device whose resources are to be reserved
3715 * @res_name: Name to be associated with resource.
3717 * Mark all PCI regions associated with PCI device @pdev as
3718 * being reserved by owner @res_name. Do not access any
3719 * address inside the PCI regions unless this call returns
3722 * Returns 0 on success, or %EBUSY on error. A warning
3723 * message is also printed on failure.
3725 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3727 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3729 EXPORT_SYMBOL(pci_request_regions);
3732 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3733 * @pdev: PCI device whose resources are to be reserved
3734 * @res_name: Name to be associated with resource.
3736 * Mark all PCI regions associated with PCI device @pdev as
3737 * being reserved by owner @res_name. Do not access any
3738 * address inside the PCI regions unless this call returns
3741 * pci_request_regions_exclusive() will mark the region so that
3742 * /dev/mem and the sysfs MMIO access will not be allowed.
3744 * Returns 0 on success, or %EBUSY on error. A warning
3745 * message is also printed on failure.
3747 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3749 return pci_request_selected_regions_exclusive(pdev,
3750 ((1 << 6) - 1), res_name);
3752 EXPORT_SYMBOL(pci_request_regions_exclusive);
3755 * Record the PCI IO range (expressed as CPU physical address + size).
3756 * Return a negative value if an error has occured, zero otherwise
3758 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
3759 resource_size_t size)
3763 struct logic_pio_hwaddr *range;
3765 if (!size || addr + size < addr)
3768 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3772 range->fwnode = fwnode;
3774 range->hw_start = addr;
3775 range->flags = LOGIC_PIO_CPU_MMIO;
3777 ret = logic_pio_register_range(range);
3785 phys_addr_t pci_pio_to_address(unsigned long pio)
3787 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3790 if (pio >= MMIO_UPPER_LIMIT)
3793 address = logic_pio_to_hwaddr(pio);
3799 unsigned long __weak pci_address_to_pio(phys_addr_t address)
3802 return logic_pio_trans_cpuaddr(address);
3804 if (address > IO_SPACE_LIMIT)
3805 return (unsigned long)-1;
3807 return (unsigned long) address;
3812 * pci_remap_iospace - Remap the memory mapped I/O space
3813 * @res: Resource describing the I/O space
3814 * @phys_addr: physical address of range to be mapped
3816 * Remap the memory mapped I/O space described by the @res
3817 * and the CPU physical address @phys_addr into virtual address space.
3818 * Only architectures that have memory mapped IO functions defined
3819 * (and the PCI_IOBASE value defined) should call this function.
3821 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3823 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3824 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3826 if (!(res->flags & IORESOURCE_IO))
3829 if (res->end > IO_SPACE_LIMIT)
3832 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3833 pgprot_device(PAGE_KERNEL));
3835 /* this architecture does not have memory mapped I/O space,
3836 so this function should never be called */
3837 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3841 EXPORT_SYMBOL(pci_remap_iospace);
3844 * pci_unmap_iospace - Unmap the memory mapped I/O space
3845 * @res: resource to be unmapped
3847 * Unmap the CPU virtual address @res from virtual address space.
3848 * Only architectures that have memory mapped IO functions defined
3849 * (and the PCI_IOBASE value defined) should call this function.
3851 void pci_unmap_iospace(struct resource *res)
3853 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3854 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3856 unmap_kernel_range(vaddr, resource_size(res));
3859 EXPORT_SYMBOL(pci_unmap_iospace);
3861 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
3863 struct resource **res = ptr;
3865 pci_unmap_iospace(*res);
3869 * devm_pci_remap_iospace - Managed pci_remap_iospace()
3870 * @dev: Generic device to remap IO address for
3871 * @res: Resource describing the I/O space
3872 * @phys_addr: physical address of range to be mapped
3874 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
3877 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
3878 phys_addr_t phys_addr)
3880 const struct resource **ptr;
3883 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
3887 error = pci_remap_iospace(res, phys_addr);
3892 devres_add(dev, ptr);
3897 EXPORT_SYMBOL(devm_pci_remap_iospace);
3900 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
3901 * @dev: Generic device to remap IO address for
3902 * @offset: Resource address to map
3903 * @size: Size of map
3905 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
3908 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
3909 resource_size_t offset,
3910 resource_size_t size)
3912 void __iomem **ptr, *addr;
3914 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
3918 addr = pci_remap_cfgspace(offset, size);
3921 devres_add(dev, ptr);
3927 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
3930 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
3931 * @dev: generic device to handle the resource for
3932 * @res: configuration space resource to be handled
3934 * Checks that a resource is a valid memory region, requests the memory
3935 * region and ioremaps with pci_remap_cfgspace() API that ensures the
3936 * proper PCI configuration space memory attributes are guaranteed.
3938 * All operations are managed and will be undone on driver detach.
3940 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
3941 * on failure. Usage example::
3943 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3944 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
3946 * return PTR_ERR(base);
3948 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
3949 struct resource *res)
3951 resource_size_t size;
3953 void __iomem *dest_ptr;
3957 if (!res || resource_type(res) != IORESOURCE_MEM) {
3958 dev_err(dev, "invalid resource\n");
3959 return IOMEM_ERR_PTR(-EINVAL);
3962 size = resource_size(res);
3963 name = res->name ?: dev_name(dev);
3965 if (!devm_request_mem_region(dev, res->start, size, name)) {
3966 dev_err(dev, "can't request region for resource %pR\n", res);
3967 return IOMEM_ERR_PTR(-EBUSY);
3970 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
3972 dev_err(dev, "ioremap failed for resource %pR\n", res);
3973 devm_release_mem_region(dev, res->start, size);
3974 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
3979 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
3981 static void __pci_set_master(struct pci_dev *dev, bool enable)
3985 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3987 cmd = old_cmd | PCI_COMMAND_MASTER;
3989 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3990 if (cmd != old_cmd) {
3991 pci_dbg(dev, "%s bus mastering\n",
3992 enable ? "enabling" : "disabling");
3993 pci_write_config_word(dev, PCI_COMMAND, cmd);
3995 dev->is_busmaster = enable;
3999 * pcibios_setup - process "pci=" kernel boot arguments
4000 * @str: string used to pass in "pci=" kernel boot arguments
4002 * Process kernel boot arguments. This is the default implementation.
4003 * Architecture specific implementations can override this as necessary.
4005 char * __weak __init pcibios_setup(char *str)
4011 * pcibios_set_master - enable PCI bus-mastering for device dev
4012 * @dev: the PCI device to enable
4014 * Enables PCI bus-mastering for the device. This is the default
4015 * implementation. Architecture specific implementations can override
4016 * this if necessary.
4018 void __weak pcibios_set_master(struct pci_dev *dev)
4022 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4023 if (pci_is_pcie(dev))
4026 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4028 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4029 else if (lat > pcibios_max_latency)
4030 lat = pcibios_max_latency;
4034 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4038 * pci_set_master - enables bus-mastering for device dev
4039 * @dev: the PCI device to enable
4041 * Enables bus-mastering on the device and calls pcibios_set_master()
4042 * to do the needed arch specific settings.
4044 void pci_set_master(struct pci_dev *dev)
4046 __pci_set_master(dev, true);
4047 pcibios_set_master(dev);
4049 EXPORT_SYMBOL(pci_set_master);
4052 * pci_clear_master - disables bus-mastering for device dev
4053 * @dev: the PCI device to disable
4055 void pci_clear_master(struct pci_dev *dev)
4057 __pci_set_master(dev, false);
4059 EXPORT_SYMBOL(pci_clear_master);
4062 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4063 * @dev: the PCI device for which MWI is to be enabled
4065 * Helper function for pci_set_mwi.
4066 * Originally copied from drivers/net/acenic.c.
4067 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4069 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4071 int pci_set_cacheline_size(struct pci_dev *dev)
4075 if (!pci_cache_line_size)
4078 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4079 equal to or multiple of the right value. */
4080 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4081 if (cacheline_size >= pci_cache_line_size &&
4082 (cacheline_size % pci_cache_line_size) == 0)
4085 /* Write the correct value. */
4086 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4088 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4089 if (cacheline_size == pci_cache_line_size)
4092 pci_printk(KERN_DEBUG, dev, "cache line size of %d is not supported\n",
4093 pci_cache_line_size << 2);
4097 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4100 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4101 * @dev: the PCI device for which MWI is enabled
4103 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4105 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4107 int pci_set_mwi(struct pci_dev *dev)
4109 #ifdef PCI_DISABLE_MWI
4115 rc = pci_set_cacheline_size(dev);
4119 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4120 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4121 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4122 cmd |= PCI_COMMAND_INVALIDATE;
4123 pci_write_config_word(dev, PCI_COMMAND, cmd);
4128 EXPORT_SYMBOL(pci_set_mwi);
4131 * pcim_set_mwi - a device-managed pci_set_mwi()
4132 * @dev: the PCI device for which MWI is enabled
4134 * Managed pci_set_mwi().
4136 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4138 int pcim_set_mwi(struct pci_dev *dev)
4140 struct pci_devres *dr;
4142 dr = find_pci_dr(dev);
4147 return pci_set_mwi(dev);
4149 EXPORT_SYMBOL(pcim_set_mwi);
4152 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4153 * @dev: the PCI device for which MWI is enabled
4155 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4156 * Callers are not required to check the return value.
4158 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4160 int pci_try_set_mwi(struct pci_dev *dev)
4162 #ifdef PCI_DISABLE_MWI
4165 return pci_set_mwi(dev);
4168 EXPORT_SYMBOL(pci_try_set_mwi);
4171 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4172 * @dev: the PCI device to disable
4174 * Disables PCI Memory-Write-Invalidate transaction on the device
4176 void pci_clear_mwi(struct pci_dev *dev)
4178 #ifndef PCI_DISABLE_MWI
4181 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4182 if (cmd & PCI_COMMAND_INVALIDATE) {
4183 cmd &= ~PCI_COMMAND_INVALIDATE;
4184 pci_write_config_word(dev, PCI_COMMAND, cmd);
4188 EXPORT_SYMBOL(pci_clear_mwi);
4191 * pci_intx - enables/disables PCI INTx for device dev
4192 * @pdev: the PCI device to operate on
4193 * @enable: boolean: whether to enable or disable PCI INTx
4195 * Enables/disables PCI INTx for device dev
4197 void pci_intx(struct pci_dev *pdev, int enable)
4199 u16 pci_command, new;
4201 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4204 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4206 new = pci_command | PCI_COMMAND_INTX_DISABLE;
4208 if (new != pci_command) {
4209 struct pci_devres *dr;
4211 pci_write_config_word(pdev, PCI_COMMAND, new);
4213 dr = find_pci_dr(pdev);
4214 if (dr && !dr->restore_intx) {
4215 dr->restore_intx = 1;
4216 dr->orig_intx = !enable;
4220 EXPORT_SYMBOL_GPL(pci_intx);
4222 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4224 struct pci_bus *bus = dev->bus;
4225 bool mask_updated = true;
4226 u32 cmd_status_dword;
4227 u16 origcmd, newcmd;
4228 unsigned long flags;
4232 * We do a single dword read to retrieve both command and status.
4233 * Document assumptions that make this possible.
4235 BUILD_BUG_ON(PCI_COMMAND % 4);
4236 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4238 raw_spin_lock_irqsave(&pci_lock, flags);
4240 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4242 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4245 * Check interrupt status register to see whether our device
4246 * triggered the interrupt (when masking) or the next IRQ is
4247 * already pending (when unmasking).
4249 if (mask != irq_pending) {
4250 mask_updated = false;
4254 origcmd = cmd_status_dword;
4255 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4257 newcmd |= PCI_COMMAND_INTX_DISABLE;
4258 if (newcmd != origcmd)
4259 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4262 raw_spin_unlock_irqrestore(&pci_lock, flags);
4264 return mask_updated;
4268 * pci_check_and_mask_intx - mask INTx on pending interrupt
4269 * @dev: the PCI device to operate on
4271 * Check if the device dev has its INTx line asserted, mask it and
4272 * return true in that case. False is returned if no interrupt was
4275 bool pci_check_and_mask_intx(struct pci_dev *dev)
4277 return pci_check_and_set_intx_mask(dev, true);
4279 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4282 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4283 * @dev: the PCI device to operate on
4285 * Check if the device dev has its INTx line asserted, unmask it if not
4286 * and return true. False is returned and the mask remains active if
4287 * there was still an interrupt pending.
4289 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4291 return pci_check_and_set_intx_mask(dev, false);
4293 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4296 * pci_wait_for_pending_transaction - waits for pending transaction
4297 * @dev: the PCI device to operate on
4299 * Return 0 if transaction is pending 1 otherwise.
4301 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4303 if (!pci_is_pcie(dev))
4306 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4307 PCI_EXP_DEVSTA_TRPND);
4309 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4311 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
4317 * After reset, the device should not silently discard config
4318 * requests, but it may still indicate that it needs more time by
4319 * responding to them with CRS completions. The Root Port will
4320 * generally synthesize ~0 data to complete the read (except when
4321 * CRS SV is enabled and the read was for the Vendor ID; in that
4322 * case it synthesizes 0x0001 data).
4324 * Wait for the device to return a non-CRS completion. Read the
4325 * Command register instead of Vendor ID so we don't have to
4326 * contend with the CRS SV value.
4328 pci_read_config_dword(dev, PCI_COMMAND, &id);
4330 if (delay > timeout) {
4331 pci_warn(dev, "not ready %dms after %s; giving up\n",
4332 delay - 1, reset_type);
4337 pci_info(dev, "not ready %dms after %s; waiting\n",
4338 delay - 1, reset_type);
4342 pci_read_config_dword(dev, PCI_COMMAND, &id);
4346 pci_info(dev, "ready %dms after %s\n", delay - 1,
4353 * pcie_has_flr - check if a device supports function level resets
4354 * @dev: device to check
4356 * Returns true if the device advertises support for PCIe function level
4359 bool pcie_has_flr(struct pci_dev *dev)
4363 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4366 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
4367 return cap & PCI_EXP_DEVCAP_FLR;
4369 EXPORT_SYMBOL_GPL(pcie_has_flr);
4372 * pcie_flr - initiate a PCIe function level reset
4373 * @dev: device to reset
4375 * Initiate a function level reset on @dev. The caller should ensure the
4376 * device supports FLR before calling this function, e.g. by using the
4377 * pcie_has_flr() helper.
4379 int pcie_flr(struct pci_dev *dev)
4381 if (!pci_wait_for_pending_transaction(dev))
4382 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4384 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4387 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4388 * 100ms, but may silently discard requests while the FLR is in
4389 * progress. Wait 100ms before trying to access the device.
4393 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4395 EXPORT_SYMBOL_GPL(pcie_flr);
4397 static int pci_af_flr(struct pci_dev *dev, int probe)
4402 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4406 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4409 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4410 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4417 * Wait for Transaction Pending bit to clear. A word-aligned test
4418 * is used, so we use the conrol offset rather than status and shift
4419 * the test bit to match.
4421 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4422 PCI_AF_STATUS_TP << 8))
4423 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4425 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4428 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4429 * updated 27 July 2006; a device must complete an FLR within
4430 * 100ms, but may silently discard requests while the FLR is in
4431 * progress. Wait 100ms before trying to access the device.
4435 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4439 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4440 * @dev: Device to reset.
4441 * @probe: If set, only check if the device can be reset this way.
4443 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4444 * unset, it will be reinitialized internally when going from PCI_D3hot to
4445 * PCI_D0. If that's the case and the device is not in a low-power state
4446 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4448 * NOTE: This causes the caller to sleep for twice the device power transition
4449 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4450 * by default (i.e. unless the @dev's d3_delay field has a different value).
4451 * Moreover, only devices in D0 can be reset by this function.
4453 static int pci_pm_reset(struct pci_dev *dev, int probe)
4457 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4460 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4461 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4467 if (dev->current_state != PCI_D0)
4470 csr &= ~PCI_PM_CTRL_STATE_MASK;
4472 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4473 pci_dev_d3_sleep(dev);
4475 csr &= ~PCI_PM_CTRL_STATE_MASK;
4477 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4478 pci_dev_d3_sleep(dev);
4480 return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS);
4483 * pcie_wait_for_link - Wait until link is active or inactive
4484 * @pdev: Bridge device
4485 * @active: waiting for active or inactive?
4487 * Use this to wait till link becomes active or inactive.
4489 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4496 * Some controllers might not implement link active reporting. In this
4497 * case, we wait for 1000 + 100 ms.
4499 if (!pdev->link_active_reporting) {
4505 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4506 * after which we should expect an link active if the reset was
4507 * successful. If so, software must wait a minimum 100ms before sending
4508 * configuration requests to devices downstream this port.
4510 * If the link fails to activate, either the device was physically
4511 * removed or the link is permanently failed.
4516 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4517 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4527 else if (ret != active)
4528 pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n",
4529 active ? "set" : "cleared");
4530 return ret == active;
4533 void pci_reset_secondary_bus(struct pci_dev *dev)
4537 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4538 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4539 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4542 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4543 * this to 2ms to ensure that we meet the minimum requirement.
4547 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
4548 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4551 * Trhfa for conventional PCI is 2^25 clock cycles.
4552 * Assuming a minimum 33MHz clock this results in a 1s
4553 * delay before we can consider subordinate devices to
4554 * be re-initialized. PCIe has some ways to shorten this,
4555 * but we don't make use of them yet.
4560 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4562 pci_reset_secondary_bus(dev);
4566 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
4567 * @dev: Bridge device
4569 * Use the bridge control register to assert reset on the secondary bus.
4570 * Devices on the secondary bus are left in power-on state.
4572 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
4574 pcibios_reset_secondary_bus(dev);
4576 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
4578 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
4580 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4582 struct pci_dev *pdev;
4584 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4585 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4588 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4595 return pci_bridge_secondary_bus_reset(dev->bus->self);
4598 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
4602 if (!hotplug || !try_module_get(hotplug->owner))
4605 if (hotplug->ops->reset_slot)
4606 rc = hotplug->ops->reset_slot(hotplug, probe);
4608 module_put(hotplug->owner);
4613 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
4615 struct pci_dev *pdev;
4617 if (dev->subordinate || !dev->slot ||
4618 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4621 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4622 if (pdev != dev && pdev->slot == dev->slot)
4625 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
4628 static void pci_dev_lock(struct pci_dev *dev)
4630 pci_cfg_access_lock(dev);
4631 /* block PM suspend, driver probe, etc. */
4632 device_lock(&dev->dev);
4635 /* Return 1 on successful lock, 0 on contention */
4636 static int pci_dev_trylock(struct pci_dev *dev)
4638 if (pci_cfg_access_trylock(dev)) {
4639 if (device_trylock(&dev->dev))
4641 pci_cfg_access_unlock(dev);
4647 static void pci_dev_unlock(struct pci_dev *dev)
4649 device_unlock(&dev->dev);
4650 pci_cfg_access_unlock(dev);
4653 static void pci_dev_save_and_disable(struct pci_dev *dev)
4655 const struct pci_error_handlers *err_handler =
4656 dev->driver ? dev->driver->err_handler : NULL;
4659 * dev->driver->err_handler->reset_prepare() is protected against
4660 * races with ->remove() by the device lock, which must be held by
4663 if (err_handler && err_handler->reset_prepare)
4664 err_handler->reset_prepare(dev);
4667 * Wake-up device prior to save. PM registers default to D0 after
4668 * reset and a simple register restore doesn't reliably return
4669 * to a non-D0 state anyway.
4671 pci_set_power_state(dev, PCI_D0);
4673 pci_save_state(dev);
4675 * Disable the device by clearing the Command register, except for
4676 * INTx-disable which is set. This not only disables MMIO and I/O port
4677 * BARs, but also prevents the device from being Bus Master, preventing
4678 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4679 * compliant devices, INTx-disable prevents legacy interrupts.
4681 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4684 static void pci_dev_restore(struct pci_dev *dev)
4686 const struct pci_error_handlers *err_handler =
4687 dev->driver ? dev->driver->err_handler : NULL;
4689 pci_restore_state(dev);
4692 * dev->driver->err_handler->reset_done() is protected against
4693 * races with ->remove() by the device lock, which must be held by
4696 if (err_handler && err_handler->reset_done)
4697 err_handler->reset_done(dev);
4701 * __pci_reset_function_locked - reset a PCI device function while holding
4702 * the @dev mutex lock.
4703 * @dev: PCI device to reset
4705 * Some devices allow an individual function to be reset without affecting
4706 * other functions in the same device. The PCI device must be responsive
4707 * to PCI config space in order to use this function.
4709 * The device function is presumed to be unused and the caller is holding
4710 * the device mutex lock when this function is called.
4711 * Resetting the device will make the contents of PCI configuration space
4712 * random, so any caller of this must be prepared to reinitialise the
4713 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4716 * Returns 0 if the device function was successfully reset or negative if the
4717 * device doesn't support resetting a single function.
4719 int __pci_reset_function_locked(struct pci_dev *dev)
4726 * A reset method returns -ENOTTY if it doesn't support this device
4727 * and we should try the next method.
4729 * If it returns 0 (success), we're finished. If it returns any
4730 * other error, we're also finished: this indicates that further
4731 * reset mechanisms might be broken on the device.
4733 rc = pci_dev_specific_reset(dev, 0);
4736 if (pcie_has_flr(dev)) {
4741 rc = pci_af_flr(dev, 0);
4744 rc = pci_pm_reset(dev, 0);
4747 rc = pci_dev_reset_slot_function(dev, 0);
4750 return pci_parent_bus_reset(dev, 0);
4752 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4755 * pci_probe_reset_function - check whether the device can be safely reset
4756 * @dev: PCI device to reset
4758 * Some devices allow an individual function to be reset without affecting
4759 * other functions in the same device. The PCI device must be responsive
4760 * to PCI config space in order to use this function.
4762 * Returns 0 if the device function can be reset or negative if the
4763 * device doesn't support resetting a single function.
4765 int pci_probe_reset_function(struct pci_dev *dev)
4771 rc = pci_dev_specific_reset(dev, 1);
4774 if (pcie_has_flr(dev))
4776 rc = pci_af_flr(dev, 1);
4779 rc = pci_pm_reset(dev, 1);
4782 rc = pci_dev_reset_slot_function(dev, 1);
4786 return pci_parent_bus_reset(dev, 1);
4790 * pci_reset_function - quiesce and reset a PCI device function
4791 * @dev: PCI device to reset
4793 * Some devices allow an individual function to be reset without affecting
4794 * other functions in the same device. The PCI device must be responsive
4795 * to PCI config space in order to use this function.
4797 * This function does not just reset the PCI portion of a device, but
4798 * clears all the state associated with the device. This function differs
4799 * from __pci_reset_function_locked() in that it saves and restores device state
4800 * over the reset and takes the PCI device lock.
4802 * Returns 0 if the device function was successfully reset or negative if the
4803 * device doesn't support resetting a single function.
4805 int pci_reset_function(struct pci_dev *dev)
4813 pci_dev_save_and_disable(dev);
4815 rc = __pci_reset_function_locked(dev);
4817 pci_dev_restore(dev);
4818 pci_dev_unlock(dev);
4822 EXPORT_SYMBOL_GPL(pci_reset_function);
4825 * pci_reset_function_locked - quiesce and reset a PCI device function
4826 * @dev: PCI device to reset
4828 * Some devices allow an individual function to be reset without affecting
4829 * other functions in the same device. The PCI device must be responsive
4830 * to PCI config space in order to use this function.
4832 * This function does not just reset the PCI portion of a device, but
4833 * clears all the state associated with the device. This function differs
4834 * from __pci_reset_function_locked() in that it saves and restores device state
4835 * over the reset. It also differs from pci_reset_function() in that it
4836 * requires the PCI device lock to be held.
4838 * Returns 0 if the device function was successfully reset or negative if the
4839 * device doesn't support resetting a single function.
4841 int pci_reset_function_locked(struct pci_dev *dev)
4848 pci_dev_save_and_disable(dev);
4850 rc = __pci_reset_function_locked(dev);
4852 pci_dev_restore(dev);
4856 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
4859 * pci_try_reset_function - quiesce and reset a PCI device function
4860 * @dev: PCI device to reset
4862 * Same as above, except return -EAGAIN if unable to lock device.
4864 int pci_try_reset_function(struct pci_dev *dev)
4871 if (!pci_dev_trylock(dev))
4874 pci_dev_save_and_disable(dev);
4875 rc = __pci_reset_function_locked(dev);
4876 pci_dev_restore(dev);
4877 pci_dev_unlock(dev);
4881 EXPORT_SYMBOL_GPL(pci_try_reset_function);
4883 /* Do any devices on or below this bus prevent a bus reset? */
4884 static bool pci_bus_resetable(struct pci_bus *bus)
4886 struct pci_dev *dev;
4889 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4892 list_for_each_entry(dev, &bus->devices, bus_list) {
4893 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4894 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4901 /* Lock devices from the top of the tree down */
4902 static void pci_bus_lock(struct pci_bus *bus)
4904 struct pci_dev *dev;
4906 list_for_each_entry(dev, &bus->devices, bus_list) {
4908 if (dev->subordinate)
4909 pci_bus_lock(dev->subordinate);
4913 /* Unlock devices from the bottom of the tree up */
4914 static void pci_bus_unlock(struct pci_bus *bus)
4916 struct pci_dev *dev;
4918 list_for_each_entry(dev, &bus->devices, bus_list) {
4919 if (dev->subordinate)
4920 pci_bus_unlock(dev->subordinate);
4921 pci_dev_unlock(dev);
4925 /* Return 1 on successful lock, 0 on contention */
4926 static int pci_bus_trylock(struct pci_bus *bus)
4928 struct pci_dev *dev;
4930 list_for_each_entry(dev, &bus->devices, bus_list) {
4931 if (!pci_dev_trylock(dev))
4933 if (dev->subordinate) {
4934 if (!pci_bus_trylock(dev->subordinate)) {
4935 pci_dev_unlock(dev);
4943 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
4944 if (dev->subordinate)
4945 pci_bus_unlock(dev->subordinate);
4946 pci_dev_unlock(dev);
4951 /* Do any devices on or below this slot prevent a bus reset? */
4952 static bool pci_slot_resetable(struct pci_slot *slot)
4954 struct pci_dev *dev;
4956 if (slot->bus->self &&
4957 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4960 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4961 if (!dev->slot || dev->slot != slot)
4963 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4964 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4971 /* Lock devices from the top of the tree down */
4972 static void pci_slot_lock(struct pci_slot *slot)
4974 struct pci_dev *dev;
4976 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4977 if (!dev->slot || dev->slot != slot)
4980 if (dev->subordinate)
4981 pci_bus_lock(dev->subordinate);
4985 /* Unlock devices from the bottom of the tree up */
4986 static void pci_slot_unlock(struct pci_slot *slot)
4988 struct pci_dev *dev;
4990 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4991 if (!dev->slot || dev->slot != slot)
4993 if (dev->subordinate)
4994 pci_bus_unlock(dev->subordinate);
4995 pci_dev_unlock(dev);
4999 /* Return 1 on successful lock, 0 on contention */
5000 static int pci_slot_trylock(struct pci_slot *slot)
5002 struct pci_dev *dev;
5004 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5005 if (!dev->slot || dev->slot != slot)
5007 if (!pci_dev_trylock(dev))
5009 if (dev->subordinate) {
5010 if (!pci_bus_trylock(dev->subordinate)) {
5011 pci_dev_unlock(dev);
5019 list_for_each_entry_continue_reverse(dev,
5020 &slot->bus->devices, bus_list) {
5021 if (!dev->slot || dev->slot != slot)
5023 if (dev->subordinate)
5024 pci_bus_unlock(dev->subordinate);
5025 pci_dev_unlock(dev);
5030 /* Save and disable devices from the top of the tree down */
5031 static void pci_bus_save_and_disable(struct pci_bus *bus)
5033 struct pci_dev *dev;
5035 list_for_each_entry(dev, &bus->devices, bus_list) {
5037 pci_dev_save_and_disable(dev);
5038 pci_dev_unlock(dev);
5039 if (dev->subordinate)
5040 pci_bus_save_and_disable(dev->subordinate);
5045 * Restore devices from top of the tree down - parent bridges need to be
5046 * restored before we can get to subordinate devices.
5048 static void pci_bus_restore(struct pci_bus *bus)
5050 struct pci_dev *dev;
5052 list_for_each_entry(dev, &bus->devices, bus_list) {
5054 pci_dev_restore(dev);
5055 pci_dev_unlock(dev);
5056 if (dev->subordinate)
5057 pci_bus_restore(dev->subordinate);
5061 /* Save and disable devices from the top of the tree down */
5062 static void pci_slot_save_and_disable(struct pci_slot *slot)
5064 struct pci_dev *dev;
5066 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5067 if (!dev->slot || dev->slot != slot)
5069 pci_dev_save_and_disable(dev);
5070 if (dev->subordinate)
5071 pci_bus_save_and_disable(dev->subordinate);
5076 * Restore devices from top of the tree down - parent bridges need to be
5077 * restored before we can get to subordinate devices.
5079 static void pci_slot_restore(struct pci_slot *slot)
5081 struct pci_dev *dev;
5083 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5084 if (!dev->slot || dev->slot != slot)
5087 pci_dev_restore(dev);
5088 pci_dev_unlock(dev);
5089 if (dev->subordinate)
5090 pci_bus_restore(dev->subordinate);
5094 static int pci_slot_reset(struct pci_slot *slot, int probe)
5098 if (!slot || !pci_slot_resetable(slot))
5102 pci_slot_lock(slot);
5106 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5109 pci_slot_unlock(slot);
5115 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5116 * @slot: PCI slot to probe
5118 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5120 int pci_probe_reset_slot(struct pci_slot *slot)
5122 return pci_slot_reset(slot, 1);
5124 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5127 * __pci_reset_slot - Try to reset a PCI slot
5128 * @slot: PCI slot to reset
5130 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5131 * independent of other slots. For instance, some slots may support slot power
5132 * control. In the case of a 1:1 bus to slot architecture, this function may
5133 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5134 * Generally a slot reset should be attempted before a bus reset. All of the
5135 * function of the slot and any subordinate buses behind the slot are reset
5136 * through this function. PCI config space of all devices in the slot and
5137 * behind the slot is saved before and restored after reset.
5139 * Same as above except return -EAGAIN if the slot cannot be locked
5141 static int __pci_reset_slot(struct pci_slot *slot)
5145 rc = pci_slot_reset(slot, 1);
5149 pci_slot_save_and_disable(slot);
5151 if (pci_slot_trylock(slot)) {
5153 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
5154 pci_slot_unlock(slot);
5158 pci_slot_restore(slot);
5163 static int pci_bus_reset(struct pci_bus *bus, int probe)
5167 if (!bus->self || !pci_bus_resetable(bus))
5177 ret = pci_bridge_secondary_bus_reset(bus->self);
5179 pci_bus_unlock(bus);
5185 * pci_bus_error_reset - reset the bridge's subordinate bus
5186 * @bridge: The parent device that connects to the bus to reset
5188 * This function will first try to reset the slots on this bus if the method is
5189 * available. If slot reset fails or is not available, this will fall back to a
5190 * secondary bus reset.
5192 int pci_bus_error_reset(struct pci_dev *bridge)
5194 struct pci_bus *bus = bridge->subordinate;
5195 struct pci_slot *slot;
5200 mutex_lock(&pci_slot_mutex);
5201 if (list_empty(&bus->slots))
5204 list_for_each_entry(slot, &bus->slots, list)
5205 if (pci_probe_reset_slot(slot))
5208 list_for_each_entry(slot, &bus->slots, list)
5209 if (pci_slot_reset(slot, 0))
5212 mutex_unlock(&pci_slot_mutex);
5215 mutex_unlock(&pci_slot_mutex);
5216 return pci_bus_reset(bridge->subordinate, 0);
5220 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5221 * @bus: PCI bus to probe
5223 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5225 int pci_probe_reset_bus(struct pci_bus *bus)
5227 return pci_bus_reset(bus, 1);
5229 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
5232 * __pci_reset_bus - Try to reset a PCI bus
5233 * @bus: top level PCI bus to reset
5235 * Same as above except return -EAGAIN if the bus cannot be locked
5237 static int __pci_reset_bus(struct pci_bus *bus)
5241 rc = pci_bus_reset(bus, 1);
5245 pci_bus_save_and_disable(bus);
5247 if (pci_bus_trylock(bus)) {
5249 rc = pci_bridge_secondary_bus_reset(bus->self);
5250 pci_bus_unlock(bus);
5254 pci_bus_restore(bus);
5260 * pci_reset_bus - Try to reset a PCI bus
5261 * @pdev: top level PCI device to reset via slot/bus
5263 * Same as above except return -EAGAIN if the bus cannot be locked
5265 int pci_reset_bus(struct pci_dev *pdev)
5267 return (!pci_probe_reset_slot(pdev->slot)) ?
5268 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
5270 EXPORT_SYMBOL_GPL(pci_reset_bus);
5273 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5274 * @dev: PCI device to query
5276 * Returns mmrbc: maximum designed memory read count in bytes
5277 * or appropriate error value.
5279 int pcix_get_max_mmrbc(struct pci_dev *dev)
5284 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5288 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5291 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5293 EXPORT_SYMBOL(pcix_get_max_mmrbc);
5296 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5297 * @dev: PCI device to query
5299 * Returns mmrbc: maximum memory read count in bytes
5300 * or appropriate error value.
5302 int pcix_get_mmrbc(struct pci_dev *dev)
5307 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5311 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5314 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5316 EXPORT_SYMBOL(pcix_get_mmrbc);
5319 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5320 * @dev: PCI device to query
5321 * @mmrbc: maximum memory read count in bytes
5322 * valid values are 512, 1024, 2048, 4096
5324 * If possible sets maximum memory read byte count, some bridges have erratas
5325 * that prevent this.
5327 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5333 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5336 v = ffs(mmrbc) - 10;
5338 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5342 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5345 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5348 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5351 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5353 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5356 cmd &= ~PCI_X_CMD_MAX_READ;
5358 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5363 EXPORT_SYMBOL(pcix_set_mmrbc);
5366 * pcie_get_readrq - get PCI Express read request size
5367 * @dev: PCI device to query
5369 * Returns maximum memory read request in bytes
5370 * or appropriate error value.
5372 int pcie_get_readrq(struct pci_dev *dev)
5376 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5378 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5380 EXPORT_SYMBOL(pcie_get_readrq);
5383 * pcie_set_readrq - set PCI Express maximum memory read request
5384 * @dev: PCI device to query
5385 * @rq: maximum memory read count in bytes
5386 * valid values are 128, 256, 512, 1024, 2048, 4096
5388 * If possible sets maximum memory read request in bytes
5390 int pcie_set_readrq(struct pci_dev *dev, int rq)
5394 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5398 * If using the "performance" PCIe config, we clamp the
5399 * read rq size to the max packet size to prevent the
5400 * host bridge generating requests larger than we can
5403 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5404 int mps = pcie_get_mps(dev);
5410 v = (ffs(rq) - 8) << 12;
5412 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5413 PCI_EXP_DEVCTL_READRQ, v);
5415 EXPORT_SYMBOL(pcie_set_readrq);
5418 * pcie_get_mps - get PCI Express maximum payload size
5419 * @dev: PCI device to query
5421 * Returns maximum payload size in bytes
5423 int pcie_get_mps(struct pci_dev *dev)
5427 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5429 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5431 EXPORT_SYMBOL(pcie_get_mps);
5434 * pcie_set_mps - set PCI Express maximum payload size
5435 * @dev: PCI device to query
5436 * @mps: maximum payload size in bytes
5437 * valid values are 128, 256, 512, 1024, 2048, 4096
5439 * If possible sets maximum payload size
5441 int pcie_set_mps(struct pci_dev *dev, int mps)
5445 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
5449 if (v > dev->pcie_mpss)
5453 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5454 PCI_EXP_DEVCTL_PAYLOAD, v);
5456 EXPORT_SYMBOL(pcie_set_mps);
5459 * pcie_bandwidth_available - determine minimum link settings of a PCIe
5460 * device and its bandwidth limitation
5461 * @dev: PCI device to query
5462 * @limiting_dev: storage for device causing the bandwidth limitation
5463 * @speed: storage for speed of limiting device
5464 * @width: storage for width of limiting device
5466 * Walk up the PCI device chain and find the point where the minimum
5467 * bandwidth is available. Return the bandwidth available there and (if
5468 * limiting_dev, speed, and width pointers are supplied) information about
5469 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
5472 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
5473 enum pci_bus_speed *speed,
5474 enum pcie_link_width *width)
5477 enum pci_bus_speed next_speed;
5478 enum pcie_link_width next_width;
5482 *speed = PCI_SPEED_UNKNOWN;
5484 *width = PCIE_LNK_WIDTH_UNKNOWN;
5489 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
5491 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
5492 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
5493 PCI_EXP_LNKSTA_NLW_SHIFT;
5495 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
5497 /* Check if current device limits the total bandwidth */
5498 if (!bw || next_bw <= bw) {
5502 *limiting_dev = dev;
5504 *speed = next_speed;
5506 *width = next_width;
5509 dev = pci_upstream_bridge(dev);
5514 EXPORT_SYMBOL(pcie_bandwidth_available);
5517 * pcie_get_speed_cap - query for the PCI device's link speed capability
5518 * @dev: PCI device to query
5520 * Query the PCI device speed capability. Return the maximum link speed
5521 * supported by the device.
5523 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
5525 u32 lnkcap2, lnkcap;
5528 * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link
5529 * Speeds Vector in Link Capabilities 2 when supported, falling
5530 * back to Max Link Speed in Link Capabilities otherwise.
5532 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
5533 if (lnkcap2) { /* PCIe r3.0-compliant */
5534 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
5535 return PCIE_SPEED_16_0GT;
5536 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
5537 return PCIE_SPEED_8_0GT;
5538 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
5539 return PCIE_SPEED_5_0GT;
5540 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
5541 return PCIE_SPEED_2_5GT;
5542 return PCI_SPEED_UNKNOWN;
5545 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5547 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
5548 return PCIE_SPEED_16_0GT;
5549 else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
5550 return PCIE_SPEED_8_0GT;
5551 else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
5552 return PCIE_SPEED_5_0GT;
5553 else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
5554 return PCIE_SPEED_2_5GT;
5557 return PCI_SPEED_UNKNOWN;
5559 EXPORT_SYMBOL(pcie_get_speed_cap);
5562 * pcie_get_width_cap - query for the PCI device's link width capability
5563 * @dev: PCI device to query
5565 * Query the PCI device width capability. Return the maximum link width
5566 * supported by the device.
5568 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
5572 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5574 return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
5576 return PCIE_LNK_WIDTH_UNKNOWN;
5578 EXPORT_SYMBOL(pcie_get_width_cap);
5581 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
5583 * @speed: storage for link speed
5584 * @width: storage for link width
5586 * Calculate a PCI device's link bandwidth by querying for its link speed
5587 * and width, multiplying them, and applying encoding overhead. The result
5588 * is in Mb/s, i.e., megabits/second of raw bandwidth.
5590 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
5591 enum pcie_link_width *width)
5593 *speed = pcie_get_speed_cap(dev);
5594 *width = pcie_get_width_cap(dev);
5596 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
5599 return *width * PCIE_SPEED2MBS_ENC(*speed);
5603 * __pcie_print_link_status - Report the PCI device's link speed and width
5604 * @dev: PCI device to query
5605 * @verbose: Print info even when enough bandwidth is available
5607 * If the available bandwidth at the device is less than the device is
5608 * capable of, report the device's maximum possible bandwidth and the
5609 * upstream link that limits its performance. If @verbose, always print
5610 * the available bandwidth, even if the device isn't constrained.
5612 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
5614 enum pcie_link_width width, width_cap;
5615 enum pci_bus_speed speed, speed_cap;
5616 struct pci_dev *limiting_dev = NULL;
5617 u32 bw_avail, bw_cap;
5619 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
5620 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
5622 if (bw_avail >= bw_cap && verbose)
5623 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
5624 bw_cap / 1000, bw_cap % 1000,
5625 PCIE_SPEED2STR(speed_cap), width_cap);
5626 else if (bw_avail < bw_cap)
5627 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
5628 bw_avail / 1000, bw_avail % 1000,
5629 PCIE_SPEED2STR(speed), width,
5630 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
5631 bw_cap / 1000, bw_cap % 1000,
5632 PCIE_SPEED2STR(speed_cap), width_cap);
5636 * pcie_print_link_status - Report the PCI device's link speed and width
5637 * @dev: PCI device to query
5639 * Report the available bandwidth at the device.
5641 void pcie_print_link_status(struct pci_dev *dev)
5643 __pcie_print_link_status(dev, true);
5645 EXPORT_SYMBOL(pcie_print_link_status);
5648 * pci_select_bars - Make BAR mask from the type of resource
5649 * @dev: the PCI device for which BAR mask is made
5650 * @flags: resource type mask to be selected
5652 * This helper routine makes bar mask from the type of resource.
5654 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
5657 for (i = 0; i < PCI_NUM_RESOURCES; i++)
5658 if (pci_resource_flags(dev, i) & flags)
5662 EXPORT_SYMBOL(pci_select_bars);
5664 /* Some architectures require additional programming to enable VGA */
5665 static arch_set_vga_state_t arch_set_vga_state;
5667 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
5669 arch_set_vga_state = func; /* NULL disables */
5672 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
5673 unsigned int command_bits, u32 flags)
5675 if (arch_set_vga_state)
5676 return arch_set_vga_state(dev, decode, command_bits,
5682 * pci_set_vga_state - set VGA decode state on device and parents if requested
5683 * @dev: the PCI device
5684 * @decode: true = enable decoding, false = disable decoding
5685 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
5686 * @flags: traverse ancestors and change bridges
5687 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
5689 int pci_set_vga_state(struct pci_dev *dev, bool decode,
5690 unsigned int command_bits, u32 flags)
5692 struct pci_bus *bus;
5693 struct pci_dev *bridge;
5697 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
5699 /* ARCH specific VGA enables */
5700 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
5704 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
5705 pci_read_config_word(dev, PCI_COMMAND, &cmd);
5707 cmd |= command_bits;
5709 cmd &= ~command_bits;
5710 pci_write_config_word(dev, PCI_COMMAND, cmd);
5713 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
5720 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
5723 cmd |= PCI_BRIDGE_CTL_VGA;
5725 cmd &= ~PCI_BRIDGE_CTL_VGA;
5726 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
5735 * pci_add_dma_alias - Add a DMA devfn alias for a device
5736 * @dev: the PCI device for which alias is added
5737 * @devfn: alias slot and function
5739 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
5740 * which is used to program permissible bus-devfn source addresses for DMA
5741 * requests in an IOMMU. These aliases factor into IOMMU group creation
5742 * and are useful for devices generating DMA requests beyond or different
5743 * from their logical bus-devfn. Examples include device quirks where the
5744 * device simply uses the wrong devfn, as well as non-transparent bridges
5745 * where the alias may be a proxy for devices in another domain.
5747 * IOMMU group creation is performed during device discovery or addition,
5748 * prior to any potential DMA mapping and therefore prior to driver probing
5749 * (especially for userspace assigned devices where IOMMU group definition
5750 * cannot be left as a userspace activity). DMA aliases should therefore
5751 * be configured via quirks, such as the PCI fixup header quirk.
5753 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
5755 if (!dev->dma_alias_mask)
5756 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
5757 sizeof(long), GFP_KERNEL);
5758 if (!dev->dma_alias_mask) {
5759 pci_warn(dev, "Unable to allocate DMA alias mask\n");
5763 set_bit(devfn, dev->dma_alias_mask);
5764 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
5765 PCI_SLOT(devfn), PCI_FUNC(devfn));
5768 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
5770 return (dev1->dma_alias_mask &&
5771 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
5772 (dev2->dma_alias_mask &&
5773 test_bit(dev1->devfn, dev2->dma_alias_mask));
5776 bool pci_device_is_present(struct pci_dev *pdev)
5780 if (pci_dev_is_disconnected(pdev))
5782 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
5784 EXPORT_SYMBOL_GPL(pci_device_is_present);
5786 void pci_ignore_hotplug(struct pci_dev *dev)
5788 struct pci_dev *bridge = dev->bus->self;
5790 dev->ignore_hotplug = 1;
5791 /* Propagate the "ignore hotplug" setting to the parent bridge. */
5793 bridge->ignore_hotplug = 1;
5795 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
5797 resource_size_t __weak pcibios_default_alignment(void)
5802 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
5803 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
5804 static DEFINE_SPINLOCK(resource_alignment_lock);
5807 * pci_specified_resource_alignment - get resource alignment specified by user.
5808 * @dev: the PCI device to get
5809 * @resize: whether or not to change resources' size when reassigning alignment
5811 * RETURNS: Resource alignment if it is specified.
5812 * Zero if it is not specified.
5814 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
5817 int align_order, count;
5818 resource_size_t align = pcibios_default_alignment();
5822 spin_lock(&resource_alignment_lock);
5823 p = resource_alignment_param;
5826 if (pci_has_flag(PCI_PROBE_ONLY)) {
5828 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
5834 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
5841 ret = pci_dev_str_match(dev, p, &p);
5844 if (align_order == -1)
5847 align = 1 << align_order;
5849 } else if (ret < 0) {
5850 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
5855 if (*p != ';' && *p != ',') {
5856 /* End of param or invalid format */
5862 spin_unlock(&resource_alignment_lock);
5866 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
5867 resource_size_t align, bool resize)
5869 struct resource *r = &dev->resource[bar];
5870 resource_size_t size;
5872 if (!(r->flags & IORESOURCE_MEM))
5875 if (r->flags & IORESOURCE_PCI_FIXED) {
5876 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
5877 bar, r, (unsigned long long)align);
5881 size = resource_size(r);
5886 * Increase the alignment of the resource. There are two ways we
5889 * 1) Increase the size of the resource. BARs are aligned on their
5890 * size, so when we reallocate space for this resource, we'll
5891 * allocate it with the larger alignment. This also prevents
5892 * assignment of any other BARs inside the alignment region, so
5893 * if we're requesting page alignment, this means no other BARs
5894 * will share the page.
5896 * The disadvantage is that this makes the resource larger than
5897 * the hardware BAR, which may break drivers that compute things
5898 * based on the resource size, e.g., to find registers at a
5899 * fixed offset before the end of the BAR.
5901 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
5902 * set r->start to the desired alignment. By itself this
5903 * doesn't prevent other BARs being put inside the alignment
5904 * region, but if we realign *every* resource of every device in
5905 * the system, none of them will share an alignment region.
5907 * When the user has requested alignment for only some devices via
5908 * the "pci=resource_alignment" argument, "resize" is true and we
5909 * use the first method. Otherwise we assume we're aligning all
5910 * devices and we use the second.
5913 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
5914 bar, r, (unsigned long long)align);
5920 r->flags &= ~IORESOURCE_SIZEALIGN;
5921 r->flags |= IORESOURCE_STARTALIGN;
5923 r->end = r->start + size - 1;
5925 r->flags |= IORESOURCE_UNSET;
5929 * This function disables memory decoding and releases memory resources
5930 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5931 * It also rounds up size to specified alignment.
5932 * Later on, the kernel will assign page-aligned memory resource back
5935 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
5939 resource_size_t align;
5941 bool resize = false;
5944 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
5945 * 3.4.1.11. Their resources are allocated from the space
5946 * described by the VF BARx register in the PF's SR-IOV capability.
5947 * We can't influence their alignment here.
5952 /* check if specified PCI is target device to reassign */
5953 align = pci_specified_resource_alignment(dev, &resize);
5957 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
5958 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
5959 pci_warn(dev, "Can't reassign resources to host bridge\n");
5963 pci_read_config_word(dev, PCI_COMMAND, &command);
5964 command &= ~PCI_COMMAND_MEMORY;
5965 pci_write_config_word(dev, PCI_COMMAND, command);
5967 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
5968 pci_request_resource_alignment(dev, i, align, resize);
5971 * Need to disable bridge's resource window,
5972 * to enable the kernel to reassign new resource
5975 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
5976 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
5977 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
5978 r = &dev->resource[i];
5979 if (!(r->flags & IORESOURCE_MEM))
5981 r->flags |= IORESOURCE_UNSET;
5982 r->end = resource_size(r) - 1;
5985 pci_disable_bridge_window(dev);
5989 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
5991 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
5992 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
5993 spin_lock(&resource_alignment_lock);
5994 strncpy(resource_alignment_param, buf, count);
5995 resource_alignment_param[count] = '\0';
5996 spin_unlock(&resource_alignment_lock);
6000 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
6003 spin_lock(&resource_alignment_lock);
6004 count = snprintf(buf, size, "%s", resource_alignment_param);
6005 spin_unlock(&resource_alignment_lock);
6009 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
6011 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
6014 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
6015 const char *buf, size_t count)
6017 return pci_set_resource_alignment_param(buf, count);
6020 static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
6021 pci_resource_alignment_store);
6023 static int __init pci_resource_alignment_sysfs_init(void)
6025 return bus_create_file(&pci_bus_type,
6026 &bus_attr_resource_alignment);
6028 late_initcall(pci_resource_alignment_sysfs_init);
6030 static void pci_no_domains(void)
6032 #ifdef CONFIG_PCI_DOMAINS
6033 pci_domains_supported = 0;
6037 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6038 static atomic_t __domain_nr = ATOMIC_INIT(-1);
6040 static int pci_get_new_domain_nr(void)
6042 return atomic_inc_return(&__domain_nr);
6045 static int of_pci_bus_find_domain_nr(struct device *parent)
6047 static int use_dt_domains = -1;
6051 domain = of_get_pci_domain_nr(parent->of_node);
6053 * Check DT domain and use_dt_domains values.
6055 * If DT domain property is valid (domain >= 0) and
6056 * use_dt_domains != 0, the DT assignment is valid since this means
6057 * we have not previously allocated a domain number by using
6058 * pci_get_new_domain_nr(); we should also update use_dt_domains to
6059 * 1, to indicate that we have just assigned a domain number from
6062 * If DT domain property value is not valid (ie domain < 0), and we
6063 * have not previously assigned a domain number from DT
6064 * (use_dt_domains != 1) we should assign a domain number by
6067 * pci_get_new_domain_nr()
6069 * API and update the use_dt_domains value to keep track of method we
6070 * are using to assign domain numbers (use_dt_domains = 0).
6072 * All other combinations imply we have a platform that is trying
6073 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
6074 * which is a recipe for domain mishandling and it is prevented by
6075 * invalidating the domain value (domain = -1) and printing a
6076 * corresponding error.
6078 if (domain >= 0 && use_dt_domains) {
6080 } else if (domain < 0 && use_dt_domains != 1) {
6082 domain = pci_get_new_domain_nr();
6085 pr_err("Node %pOF has ", parent->of_node);
6086 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
6093 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
6095 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
6096 acpi_pci_bus_find_domain_nr(bus);
6101 * pci_ext_cfg_avail - can we access extended PCI config space?
6103 * Returns 1 if we can access PCI extended config space (offsets
6104 * greater than 0xff). This is the default implementation. Architecture
6105 * implementations can override this.
6107 int __weak pci_ext_cfg_avail(void)
6112 void __weak pci_fixup_cardbus(struct pci_bus *bus)
6115 EXPORT_SYMBOL(pci_fixup_cardbus);
6117 static int __init pci_setup(char *str)
6120 char *k = strchr(str, ',');
6123 if (*str && (str = pcibios_setup(str)) && *str) {
6124 if (!strcmp(str, "nomsi")) {
6126 } else if (!strncmp(str, "noats", 5)) {
6127 pr_info("PCIe: ATS is disabled\n");
6128 pcie_ats_disabled = true;
6129 } else if (!strcmp(str, "noaer")) {
6131 } else if (!strcmp(str, "earlydump")) {
6132 pci_early_dump = true;
6133 } else if (!strncmp(str, "realloc=", 8)) {
6134 pci_realloc_get_opt(str + 8);
6135 } else if (!strncmp(str, "realloc", 7)) {
6136 pci_realloc_get_opt("on");
6137 } else if (!strcmp(str, "nodomains")) {
6139 } else if (!strncmp(str, "noari", 5)) {
6140 pcie_ari_disabled = true;
6141 } else if (!strncmp(str, "cbiosize=", 9)) {
6142 pci_cardbus_io_size = memparse(str + 9, &str);
6143 } else if (!strncmp(str, "cbmemsize=", 10)) {
6144 pci_cardbus_mem_size = memparse(str + 10, &str);
6145 } else if (!strncmp(str, "resource_alignment=", 19)) {
6146 pci_set_resource_alignment_param(str + 19,
6148 } else if (!strncmp(str, "ecrc=", 5)) {
6149 pcie_ecrc_get_policy(str + 5);
6150 } else if (!strncmp(str, "hpiosize=", 9)) {
6151 pci_hotplug_io_size = memparse(str + 9, &str);
6152 } else if (!strncmp(str, "hpmemsize=", 10)) {
6153 pci_hotplug_mem_size = memparse(str + 10, &str);
6154 } else if (!strncmp(str, "hpbussize=", 10)) {
6155 pci_hotplug_bus_size =
6156 simple_strtoul(str + 10, &str, 0);
6157 if (pci_hotplug_bus_size > 0xff)
6158 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
6159 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
6160 pcie_bus_config = PCIE_BUS_TUNE_OFF;
6161 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
6162 pcie_bus_config = PCIE_BUS_SAFE;
6163 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
6164 pcie_bus_config = PCIE_BUS_PERFORMANCE;
6165 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
6166 pcie_bus_config = PCIE_BUS_PEER2PEER;
6167 } else if (!strncmp(str, "pcie_scan_all", 13)) {
6168 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
6169 } else if (!strncmp(str, "disable_acs_redir=", 18)) {
6170 disable_acs_redir_param = str + 18;
6172 printk(KERN_ERR "PCI: Unknown option `%s'\n",
6180 early_param("pci", pci_setup);