1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
17 #include <linux/of_pci.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pci-aspm.h>
27 #include <linux/pm_wakeup.h>
28 #include <linux/interrupt.h>
29 #include <linux/device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/pci_hotplug.h>
32 #include <linux/vmalloc.h>
33 #include <linux/pci-ats.h>
34 #include <asm/setup.h>
36 #include <linux/aer.h>
39 const char *pci_power_names[] = {
40 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
42 EXPORT_SYMBOL_GPL(pci_power_names);
44 int isa_dma_bridge_buggy;
45 EXPORT_SYMBOL(isa_dma_bridge_buggy);
48 EXPORT_SYMBOL(pci_pci_problems);
50 unsigned int pci_pm_d3_delay;
52 static void pci_pme_list_scan(struct work_struct *work);
54 static LIST_HEAD(pci_pme_list);
55 static DEFINE_MUTEX(pci_pme_list_mutex);
56 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
58 struct pci_pme_device {
59 struct list_head list;
63 #define PME_TIMEOUT 1000 /* How long between PME checks */
65 static void pci_dev_d3_sleep(struct pci_dev *dev)
67 unsigned int delay = dev->d3_delay;
69 if (delay < pci_pm_d3_delay)
70 delay = pci_pm_d3_delay;
76 #ifdef CONFIG_PCI_DOMAINS
77 int pci_domains_supported = 1;
80 #define DEFAULT_CARDBUS_IO_SIZE (256)
81 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
82 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
83 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
84 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
86 #define DEFAULT_HOTPLUG_IO_SIZE (256)
87 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
88 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
89 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
90 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
92 #define DEFAULT_HOTPLUG_BUS_SIZE 1
93 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
95 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
98 * The default CLS is used if arch didn't set CLS explicitly and not
99 * all pci devices agree on the same value. Arch can override either
100 * the dfl or actual value as it sees fit. Don't forget this is
101 * measured in 32-bit words, not bytes.
103 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
104 u8 pci_cache_line_size;
107 * If we set up a device for bus mastering, we need to check the latency
108 * timer as certain BIOSes forget to set it properly.
110 unsigned int pcibios_max_latency = 255;
112 /* If set, the PCIe ARI capability will not be used. */
113 static bool pcie_ari_disabled;
115 /* If set, the PCIe ATS capability will not be used. */
116 static bool pcie_ats_disabled;
118 bool pci_ats_disabled(void)
120 return pcie_ats_disabled;
123 /* Disable bridge_d3 for all PCIe ports */
124 static bool pci_bridge_d3_disable;
125 /* Force bridge_d3 for all PCIe ports */
126 static bool pci_bridge_d3_force;
128 static int __init pcie_port_pm_setup(char *str)
130 if (!strcmp(str, "off"))
131 pci_bridge_d3_disable = true;
132 else if (!strcmp(str, "force"))
133 pci_bridge_d3_force = true;
136 __setup("pcie_port_pm=", pcie_port_pm_setup);
138 /* Time to wait after a reset for device to become responsive */
139 #define PCIE_RESET_READY_POLL_MS 60000
142 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
143 * @bus: pointer to PCI bus structure to search
145 * Given a PCI bus, returns the highest PCI bus number present in the set
146 * including the given PCI bus and its list of child PCI buses.
148 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
151 unsigned char max, n;
153 max = bus->busn_res.end;
154 list_for_each_entry(tmp, &bus->children, node) {
155 n = pci_bus_max_busnr(tmp);
161 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
163 #ifdef CONFIG_HAS_IOMEM
164 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
166 struct resource *res = &pdev->resource[bar];
169 * Make sure the BAR is actually a memory resource, not an IO resource
171 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
172 pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
175 return ioremap_nocache(res->start, resource_size(res));
177 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
179 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
182 * Make sure the BAR is actually a memory resource, not an IO resource
184 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
188 return ioremap_wc(pci_resource_start(pdev, bar),
189 pci_resource_len(pdev, bar));
191 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
195 * pci_dev_str_match_path - test if a path string matches a device
196 * @dev: the PCI device to test
197 * @p: string to match the device against
198 * @endptr: pointer to the string after the match
200 * Test if a string (typically from a kernel parameter) formatted as a
201 * path of device/function addresses matches a PCI device. The string must
204 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
206 * A path for a device can be obtained using 'lspci -t'. Using a path
207 * is more robust against bus renumbering than using only a single bus,
208 * device and function address.
210 * Returns 1 if the string matches the device, 0 if it does not and
211 * a negative error code if it fails to parse the string.
213 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
217 int seg, bus, slot, func;
221 *endptr = strchrnul(path, ';');
223 wpath = kmemdup_nul(path, *endptr - path, GFP_KERNEL);
228 p = strrchr(wpath, '/');
231 ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
237 if (dev->devfn != PCI_DEVFN(slot, func)) {
243 * Note: we don't need to get a reference to the upstream
244 * bridge because we hold a reference to the top level
245 * device which should hold a reference to the bridge,
248 dev = pci_upstream_bridge(dev);
257 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
261 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
268 ret = (seg == pci_domain_nr(dev->bus) &&
269 bus == dev->bus->number &&
270 dev->devfn == PCI_DEVFN(slot, func));
278 * pci_dev_str_match - test if a string matches a device
279 * @dev: the PCI device to test
280 * @p: string to match the device against
281 * @endptr: pointer to the string after the match
283 * Test if a string (typically from a kernel parameter) matches a specified
284 * PCI device. The string may be of one of the following formats:
286 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
287 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
289 * The first format specifies a PCI bus/device/function address which
290 * may change if new hardware is inserted, if motherboard firmware changes,
291 * or due to changes caused in kernel parameters. If the domain is
292 * left unspecified, it is taken to be 0. In order to be robust against
293 * bus renumbering issues, a path of PCI device/function numbers may be used
294 * to address the specific device. The path for a device can be determined
295 * through the use of 'lspci -t'.
297 * The second format matches devices using IDs in the configuration
298 * space which may match multiple devices in the system. A value of 0
299 * for any field will match all devices. (Note: this differs from
300 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
301 * legacy reasons and convenience so users don't have to specify
302 * FFFFFFFFs on the command line.)
304 * Returns 1 if the string matches the device, 0 if it does not and
305 * a negative error code if the string cannot be parsed.
307 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
312 unsigned short vendor, device, subsystem_vendor, subsystem_device;
314 if (strncmp(p, "pci:", 4) == 0) {
315 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
317 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
318 &subsystem_vendor, &subsystem_device, &count);
320 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
324 subsystem_vendor = 0;
325 subsystem_device = 0;
330 if ((!vendor || vendor == dev->vendor) &&
331 (!device || device == dev->device) &&
332 (!subsystem_vendor ||
333 subsystem_vendor == dev->subsystem_vendor) &&
334 (!subsystem_device ||
335 subsystem_device == dev->subsystem_device))
339 * PCI Bus, Device, Function IDs are specified
340 * (optionally, may include a path of devfns following it)
342 ret = pci_dev_str_match_path(dev, p, &p);
357 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
358 u8 pos, int cap, int *ttl)
363 pci_bus_read_config_byte(bus, devfn, pos, &pos);
369 pci_bus_read_config_word(bus, devfn, pos, &ent);
381 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
384 int ttl = PCI_FIND_CAP_TTL;
386 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
389 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
391 return __pci_find_next_cap(dev->bus, dev->devfn,
392 pos + PCI_CAP_LIST_NEXT, cap);
394 EXPORT_SYMBOL_GPL(pci_find_next_capability);
396 static int __pci_bus_find_cap_start(struct pci_bus *bus,
397 unsigned int devfn, u8 hdr_type)
401 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
402 if (!(status & PCI_STATUS_CAP_LIST))
406 case PCI_HEADER_TYPE_NORMAL:
407 case PCI_HEADER_TYPE_BRIDGE:
408 return PCI_CAPABILITY_LIST;
409 case PCI_HEADER_TYPE_CARDBUS:
410 return PCI_CB_CAPABILITY_LIST;
417 * pci_find_capability - query for devices' capabilities
418 * @dev: PCI device to query
419 * @cap: capability code
421 * Tell if a device supports a given PCI capability.
422 * Returns the address of the requested capability structure within the
423 * device's PCI configuration space or 0 in case the device does not
424 * support it. Possible values for @cap:
426 * %PCI_CAP_ID_PM Power Management
427 * %PCI_CAP_ID_AGP Accelerated Graphics Port
428 * %PCI_CAP_ID_VPD Vital Product Data
429 * %PCI_CAP_ID_SLOTID Slot Identification
430 * %PCI_CAP_ID_MSI Message Signalled Interrupts
431 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
432 * %PCI_CAP_ID_PCIX PCI-X
433 * %PCI_CAP_ID_EXP PCI Express
435 int pci_find_capability(struct pci_dev *dev, int cap)
439 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
441 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
445 EXPORT_SYMBOL(pci_find_capability);
448 * pci_bus_find_capability - query for devices' capabilities
449 * @bus: the PCI bus to query
450 * @devfn: PCI device to query
451 * @cap: capability code
453 * Like pci_find_capability() but works for pci devices that do not have a
454 * pci_dev structure set up yet.
456 * Returns the address of the requested capability structure within the
457 * device's PCI configuration space or 0 in case the device does not
460 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
465 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
467 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
469 pos = __pci_find_next_cap(bus, devfn, pos, cap);
473 EXPORT_SYMBOL(pci_bus_find_capability);
476 * pci_find_next_ext_capability - Find an extended capability
477 * @dev: PCI device to query
478 * @start: address at which to start looking (0 to start at beginning of list)
479 * @cap: capability code
481 * Returns the address of the next matching extended capability structure
482 * within the device's PCI configuration space or 0 if the device does
483 * not support it. Some capabilities can occur several times, e.g., the
484 * vendor-specific capability, and this provides a way to find them all.
486 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
490 int pos = PCI_CFG_SPACE_SIZE;
492 /* minimum 8 bytes per capability */
493 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
495 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
501 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
505 * If we have no capabilities, this is indicated by cap ID,
506 * cap version and next pointer all being 0.
512 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
515 pos = PCI_EXT_CAP_NEXT(header);
516 if (pos < PCI_CFG_SPACE_SIZE)
519 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
525 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
528 * pci_find_ext_capability - Find an extended capability
529 * @dev: PCI device to query
530 * @cap: capability code
532 * Returns the address of the requested extended capability structure
533 * within the device's PCI configuration space or 0 if the device does
534 * not support it. Possible values for @cap:
536 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
537 * %PCI_EXT_CAP_ID_VC Virtual Channel
538 * %PCI_EXT_CAP_ID_DSN Device Serial Number
539 * %PCI_EXT_CAP_ID_PWR Power Budgeting
541 int pci_find_ext_capability(struct pci_dev *dev, int cap)
543 return pci_find_next_ext_capability(dev, 0, cap);
545 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
547 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
549 int rc, ttl = PCI_FIND_CAP_TTL;
552 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
553 mask = HT_3BIT_CAP_MASK;
555 mask = HT_5BIT_CAP_MASK;
557 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
558 PCI_CAP_ID_HT, &ttl);
560 rc = pci_read_config_byte(dev, pos + 3, &cap);
561 if (rc != PCIBIOS_SUCCESSFUL)
564 if ((cap & mask) == ht_cap)
567 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
568 pos + PCI_CAP_LIST_NEXT,
569 PCI_CAP_ID_HT, &ttl);
575 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
576 * @dev: PCI device to query
577 * @pos: Position from which to continue searching
578 * @ht_cap: Hypertransport capability code
580 * To be used in conjunction with pci_find_ht_capability() to search for
581 * all capabilities matching @ht_cap. @pos should always be a value returned
582 * from pci_find_ht_capability().
584 * NB. To be 100% safe against broken PCI devices, the caller should take
585 * steps to avoid an infinite loop.
587 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
589 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
591 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
594 * pci_find_ht_capability - query a device's Hypertransport capabilities
595 * @dev: PCI device to query
596 * @ht_cap: Hypertransport capability code
598 * Tell if a device supports a given Hypertransport capability.
599 * Returns an address within the device's PCI configuration space
600 * or 0 in case the device does not support the request capability.
601 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
602 * which has a Hypertransport capability matching @ht_cap.
604 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
608 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
610 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
614 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
617 * pci_find_parent_resource - return resource region of parent bus of given region
618 * @dev: PCI device structure contains resources to be searched
619 * @res: child resource record for which parent is sought
621 * For given resource region of given device, return the resource
622 * region of parent bus the given region is contained in.
624 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
625 struct resource *res)
627 const struct pci_bus *bus = dev->bus;
631 pci_bus_for_each_resource(bus, r, i) {
634 if (resource_contains(r, res)) {
637 * If the window is prefetchable but the BAR is
638 * not, the allocator made a mistake.
640 if (r->flags & IORESOURCE_PREFETCH &&
641 !(res->flags & IORESOURCE_PREFETCH))
645 * If we're below a transparent bridge, there may
646 * be both a positively-decoded aperture and a
647 * subtractively-decoded region that contain the BAR.
648 * We want the positively-decoded one, so this depends
649 * on pci_bus_for_each_resource() giving us those
657 EXPORT_SYMBOL(pci_find_parent_resource);
660 * pci_find_resource - Return matching PCI device resource
661 * @dev: PCI device to query
662 * @res: Resource to look for
664 * Goes over standard PCI resources (BARs) and checks if the given resource
665 * is partially or fully contained in any of them. In that case the
666 * matching resource is returned, %NULL otherwise.
668 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
672 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
673 struct resource *r = &dev->resource[i];
675 if (r->start && resource_contains(r, res))
681 EXPORT_SYMBOL(pci_find_resource);
684 * pci_find_pcie_root_port - return PCIe Root Port
685 * @dev: PCI device to query
687 * Traverse up the parent chain and return the PCIe Root Port PCI Device
688 * for a given PCI Device.
690 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
692 struct pci_dev *bridge, *highest_pcie_bridge = dev;
694 bridge = pci_upstream_bridge(dev);
695 while (bridge && pci_is_pcie(bridge)) {
696 highest_pcie_bridge = bridge;
697 bridge = pci_upstream_bridge(bridge);
700 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
703 return highest_pcie_bridge;
705 EXPORT_SYMBOL(pci_find_pcie_root_port);
708 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
709 * @dev: the PCI device to operate on
710 * @pos: config space offset of status word
711 * @mask: mask of bit(s) to care about in status word
713 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
715 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
719 /* Wait for Transaction Pending bit clean */
720 for (i = 0; i < 4; i++) {
723 msleep((1 << (i - 1)) * 100);
725 pci_read_config_word(dev, pos, &status);
726 if (!(status & mask))
734 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
735 * @dev: PCI device to have its BARs restored
737 * Restore the BAR values for a given device, so as to make it
738 * accessible by its driver.
740 static void pci_restore_bars(struct pci_dev *dev)
744 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
745 pci_update_resource(dev, i);
748 static const struct pci_platform_pm_ops *pci_platform_pm;
750 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
752 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
753 !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
755 pci_platform_pm = ops;
759 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
761 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
764 static inline int platform_pci_set_power_state(struct pci_dev *dev,
767 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
770 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
772 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
775 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
777 return pci_platform_pm ?
778 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
781 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
783 return pci_platform_pm ?
784 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
787 static inline bool platform_pci_need_resume(struct pci_dev *dev)
789 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
793 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
795 * @dev: PCI device to handle.
796 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
799 * -EINVAL if the requested state is invalid.
800 * -EIO if device does not support PCI PM or its PM capabilities register has a
801 * wrong version, or device doesn't support the requested state.
802 * 0 if device already is in the requested state.
803 * 0 if device's power state has been successfully changed.
805 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
808 bool need_restore = false;
810 /* Check if we're already there */
811 if (dev->current_state == state)
817 if (state < PCI_D0 || state > PCI_D3hot)
820 /* Validate current state:
821 * Can enter D0 from any state, but if we can only go deeper
822 * to sleep if we're already in a low power state
824 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
825 && dev->current_state > state) {
826 pci_err(dev, "invalid power transition (from state %d to %d)\n",
827 dev->current_state, state);
831 /* check if this device supports the desired state */
832 if ((state == PCI_D1 && !dev->d1_support)
833 || (state == PCI_D2 && !dev->d2_support))
836 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
838 /* If we're (effectively) in D3, force entire word to 0.
839 * This doesn't affect PME_Status, disables PME_En, and
840 * sets PowerState to 0.
842 switch (dev->current_state) {
846 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
851 case PCI_UNKNOWN: /* Boot-up */
852 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
853 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
855 /* Fall-through: force to D0 */
861 /* enter specified state */
862 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
864 /* Mandatory power management transition delays */
865 /* see PCI PM 1.1 5.6.1 table 18 */
866 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
867 pci_dev_d3_sleep(dev);
868 else if (state == PCI_D2 || dev->current_state == PCI_D2)
869 udelay(PCI_PM_D2_DELAY);
871 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
872 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
873 if (dev->current_state != state && printk_ratelimit())
874 pci_info(dev, "Refused to change power state, currently in D%d\n",
878 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
879 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
880 * from D3hot to D0 _may_ perform an internal reset, thereby
881 * going to "D0 Uninitialized" rather than "D0 Initialized".
882 * For example, at least some versions of the 3c905B and the
883 * 3c556B exhibit this behaviour.
885 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
886 * devices in a D3hot state at boot. Consequently, we need to
887 * restore at least the BARs so that the device will be
888 * accessible to its driver.
891 pci_restore_bars(dev);
894 pcie_aspm_pm_state_change(dev->bus->self);
900 * pci_update_current_state - Read power state of given device and cache it
901 * @dev: PCI device to handle.
902 * @state: State to cache in case the device doesn't have the PM capability
904 * The power state is read from the PMCSR register, which however is
905 * inaccessible in D3cold. The platform firmware is therefore queried first
906 * to detect accessibility of the register. In case the platform firmware
907 * reports an incorrect state or the device isn't power manageable by the
908 * platform at all, we try to detect D3cold by testing accessibility of the
909 * vendor ID in config space.
911 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
913 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
914 !pci_device_is_present(dev)) {
915 dev->current_state = PCI_D3cold;
916 } else if (dev->pm_cap) {
919 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
920 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
922 dev->current_state = state;
927 * pci_power_up - Put the given device into D0 forcibly
928 * @dev: PCI device to power up
930 void pci_power_up(struct pci_dev *dev)
932 if (platform_pci_power_manageable(dev))
933 platform_pci_set_power_state(dev, PCI_D0);
935 pci_raw_set_power_state(dev, PCI_D0);
936 pci_update_current_state(dev, PCI_D0);
940 * pci_platform_power_transition - Use platform to change device power state
941 * @dev: PCI device to handle.
942 * @state: State to put the device into.
944 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
948 if (platform_pci_power_manageable(dev)) {
949 error = platform_pci_set_power_state(dev, state);
951 pci_update_current_state(dev, state);
955 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
956 dev->current_state = PCI_D0;
962 * pci_wakeup - Wake up a PCI device
963 * @pci_dev: Device to handle.
964 * @ign: ignored parameter
966 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
968 pci_wakeup_event(pci_dev);
969 pm_request_resume(&pci_dev->dev);
974 * pci_wakeup_bus - Walk given bus and wake up devices on it
975 * @bus: Top bus of the subtree to walk.
977 void pci_wakeup_bus(struct pci_bus *bus)
980 pci_walk_bus(bus, pci_wakeup, NULL);
984 * __pci_start_power_transition - Start power transition of a PCI device
985 * @dev: PCI device to handle.
986 * @state: State to put the device into.
988 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
990 if (state == PCI_D0) {
991 pci_platform_power_transition(dev, PCI_D0);
993 * Mandatory power management transition delays, see
994 * PCI Express Base Specification Revision 2.0 Section
995 * 6.6.1: Conventional Reset. Do not delay for
996 * devices powered on/off by corresponding bridge,
997 * because have already delayed for the bridge.
999 if (dev->runtime_d3cold) {
1000 if (dev->d3cold_delay)
1001 msleep(dev->d3cold_delay);
1003 * When powering on a bridge from D3cold, the
1004 * whole hierarchy may be powered on into
1005 * D0uninitialized state, resume them to give
1006 * them a chance to suspend again
1008 pci_wakeup_bus(dev->subordinate);
1014 * __pci_dev_set_current_state - Set current state of a PCI device
1015 * @dev: Device to handle
1016 * @data: pointer to state to be set
1018 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1020 pci_power_t state = *(pci_power_t *)data;
1022 dev->current_state = state;
1027 * pci_bus_set_current_state - Walk given bus and set current state of devices
1028 * @bus: Top bus of the subtree to walk.
1029 * @state: state to be set
1031 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1034 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1038 * __pci_complete_power_transition - Complete power transition of a PCI device
1039 * @dev: PCI device to handle.
1040 * @state: State to put the device into.
1042 * This function should not be called directly by device drivers.
1044 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
1048 if (state <= PCI_D0)
1050 ret = pci_platform_power_transition(dev, state);
1051 /* Power off the bridge may power off the whole hierarchy */
1052 if (!ret && state == PCI_D3cold)
1053 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1056 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
1059 * pci_set_power_state - Set the power state of a PCI device
1060 * @dev: PCI device to handle.
1061 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1063 * Transition a device to a new power state, using the platform firmware and/or
1064 * the device's PCI PM registers.
1067 * -EINVAL if the requested state is invalid.
1068 * -EIO if device does not support PCI PM or its PM capabilities register has a
1069 * wrong version, or device doesn't support the requested state.
1070 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1071 * 0 if device already is in the requested state.
1072 * 0 if the transition is to D3 but D3 is not supported.
1073 * 0 if device's power state has been successfully changed.
1075 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1079 /* bound the state we're entering */
1080 if (state > PCI_D3cold)
1082 else if (state < PCI_D0)
1084 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1086 * If the device or the parent bridge do not support PCI PM,
1087 * ignore the request if we're doing anything other than putting
1088 * it into D0 (which would only happen on boot).
1092 /* Check if we're already there */
1093 if (dev->current_state == state)
1096 __pci_start_power_transition(dev, state);
1098 /* This device is quirked not to be put into D3, so
1099 don't put it in D3 */
1100 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1104 * To put device in D3cold, we put device into D3hot in native
1105 * way, then put device into D3cold with platform ops
1107 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
1110 if (!__pci_complete_power_transition(dev, state))
1115 EXPORT_SYMBOL(pci_set_power_state);
1118 * pci_choose_state - Choose the power state of a PCI device
1119 * @dev: PCI device to be suspended
1120 * @state: target sleep state for the whole system. This is the value
1121 * that is passed to suspend() function.
1123 * Returns PCI power state suitable for given device and given system
1127 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
1134 ret = platform_pci_choose_state(dev);
1135 if (ret != PCI_POWER_ERROR)
1138 switch (state.event) {
1141 case PM_EVENT_FREEZE:
1142 case PM_EVENT_PRETHAW:
1143 /* REVISIT both freeze and pre-thaw "should" use D0 */
1144 case PM_EVENT_SUSPEND:
1145 case PM_EVENT_HIBERNATE:
1148 pci_info(dev, "unrecognized suspend event %d\n",
1154 EXPORT_SYMBOL(pci_choose_state);
1156 #define PCI_EXP_SAVE_REGS 7
1158 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1159 u16 cap, bool extended)
1161 struct pci_cap_saved_state *tmp;
1163 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1164 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1170 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1172 return _pci_find_saved_cap(dev, cap, false);
1175 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1177 return _pci_find_saved_cap(dev, cap, true);
1180 static int pci_save_pcie_state(struct pci_dev *dev)
1183 struct pci_cap_saved_state *save_state;
1186 if (!pci_is_pcie(dev))
1189 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1191 pci_err(dev, "buffer not found in %s\n", __func__);
1195 cap = (u16 *)&save_state->cap.data[0];
1196 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1197 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1198 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1199 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1200 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1201 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1202 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1207 static void pci_restore_pcie_state(struct pci_dev *dev)
1210 struct pci_cap_saved_state *save_state;
1213 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1217 cap = (u16 *)&save_state->cap.data[0];
1218 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1219 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1220 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1221 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1222 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1223 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1224 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1228 static int pci_save_pcix_state(struct pci_dev *dev)
1231 struct pci_cap_saved_state *save_state;
1233 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1237 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1239 pci_err(dev, "buffer not found in %s\n", __func__);
1243 pci_read_config_word(dev, pos + PCI_X_CMD,
1244 (u16 *)save_state->cap.data);
1249 static void pci_restore_pcix_state(struct pci_dev *dev)
1252 struct pci_cap_saved_state *save_state;
1255 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1256 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1257 if (!save_state || !pos)
1259 cap = (u16 *)&save_state->cap.data[0];
1261 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1266 * pci_save_state - save the PCI configuration space of a device before suspending
1267 * @dev: - PCI device that we're dealing with
1269 int pci_save_state(struct pci_dev *dev)
1272 /* XXX: 100% dword access ok here? */
1273 for (i = 0; i < 16; i++)
1274 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1275 dev->state_saved = true;
1277 i = pci_save_pcie_state(dev);
1281 i = pci_save_pcix_state(dev);
1285 return pci_save_vc_state(dev);
1287 EXPORT_SYMBOL(pci_save_state);
1289 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1290 u32 saved_val, int retry)
1294 pci_read_config_dword(pdev, offset, &val);
1295 if (val == saved_val)
1299 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1300 offset, val, saved_val);
1301 pci_write_config_dword(pdev, offset, saved_val);
1305 pci_read_config_dword(pdev, offset, &val);
1306 if (val == saved_val)
1313 static void pci_restore_config_space_range(struct pci_dev *pdev,
1314 int start, int end, int retry)
1318 for (index = end; index >= start; index--)
1319 pci_restore_config_dword(pdev, 4 * index,
1320 pdev->saved_config_space[index],
1324 static void pci_restore_config_space(struct pci_dev *pdev)
1326 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1327 pci_restore_config_space_range(pdev, 10, 15, 0);
1328 /* Restore BARs before the command register. */
1329 pci_restore_config_space_range(pdev, 4, 9, 10);
1330 pci_restore_config_space_range(pdev, 0, 3, 0);
1332 pci_restore_config_space_range(pdev, 0, 15, 0);
1337 * pci_restore_state - Restore the saved state of a PCI device
1338 * @dev: - PCI device that we're dealing with
1340 void pci_restore_state(struct pci_dev *dev)
1342 if (!dev->state_saved)
1345 /* PCI Express register must be restored first */
1346 pci_restore_pcie_state(dev);
1347 pci_restore_pasid_state(dev);
1348 pci_restore_pri_state(dev);
1349 pci_restore_ats_state(dev);
1350 pci_restore_vc_state(dev);
1352 pci_cleanup_aer_error_status_regs(dev);
1354 pci_restore_config_space(dev);
1356 pci_restore_pcix_state(dev);
1357 pci_restore_msi_state(dev);
1359 /* Restore ACS and IOV configuration state */
1360 pci_enable_acs(dev);
1361 pci_restore_iov_state(dev);
1363 dev->state_saved = false;
1365 EXPORT_SYMBOL(pci_restore_state);
1367 struct pci_saved_state {
1368 u32 config_space[16];
1369 struct pci_cap_saved_data cap[0];
1373 * pci_store_saved_state - Allocate and return an opaque struct containing
1374 * the device saved state.
1375 * @dev: PCI device that we're dealing with
1377 * Return NULL if no state or error.
1379 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1381 struct pci_saved_state *state;
1382 struct pci_cap_saved_state *tmp;
1383 struct pci_cap_saved_data *cap;
1386 if (!dev->state_saved)
1389 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1391 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1392 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1394 state = kzalloc(size, GFP_KERNEL);
1398 memcpy(state->config_space, dev->saved_config_space,
1399 sizeof(state->config_space));
1402 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1403 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1404 memcpy(cap, &tmp->cap, len);
1405 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1407 /* Empty cap_save terminates list */
1411 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1414 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1415 * @dev: PCI device that we're dealing with
1416 * @state: Saved state returned from pci_store_saved_state()
1418 int pci_load_saved_state(struct pci_dev *dev,
1419 struct pci_saved_state *state)
1421 struct pci_cap_saved_data *cap;
1423 dev->state_saved = false;
1428 memcpy(dev->saved_config_space, state->config_space,
1429 sizeof(state->config_space));
1433 struct pci_cap_saved_state *tmp;
1435 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1436 if (!tmp || tmp->cap.size != cap->size)
1439 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1440 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1441 sizeof(struct pci_cap_saved_data) + cap->size);
1444 dev->state_saved = true;
1447 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1450 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1451 * and free the memory allocated for it.
1452 * @dev: PCI device that we're dealing with
1453 * @state: Pointer to saved state returned from pci_store_saved_state()
1455 int pci_load_and_free_saved_state(struct pci_dev *dev,
1456 struct pci_saved_state **state)
1458 int ret = pci_load_saved_state(dev, *state);
1463 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1465 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1467 return pci_enable_resources(dev, bars);
1470 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1473 struct pci_dev *bridge;
1477 err = pci_set_power_state(dev, PCI_D0);
1478 if (err < 0 && err != -EIO)
1481 bridge = pci_upstream_bridge(dev);
1483 pcie_aspm_powersave_config_link(bridge);
1485 err = pcibios_enable_device(dev, bars);
1488 pci_fixup_device(pci_fixup_enable, dev);
1490 if (dev->msi_enabled || dev->msix_enabled)
1493 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1495 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1496 if (cmd & PCI_COMMAND_INTX_DISABLE)
1497 pci_write_config_word(dev, PCI_COMMAND,
1498 cmd & ~PCI_COMMAND_INTX_DISABLE);
1505 * pci_reenable_device - Resume abandoned device
1506 * @dev: PCI device to be resumed
1508 * Note this function is a backend of pci_default_resume and is not supposed
1509 * to be called by normal code, write proper resume handler and use it instead.
1511 int pci_reenable_device(struct pci_dev *dev)
1513 if (pci_is_enabled(dev))
1514 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1517 EXPORT_SYMBOL(pci_reenable_device);
1519 static void pci_enable_bridge(struct pci_dev *dev)
1521 struct pci_dev *bridge;
1524 bridge = pci_upstream_bridge(dev);
1526 pci_enable_bridge(bridge);
1528 if (pci_is_enabled(dev)) {
1529 if (!dev->is_busmaster)
1530 pci_set_master(dev);
1534 retval = pci_enable_device(dev);
1536 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1538 pci_set_master(dev);
1541 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1543 struct pci_dev *bridge;
1548 * Power state could be unknown at this point, either due to a fresh
1549 * boot or a device removal call. So get the current power state
1550 * so that things like MSI message writing will behave as expected
1551 * (e.g. if the device really is in D0 at enable time).
1555 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1556 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1559 if (atomic_inc_return(&dev->enable_cnt) > 1)
1560 return 0; /* already enabled */
1562 bridge = pci_upstream_bridge(dev);
1564 pci_enable_bridge(bridge);
1566 /* only skip sriov related */
1567 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1568 if (dev->resource[i].flags & flags)
1570 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1571 if (dev->resource[i].flags & flags)
1574 err = do_pci_enable_device(dev, bars);
1576 atomic_dec(&dev->enable_cnt);
1581 * pci_enable_device_io - Initialize a device for use with IO space
1582 * @dev: PCI device to be initialized
1584 * Initialize device before it's used by a driver. Ask low-level code
1585 * to enable I/O resources. Wake up the device if it was suspended.
1586 * Beware, this function can fail.
1588 int pci_enable_device_io(struct pci_dev *dev)
1590 return pci_enable_device_flags(dev, IORESOURCE_IO);
1592 EXPORT_SYMBOL(pci_enable_device_io);
1595 * pci_enable_device_mem - Initialize a device for use with Memory space
1596 * @dev: PCI device to be initialized
1598 * Initialize device before it's used by a driver. Ask low-level code
1599 * to enable Memory resources. Wake up the device if it was suspended.
1600 * Beware, this function can fail.
1602 int pci_enable_device_mem(struct pci_dev *dev)
1604 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1606 EXPORT_SYMBOL(pci_enable_device_mem);
1609 * pci_enable_device - Initialize device before it's used by a driver.
1610 * @dev: PCI device to be initialized
1612 * Initialize device before it's used by a driver. Ask low-level code
1613 * to enable I/O and memory. Wake up the device if it was suspended.
1614 * Beware, this function can fail.
1616 * Note we don't actually enable the device many times if we call
1617 * this function repeatedly (we just increment the count).
1619 int pci_enable_device(struct pci_dev *dev)
1621 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1623 EXPORT_SYMBOL(pci_enable_device);
1626 * Managed PCI resources. This manages device on/off, intx/msi/msix
1627 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1628 * there's no need to track it separately. pci_devres is initialized
1629 * when a device is enabled using managed PCI device enable interface.
1632 unsigned int enabled:1;
1633 unsigned int pinned:1;
1634 unsigned int orig_intx:1;
1635 unsigned int restore_intx:1;
1640 static void pcim_release(struct device *gendev, void *res)
1642 struct pci_dev *dev = to_pci_dev(gendev);
1643 struct pci_devres *this = res;
1646 if (dev->msi_enabled)
1647 pci_disable_msi(dev);
1648 if (dev->msix_enabled)
1649 pci_disable_msix(dev);
1651 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1652 if (this->region_mask & (1 << i))
1653 pci_release_region(dev, i);
1658 if (this->restore_intx)
1659 pci_intx(dev, this->orig_intx);
1661 if (this->enabled && !this->pinned)
1662 pci_disable_device(dev);
1665 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1667 struct pci_devres *dr, *new_dr;
1669 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1673 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1676 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1679 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1681 if (pci_is_managed(pdev))
1682 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1687 * pcim_enable_device - Managed pci_enable_device()
1688 * @pdev: PCI device to be initialized
1690 * Managed pci_enable_device().
1692 int pcim_enable_device(struct pci_dev *pdev)
1694 struct pci_devres *dr;
1697 dr = get_pci_dr(pdev);
1703 rc = pci_enable_device(pdev);
1705 pdev->is_managed = 1;
1710 EXPORT_SYMBOL(pcim_enable_device);
1713 * pcim_pin_device - Pin managed PCI device
1714 * @pdev: PCI device to pin
1716 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1717 * driver detach. @pdev must have been enabled with
1718 * pcim_enable_device().
1720 void pcim_pin_device(struct pci_dev *pdev)
1722 struct pci_devres *dr;
1724 dr = find_pci_dr(pdev);
1725 WARN_ON(!dr || !dr->enabled);
1729 EXPORT_SYMBOL(pcim_pin_device);
1732 * pcibios_add_device - provide arch specific hooks when adding device dev
1733 * @dev: the PCI device being added
1735 * Permits the platform to provide architecture specific functionality when
1736 * devices are added. This is the default implementation. Architecture
1737 * implementations can override this.
1739 int __weak pcibios_add_device(struct pci_dev *dev)
1745 * pcibios_release_device - provide arch specific hooks when releasing device dev
1746 * @dev: the PCI device being released
1748 * Permits the platform to provide architecture specific functionality when
1749 * devices are released. This is the default implementation. Architecture
1750 * implementations can override this.
1752 void __weak pcibios_release_device(struct pci_dev *dev) {}
1755 * pcibios_disable_device - disable arch specific PCI resources for device dev
1756 * @dev: the PCI device to disable
1758 * Disables architecture specific PCI resources for the device. This
1759 * is the default implementation. Architecture implementations can
1762 void __weak pcibios_disable_device(struct pci_dev *dev) {}
1765 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1766 * @irq: ISA IRQ to penalize
1767 * @active: IRQ active or not
1769 * Permits the platform to provide architecture-specific functionality when
1770 * penalizing ISA IRQs. This is the default implementation. Architecture
1771 * implementations can override this.
1773 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1775 static void do_pci_disable_device(struct pci_dev *dev)
1779 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1780 if (pci_command & PCI_COMMAND_MASTER) {
1781 pci_command &= ~PCI_COMMAND_MASTER;
1782 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1785 pcibios_disable_device(dev);
1789 * pci_disable_enabled_device - Disable device without updating enable_cnt
1790 * @dev: PCI device to disable
1792 * NOTE: This function is a backend of PCI power management routines and is
1793 * not supposed to be called drivers.
1795 void pci_disable_enabled_device(struct pci_dev *dev)
1797 if (pci_is_enabled(dev))
1798 do_pci_disable_device(dev);
1802 * pci_disable_device - Disable PCI device after use
1803 * @dev: PCI device to be disabled
1805 * Signal to the system that the PCI device is not in use by the system
1806 * anymore. This only involves disabling PCI bus-mastering, if active.
1808 * Note we don't actually disable the device until all callers of
1809 * pci_enable_device() have called pci_disable_device().
1811 void pci_disable_device(struct pci_dev *dev)
1813 struct pci_devres *dr;
1815 dr = find_pci_dr(dev);
1819 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1820 "disabling already-disabled device");
1822 if (atomic_dec_return(&dev->enable_cnt) != 0)
1825 do_pci_disable_device(dev);
1827 dev->is_busmaster = 0;
1829 EXPORT_SYMBOL(pci_disable_device);
1832 * pcibios_set_pcie_reset_state - set reset state for device dev
1833 * @dev: the PCIe device reset
1834 * @state: Reset state to enter into
1837 * Sets the PCIe reset state for the device. This is the default
1838 * implementation. Architecture implementations can override this.
1840 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1841 enum pcie_reset_state state)
1847 * pci_set_pcie_reset_state - set reset state for device dev
1848 * @dev: the PCIe device reset
1849 * @state: Reset state to enter into
1852 * Sets the PCI reset state for the device.
1854 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1856 return pcibios_set_pcie_reset_state(dev, state);
1858 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1861 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
1862 * @dev: PCIe root port or event collector.
1864 void pcie_clear_root_pme_status(struct pci_dev *dev)
1866 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
1870 * pci_check_pme_status - Check if given device has generated PME.
1871 * @dev: Device to check.
1873 * Check the PME status of the device and if set, clear it and clear PME enable
1874 * (if set). Return 'true' if PME status and PME enable were both set or
1875 * 'false' otherwise.
1877 bool pci_check_pme_status(struct pci_dev *dev)
1886 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1887 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1888 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1891 /* Clear PME status. */
1892 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1893 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1894 /* Disable PME to avoid interrupt flood. */
1895 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1899 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1905 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1906 * @dev: Device to handle.
1907 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1909 * Check if @dev has generated PME and queue a resume request for it in that
1912 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1914 if (pme_poll_reset && dev->pme_poll)
1915 dev->pme_poll = false;
1917 if (pci_check_pme_status(dev)) {
1918 pci_wakeup_event(dev);
1919 pm_request_resume(&dev->dev);
1925 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1926 * @bus: Top bus of the subtree to walk.
1928 void pci_pme_wakeup_bus(struct pci_bus *bus)
1931 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1936 * pci_pme_capable - check the capability of PCI device to generate PME#
1937 * @dev: PCI device to handle.
1938 * @state: PCI state from which device will issue PME#.
1940 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1945 return !!(dev->pme_support & (1 << state));
1947 EXPORT_SYMBOL(pci_pme_capable);
1949 static void pci_pme_list_scan(struct work_struct *work)
1951 struct pci_pme_device *pme_dev, *n;
1953 mutex_lock(&pci_pme_list_mutex);
1954 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1955 if (pme_dev->dev->pme_poll) {
1956 struct pci_dev *bridge;
1958 bridge = pme_dev->dev->bus->self;
1960 * If bridge is in low power state, the
1961 * configuration space of subordinate devices
1962 * may be not accessible
1964 if (bridge && bridge->current_state != PCI_D0)
1966 pci_pme_wakeup(pme_dev->dev, NULL);
1968 list_del(&pme_dev->list);
1972 if (!list_empty(&pci_pme_list))
1973 queue_delayed_work(system_freezable_wq, &pci_pme_work,
1974 msecs_to_jiffies(PME_TIMEOUT));
1975 mutex_unlock(&pci_pme_list_mutex);
1978 static void __pci_pme_active(struct pci_dev *dev, bool enable)
1982 if (!dev->pme_support)
1985 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1986 /* Clear PME_Status by writing 1 to it and enable PME# */
1987 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1989 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1991 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1995 * pci_pme_restore - Restore PME configuration after config space restore.
1996 * @dev: PCI device to update.
1998 void pci_pme_restore(struct pci_dev *dev)
2002 if (!dev->pme_support)
2005 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2006 if (dev->wakeup_prepared) {
2007 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2008 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2010 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2011 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2013 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2017 * pci_pme_active - enable or disable PCI device's PME# function
2018 * @dev: PCI device to handle.
2019 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2021 * The caller must verify that the device is capable of generating PME# before
2022 * calling this function with @enable equal to 'true'.
2024 void pci_pme_active(struct pci_dev *dev, bool enable)
2026 __pci_pme_active(dev, enable);
2029 * PCI (as opposed to PCIe) PME requires that the device have
2030 * its PME# line hooked up correctly. Not all hardware vendors
2031 * do this, so the PME never gets delivered and the device
2032 * remains asleep. The easiest way around this is to
2033 * periodically walk the list of suspended devices and check
2034 * whether any have their PME flag set. The assumption is that
2035 * we'll wake up often enough anyway that this won't be a huge
2036 * hit, and the power savings from the devices will still be a
2039 * Although PCIe uses in-band PME message instead of PME# line
2040 * to report PME, PME does not work for some PCIe devices in
2041 * reality. For example, there are devices that set their PME
2042 * status bits, but don't really bother to send a PME message;
2043 * there are PCI Express Root Ports that don't bother to
2044 * trigger interrupts when they receive PME messages from the
2045 * devices below. So PME poll is used for PCIe devices too.
2048 if (dev->pme_poll) {
2049 struct pci_pme_device *pme_dev;
2051 pme_dev = kmalloc(sizeof(struct pci_pme_device),
2054 pci_warn(dev, "can't enable PME#\n");
2058 mutex_lock(&pci_pme_list_mutex);
2059 list_add(&pme_dev->list, &pci_pme_list);
2060 if (list_is_singular(&pci_pme_list))
2061 queue_delayed_work(system_freezable_wq,
2063 msecs_to_jiffies(PME_TIMEOUT));
2064 mutex_unlock(&pci_pme_list_mutex);
2066 mutex_lock(&pci_pme_list_mutex);
2067 list_for_each_entry(pme_dev, &pci_pme_list, list) {
2068 if (pme_dev->dev == dev) {
2069 list_del(&pme_dev->list);
2074 mutex_unlock(&pci_pme_list_mutex);
2078 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2080 EXPORT_SYMBOL(pci_pme_active);
2083 * __pci_enable_wake - enable PCI device as wakeup event source
2084 * @dev: PCI device affected
2085 * @state: PCI state from which device will issue wakeup events
2086 * @enable: True to enable event generation; false to disable
2088 * This enables the device as a wakeup event source, or disables it.
2089 * When such events involves platform-specific hooks, those hooks are
2090 * called automatically by this routine.
2092 * Devices with legacy power management (no standard PCI PM capabilities)
2093 * always require such platform hooks.
2096 * 0 is returned on success
2097 * -EINVAL is returned if device is not supposed to wake up the system
2098 * Error code depending on the platform is returned if both the platform and
2099 * the native mechanism fail to enable the generation of wake-up events
2101 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2106 * Bridges can only signal wakeup on behalf of subordinate devices,
2107 * but that is set up elsewhere, so skip them.
2109 if (pci_has_subordinate(dev))
2112 /* Don't do the same thing twice in a row for one device. */
2113 if (!!enable == !!dev->wakeup_prepared)
2117 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2118 * Anderson we should be doing PME# wake enable followed by ACPI wake
2119 * enable. To disable wake-up we call the platform first, for symmetry.
2125 if (pci_pme_capable(dev, state))
2126 pci_pme_active(dev, true);
2129 error = platform_pci_set_wakeup(dev, true);
2133 dev->wakeup_prepared = true;
2135 platform_pci_set_wakeup(dev, false);
2136 pci_pme_active(dev, false);
2137 dev->wakeup_prepared = false;
2144 * pci_enable_wake - change wakeup settings for a PCI device
2145 * @pci_dev: Target device
2146 * @state: PCI state from which device will issue wakeup events
2147 * @enable: Whether or not to enable event generation
2149 * If @enable is set, check device_may_wakeup() for the device before calling
2150 * __pci_enable_wake() for it.
2152 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2154 if (enable && !device_may_wakeup(&pci_dev->dev))
2157 return __pci_enable_wake(pci_dev, state, enable);
2159 EXPORT_SYMBOL(pci_enable_wake);
2162 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2163 * @dev: PCI device to prepare
2164 * @enable: True to enable wake-up event generation; false to disable
2166 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2167 * and this function allows them to set that up cleanly - pci_enable_wake()
2168 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2169 * ordering constraints.
2171 * This function only returns error code if the device is not allowed to wake
2172 * up the system from sleep or it is not capable of generating PME# from both
2173 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2175 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2177 return pci_pme_capable(dev, PCI_D3cold) ?
2178 pci_enable_wake(dev, PCI_D3cold, enable) :
2179 pci_enable_wake(dev, PCI_D3hot, enable);
2181 EXPORT_SYMBOL(pci_wake_from_d3);
2184 * pci_target_state - find an appropriate low power state for a given PCI dev
2186 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2188 * Use underlying platform code to find a supported low power state for @dev.
2189 * If the platform can't manage @dev, return the deepest state from which it
2190 * can generate wake events, based on any available PME info.
2192 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2194 pci_power_t target_state = PCI_D3hot;
2196 if (platform_pci_power_manageable(dev)) {
2198 * Call the platform to find the target state for the device.
2200 pci_power_t state = platform_pci_choose_state(dev);
2203 case PCI_POWER_ERROR:
2208 if (pci_no_d1d2(dev))
2211 target_state = state;
2214 return target_state;
2218 target_state = PCI_D0;
2221 * If the device is in D3cold even though it's not power-manageable by
2222 * the platform, it may have been powered down by non-standard means.
2223 * Best to let it slumber.
2225 if (dev->current_state == PCI_D3cold)
2226 target_state = PCI_D3cold;
2230 * Find the deepest state from which the device can generate
2233 if (dev->pme_support) {
2235 && !(dev->pme_support & (1 << target_state)))
2240 return target_state;
2244 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2245 * @dev: Device to handle.
2247 * Choose the power state appropriate for the device depending on whether
2248 * it can wake up the system and/or is power manageable by the platform
2249 * (PCI_D3hot is the default) and put the device into that state.
2251 int pci_prepare_to_sleep(struct pci_dev *dev)
2253 bool wakeup = device_may_wakeup(&dev->dev);
2254 pci_power_t target_state = pci_target_state(dev, wakeup);
2257 if (target_state == PCI_POWER_ERROR)
2260 pci_enable_wake(dev, target_state, wakeup);
2262 error = pci_set_power_state(dev, target_state);
2265 pci_enable_wake(dev, target_state, false);
2269 EXPORT_SYMBOL(pci_prepare_to_sleep);
2272 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2273 * @dev: Device to handle.
2275 * Disable device's system wake-up capability and put it into D0.
2277 int pci_back_from_sleep(struct pci_dev *dev)
2279 pci_enable_wake(dev, PCI_D0, false);
2280 return pci_set_power_state(dev, PCI_D0);
2282 EXPORT_SYMBOL(pci_back_from_sleep);
2285 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2286 * @dev: PCI device being suspended.
2288 * Prepare @dev to generate wake-up events at run time and put it into a low
2291 int pci_finish_runtime_suspend(struct pci_dev *dev)
2293 pci_power_t target_state;
2296 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2297 if (target_state == PCI_POWER_ERROR)
2300 dev->runtime_d3cold = target_state == PCI_D3cold;
2302 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2304 error = pci_set_power_state(dev, target_state);
2307 pci_enable_wake(dev, target_state, false);
2308 dev->runtime_d3cold = false;
2315 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2316 * @dev: Device to check.
2318 * Return true if the device itself is capable of generating wake-up events
2319 * (through the platform or using the native PCIe PME) or if the device supports
2320 * PME and one of its upstream bridges can generate wake-up events.
2322 bool pci_dev_run_wake(struct pci_dev *dev)
2324 struct pci_bus *bus = dev->bus;
2326 if (!dev->pme_support)
2329 /* PME-capable in principle, but not from the target power state */
2330 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2333 if (device_can_wakeup(&dev->dev))
2336 while (bus->parent) {
2337 struct pci_dev *bridge = bus->self;
2339 if (device_can_wakeup(&bridge->dev))
2345 /* We have reached the root bus. */
2347 return device_can_wakeup(bus->bridge);
2351 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2354 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2355 * @pci_dev: Device to check.
2357 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2358 * reconfigured due to wakeup settings difference between system and runtime
2359 * suspend and the current power state of it is suitable for the upcoming
2360 * (system) transition.
2362 * If the device is not configured for system wakeup, disable PME for it before
2363 * returning 'true' to prevent it from waking up the system unnecessarily.
2365 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2367 struct device *dev = &pci_dev->dev;
2368 bool wakeup = device_may_wakeup(dev);
2370 if (!pm_runtime_suspended(dev)
2371 || pci_target_state(pci_dev, wakeup) != pci_dev->current_state
2372 || platform_pci_need_resume(pci_dev))
2376 * At this point the device is good to go unless it's been configured
2377 * to generate PME at the runtime suspend time, but it is not supposed
2378 * to wake up the system. In that case, simply disable PME for it
2379 * (it will have to be re-enabled on exit from system resume).
2381 * If the device's power state is D3cold and the platform check above
2382 * hasn't triggered, the device's configuration is suitable and we don't
2383 * need to manipulate it at all.
2385 spin_lock_irq(&dev->power.lock);
2387 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2389 __pci_pme_active(pci_dev, false);
2391 spin_unlock_irq(&dev->power.lock);
2396 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2397 * @pci_dev: Device to handle.
2399 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2400 * it might have been disabled during the prepare phase of system suspend if
2401 * the device was not configured for system wakeup.
2403 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2405 struct device *dev = &pci_dev->dev;
2407 if (!pci_dev_run_wake(pci_dev))
2410 spin_lock_irq(&dev->power.lock);
2412 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2413 __pci_pme_active(pci_dev, true);
2415 spin_unlock_irq(&dev->power.lock);
2418 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2420 struct device *dev = &pdev->dev;
2421 struct device *parent = dev->parent;
2424 pm_runtime_get_sync(parent);
2425 pm_runtime_get_noresume(dev);
2427 * pdev->current_state is set to PCI_D3cold during suspending,
2428 * so wait until suspending completes
2430 pm_runtime_barrier(dev);
2432 * Only need to resume devices in D3cold, because config
2433 * registers are still accessible for devices suspended but
2436 if (pdev->current_state == PCI_D3cold)
2437 pm_runtime_resume(dev);
2440 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2442 struct device *dev = &pdev->dev;
2443 struct device *parent = dev->parent;
2445 pm_runtime_put(dev);
2447 pm_runtime_put_sync(parent);
2451 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2452 * @bridge: Bridge to check
2454 * This function checks if it is possible to move the bridge to D3.
2455 * Currently we only allow D3 for recent enough PCIe ports.
2457 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2459 if (!pci_is_pcie(bridge))
2462 switch (pci_pcie_type(bridge)) {
2463 case PCI_EXP_TYPE_ROOT_PORT:
2464 case PCI_EXP_TYPE_UPSTREAM:
2465 case PCI_EXP_TYPE_DOWNSTREAM:
2466 if (pci_bridge_d3_disable)
2470 * Hotplug interrupts cannot be delivered if the link is down,
2471 * so parents of a hotplug port must stay awake. In addition,
2472 * hotplug ports handled by firmware in System Management Mode
2473 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2474 * For simplicity, disallow in general for now.
2476 if (bridge->is_hotplug_bridge)
2479 if (pci_bridge_d3_force)
2483 * It should be safe to put PCIe ports from 2015 or newer
2486 if (dmi_get_bios_year() >= 2015)
2494 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2496 bool *d3cold_ok = data;
2498 if (/* The device needs to be allowed to go D3cold ... */
2499 dev->no_d3cold || !dev->d3cold_allowed ||
2501 /* ... and if it is wakeup capable to do so from D3cold. */
2502 (device_may_wakeup(&dev->dev) &&
2503 !pci_pme_capable(dev, PCI_D3cold)) ||
2505 /* If it is a bridge it must be allowed to go to D3. */
2506 !pci_power_manageable(dev))
2514 * pci_bridge_d3_update - Update bridge D3 capabilities
2515 * @dev: PCI device which is changed
2517 * Update upstream bridge PM capabilities accordingly depending on if the
2518 * device PM configuration was changed or the device is being removed. The
2519 * change is also propagated upstream.
2521 void pci_bridge_d3_update(struct pci_dev *dev)
2523 bool remove = !device_is_registered(&dev->dev);
2524 struct pci_dev *bridge;
2525 bool d3cold_ok = true;
2527 bridge = pci_upstream_bridge(dev);
2528 if (!bridge || !pci_bridge_d3_possible(bridge))
2532 * If D3 is currently allowed for the bridge, removing one of its
2533 * children won't change that.
2535 if (remove && bridge->bridge_d3)
2539 * If D3 is currently allowed for the bridge and a child is added or
2540 * changed, disallowance of D3 can only be caused by that child, so
2541 * we only need to check that single device, not any of its siblings.
2543 * If D3 is currently not allowed for the bridge, checking the device
2544 * first may allow us to skip checking its siblings.
2547 pci_dev_check_d3cold(dev, &d3cold_ok);
2550 * If D3 is currently not allowed for the bridge, this may be caused
2551 * either by the device being changed/removed or any of its siblings,
2552 * so we need to go through all children to find out if one of them
2553 * continues to block D3.
2555 if (d3cold_ok && !bridge->bridge_d3)
2556 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2559 if (bridge->bridge_d3 != d3cold_ok) {
2560 bridge->bridge_d3 = d3cold_ok;
2561 /* Propagate change to upstream bridges */
2562 pci_bridge_d3_update(bridge);
2567 * pci_d3cold_enable - Enable D3cold for device
2568 * @dev: PCI device to handle
2570 * This function can be used in drivers to enable D3cold from the device
2571 * they handle. It also updates upstream PCI bridge PM capabilities
2574 void pci_d3cold_enable(struct pci_dev *dev)
2576 if (dev->no_d3cold) {
2577 dev->no_d3cold = false;
2578 pci_bridge_d3_update(dev);
2581 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2584 * pci_d3cold_disable - Disable D3cold for device
2585 * @dev: PCI device to handle
2587 * This function can be used in drivers to disable D3cold from the device
2588 * they handle. It also updates upstream PCI bridge PM capabilities
2591 void pci_d3cold_disable(struct pci_dev *dev)
2593 if (!dev->no_d3cold) {
2594 dev->no_d3cold = true;
2595 pci_bridge_d3_update(dev);
2598 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2601 * pci_pm_init - Initialize PM functions of given PCI device
2602 * @dev: PCI device to handle.
2604 void pci_pm_init(struct pci_dev *dev)
2609 pm_runtime_forbid(&dev->dev);
2610 pm_runtime_set_active(&dev->dev);
2611 pm_runtime_enable(&dev->dev);
2612 device_enable_async_suspend(&dev->dev);
2613 dev->wakeup_prepared = false;
2616 dev->pme_support = 0;
2618 /* find PCI PM capability in list */
2619 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2622 /* Check device's ability to generate PME# */
2623 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2625 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2626 pci_err(dev, "unsupported PM cap regs version (%u)\n",
2627 pmc & PCI_PM_CAP_VER_MASK);
2632 dev->d3_delay = PCI_PM_D3_WAIT;
2633 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2634 dev->bridge_d3 = pci_bridge_d3_possible(dev);
2635 dev->d3cold_allowed = true;
2637 dev->d1_support = false;
2638 dev->d2_support = false;
2639 if (!pci_no_d1d2(dev)) {
2640 if (pmc & PCI_PM_CAP_D1)
2641 dev->d1_support = true;
2642 if (pmc & PCI_PM_CAP_D2)
2643 dev->d2_support = true;
2645 if (dev->d1_support || dev->d2_support)
2646 pci_printk(KERN_DEBUG, dev, "supports%s%s\n",
2647 dev->d1_support ? " D1" : "",
2648 dev->d2_support ? " D2" : "");
2651 pmc &= PCI_PM_CAP_PME_MASK;
2653 pci_printk(KERN_DEBUG, dev, "PME# supported from%s%s%s%s%s\n",
2654 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2655 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2656 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2657 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2658 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2659 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2660 dev->pme_poll = true;
2662 * Make device's PM flags reflect the wake-up capability, but
2663 * let the user space enable it to wake up the system as needed.
2665 device_set_wakeup_capable(&dev->dev, true);
2666 /* Disable the PME# generation functionality */
2667 pci_pme_active(dev, false);
2671 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2673 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
2677 case PCI_EA_P_VF_MEM:
2678 flags |= IORESOURCE_MEM;
2680 case PCI_EA_P_MEM_PREFETCH:
2681 case PCI_EA_P_VF_MEM_PREFETCH:
2682 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2685 flags |= IORESOURCE_IO;
2694 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2697 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2698 return &dev->resource[bei];
2699 #ifdef CONFIG_PCI_IOV
2700 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2701 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2702 return &dev->resource[PCI_IOV_RESOURCES +
2703 bei - PCI_EA_BEI_VF_BAR0];
2705 else if (bei == PCI_EA_BEI_ROM)
2706 return &dev->resource[PCI_ROM_RESOURCE];
2711 /* Read an Enhanced Allocation (EA) entry */
2712 static int pci_ea_read(struct pci_dev *dev, int offset)
2714 struct resource *res;
2715 int ent_size, ent_offset = offset;
2716 resource_size_t start, end;
2717 unsigned long flags;
2718 u32 dw0, bei, base, max_offset;
2720 bool support_64 = (sizeof(resource_size_t) >= 8);
2722 pci_read_config_dword(dev, ent_offset, &dw0);
2725 /* Entry size field indicates DWORDs after 1st */
2726 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2728 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2731 bei = (dw0 & PCI_EA_BEI) >> 4;
2732 prop = (dw0 & PCI_EA_PP) >> 8;
2735 * If the Property is in the reserved range, try the Secondary
2738 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2739 prop = (dw0 & PCI_EA_SP) >> 16;
2740 if (prop > PCI_EA_P_BRIDGE_IO)
2743 res = pci_ea_get_resource(dev, bei, prop);
2745 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
2749 flags = pci_ea_flags(dev, prop);
2751 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
2756 pci_read_config_dword(dev, ent_offset, &base);
2757 start = (base & PCI_EA_FIELD_MASK);
2760 /* Read MaxOffset */
2761 pci_read_config_dword(dev, ent_offset, &max_offset);
2764 /* Read Base MSBs (if 64-bit entry) */
2765 if (base & PCI_EA_IS_64) {
2768 pci_read_config_dword(dev, ent_offset, &base_upper);
2771 flags |= IORESOURCE_MEM_64;
2773 /* entry starts above 32-bit boundary, can't use */
2774 if (!support_64 && base_upper)
2778 start |= ((u64)base_upper << 32);
2781 end = start + (max_offset | 0x03);
2783 /* Read MaxOffset MSBs (if 64-bit entry) */
2784 if (max_offset & PCI_EA_IS_64) {
2785 u32 max_offset_upper;
2787 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2790 flags |= IORESOURCE_MEM_64;
2792 /* entry too big, can't use */
2793 if (!support_64 && max_offset_upper)
2797 end += ((u64)max_offset_upper << 32);
2801 pci_err(dev, "EA Entry crosses address boundary\n");
2805 if (ent_size != ent_offset - offset) {
2806 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
2807 ent_size, ent_offset - offset);
2811 res->name = pci_name(dev);
2816 if (bei <= PCI_EA_BEI_BAR5)
2817 pci_printk(KERN_DEBUG, dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2819 else if (bei == PCI_EA_BEI_ROM)
2820 pci_printk(KERN_DEBUG, dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2822 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2823 pci_printk(KERN_DEBUG, dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2824 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2826 pci_printk(KERN_DEBUG, dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2830 return offset + ent_size;
2833 /* Enhanced Allocation Initialization */
2834 void pci_ea_init(struct pci_dev *dev)
2841 /* find PCI EA capability in list */
2842 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2846 /* determine the number of entries */
2847 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2849 num_ent &= PCI_EA_NUM_ENT_MASK;
2851 offset = ea + PCI_EA_FIRST_ENT;
2853 /* Skip DWORD 2 for type 1 functions */
2854 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2857 /* parse each EA entry */
2858 for (i = 0; i < num_ent; ++i)
2859 offset = pci_ea_read(dev, offset);
2862 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2863 struct pci_cap_saved_state *new_cap)
2865 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2869 * _pci_add_cap_save_buffer - allocate buffer for saving given
2870 * capability registers
2871 * @dev: the PCI device
2872 * @cap: the capability to allocate the buffer for
2873 * @extended: Standard or Extended capability ID
2874 * @size: requested size of the buffer
2876 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2877 bool extended, unsigned int size)
2880 struct pci_cap_saved_state *save_state;
2883 pos = pci_find_ext_capability(dev, cap);
2885 pos = pci_find_capability(dev, cap);
2890 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2894 save_state->cap.cap_nr = cap;
2895 save_state->cap.cap_extended = extended;
2896 save_state->cap.size = size;
2897 pci_add_saved_cap(dev, save_state);
2902 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2904 return _pci_add_cap_save_buffer(dev, cap, false, size);
2907 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2909 return _pci_add_cap_save_buffer(dev, cap, true, size);
2913 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2914 * @dev: the PCI device
2916 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2920 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2921 PCI_EXP_SAVE_REGS * sizeof(u16));
2923 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
2925 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2927 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
2929 pci_allocate_vc_save_buffers(dev);
2932 void pci_free_cap_save_buffers(struct pci_dev *dev)
2934 struct pci_cap_saved_state *tmp;
2935 struct hlist_node *n;
2937 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2942 * pci_configure_ari - enable or disable ARI forwarding
2943 * @dev: the PCI device
2945 * If @dev and its upstream bridge both support ARI, enable ARI in the
2946 * bridge. Otherwise, disable ARI in the bridge.
2948 void pci_configure_ari(struct pci_dev *dev)
2951 struct pci_dev *bridge;
2953 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2956 bridge = dev->bus->self;
2960 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2961 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2964 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2965 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2966 PCI_EXP_DEVCTL2_ARI);
2967 bridge->ari_enabled = 1;
2969 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2970 PCI_EXP_DEVCTL2_ARI);
2971 bridge->ari_enabled = 0;
2975 static int pci_acs_enable;
2978 * pci_request_acs - ask for ACS to be enabled if supported
2980 void pci_request_acs(void)
2986 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2987 * @dev: the PCI device
2989 static void pci_std_enable_acs(struct pci_dev *dev)
2995 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2999 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
3000 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
3002 /* Source Validation */
3003 ctrl |= (cap & PCI_ACS_SV);
3005 /* P2P Request Redirect */
3006 ctrl |= (cap & PCI_ACS_RR);
3008 /* P2P Completion Redirect */
3009 ctrl |= (cap & PCI_ACS_CR);
3011 /* Upstream Forwarding */
3012 ctrl |= (cap & PCI_ACS_UF);
3014 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
3018 * pci_enable_acs - enable ACS if hardware support it
3019 * @dev: the PCI device
3021 void pci_enable_acs(struct pci_dev *dev)
3023 if (!pci_acs_enable)
3026 if (!pci_dev_specific_enable_acs(dev))
3029 pci_std_enable_acs(dev);
3032 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3037 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
3042 * Except for egress control, capabilities are either required
3043 * or only required if controllable. Features missing from the
3044 * capability field can therefore be assumed as hard-wired enabled.
3046 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3047 acs_flags &= (cap | PCI_ACS_EC);
3049 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3050 return (ctrl & acs_flags) == acs_flags;
3054 * pci_acs_enabled - test ACS against required flags for a given device
3055 * @pdev: device to test
3056 * @acs_flags: required PCI ACS flags
3058 * Return true if the device supports the provided flags. Automatically
3059 * filters out flags that are not implemented on multifunction devices.
3061 * Note that this interface checks the effective ACS capabilities of the
3062 * device rather than the actual capabilities. For instance, most single
3063 * function endpoints are not required to support ACS because they have no
3064 * opportunity for peer-to-peer access. We therefore return 'true'
3065 * regardless of whether the device exposes an ACS capability. This makes
3066 * it much easier for callers of this function to ignore the actual type
3067 * or topology of the device when testing ACS support.
3069 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3073 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3078 * Conventional PCI and PCI-X devices never support ACS, either
3079 * effectively or actually. The shared bus topology implies that
3080 * any device on the bus can receive or snoop DMA.
3082 if (!pci_is_pcie(pdev))
3085 switch (pci_pcie_type(pdev)) {
3087 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3088 * but since their primary interface is PCI/X, we conservatively
3089 * handle them as we would a non-PCIe device.
3091 case PCI_EXP_TYPE_PCIE_BRIDGE:
3093 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3094 * applicable... must never implement an ACS Extended Capability...".
3095 * This seems arbitrary, but we take a conservative interpretation
3096 * of this statement.
3098 case PCI_EXP_TYPE_PCI_BRIDGE:
3099 case PCI_EXP_TYPE_RC_EC:
3102 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3103 * implement ACS in order to indicate their peer-to-peer capabilities,
3104 * regardless of whether they are single- or multi-function devices.
3106 case PCI_EXP_TYPE_DOWNSTREAM:
3107 case PCI_EXP_TYPE_ROOT_PORT:
3108 return pci_acs_flags_enabled(pdev, acs_flags);
3110 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3111 * implemented by the remaining PCIe types to indicate peer-to-peer
3112 * capabilities, but only when they are part of a multifunction
3113 * device. The footnote for section 6.12 indicates the specific
3114 * PCIe types included here.
3116 case PCI_EXP_TYPE_ENDPOINT:
3117 case PCI_EXP_TYPE_UPSTREAM:
3118 case PCI_EXP_TYPE_LEG_END:
3119 case PCI_EXP_TYPE_RC_END:
3120 if (!pdev->multifunction)
3123 return pci_acs_flags_enabled(pdev, acs_flags);
3127 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3128 * to single function devices with the exception of downstream ports.
3134 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
3135 * @start: starting downstream device
3136 * @end: ending upstream device or NULL to search to the root bus
3137 * @acs_flags: required flags
3139 * Walk up a device tree from start to end testing PCI ACS support. If
3140 * any step along the way does not support the required flags, return false.
3142 bool pci_acs_path_enabled(struct pci_dev *start,
3143 struct pci_dev *end, u16 acs_flags)
3145 struct pci_dev *pdev, *parent = start;
3150 if (!pci_acs_enabled(pdev, acs_flags))
3153 if (pci_is_root_bus(pdev->bus))
3154 return (end == NULL);
3156 parent = pdev->bus->self;
3157 } while (pdev != end);
3163 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3167 * Helper to find the position of the ctrl register for a BAR.
3168 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3169 * Returns -ENOENT if no ctrl register for the BAR could be found.
3171 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3173 unsigned int pos, nbars, i;
3176 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3180 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3181 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3182 PCI_REBAR_CTRL_NBAR_SHIFT;
3184 for (i = 0; i < nbars; i++, pos += 8) {
3187 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3188 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3197 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3199 * @bar: BAR to query
3201 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3202 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3204 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3209 pos = pci_rebar_find_pos(pdev, bar);
3213 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3214 return (cap & PCI_REBAR_CAP_SIZES) >> 4;
3218 * pci_rebar_get_current_size - get the current size of a BAR
3220 * @bar: BAR to set size to
3222 * Read the size of a BAR from the resizable BAR config.
3223 * Returns size if found or negative error code.
3225 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3230 pos = pci_rebar_find_pos(pdev, bar);
3234 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3235 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> 8;
3239 * pci_rebar_set_size - set a new size for a BAR
3241 * @bar: BAR to set size to
3242 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3244 * Set the new size of a BAR as defined in the spec.
3245 * Returns zero if resizing was successful, error code otherwise.
3247 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3252 pos = pci_rebar_find_pos(pdev, bar);
3256 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3257 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3259 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3264 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3265 * @dev: the PCI device
3266 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3267 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3268 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3269 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3271 * Return 0 if all upstream bridges support AtomicOp routing, egress
3272 * blocking is disabled on all upstream ports, and the root port supports
3273 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3274 * AtomicOp completion), or negative otherwise.
3276 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3278 struct pci_bus *bus = dev->bus;
3279 struct pci_dev *bridge;
3282 if (!pci_is_pcie(dev))
3286 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3287 * AtomicOp requesters. For now, we only support endpoints as
3288 * requesters and root ports as completers. No endpoints as
3289 * completers, and no peer-to-peer.
3292 switch (pci_pcie_type(dev)) {
3293 case PCI_EXP_TYPE_ENDPOINT:
3294 case PCI_EXP_TYPE_LEG_END:
3295 case PCI_EXP_TYPE_RC_END:
3301 while (bus->parent) {
3304 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3306 switch (pci_pcie_type(bridge)) {
3307 /* Ensure switch ports support AtomicOp routing */
3308 case PCI_EXP_TYPE_UPSTREAM:
3309 case PCI_EXP_TYPE_DOWNSTREAM:
3310 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3314 /* Ensure root port supports all the sizes we care about */
3315 case PCI_EXP_TYPE_ROOT_PORT:
3316 if ((cap & cap_mask) != cap_mask)
3321 /* Ensure upstream ports don't block AtomicOps on egress */
3322 if (!bridge->has_secondary_link) {
3323 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3325 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3332 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3333 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3336 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3339 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3340 * @dev: the PCI device
3341 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3343 * Perform INTx swizzling for a device behind one level of bridge. This is
3344 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3345 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3346 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3347 * the PCI Express Base Specification, Revision 2.1)
3349 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3353 if (pci_ari_enabled(dev->bus))
3356 slot = PCI_SLOT(dev->devfn);
3358 return (((pin - 1) + slot) % 4) + 1;
3361 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3369 while (!pci_is_root_bus(dev->bus)) {
3370 pin = pci_swizzle_interrupt_pin(dev, pin);
3371 dev = dev->bus->self;
3378 * pci_common_swizzle - swizzle INTx all the way to root bridge
3379 * @dev: the PCI device
3380 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3382 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3383 * bridges all the way up to a PCI root bus.
3385 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3389 while (!pci_is_root_bus(dev->bus)) {
3390 pin = pci_swizzle_interrupt_pin(dev, pin);
3391 dev = dev->bus->self;
3394 return PCI_SLOT(dev->devfn);
3396 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3399 * pci_release_region - Release a PCI bar
3400 * @pdev: PCI device whose resources were previously reserved by pci_request_region
3401 * @bar: BAR to release
3403 * Releases the PCI I/O and memory resources previously reserved by a
3404 * successful call to pci_request_region. Call this function only
3405 * after all use of the PCI regions has ceased.
3407 void pci_release_region(struct pci_dev *pdev, int bar)
3409 struct pci_devres *dr;
3411 if (pci_resource_len(pdev, bar) == 0)
3413 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3414 release_region(pci_resource_start(pdev, bar),
3415 pci_resource_len(pdev, bar));
3416 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3417 release_mem_region(pci_resource_start(pdev, bar),
3418 pci_resource_len(pdev, bar));
3420 dr = find_pci_dr(pdev);
3422 dr->region_mask &= ~(1 << bar);
3424 EXPORT_SYMBOL(pci_release_region);
3427 * __pci_request_region - Reserved PCI I/O and memory resource
3428 * @pdev: PCI device whose resources are to be reserved
3429 * @bar: BAR to be reserved
3430 * @res_name: Name to be associated with resource.
3431 * @exclusive: whether the region access is exclusive or not
3433 * Mark the PCI region associated with PCI device @pdev BR @bar as
3434 * being reserved by owner @res_name. Do not access any
3435 * address inside the PCI regions unless this call returns
3438 * If @exclusive is set, then the region is marked so that userspace
3439 * is explicitly not allowed to map the resource via /dev/mem or
3440 * sysfs MMIO access.
3442 * Returns 0 on success, or %EBUSY on error. A warning
3443 * message is also printed on failure.
3445 static int __pci_request_region(struct pci_dev *pdev, int bar,
3446 const char *res_name, int exclusive)
3448 struct pci_devres *dr;
3450 if (pci_resource_len(pdev, bar) == 0)
3453 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3454 if (!request_region(pci_resource_start(pdev, bar),
3455 pci_resource_len(pdev, bar), res_name))
3457 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3458 if (!__request_mem_region(pci_resource_start(pdev, bar),
3459 pci_resource_len(pdev, bar), res_name,
3464 dr = find_pci_dr(pdev);
3466 dr->region_mask |= 1 << bar;
3471 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3472 &pdev->resource[bar]);
3477 * pci_request_region - Reserve PCI I/O and memory resource
3478 * @pdev: PCI device whose resources are to be reserved
3479 * @bar: BAR to be reserved
3480 * @res_name: Name to be associated with resource
3482 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3483 * being reserved by owner @res_name. Do not access any
3484 * address inside the PCI regions unless this call returns
3487 * Returns 0 on success, or %EBUSY on error. A warning
3488 * message is also printed on failure.
3490 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3492 return __pci_request_region(pdev, bar, res_name, 0);
3494 EXPORT_SYMBOL(pci_request_region);
3497 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3498 * @pdev: PCI device whose resources are to be reserved
3499 * @bar: BAR to be reserved
3500 * @res_name: Name to be associated with resource.
3502 * Mark the PCI region associated with PCI device @pdev BR @bar as
3503 * being reserved by owner @res_name. Do not access any
3504 * address inside the PCI regions unless this call returns
3507 * Returns 0 on success, or %EBUSY on error. A warning
3508 * message is also printed on failure.
3510 * The key difference that _exclusive makes it that userspace is
3511 * explicitly not allowed to map the resource via /dev/mem or
3514 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3515 const char *res_name)
3517 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3519 EXPORT_SYMBOL(pci_request_region_exclusive);
3522 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3523 * @pdev: PCI device whose resources were previously reserved
3524 * @bars: Bitmask of BARs to be released
3526 * Release selected PCI I/O and memory resources previously reserved.
3527 * Call this function only after all use of the PCI regions has ceased.
3529 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3533 for (i = 0; i < 6; i++)
3534 if (bars & (1 << i))
3535 pci_release_region(pdev, i);
3537 EXPORT_SYMBOL(pci_release_selected_regions);
3539 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3540 const char *res_name, int excl)
3544 for (i = 0; i < 6; i++)
3545 if (bars & (1 << i))
3546 if (__pci_request_region(pdev, i, res_name, excl))
3552 if (bars & (1 << i))
3553 pci_release_region(pdev, i);
3560 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3561 * @pdev: PCI device whose resources are to be reserved
3562 * @bars: Bitmask of BARs to be requested
3563 * @res_name: Name to be associated with resource
3565 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3566 const char *res_name)
3568 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3570 EXPORT_SYMBOL(pci_request_selected_regions);
3572 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3573 const char *res_name)
3575 return __pci_request_selected_regions(pdev, bars, res_name,
3576 IORESOURCE_EXCLUSIVE);
3578 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3581 * pci_release_regions - Release reserved PCI I/O and memory resources
3582 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3584 * Releases all PCI I/O and memory resources previously reserved by a
3585 * successful call to pci_request_regions. Call this function only
3586 * after all use of the PCI regions has ceased.
3589 void pci_release_regions(struct pci_dev *pdev)
3591 pci_release_selected_regions(pdev, (1 << 6) - 1);
3593 EXPORT_SYMBOL(pci_release_regions);
3596 * pci_request_regions - Reserved PCI I/O and memory resources
3597 * @pdev: PCI device whose resources are to be reserved
3598 * @res_name: Name to be associated with resource.
3600 * Mark all PCI regions associated with PCI device @pdev as
3601 * being reserved by owner @res_name. Do not access any
3602 * address inside the PCI regions unless this call returns
3605 * Returns 0 on success, or %EBUSY on error. A warning
3606 * message is also printed on failure.
3608 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3610 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3612 EXPORT_SYMBOL(pci_request_regions);
3615 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3616 * @pdev: PCI device whose resources are to be reserved
3617 * @res_name: Name to be associated with resource.
3619 * Mark all PCI regions associated with PCI device @pdev as
3620 * being reserved by owner @res_name. Do not access any
3621 * address inside the PCI regions unless this call returns
3624 * pci_request_regions_exclusive() will mark the region so that
3625 * /dev/mem and the sysfs MMIO access will not be allowed.
3627 * Returns 0 on success, or %EBUSY on error. A warning
3628 * message is also printed on failure.
3630 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3632 return pci_request_selected_regions_exclusive(pdev,
3633 ((1 << 6) - 1), res_name);
3635 EXPORT_SYMBOL(pci_request_regions_exclusive);
3638 * Record the PCI IO range (expressed as CPU physical address + size).
3639 * Return a negative value if an error has occured, zero otherwise
3641 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
3642 resource_size_t size)
3646 struct logic_pio_hwaddr *range;
3648 if (!size || addr + size < addr)
3651 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3655 range->fwnode = fwnode;
3657 range->hw_start = addr;
3658 range->flags = LOGIC_PIO_CPU_MMIO;
3660 ret = logic_pio_register_range(range);
3668 phys_addr_t pci_pio_to_address(unsigned long pio)
3670 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3673 if (pio >= MMIO_UPPER_LIMIT)
3676 address = logic_pio_to_hwaddr(pio);
3682 unsigned long __weak pci_address_to_pio(phys_addr_t address)
3685 return logic_pio_trans_cpuaddr(address);
3687 if (address > IO_SPACE_LIMIT)
3688 return (unsigned long)-1;
3690 return (unsigned long) address;
3695 * pci_remap_iospace - Remap the memory mapped I/O space
3696 * @res: Resource describing the I/O space
3697 * @phys_addr: physical address of range to be mapped
3699 * Remap the memory mapped I/O space described by the @res
3700 * and the CPU physical address @phys_addr into virtual address space.
3701 * Only architectures that have memory mapped IO functions defined
3702 * (and the PCI_IOBASE value defined) should call this function.
3704 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3706 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3707 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3709 if (!(res->flags & IORESOURCE_IO))
3712 if (res->end > IO_SPACE_LIMIT)
3715 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3716 pgprot_device(PAGE_KERNEL));
3718 /* this architecture does not have memory mapped I/O space,
3719 so this function should never be called */
3720 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3724 EXPORT_SYMBOL(pci_remap_iospace);
3727 * pci_unmap_iospace - Unmap the memory mapped I/O space
3728 * @res: resource to be unmapped
3730 * Unmap the CPU virtual address @res from virtual address space.
3731 * Only architectures that have memory mapped IO functions defined
3732 * (and the PCI_IOBASE value defined) should call this function.
3734 void pci_unmap_iospace(struct resource *res)
3736 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3737 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3739 unmap_kernel_range(vaddr, resource_size(res));
3742 EXPORT_SYMBOL(pci_unmap_iospace);
3745 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
3746 * @dev: Generic device to remap IO address for
3747 * @offset: Resource address to map
3748 * @size: Size of map
3750 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
3753 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
3754 resource_size_t offset,
3755 resource_size_t size)
3757 void __iomem **ptr, *addr;
3759 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
3763 addr = pci_remap_cfgspace(offset, size);
3766 devres_add(dev, ptr);
3772 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
3775 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
3776 * @dev: generic device to handle the resource for
3777 * @res: configuration space resource to be handled
3779 * Checks that a resource is a valid memory region, requests the memory
3780 * region and ioremaps with pci_remap_cfgspace() API that ensures the
3781 * proper PCI configuration space memory attributes are guaranteed.
3783 * All operations are managed and will be undone on driver detach.
3785 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
3786 * on failure. Usage example::
3788 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3789 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
3791 * return PTR_ERR(base);
3793 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
3794 struct resource *res)
3796 resource_size_t size;
3798 void __iomem *dest_ptr;
3802 if (!res || resource_type(res) != IORESOURCE_MEM) {
3803 dev_err(dev, "invalid resource\n");
3804 return IOMEM_ERR_PTR(-EINVAL);
3807 size = resource_size(res);
3808 name = res->name ?: dev_name(dev);
3810 if (!devm_request_mem_region(dev, res->start, size, name)) {
3811 dev_err(dev, "can't request region for resource %pR\n", res);
3812 return IOMEM_ERR_PTR(-EBUSY);
3815 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
3817 dev_err(dev, "ioremap failed for resource %pR\n", res);
3818 devm_release_mem_region(dev, res->start, size);
3819 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
3824 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
3826 static void __pci_set_master(struct pci_dev *dev, bool enable)
3830 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3832 cmd = old_cmd | PCI_COMMAND_MASTER;
3834 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3835 if (cmd != old_cmd) {
3836 pci_dbg(dev, "%s bus mastering\n",
3837 enable ? "enabling" : "disabling");
3838 pci_write_config_word(dev, PCI_COMMAND, cmd);
3840 dev->is_busmaster = enable;
3844 * pcibios_setup - process "pci=" kernel boot arguments
3845 * @str: string used to pass in "pci=" kernel boot arguments
3847 * Process kernel boot arguments. This is the default implementation.
3848 * Architecture specific implementations can override this as necessary.
3850 char * __weak __init pcibios_setup(char *str)
3856 * pcibios_set_master - enable PCI bus-mastering for device dev
3857 * @dev: the PCI device to enable
3859 * Enables PCI bus-mastering for the device. This is the default
3860 * implementation. Architecture specific implementations can override
3861 * this if necessary.
3863 void __weak pcibios_set_master(struct pci_dev *dev)
3867 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3868 if (pci_is_pcie(dev))
3871 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
3873 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
3874 else if (lat > pcibios_max_latency)
3875 lat = pcibios_max_latency;
3879 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
3883 * pci_set_master - enables bus-mastering for device dev
3884 * @dev: the PCI device to enable
3886 * Enables bus-mastering on the device and calls pcibios_set_master()
3887 * to do the needed arch specific settings.
3889 void pci_set_master(struct pci_dev *dev)
3891 __pci_set_master(dev, true);
3892 pcibios_set_master(dev);
3894 EXPORT_SYMBOL(pci_set_master);
3897 * pci_clear_master - disables bus-mastering for device dev
3898 * @dev: the PCI device to disable
3900 void pci_clear_master(struct pci_dev *dev)
3902 __pci_set_master(dev, false);
3904 EXPORT_SYMBOL(pci_clear_master);
3907 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3908 * @dev: the PCI device for which MWI is to be enabled
3910 * Helper function for pci_set_mwi.
3911 * Originally copied from drivers/net/acenic.c.
3912 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3914 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3916 int pci_set_cacheline_size(struct pci_dev *dev)
3920 if (!pci_cache_line_size)
3923 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3924 equal to or multiple of the right value. */
3925 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3926 if (cacheline_size >= pci_cache_line_size &&
3927 (cacheline_size % pci_cache_line_size) == 0)
3930 /* Write the correct value. */
3931 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
3933 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3934 if (cacheline_size == pci_cache_line_size)
3937 pci_printk(KERN_DEBUG, dev, "cache line size of %d is not supported\n",
3938 pci_cache_line_size << 2);
3942 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
3945 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3946 * @dev: the PCI device for which MWI is enabled
3948 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3950 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3952 int pci_set_mwi(struct pci_dev *dev)
3954 #ifdef PCI_DISABLE_MWI
3960 rc = pci_set_cacheline_size(dev);
3964 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3965 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
3966 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
3967 cmd |= PCI_COMMAND_INVALIDATE;
3968 pci_write_config_word(dev, PCI_COMMAND, cmd);
3973 EXPORT_SYMBOL(pci_set_mwi);
3976 * pcim_set_mwi - a device-managed pci_set_mwi()
3977 * @dev: the PCI device for which MWI is enabled
3979 * Managed pci_set_mwi().
3981 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3983 int pcim_set_mwi(struct pci_dev *dev)
3985 struct pci_devres *dr;
3987 dr = find_pci_dr(dev);
3992 return pci_set_mwi(dev);
3994 EXPORT_SYMBOL(pcim_set_mwi);
3997 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3998 * @dev: the PCI device for which MWI is enabled
4000 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4001 * Callers are not required to check the return value.
4003 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4005 int pci_try_set_mwi(struct pci_dev *dev)
4007 #ifdef PCI_DISABLE_MWI
4010 return pci_set_mwi(dev);
4013 EXPORT_SYMBOL(pci_try_set_mwi);
4016 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4017 * @dev: the PCI device to disable
4019 * Disables PCI Memory-Write-Invalidate transaction on the device
4021 void pci_clear_mwi(struct pci_dev *dev)
4023 #ifndef PCI_DISABLE_MWI
4026 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4027 if (cmd & PCI_COMMAND_INVALIDATE) {
4028 cmd &= ~PCI_COMMAND_INVALIDATE;
4029 pci_write_config_word(dev, PCI_COMMAND, cmd);
4033 EXPORT_SYMBOL(pci_clear_mwi);
4036 * pci_intx - enables/disables PCI INTx for device dev
4037 * @pdev: the PCI device to operate on
4038 * @enable: boolean: whether to enable or disable PCI INTx
4040 * Enables/disables PCI INTx for device dev
4042 void pci_intx(struct pci_dev *pdev, int enable)
4044 u16 pci_command, new;
4046 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4049 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4051 new = pci_command | PCI_COMMAND_INTX_DISABLE;
4053 if (new != pci_command) {
4054 struct pci_devres *dr;
4056 pci_write_config_word(pdev, PCI_COMMAND, new);
4058 dr = find_pci_dr(pdev);
4059 if (dr && !dr->restore_intx) {
4060 dr->restore_intx = 1;
4061 dr->orig_intx = !enable;
4065 EXPORT_SYMBOL_GPL(pci_intx);
4067 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4069 struct pci_bus *bus = dev->bus;
4070 bool mask_updated = true;
4071 u32 cmd_status_dword;
4072 u16 origcmd, newcmd;
4073 unsigned long flags;
4077 * We do a single dword read to retrieve both command and status.
4078 * Document assumptions that make this possible.
4080 BUILD_BUG_ON(PCI_COMMAND % 4);
4081 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4083 raw_spin_lock_irqsave(&pci_lock, flags);
4085 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4087 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4090 * Check interrupt status register to see whether our device
4091 * triggered the interrupt (when masking) or the next IRQ is
4092 * already pending (when unmasking).
4094 if (mask != irq_pending) {
4095 mask_updated = false;
4099 origcmd = cmd_status_dword;
4100 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4102 newcmd |= PCI_COMMAND_INTX_DISABLE;
4103 if (newcmd != origcmd)
4104 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4107 raw_spin_unlock_irqrestore(&pci_lock, flags);
4109 return mask_updated;
4113 * pci_check_and_mask_intx - mask INTx on pending interrupt
4114 * @dev: the PCI device to operate on
4116 * Check if the device dev has its INTx line asserted, mask it and
4117 * return true in that case. False is returned if no interrupt was
4120 bool pci_check_and_mask_intx(struct pci_dev *dev)
4122 return pci_check_and_set_intx_mask(dev, true);
4124 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4127 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4128 * @dev: the PCI device to operate on
4130 * Check if the device dev has its INTx line asserted, unmask it if not
4131 * and return true. False is returned and the mask remains active if
4132 * there was still an interrupt pending.
4134 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4136 return pci_check_and_set_intx_mask(dev, false);
4138 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4141 * pci_wait_for_pending_transaction - waits for pending transaction
4142 * @dev: the PCI device to operate on
4144 * Return 0 if transaction is pending 1 otherwise.
4146 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4148 if (!pci_is_pcie(dev))
4151 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4152 PCI_EXP_DEVSTA_TRPND);
4154 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4156 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
4162 * After reset, the device should not silently discard config
4163 * requests, but it may still indicate that it needs more time by
4164 * responding to them with CRS completions. The Root Port will
4165 * generally synthesize ~0 data to complete the read (except when
4166 * CRS SV is enabled and the read was for the Vendor ID; in that
4167 * case it synthesizes 0x0001 data).
4169 * Wait for the device to return a non-CRS completion. Read the
4170 * Command register instead of Vendor ID so we don't have to
4171 * contend with the CRS SV value.
4173 pci_read_config_dword(dev, PCI_COMMAND, &id);
4175 if (delay > timeout) {
4176 pci_warn(dev, "not ready %dms after %s; giving up\n",
4177 delay - 1, reset_type);
4182 pci_info(dev, "not ready %dms after %s; waiting\n",
4183 delay - 1, reset_type);
4187 pci_read_config_dword(dev, PCI_COMMAND, &id);
4191 pci_info(dev, "ready %dms after %s\n", delay - 1,
4198 * pcie_has_flr - check if a device supports function level resets
4199 * @dev: device to check
4201 * Returns true if the device advertises support for PCIe function level
4204 static bool pcie_has_flr(struct pci_dev *dev)
4208 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4211 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
4212 return cap & PCI_EXP_DEVCAP_FLR;
4216 * pcie_flr - initiate a PCIe function level reset
4217 * @dev: device to reset
4219 * Initiate a function level reset on @dev. The caller should ensure the
4220 * device supports FLR before calling this function, e.g. by using the
4221 * pcie_has_flr() helper.
4223 int pcie_flr(struct pci_dev *dev)
4225 if (!pci_wait_for_pending_transaction(dev))
4226 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4228 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4231 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4232 * 100ms, but may silently discard requests while the FLR is in
4233 * progress. Wait 100ms before trying to access the device.
4237 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4239 EXPORT_SYMBOL_GPL(pcie_flr);
4241 static int pci_af_flr(struct pci_dev *dev, int probe)
4246 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4250 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4253 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4254 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4261 * Wait for Transaction Pending bit to clear. A word-aligned test
4262 * is used, so we use the conrol offset rather than status and shift
4263 * the test bit to match.
4265 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4266 PCI_AF_STATUS_TP << 8))
4267 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4269 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4272 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4273 * updated 27 July 2006; a device must complete an FLR within
4274 * 100ms, but may silently discard requests while the FLR is in
4275 * progress. Wait 100ms before trying to access the device.
4279 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4283 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4284 * @dev: Device to reset.
4285 * @probe: If set, only check if the device can be reset this way.
4287 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4288 * unset, it will be reinitialized internally when going from PCI_D3hot to
4289 * PCI_D0. If that's the case and the device is not in a low-power state
4290 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4292 * NOTE: This causes the caller to sleep for twice the device power transition
4293 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4294 * by default (i.e. unless the @dev's d3_delay field has a different value).
4295 * Moreover, only devices in D0 can be reset by this function.
4297 static int pci_pm_reset(struct pci_dev *dev, int probe)
4301 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4304 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4305 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4311 if (dev->current_state != PCI_D0)
4314 csr &= ~PCI_PM_CTRL_STATE_MASK;
4316 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4317 pci_dev_d3_sleep(dev);
4319 csr &= ~PCI_PM_CTRL_STATE_MASK;
4321 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4322 pci_dev_d3_sleep(dev);
4324 return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS);
4327 * pcie_wait_for_link - Wait until link is active or inactive
4328 * @pdev: Bridge device
4329 * @active: waiting for active or inactive?
4331 * Use this to wait till link becomes active or inactive.
4333 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4340 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4341 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4350 pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n",
4351 active ? "set" : "cleared");
4356 void pci_reset_secondary_bus(struct pci_dev *dev)
4360 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4361 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4362 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4365 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4366 * this to 2ms to ensure that we meet the minimum requirement.
4370 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
4371 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4374 * Trhfa for conventional PCI is 2^25 clock cycles.
4375 * Assuming a minimum 33MHz clock this results in a 1s
4376 * delay before we can consider subordinate devices to
4377 * be re-initialized. PCIe has some ways to shorten this,
4378 * but we don't make use of them yet.
4383 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4385 pci_reset_secondary_bus(dev);
4389 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
4390 * @dev: Bridge device
4392 * Use the bridge control register to assert reset on the secondary bus.
4393 * Devices on the secondary bus are left in power-on state.
4395 int pci_reset_bridge_secondary_bus(struct pci_dev *dev)
4397 pcibios_reset_secondary_bus(dev);
4399 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
4401 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
4403 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4405 struct pci_dev *pdev;
4407 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4408 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4411 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4418 pci_reset_bridge_secondary_bus(dev->bus->self);
4423 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
4427 if (!hotplug || !try_module_get(hotplug->ops->owner))
4430 if (hotplug->ops->reset_slot)
4431 rc = hotplug->ops->reset_slot(hotplug, probe);
4433 module_put(hotplug->ops->owner);
4438 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
4440 struct pci_dev *pdev;
4442 if (dev->subordinate || !dev->slot ||
4443 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4446 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4447 if (pdev != dev && pdev->slot == dev->slot)
4450 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
4453 static void pci_dev_lock(struct pci_dev *dev)
4455 pci_cfg_access_lock(dev);
4456 /* block PM suspend, driver probe, etc. */
4457 device_lock(&dev->dev);
4460 /* Return 1 on successful lock, 0 on contention */
4461 static int pci_dev_trylock(struct pci_dev *dev)
4463 if (pci_cfg_access_trylock(dev)) {
4464 if (device_trylock(&dev->dev))
4466 pci_cfg_access_unlock(dev);
4472 static void pci_dev_unlock(struct pci_dev *dev)
4474 device_unlock(&dev->dev);
4475 pci_cfg_access_unlock(dev);
4478 static void pci_dev_save_and_disable(struct pci_dev *dev)
4480 const struct pci_error_handlers *err_handler =
4481 dev->driver ? dev->driver->err_handler : NULL;
4484 * dev->driver->err_handler->reset_prepare() is protected against
4485 * races with ->remove() by the device lock, which must be held by
4488 if (err_handler && err_handler->reset_prepare)
4489 err_handler->reset_prepare(dev);
4492 * Wake-up device prior to save. PM registers default to D0 after
4493 * reset and a simple register restore doesn't reliably return
4494 * to a non-D0 state anyway.
4496 pci_set_power_state(dev, PCI_D0);
4498 pci_save_state(dev);
4500 * Disable the device by clearing the Command register, except for
4501 * INTx-disable which is set. This not only disables MMIO and I/O port
4502 * BARs, but also prevents the device from being Bus Master, preventing
4503 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4504 * compliant devices, INTx-disable prevents legacy interrupts.
4506 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4509 static void pci_dev_restore(struct pci_dev *dev)
4511 const struct pci_error_handlers *err_handler =
4512 dev->driver ? dev->driver->err_handler : NULL;
4514 pci_restore_state(dev);
4517 * dev->driver->err_handler->reset_done() is protected against
4518 * races with ->remove() by the device lock, which must be held by
4521 if (err_handler && err_handler->reset_done)
4522 err_handler->reset_done(dev);
4526 * __pci_reset_function_locked - reset a PCI device function while holding
4527 * the @dev mutex lock.
4528 * @dev: PCI device to reset
4530 * Some devices allow an individual function to be reset without affecting
4531 * other functions in the same device. The PCI device must be responsive
4532 * to PCI config space in order to use this function.
4534 * The device function is presumed to be unused and the caller is holding
4535 * the device mutex lock when this function is called.
4536 * Resetting the device will make the contents of PCI configuration space
4537 * random, so any caller of this must be prepared to reinitialise the
4538 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4541 * Returns 0 if the device function was successfully reset or negative if the
4542 * device doesn't support resetting a single function.
4544 int __pci_reset_function_locked(struct pci_dev *dev)
4551 * A reset method returns -ENOTTY if it doesn't support this device
4552 * and we should try the next method.
4554 * If it returns 0 (success), we're finished. If it returns any
4555 * other error, we're also finished: this indicates that further
4556 * reset mechanisms might be broken on the device.
4558 rc = pci_dev_specific_reset(dev, 0);
4561 if (pcie_has_flr(dev)) {
4566 rc = pci_af_flr(dev, 0);
4569 rc = pci_pm_reset(dev, 0);
4572 rc = pci_dev_reset_slot_function(dev, 0);
4575 return pci_parent_bus_reset(dev, 0);
4577 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4580 * pci_probe_reset_function - check whether the device can be safely reset
4581 * @dev: PCI device to reset
4583 * Some devices allow an individual function to be reset without affecting
4584 * other functions in the same device. The PCI device must be responsive
4585 * to PCI config space in order to use this function.
4587 * Returns 0 if the device function can be reset or negative if the
4588 * device doesn't support resetting a single function.
4590 int pci_probe_reset_function(struct pci_dev *dev)
4596 rc = pci_dev_specific_reset(dev, 1);
4599 if (pcie_has_flr(dev))
4601 rc = pci_af_flr(dev, 1);
4604 rc = pci_pm_reset(dev, 1);
4607 rc = pci_dev_reset_slot_function(dev, 1);
4611 return pci_parent_bus_reset(dev, 1);
4615 * pci_reset_function - quiesce and reset a PCI device function
4616 * @dev: PCI device to reset
4618 * Some devices allow an individual function to be reset without affecting
4619 * other functions in the same device. The PCI device must be responsive
4620 * to PCI config space in order to use this function.
4622 * This function does not just reset the PCI portion of a device, but
4623 * clears all the state associated with the device. This function differs
4624 * from __pci_reset_function_locked() in that it saves and restores device state
4625 * over the reset and takes the PCI device lock.
4627 * Returns 0 if the device function was successfully reset or negative if the
4628 * device doesn't support resetting a single function.
4630 int pci_reset_function(struct pci_dev *dev)
4638 pci_dev_save_and_disable(dev);
4640 rc = __pci_reset_function_locked(dev);
4642 pci_dev_restore(dev);
4643 pci_dev_unlock(dev);
4647 EXPORT_SYMBOL_GPL(pci_reset_function);
4650 * pci_reset_function_locked - quiesce and reset a PCI device function
4651 * @dev: PCI device to reset
4653 * Some devices allow an individual function to be reset without affecting
4654 * other functions in the same device. The PCI device must be responsive
4655 * to PCI config space in order to use this function.
4657 * This function does not just reset the PCI portion of a device, but
4658 * clears all the state associated with the device. This function differs
4659 * from __pci_reset_function_locked() in that it saves and restores device state
4660 * over the reset. It also differs from pci_reset_function() in that it
4661 * requires the PCI device lock to be held.
4663 * Returns 0 if the device function was successfully reset or negative if the
4664 * device doesn't support resetting a single function.
4666 int pci_reset_function_locked(struct pci_dev *dev)
4673 pci_dev_save_and_disable(dev);
4675 rc = __pci_reset_function_locked(dev);
4677 pci_dev_restore(dev);
4681 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
4684 * pci_try_reset_function - quiesce and reset a PCI device function
4685 * @dev: PCI device to reset
4687 * Same as above, except return -EAGAIN if unable to lock device.
4689 int pci_try_reset_function(struct pci_dev *dev)
4696 if (!pci_dev_trylock(dev))
4699 pci_dev_save_and_disable(dev);
4700 rc = __pci_reset_function_locked(dev);
4701 pci_dev_restore(dev);
4702 pci_dev_unlock(dev);
4706 EXPORT_SYMBOL_GPL(pci_try_reset_function);
4708 /* Do any devices on or below this bus prevent a bus reset? */
4709 static bool pci_bus_resetable(struct pci_bus *bus)
4711 struct pci_dev *dev;
4714 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4717 list_for_each_entry(dev, &bus->devices, bus_list) {
4718 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4719 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4726 /* Lock devices from the top of the tree down */
4727 static void pci_bus_lock(struct pci_bus *bus)
4729 struct pci_dev *dev;
4731 list_for_each_entry(dev, &bus->devices, bus_list) {
4733 if (dev->subordinate)
4734 pci_bus_lock(dev->subordinate);
4738 /* Unlock devices from the bottom of the tree up */
4739 static void pci_bus_unlock(struct pci_bus *bus)
4741 struct pci_dev *dev;
4743 list_for_each_entry(dev, &bus->devices, bus_list) {
4744 if (dev->subordinate)
4745 pci_bus_unlock(dev->subordinate);
4746 pci_dev_unlock(dev);
4750 /* Return 1 on successful lock, 0 on contention */
4751 static int pci_bus_trylock(struct pci_bus *bus)
4753 struct pci_dev *dev;
4755 list_for_each_entry(dev, &bus->devices, bus_list) {
4756 if (!pci_dev_trylock(dev))
4758 if (dev->subordinate) {
4759 if (!pci_bus_trylock(dev->subordinate)) {
4760 pci_dev_unlock(dev);
4768 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
4769 if (dev->subordinate)
4770 pci_bus_unlock(dev->subordinate);
4771 pci_dev_unlock(dev);
4776 /* Do any devices on or below this slot prevent a bus reset? */
4777 static bool pci_slot_resetable(struct pci_slot *slot)
4779 struct pci_dev *dev;
4781 if (slot->bus->self &&
4782 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4785 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4786 if (!dev->slot || dev->slot != slot)
4788 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4789 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4796 /* Lock devices from the top of the tree down */
4797 static void pci_slot_lock(struct pci_slot *slot)
4799 struct pci_dev *dev;
4801 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4802 if (!dev->slot || dev->slot != slot)
4805 if (dev->subordinate)
4806 pci_bus_lock(dev->subordinate);
4810 /* Unlock devices from the bottom of the tree up */
4811 static void pci_slot_unlock(struct pci_slot *slot)
4813 struct pci_dev *dev;
4815 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4816 if (!dev->slot || dev->slot != slot)
4818 if (dev->subordinate)
4819 pci_bus_unlock(dev->subordinate);
4820 pci_dev_unlock(dev);
4824 /* Return 1 on successful lock, 0 on contention */
4825 static int pci_slot_trylock(struct pci_slot *slot)
4827 struct pci_dev *dev;
4829 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4830 if (!dev->slot || dev->slot != slot)
4832 if (!pci_dev_trylock(dev))
4834 if (dev->subordinate) {
4835 if (!pci_bus_trylock(dev->subordinate)) {
4836 pci_dev_unlock(dev);
4844 list_for_each_entry_continue_reverse(dev,
4845 &slot->bus->devices, bus_list) {
4846 if (!dev->slot || dev->slot != slot)
4848 if (dev->subordinate)
4849 pci_bus_unlock(dev->subordinate);
4850 pci_dev_unlock(dev);
4855 /* Save and disable devices from the top of the tree down */
4856 static void pci_bus_save_and_disable(struct pci_bus *bus)
4858 struct pci_dev *dev;
4860 list_for_each_entry(dev, &bus->devices, bus_list) {
4862 pci_dev_save_and_disable(dev);
4863 pci_dev_unlock(dev);
4864 if (dev->subordinate)
4865 pci_bus_save_and_disable(dev->subordinate);
4870 * Restore devices from top of the tree down - parent bridges need to be
4871 * restored before we can get to subordinate devices.
4873 static void pci_bus_restore(struct pci_bus *bus)
4875 struct pci_dev *dev;
4877 list_for_each_entry(dev, &bus->devices, bus_list) {
4879 pci_dev_restore(dev);
4880 pci_dev_unlock(dev);
4881 if (dev->subordinate)
4882 pci_bus_restore(dev->subordinate);
4886 /* Save and disable devices from the top of the tree down */
4887 static void pci_slot_save_and_disable(struct pci_slot *slot)
4889 struct pci_dev *dev;
4891 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4892 if (!dev->slot || dev->slot != slot)
4894 pci_dev_save_and_disable(dev);
4895 if (dev->subordinate)
4896 pci_bus_save_and_disable(dev->subordinate);
4901 * Restore devices from top of the tree down - parent bridges need to be
4902 * restored before we can get to subordinate devices.
4904 static void pci_slot_restore(struct pci_slot *slot)
4906 struct pci_dev *dev;
4908 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4909 if (!dev->slot || dev->slot != slot)
4912 pci_dev_restore(dev);
4913 pci_dev_unlock(dev);
4914 if (dev->subordinate)
4915 pci_bus_restore(dev->subordinate);
4919 static int pci_slot_reset(struct pci_slot *slot, int probe)
4923 if (!slot || !pci_slot_resetable(slot))
4927 pci_slot_lock(slot);
4931 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
4934 pci_slot_unlock(slot);
4940 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4941 * @slot: PCI slot to probe
4943 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4945 int pci_probe_reset_slot(struct pci_slot *slot)
4947 return pci_slot_reset(slot, 1);
4949 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
4952 * pci_reset_slot - reset a PCI slot
4953 * @slot: PCI slot to reset
4955 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4956 * independent of other slots. For instance, some slots may support slot power
4957 * control. In the case of a 1:1 bus to slot architecture, this function may
4958 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4959 * Generally a slot reset should be attempted before a bus reset. All of the
4960 * function of the slot and any subordinate buses behind the slot are reset
4961 * through this function. PCI config space of all devices in the slot and
4962 * behind the slot is saved before and restored after reset.
4964 * Return 0 on success, non-zero on error.
4966 int pci_reset_slot(struct pci_slot *slot)
4970 rc = pci_slot_reset(slot, 1);
4974 pci_slot_save_and_disable(slot);
4976 rc = pci_slot_reset(slot, 0);
4978 pci_slot_restore(slot);
4982 EXPORT_SYMBOL_GPL(pci_reset_slot);
4985 * pci_try_reset_slot - Try to reset a PCI slot
4986 * @slot: PCI slot to reset
4988 * Same as above except return -EAGAIN if the slot cannot be locked
4990 int pci_try_reset_slot(struct pci_slot *slot)
4994 rc = pci_slot_reset(slot, 1);
4998 pci_slot_save_and_disable(slot);
5000 if (pci_slot_trylock(slot)) {
5002 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
5003 pci_slot_unlock(slot);
5007 pci_slot_restore(slot);
5011 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
5013 static int pci_bus_reset(struct pci_bus *bus, int probe)
5015 if (!bus->self || !pci_bus_resetable(bus))
5025 pci_reset_bridge_secondary_bus(bus->self);
5027 pci_bus_unlock(bus);
5033 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5034 * @bus: PCI bus to probe
5036 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5038 int pci_probe_reset_bus(struct pci_bus *bus)
5040 return pci_bus_reset(bus, 1);
5042 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
5045 * pci_reset_bus - reset a PCI bus
5046 * @bus: top level PCI bus to reset
5048 * Do a bus reset on the given bus and any subordinate buses, saving
5049 * and restoring state of all devices.
5051 * Return 0 on success, non-zero on error.
5053 int pci_reset_bus(struct pci_bus *bus)
5057 rc = pci_bus_reset(bus, 1);
5061 pci_bus_save_and_disable(bus);
5063 rc = pci_bus_reset(bus, 0);
5065 pci_bus_restore(bus);
5069 EXPORT_SYMBOL_GPL(pci_reset_bus);
5072 * pci_try_reset_bus - Try to reset a PCI bus
5073 * @bus: top level PCI bus to reset
5075 * Same as above except return -EAGAIN if the bus cannot be locked
5077 int pci_try_reset_bus(struct pci_bus *bus)
5081 rc = pci_bus_reset(bus, 1);
5085 pci_bus_save_and_disable(bus);
5087 if (pci_bus_trylock(bus)) {
5089 pci_reset_bridge_secondary_bus(bus->self);
5090 pci_bus_unlock(bus);
5094 pci_bus_restore(bus);
5098 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
5101 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5102 * @dev: PCI device to query
5104 * Returns mmrbc: maximum designed memory read count in bytes
5105 * or appropriate error value.
5107 int pcix_get_max_mmrbc(struct pci_dev *dev)
5112 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5116 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5119 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5121 EXPORT_SYMBOL(pcix_get_max_mmrbc);
5124 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5125 * @dev: PCI device to query
5127 * Returns mmrbc: maximum memory read count in bytes
5128 * or appropriate error value.
5130 int pcix_get_mmrbc(struct pci_dev *dev)
5135 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5139 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5142 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5144 EXPORT_SYMBOL(pcix_get_mmrbc);
5147 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5148 * @dev: PCI device to query
5149 * @mmrbc: maximum memory read count in bytes
5150 * valid values are 512, 1024, 2048, 4096
5152 * If possible sets maximum memory read byte count, some bridges have erratas
5153 * that prevent this.
5155 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5161 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5164 v = ffs(mmrbc) - 10;
5166 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5170 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5173 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5176 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5179 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5181 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5184 cmd &= ~PCI_X_CMD_MAX_READ;
5186 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5191 EXPORT_SYMBOL(pcix_set_mmrbc);
5194 * pcie_get_readrq - get PCI Express read request size
5195 * @dev: PCI device to query
5197 * Returns maximum memory read request in bytes
5198 * or appropriate error value.
5200 int pcie_get_readrq(struct pci_dev *dev)
5204 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5206 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5208 EXPORT_SYMBOL(pcie_get_readrq);
5211 * pcie_set_readrq - set PCI Express maximum memory read request
5212 * @dev: PCI device to query
5213 * @rq: maximum memory read count in bytes
5214 * valid values are 128, 256, 512, 1024, 2048, 4096
5216 * If possible sets maximum memory read request in bytes
5218 int pcie_set_readrq(struct pci_dev *dev, int rq)
5222 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5226 * If using the "performance" PCIe config, we clamp the
5227 * read rq size to the max packet size to prevent the
5228 * host bridge generating requests larger than we can
5231 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5232 int mps = pcie_get_mps(dev);
5238 v = (ffs(rq) - 8) << 12;
5240 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5241 PCI_EXP_DEVCTL_READRQ, v);
5243 EXPORT_SYMBOL(pcie_set_readrq);
5246 * pcie_get_mps - get PCI Express maximum payload size
5247 * @dev: PCI device to query
5249 * Returns maximum payload size in bytes
5251 int pcie_get_mps(struct pci_dev *dev)
5255 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5257 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5259 EXPORT_SYMBOL(pcie_get_mps);
5262 * pcie_set_mps - set PCI Express maximum payload size
5263 * @dev: PCI device to query
5264 * @mps: maximum payload size in bytes
5265 * valid values are 128, 256, 512, 1024, 2048, 4096
5267 * If possible sets maximum payload size
5269 int pcie_set_mps(struct pci_dev *dev, int mps)
5273 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
5277 if (v > dev->pcie_mpss)
5281 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5282 PCI_EXP_DEVCTL_PAYLOAD, v);
5284 EXPORT_SYMBOL(pcie_set_mps);
5287 * pcie_bandwidth_available - determine minimum link settings of a PCIe
5288 * device and its bandwidth limitation
5289 * @dev: PCI device to query
5290 * @limiting_dev: storage for device causing the bandwidth limitation
5291 * @speed: storage for speed of limiting device
5292 * @width: storage for width of limiting device
5294 * Walk up the PCI device chain and find the point where the minimum
5295 * bandwidth is available. Return the bandwidth available there and (if
5296 * limiting_dev, speed, and width pointers are supplied) information about
5297 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
5300 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
5301 enum pci_bus_speed *speed,
5302 enum pcie_link_width *width)
5305 enum pci_bus_speed next_speed;
5306 enum pcie_link_width next_width;
5310 *speed = PCI_SPEED_UNKNOWN;
5312 *width = PCIE_LNK_WIDTH_UNKNOWN;
5317 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
5319 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
5320 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
5321 PCI_EXP_LNKSTA_NLW_SHIFT;
5323 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
5325 /* Check if current device limits the total bandwidth */
5326 if (!bw || next_bw <= bw) {
5330 *limiting_dev = dev;
5332 *speed = next_speed;
5334 *width = next_width;
5337 dev = pci_upstream_bridge(dev);
5342 EXPORT_SYMBOL(pcie_bandwidth_available);
5345 * pcie_get_speed_cap - query for the PCI device's link speed capability
5346 * @dev: PCI device to query
5348 * Query the PCI device speed capability. Return the maximum link speed
5349 * supported by the device.
5351 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
5353 u32 lnkcap2, lnkcap;
5356 * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link
5357 * Speeds Vector in Link Capabilities 2 when supported, falling
5358 * back to Max Link Speed in Link Capabilities otherwise.
5360 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
5361 if (lnkcap2) { /* PCIe r3.0-compliant */
5362 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
5363 return PCIE_SPEED_16_0GT;
5364 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
5365 return PCIE_SPEED_8_0GT;
5366 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
5367 return PCIE_SPEED_5_0GT;
5368 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
5369 return PCIE_SPEED_2_5GT;
5370 return PCI_SPEED_UNKNOWN;
5373 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5375 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
5376 return PCIE_SPEED_16_0GT;
5377 else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
5378 return PCIE_SPEED_8_0GT;
5379 else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
5380 return PCIE_SPEED_5_0GT;
5381 else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
5382 return PCIE_SPEED_2_5GT;
5385 return PCI_SPEED_UNKNOWN;
5389 * pcie_get_width_cap - query for the PCI device's link width capability
5390 * @dev: PCI device to query
5392 * Query the PCI device width capability. Return the maximum link width
5393 * supported by the device.
5395 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
5399 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5401 return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
5403 return PCIE_LNK_WIDTH_UNKNOWN;
5407 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
5409 * @speed: storage for link speed
5410 * @width: storage for link width
5412 * Calculate a PCI device's link bandwidth by querying for its link speed
5413 * and width, multiplying them, and applying encoding overhead. The result
5414 * is in Mb/s, i.e., megabits/second of raw bandwidth.
5416 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
5417 enum pcie_link_width *width)
5419 *speed = pcie_get_speed_cap(dev);
5420 *width = pcie_get_width_cap(dev);
5422 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
5425 return *width * PCIE_SPEED2MBS_ENC(*speed);
5429 * pcie_print_link_status - Report the PCI device's link speed and width
5430 * @dev: PCI device to query
5432 * Report the available bandwidth at the device. If this is less than the
5433 * device is capable of, report the device's maximum possible bandwidth and
5434 * the upstream link that limits its performance to less than that.
5436 void pcie_print_link_status(struct pci_dev *dev)
5438 enum pcie_link_width width, width_cap;
5439 enum pci_bus_speed speed, speed_cap;
5440 struct pci_dev *limiting_dev = NULL;
5441 u32 bw_avail, bw_cap;
5443 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
5444 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
5446 if (bw_avail >= bw_cap)
5447 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
5448 bw_cap / 1000, bw_cap % 1000,
5449 PCIE_SPEED2STR(speed_cap), width_cap);
5451 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
5452 bw_avail / 1000, bw_avail % 1000,
5453 PCIE_SPEED2STR(speed), width,
5454 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
5455 bw_cap / 1000, bw_cap % 1000,
5456 PCIE_SPEED2STR(speed_cap), width_cap);
5458 EXPORT_SYMBOL(pcie_print_link_status);
5461 * pci_select_bars - Make BAR mask from the type of resource
5462 * @dev: the PCI device for which BAR mask is made
5463 * @flags: resource type mask to be selected
5465 * This helper routine makes bar mask from the type of resource.
5467 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
5470 for (i = 0; i < PCI_NUM_RESOURCES; i++)
5471 if (pci_resource_flags(dev, i) & flags)
5475 EXPORT_SYMBOL(pci_select_bars);
5477 /* Some architectures require additional programming to enable VGA */
5478 static arch_set_vga_state_t arch_set_vga_state;
5480 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
5482 arch_set_vga_state = func; /* NULL disables */
5485 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
5486 unsigned int command_bits, u32 flags)
5488 if (arch_set_vga_state)
5489 return arch_set_vga_state(dev, decode, command_bits,
5495 * pci_set_vga_state - set VGA decode state on device and parents if requested
5496 * @dev: the PCI device
5497 * @decode: true = enable decoding, false = disable decoding
5498 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
5499 * @flags: traverse ancestors and change bridges
5500 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
5502 int pci_set_vga_state(struct pci_dev *dev, bool decode,
5503 unsigned int command_bits, u32 flags)
5505 struct pci_bus *bus;
5506 struct pci_dev *bridge;
5510 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
5512 /* ARCH specific VGA enables */
5513 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
5517 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
5518 pci_read_config_word(dev, PCI_COMMAND, &cmd);
5520 cmd |= command_bits;
5522 cmd &= ~command_bits;
5523 pci_write_config_word(dev, PCI_COMMAND, cmd);
5526 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
5533 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
5536 cmd |= PCI_BRIDGE_CTL_VGA;
5538 cmd &= ~PCI_BRIDGE_CTL_VGA;
5539 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
5548 * pci_add_dma_alias - Add a DMA devfn alias for a device
5549 * @dev: the PCI device for which alias is added
5550 * @devfn: alias slot and function
5552 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
5553 * It should be called early, preferably as PCI fixup header quirk.
5555 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
5557 if (!dev->dma_alias_mask)
5558 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
5559 sizeof(long), GFP_KERNEL);
5560 if (!dev->dma_alias_mask) {
5561 pci_warn(dev, "Unable to allocate DMA alias mask\n");
5565 set_bit(devfn, dev->dma_alias_mask);
5566 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
5567 PCI_SLOT(devfn), PCI_FUNC(devfn));
5570 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
5572 return (dev1->dma_alias_mask &&
5573 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
5574 (dev2->dma_alias_mask &&
5575 test_bit(dev1->devfn, dev2->dma_alias_mask));
5578 bool pci_device_is_present(struct pci_dev *pdev)
5582 if (pci_dev_is_disconnected(pdev))
5584 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
5586 EXPORT_SYMBOL_GPL(pci_device_is_present);
5588 void pci_ignore_hotplug(struct pci_dev *dev)
5590 struct pci_dev *bridge = dev->bus->self;
5592 dev->ignore_hotplug = 1;
5593 /* Propagate the "ignore hotplug" setting to the parent bridge. */
5595 bridge->ignore_hotplug = 1;
5597 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
5599 resource_size_t __weak pcibios_default_alignment(void)
5604 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
5605 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
5606 static DEFINE_SPINLOCK(resource_alignment_lock);
5609 * pci_specified_resource_alignment - get resource alignment specified by user.
5610 * @dev: the PCI device to get
5611 * @resize: whether or not to change resources' size when reassigning alignment
5613 * RETURNS: Resource alignment if it is specified.
5614 * Zero if it is not specified.
5616 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
5619 int align_order, count;
5620 resource_size_t align = pcibios_default_alignment();
5624 spin_lock(&resource_alignment_lock);
5625 p = resource_alignment_param;
5628 if (pci_has_flag(PCI_PROBE_ONLY)) {
5630 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
5636 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
5643 ret = pci_dev_str_match(dev, p, &p);
5646 if (align_order == -1)
5649 align = 1 << align_order;
5651 } else if (ret < 0) {
5652 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
5657 if (*p != ';' && *p != ',') {
5658 /* End of param or invalid format */
5664 spin_unlock(&resource_alignment_lock);
5668 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
5669 resource_size_t align, bool resize)
5671 struct resource *r = &dev->resource[bar];
5672 resource_size_t size;
5674 if (!(r->flags & IORESOURCE_MEM))
5677 if (r->flags & IORESOURCE_PCI_FIXED) {
5678 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
5679 bar, r, (unsigned long long)align);
5683 size = resource_size(r);
5688 * Increase the alignment of the resource. There are two ways we
5691 * 1) Increase the size of the resource. BARs are aligned on their
5692 * size, so when we reallocate space for this resource, we'll
5693 * allocate it with the larger alignment. This also prevents
5694 * assignment of any other BARs inside the alignment region, so
5695 * if we're requesting page alignment, this means no other BARs
5696 * will share the page.
5698 * The disadvantage is that this makes the resource larger than
5699 * the hardware BAR, which may break drivers that compute things
5700 * based on the resource size, e.g., to find registers at a
5701 * fixed offset before the end of the BAR.
5703 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
5704 * set r->start to the desired alignment. By itself this
5705 * doesn't prevent other BARs being put inside the alignment
5706 * region, but if we realign *every* resource of every device in
5707 * the system, none of them will share an alignment region.
5709 * When the user has requested alignment for only some devices via
5710 * the "pci=resource_alignment" argument, "resize" is true and we
5711 * use the first method. Otherwise we assume we're aligning all
5712 * devices and we use the second.
5715 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
5716 bar, r, (unsigned long long)align);
5722 r->flags &= ~IORESOURCE_SIZEALIGN;
5723 r->flags |= IORESOURCE_STARTALIGN;
5725 r->end = r->start + size - 1;
5727 r->flags |= IORESOURCE_UNSET;
5731 * This function disables memory decoding and releases memory resources
5732 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5733 * It also rounds up size to specified alignment.
5734 * Later on, the kernel will assign page-aligned memory resource back
5737 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
5741 resource_size_t align;
5743 bool resize = false;
5746 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
5747 * 3.4.1.11. Their resources are allocated from the space
5748 * described by the VF BARx register in the PF's SR-IOV capability.
5749 * We can't influence their alignment here.
5754 /* check if specified PCI is target device to reassign */
5755 align = pci_specified_resource_alignment(dev, &resize);
5759 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
5760 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
5761 pci_warn(dev, "Can't reassign resources to host bridge\n");
5765 pci_read_config_word(dev, PCI_COMMAND, &command);
5766 command &= ~PCI_COMMAND_MEMORY;
5767 pci_write_config_word(dev, PCI_COMMAND, command);
5769 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
5770 pci_request_resource_alignment(dev, i, align, resize);
5773 * Need to disable bridge's resource window,
5774 * to enable the kernel to reassign new resource
5777 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
5778 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
5779 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
5780 r = &dev->resource[i];
5781 if (!(r->flags & IORESOURCE_MEM))
5783 r->flags |= IORESOURCE_UNSET;
5784 r->end = resource_size(r) - 1;
5787 pci_disable_bridge_window(dev);
5791 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
5793 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
5794 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
5795 spin_lock(&resource_alignment_lock);
5796 strncpy(resource_alignment_param, buf, count);
5797 resource_alignment_param[count] = '\0';
5798 spin_unlock(&resource_alignment_lock);
5802 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
5805 spin_lock(&resource_alignment_lock);
5806 count = snprintf(buf, size, "%s", resource_alignment_param);
5807 spin_unlock(&resource_alignment_lock);
5811 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
5813 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
5816 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
5817 const char *buf, size_t count)
5819 return pci_set_resource_alignment_param(buf, count);
5822 static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
5823 pci_resource_alignment_store);
5825 static int __init pci_resource_alignment_sysfs_init(void)
5827 return bus_create_file(&pci_bus_type,
5828 &bus_attr_resource_alignment);
5830 late_initcall(pci_resource_alignment_sysfs_init);
5832 static void pci_no_domains(void)
5834 #ifdef CONFIG_PCI_DOMAINS
5835 pci_domains_supported = 0;
5839 #ifdef CONFIG_PCI_DOMAINS_GENERIC
5840 static atomic_t __domain_nr = ATOMIC_INIT(-1);
5842 static int pci_get_new_domain_nr(void)
5844 return atomic_inc_return(&__domain_nr);
5847 static int of_pci_bus_find_domain_nr(struct device *parent)
5849 static int use_dt_domains = -1;
5853 domain = of_get_pci_domain_nr(parent->of_node);
5855 * Check DT domain and use_dt_domains values.
5857 * If DT domain property is valid (domain >= 0) and
5858 * use_dt_domains != 0, the DT assignment is valid since this means
5859 * we have not previously allocated a domain number by using
5860 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5861 * 1, to indicate that we have just assigned a domain number from
5864 * If DT domain property value is not valid (ie domain < 0), and we
5865 * have not previously assigned a domain number from DT
5866 * (use_dt_domains != 1) we should assign a domain number by
5869 * pci_get_new_domain_nr()
5871 * API and update the use_dt_domains value to keep track of method we
5872 * are using to assign domain numbers (use_dt_domains = 0).
5874 * All other combinations imply we have a platform that is trying
5875 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5876 * which is a recipe for domain mishandling and it is prevented by
5877 * invalidating the domain value (domain = -1) and printing a
5878 * corresponding error.
5880 if (domain >= 0 && use_dt_domains) {
5882 } else if (domain < 0 && use_dt_domains != 1) {
5884 domain = pci_get_new_domain_nr();
5887 pr_err("Node %pOF has ", parent->of_node);
5888 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
5895 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
5897 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
5898 acpi_pci_bus_find_domain_nr(bus);
5903 * pci_ext_cfg_avail - can we access extended PCI config space?
5905 * Returns 1 if we can access PCI extended config space (offsets
5906 * greater than 0xff). This is the default implementation. Architecture
5907 * implementations can override this.
5909 int __weak pci_ext_cfg_avail(void)
5914 void __weak pci_fixup_cardbus(struct pci_bus *bus)
5917 EXPORT_SYMBOL(pci_fixup_cardbus);
5919 static int __init pci_setup(char *str)
5922 char *k = strchr(str, ',');
5925 if (*str && (str = pcibios_setup(str)) && *str) {
5926 if (!strcmp(str, "nomsi")) {
5928 } else if (!strncmp(str, "noats", 5)) {
5929 pr_info("PCIe: ATS is disabled\n");
5930 pcie_ats_disabled = true;
5931 } else if (!strcmp(str, "noaer")) {
5933 } else if (!strncmp(str, "realloc=", 8)) {
5934 pci_realloc_get_opt(str + 8);
5935 } else if (!strncmp(str, "realloc", 7)) {
5936 pci_realloc_get_opt("on");
5937 } else if (!strcmp(str, "nodomains")) {
5939 } else if (!strncmp(str, "noari", 5)) {
5940 pcie_ari_disabled = true;
5941 } else if (!strncmp(str, "cbiosize=", 9)) {
5942 pci_cardbus_io_size = memparse(str + 9, &str);
5943 } else if (!strncmp(str, "cbmemsize=", 10)) {
5944 pci_cardbus_mem_size = memparse(str + 10, &str);
5945 } else if (!strncmp(str, "resource_alignment=", 19)) {
5946 pci_set_resource_alignment_param(str + 19,
5948 } else if (!strncmp(str, "ecrc=", 5)) {
5949 pcie_ecrc_get_policy(str + 5);
5950 } else if (!strncmp(str, "hpiosize=", 9)) {
5951 pci_hotplug_io_size = memparse(str + 9, &str);
5952 } else if (!strncmp(str, "hpmemsize=", 10)) {
5953 pci_hotplug_mem_size = memparse(str + 10, &str);
5954 } else if (!strncmp(str, "hpbussize=", 10)) {
5955 pci_hotplug_bus_size =
5956 simple_strtoul(str + 10, &str, 0);
5957 if (pci_hotplug_bus_size > 0xff)
5958 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
5959 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
5960 pcie_bus_config = PCIE_BUS_TUNE_OFF;
5961 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
5962 pcie_bus_config = PCIE_BUS_SAFE;
5963 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
5964 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5965 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
5966 pcie_bus_config = PCIE_BUS_PEER2PEER;
5967 } else if (!strncmp(str, "pcie_scan_all", 13)) {
5968 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
5970 printk(KERN_ERR "PCI: Unknown option `%s'\n",
5978 early_param("pci", pci_setup);