1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
17 #include <linux/of_pci.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pci-ats.h>
33 #include <asm/setup.h>
35 #include <linux/aer.h>
38 DEFINE_MUTEX(pci_slot_mutex);
40 const char *pci_power_names[] = {
41 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
43 EXPORT_SYMBOL_GPL(pci_power_names);
45 int isa_dma_bridge_buggy;
46 EXPORT_SYMBOL(isa_dma_bridge_buggy);
49 EXPORT_SYMBOL(pci_pci_problems);
51 unsigned int pci_pm_d3_delay;
53 static void pci_pme_list_scan(struct work_struct *work);
55 static LIST_HEAD(pci_pme_list);
56 static DEFINE_MUTEX(pci_pme_list_mutex);
57 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
59 struct pci_pme_device {
60 struct list_head list;
64 #define PME_TIMEOUT 1000 /* How long between PME checks */
66 static void pci_dev_d3_sleep(struct pci_dev *dev)
68 unsigned int delay = dev->d3_delay;
70 if (delay < pci_pm_d3_delay)
71 delay = pci_pm_d3_delay;
77 #ifdef CONFIG_PCI_DOMAINS
78 int pci_domains_supported = 1;
81 #define DEFAULT_CARDBUS_IO_SIZE (256)
82 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
83 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
84 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
85 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
87 #define DEFAULT_HOTPLUG_IO_SIZE (256)
88 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
89 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
90 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
91 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
93 #define DEFAULT_HOTPLUG_BUS_SIZE 1
94 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
96 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
99 * The default CLS is used if arch didn't set CLS explicitly and not
100 * all pci devices agree on the same value. Arch can override either
101 * the dfl or actual value as it sees fit. Don't forget this is
102 * measured in 32-bit words, not bytes.
104 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
105 u8 pci_cache_line_size;
108 * If we set up a device for bus mastering, we need to check the latency
109 * timer as certain BIOSes forget to set it properly.
111 unsigned int pcibios_max_latency = 255;
113 /* If set, the PCIe ARI capability will not be used. */
114 static bool pcie_ari_disabled;
116 /* If set, the PCIe ATS capability will not be used. */
117 static bool pcie_ats_disabled;
119 /* If set, the PCI config space of each device is printed during boot. */
122 bool pci_ats_disabled(void)
124 return pcie_ats_disabled;
127 /* Disable bridge_d3 for all PCIe ports */
128 static bool pci_bridge_d3_disable;
129 /* Force bridge_d3 for all PCIe ports */
130 static bool pci_bridge_d3_force;
132 static int __init pcie_port_pm_setup(char *str)
134 if (!strcmp(str, "off"))
135 pci_bridge_d3_disable = true;
136 else if (!strcmp(str, "force"))
137 pci_bridge_d3_force = true;
140 __setup("pcie_port_pm=", pcie_port_pm_setup);
142 /* Time to wait after a reset for device to become responsive */
143 #define PCIE_RESET_READY_POLL_MS 60000
146 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
147 * @bus: pointer to PCI bus structure to search
149 * Given a PCI bus, returns the highest PCI bus number present in the set
150 * including the given PCI bus and its list of child PCI buses.
152 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
155 unsigned char max, n;
157 max = bus->busn_res.end;
158 list_for_each_entry(tmp, &bus->children, node) {
159 n = pci_bus_max_busnr(tmp);
165 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
167 #ifdef CONFIG_HAS_IOMEM
168 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
170 struct resource *res = &pdev->resource[bar];
173 * Make sure the BAR is actually a memory resource, not an IO resource
175 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
176 pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
179 return ioremap_nocache(res->start, resource_size(res));
181 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
183 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
186 * Make sure the BAR is actually a memory resource, not an IO resource
188 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
192 return ioremap_wc(pci_resource_start(pdev, bar),
193 pci_resource_len(pdev, bar));
195 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
199 * pci_dev_str_match_path - test if a path string matches a device
200 * @dev: the PCI device to test
201 * @p: string to match the device against
202 * @endptr: pointer to the string after the match
204 * Test if a string (typically from a kernel parameter) formatted as a
205 * path of device/function addresses matches a PCI device. The string must
208 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
210 * A path for a device can be obtained using 'lspci -t'. Using a path
211 * is more robust against bus renumbering than using only a single bus,
212 * device and function address.
214 * Returns 1 if the string matches the device, 0 if it does not and
215 * a negative error code if it fails to parse the string.
217 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
221 int seg, bus, slot, func;
225 *endptr = strchrnul(path, ';');
227 wpath = kmemdup_nul(path, *endptr - path, GFP_KERNEL);
232 p = strrchr(wpath, '/');
235 ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
241 if (dev->devfn != PCI_DEVFN(slot, func)) {
247 * Note: we don't need to get a reference to the upstream
248 * bridge because we hold a reference to the top level
249 * device which should hold a reference to the bridge,
252 dev = pci_upstream_bridge(dev);
261 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
265 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
272 ret = (seg == pci_domain_nr(dev->bus) &&
273 bus == dev->bus->number &&
274 dev->devfn == PCI_DEVFN(slot, func));
282 * pci_dev_str_match - test if a string matches a device
283 * @dev: the PCI device to test
284 * @p: string to match the device against
285 * @endptr: pointer to the string after the match
287 * Test if a string (typically from a kernel parameter) matches a specified
288 * PCI device. The string may be of one of the following formats:
290 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
291 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
293 * The first format specifies a PCI bus/device/function address which
294 * may change if new hardware is inserted, if motherboard firmware changes,
295 * or due to changes caused in kernel parameters. If the domain is
296 * left unspecified, it is taken to be 0. In order to be robust against
297 * bus renumbering issues, a path of PCI device/function numbers may be used
298 * to address the specific device. The path for a device can be determined
299 * through the use of 'lspci -t'.
301 * The second format matches devices using IDs in the configuration
302 * space which may match multiple devices in the system. A value of 0
303 * for any field will match all devices. (Note: this differs from
304 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
305 * legacy reasons and convenience so users don't have to specify
306 * FFFFFFFFs on the command line.)
308 * Returns 1 if the string matches the device, 0 if it does not and
309 * a negative error code if the string cannot be parsed.
311 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
316 unsigned short vendor, device, subsystem_vendor, subsystem_device;
318 if (strncmp(p, "pci:", 4) == 0) {
319 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
321 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
322 &subsystem_vendor, &subsystem_device, &count);
324 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
328 subsystem_vendor = 0;
329 subsystem_device = 0;
334 if ((!vendor || vendor == dev->vendor) &&
335 (!device || device == dev->device) &&
336 (!subsystem_vendor ||
337 subsystem_vendor == dev->subsystem_vendor) &&
338 (!subsystem_device ||
339 subsystem_device == dev->subsystem_device))
343 * PCI Bus, Device, Function IDs are specified
344 * (optionally, may include a path of devfns following it)
346 ret = pci_dev_str_match_path(dev, p, &p);
361 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
362 u8 pos, int cap, int *ttl)
367 pci_bus_read_config_byte(bus, devfn, pos, &pos);
373 pci_bus_read_config_word(bus, devfn, pos, &ent);
385 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
388 int ttl = PCI_FIND_CAP_TTL;
390 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
393 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
395 return __pci_find_next_cap(dev->bus, dev->devfn,
396 pos + PCI_CAP_LIST_NEXT, cap);
398 EXPORT_SYMBOL_GPL(pci_find_next_capability);
400 static int __pci_bus_find_cap_start(struct pci_bus *bus,
401 unsigned int devfn, u8 hdr_type)
405 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
406 if (!(status & PCI_STATUS_CAP_LIST))
410 case PCI_HEADER_TYPE_NORMAL:
411 case PCI_HEADER_TYPE_BRIDGE:
412 return PCI_CAPABILITY_LIST;
413 case PCI_HEADER_TYPE_CARDBUS:
414 return PCI_CB_CAPABILITY_LIST;
421 * pci_find_capability - query for devices' capabilities
422 * @dev: PCI device to query
423 * @cap: capability code
425 * Tell if a device supports a given PCI capability.
426 * Returns the address of the requested capability structure within the
427 * device's PCI configuration space or 0 in case the device does not
428 * support it. Possible values for @cap:
430 * %PCI_CAP_ID_PM Power Management
431 * %PCI_CAP_ID_AGP Accelerated Graphics Port
432 * %PCI_CAP_ID_VPD Vital Product Data
433 * %PCI_CAP_ID_SLOTID Slot Identification
434 * %PCI_CAP_ID_MSI Message Signalled Interrupts
435 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
436 * %PCI_CAP_ID_PCIX PCI-X
437 * %PCI_CAP_ID_EXP PCI Express
439 int pci_find_capability(struct pci_dev *dev, int cap)
443 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
445 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
449 EXPORT_SYMBOL(pci_find_capability);
452 * pci_bus_find_capability - query for devices' capabilities
453 * @bus: the PCI bus to query
454 * @devfn: PCI device to query
455 * @cap: capability code
457 * Like pci_find_capability() but works for pci devices that do not have a
458 * pci_dev structure set up yet.
460 * Returns the address of the requested capability structure within the
461 * device's PCI configuration space or 0 in case the device does not
464 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
469 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
471 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
473 pos = __pci_find_next_cap(bus, devfn, pos, cap);
477 EXPORT_SYMBOL(pci_bus_find_capability);
480 * pci_find_next_ext_capability - Find an extended capability
481 * @dev: PCI device to query
482 * @start: address at which to start looking (0 to start at beginning of list)
483 * @cap: capability code
485 * Returns the address of the next matching extended capability structure
486 * within the device's PCI configuration space or 0 if the device does
487 * not support it. Some capabilities can occur several times, e.g., the
488 * vendor-specific capability, and this provides a way to find them all.
490 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
494 int pos = PCI_CFG_SPACE_SIZE;
496 /* minimum 8 bytes per capability */
497 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
499 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
505 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
509 * If we have no capabilities, this is indicated by cap ID,
510 * cap version and next pointer all being 0.
516 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
519 pos = PCI_EXT_CAP_NEXT(header);
520 if (pos < PCI_CFG_SPACE_SIZE)
523 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
529 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
532 * pci_find_ext_capability - Find an extended capability
533 * @dev: PCI device to query
534 * @cap: capability code
536 * Returns the address of the requested extended capability structure
537 * within the device's PCI configuration space or 0 if the device does
538 * not support it. Possible values for @cap:
540 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
541 * %PCI_EXT_CAP_ID_VC Virtual Channel
542 * %PCI_EXT_CAP_ID_DSN Device Serial Number
543 * %PCI_EXT_CAP_ID_PWR Power Budgeting
545 int pci_find_ext_capability(struct pci_dev *dev, int cap)
547 return pci_find_next_ext_capability(dev, 0, cap);
549 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
551 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
553 int rc, ttl = PCI_FIND_CAP_TTL;
556 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
557 mask = HT_3BIT_CAP_MASK;
559 mask = HT_5BIT_CAP_MASK;
561 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
562 PCI_CAP_ID_HT, &ttl);
564 rc = pci_read_config_byte(dev, pos + 3, &cap);
565 if (rc != PCIBIOS_SUCCESSFUL)
568 if ((cap & mask) == ht_cap)
571 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
572 pos + PCI_CAP_LIST_NEXT,
573 PCI_CAP_ID_HT, &ttl);
579 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
580 * @dev: PCI device to query
581 * @pos: Position from which to continue searching
582 * @ht_cap: Hypertransport capability code
584 * To be used in conjunction with pci_find_ht_capability() to search for
585 * all capabilities matching @ht_cap. @pos should always be a value returned
586 * from pci_find_ht_capability().
588 * NB. To be 100% safe against broken PCI devices, the caller should take
589 * steps to avoid an infinite loop.
591 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
593 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
595 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
598 * pci_find_ht_capability - query a device's Hypertransport capabilities
599 * @dev: PCI device to query
600 * @ht_cap: Hypertransport capability code
602 * Tell if a device supports a given Hypertransport capability.
603 * Returns an address within the device's PCI configuration space
604 * or 0 in case the device does not support the request capability.
605 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
606 * which has a Hypertransport capability matching @ht_cap.
608 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
612 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
614 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
618 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
621 * pci_find_parent_resource - return resource region of parent bus of given region
622 * @dev: PCI device structure contains resources to be searched
623 * @res: child resource record for which parent is sought
625 * For given resource region of given device, return the resource
626 * region of parent bus the given region is contained in.
628 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
629 struct resource *res)
631 const struct pci_bus *bus = dev->bus;
635 pci_bus_for_each_resource(bus, r, i) {
638 if (resource_contains(r, res)) {
641 * If the window is prefetchable but the BAR is
642 * not, the allocator made a mistake.
644 if (r->flags & IORESOURCE_PREFETCH &&
645 !(res->flags & IORESOURCE_PREFETCH))
649 * If we're below a transparent bridge, there may
650 * be both a positively-decoded aperture and a
651 * subtractively-decoded region that contain the BAR.
652 * We want the positively-decoded one, so this depends
653 * on pci_bus_for_each_resource() giving us those
661 EXPORT_SYMBOL(pci_find_parent_resource);
664 * pci_find_resource - Return matching PCI device resource
665 * @dev: PCI device to query
666 * @res: Resource to look for
668 * Goes over standard PCI resources (BARs) and checks if the given resource
669 * is partially or fully contained in any of them. In that case the
670 * matching resource is returned, %NULL otherwise.
672 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
676 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
677 struct resource *r = &dev->resource[i];
679 if (r->start && resource_contains(r, res))
685 EXPORT_SYMBOL(pci_find_resource);
688 * pci_find_pcie_root_port - return PCIe Root Port
689 * @dev: PCI device to query
691 * Traverse up the parent chain and return the PCIe Root Port PCI Device
692 * for a given PCI Device.
694 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
696 struct pci_dev *bridge, *highest_pcie_bridge = dev;
698 bridge = pci_upstream_bridge(dev);
699 while (bridge && pci_is_pcie(bridge)) {
700 highest_pcie_bridge = bridge;
701 bridge = pci_upstream_bridge(bridge);
704 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
707 return highest_pcie_bridge;
709 EXPORT_SYMBOL(pci_find_pcie_root_port);
712 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
713 * @dev: the PCI device to operate on
714 * @pos: config space offset of status word
715 * @mask: mask of bit(s) to care about in status word
717 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
719 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
723 /* Wait for Transaction Pending bit clean */
724 for (i = 0; i < 4; i++) {
727 msleep((1 << (i - 1)) * 100);
729 pci_read_config_word(dev, pos, &status);
730 if (!(status & mask))
738 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
739 * @dev: PCI device to have its BARs restored
741 * Restore the BAR values for a given device, so as to make it
742 * accessible by its driver.
744 static void pci_restore_bars(struct pci_dev *dev)
748 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
749 pci_update_resource(dev, i);
752 static const struct pci_platform_pm_ops *pci_platform_pm;
754 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
756 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
757 !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
759 pci_platform_pm = ops;
763 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
765 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
768 static inline int platform_pci_set_power_state(struct pci_dev *dev,
771 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
774 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
776 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
779 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
781 return pci_platform_pm ?
782 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
785 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
787 return pci_platform_pm ?
788 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
791 static inline bool platform_pci_need_resume(struct pci_dev *dev)
793 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
796 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
798 return pci_platform_pm ? pci_platform_pm->bridge_d3(dev) : false;
802 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
804 * @dev: PCI device to handle.
805 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
808 * -EINVAL if the requested state is invalid.
809 * -EIO if device does not support PCI PM or its PM capabilities register has a
810 * wrong version, or device doesn't support the requested state.
811 * 0 if device already is in the requested state.
812 * 0 if device's power state has been successfully changed.
814 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
817 bool need_restore = false;
819 /* Check if we're already there */
820 if (dev->current_state == state)
826 if (state < PCI_D0 || state > PCI_D3hot)
829 /* Validate current state:
830 * Can enter D0 from any state, but if we can only go deeper
831 * to sleep if we're already in a low power state
833 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
834 && dev->current_state > state) {
835 pci_err(dev, "invalid power transition (from state %d to %d)\n",
836 dev->current_state, state);
840 /* check if this device supports the desired state */
841 if ((state == PCI_D1 && !dev->d1_support)
842 || (state == PCI_D2 && !dev->d2_support))
845 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
847 /* If we're (effectively) in D3, force entire word to 0.
848 * This doesn't affect PME_Status, disables PME_En, and
849 * sets PowerState to 0.
851 switch (dev->current_state) {
855 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
860 case PCI_UNKNOWN: /* Boot-up */
861 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
862 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
864 /* Fall-through: force to D0 */
870 /* enter specified state */
871 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
873 /* Mandatory power management transition delays */
874 /* see PCI PM 1.1 5.6.1 table 18 */
875 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
876 pci_dev_d3_sleep(dev);
877 else if (state == PCI_D2 || dev->current_state == PCI_D2)
878 udelay(PCI_PM_D2_DELAY);
880 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
881 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
882 if (dev->current_state != state && printk_ratelimit())
883 pci_info(dev, "Refused to change power state, currently in D%d\n",
887 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
888 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
889 * from D3hot to D0 _may_ perform an internal reset, thereby
890 * going to "D0 Uninitialized" rather than "D0 Initialized".
891 * For example, at least some versions of the 3c905B and the
892 * 3c556B exhibit this behaviour.
894 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
895 * devices in a D3hot state at boot. Consequently, we need to
896 * restore at least the BARs so that the device will be
897 * accessible to its driver.
900 pci_restore_bars(dev);
903 pcie_aspm_pm_state_change(dev->bus->self);
909 * pci_update_current_state - Read power state of given device and cache it
910 * @dev: PCI device to handle.
911 * @state: State to cache in case the device doesn't have the PM capability
913 * The power state is read from the PMCSR register, which however is
914 * inaccessible in D3cold. The platform firmware is therefore queried first
915 * to detect accessibility of the register. In case the platform firmware
916 * reports an incorrect state or the device isn't power manageable by the
917 * platform at all, we try to detect D3cold by testing accessibility of the
918 * vendor ID in config space.
920 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
922 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
923 !pci_device_is_present(dev)) {
924 dev->current_state = PCI_D3cold;
925 } else if (dev->pm_cap) {
928 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
929 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
931 dev->current_state = state;
936 * pci_power_up - Put the given device into D0 forcibly
937 * @dev: PCI device to power up
939 void pci_power_up(struct pci_dev *dev)
941 if (platform_pci_power_manageable(dev))
942 platform_pci_set_power_state(dev, PCI_D0);
944 pci_raw_set_power_state(dev, PCI_D0);
945 pci_update_current_state(dev, PCI_D0);
949 * pci_platform_power_transition - Use platform to change device power state
950 * @dev: PCI device to handle.
951 * @state: State to put the device into.
953 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
957 if (platform_pci_power_manageable(dev)) {
958 error = platform_pci_set_power_state(dev, state);
960 pci_update_current_state(dev, state);
964 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
965 dev->current_state = PCI_D0;
971 * pci_wakeup - Wake up a PCI device
972 * @pci_dev: Device to handle.
973 * @ign: ignored parameter
975 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
977 pci_wakeup_event(pci_dev);
978 pm_request_resume(&pci_dev->dev);
983 * pci_wakeup_bus - Walk given bus and wake up devices on it
984 * @bus: Top bus of the subtree to walk.
986 void pci_wakeup_bus(struct pci_bus *bus)
989 pci_walk_bus(bus, pci_wakeup, NULL);
993 * __pci_start_power_transition - Start power transition of a PCI device
994 * @dev: PCI device to handle.
995 * @state: State to put the device into.
997 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
999 if (state == PCI_D0) {
1000 pci_platform_power_transition(dev, PCI_D0);
1002 * Mandatory power management transition delays, see
1003 * PCI Express Base Specification Revision 2.0 Section
1004 * 6.6.1: Conventional Reset. Do not delay for
1005 * devices powered on/off by corresponding bridge,
1006 * because have already delayed for the bridge.
1008 if (dev->runtime_d3cold) {
1009 if (dev->d3cold_delay)
1010 msleep(dev->d3cold_delay);
1012 * When powering on a bridge from D3cold, the
1013 * whole hierarchy may be powered on into
1014 * D0uninitialized state, resume them to give
1015 * them a chance to suspend again
1017 pci_wakeup_bus(dev->subordinate);
1023 * __pci_dev_set_current_state - Set current state of a PCI device
1024 * @dev: Device to handle
1025 * @data: pointer to state to be set
1027 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1029 pci_power_t state = *(pci_power_t *)data;
1031 dev->current_state = state;
1036 * pci_bus_set_current_state - Walk given bus and set current state of devices
1037 * @bus: Top bus of the subtree to walk.
1038 * @state: state to be set
1040 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1043 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1047 * __pci_complete_power_transition - Complete power transition of a PCI device
1048 * @dev: PCI device to handle.
1049 * @state: State to put the device into.
1051 * This function should not be called directly by device drivers.
1053 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
1057 if (state <= PCI_D0)
1059 ret = pci_platform_power_transition(dev, state);
1060 /* Power off the bridge may power off the whole hierarchy */
1061 if (!ret && state == PCI_D3cold)
1062 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1065 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
1068 * pci_set_power_state - Set the power state of a PCI device
1069 * @dev: PCI device to handle.
1070 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1072 * Transition a device to a new power state, using the platform firmware and/or
1073 * the device's PCI PM registers.
1076 * -EINVAL if the requested state is invalid.
1077 * -EIO if device does not support PCI PM or its PM capabilities register has a
1078 * wrong version, or device doesn't support the requested state.
1079 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1080 * 0 if device already is in the requested state.
1081 * 0 if the transition is to D3 but D3 is not supported.
1082 * 0 if device's power state has been successfully changed.
1084 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1088 /* bound the state we're entering */
1089 if (state > PCI_D3cold)
1091 else if (state < PCI_D0)
1093 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1095 * If the device or the parent bridge do not support PCI PM,
1096 * ignore the request if we're doing anything other than putting
1097 * it into D0 (which would only happen on boot).
1101 /* Check if we're already there */
1102 if (dev->current_state == state)
1105 __pci_start_power_transition(dev, state);
1107 /* This device is quirked not to be put into D3, so
1108 don't put it in D3 */
1109 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1113 * To put device in D3cold, we put device into D3hot in native
1114 * way, then put device into D3cold with platform ops
1116 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
1119 if (!__pci_complete_power_transition(dev, state))
1124 EXPORT_SYMBOL(pci_set_power_state);
1127 * pci_choose_state - Choose the power state of a PCI device
1128 * @dev: PCI device to be suspended
1129 * @state: target sleep state for the whole system. This is the value
1130 * that is passed to suspend() function.
1132 * Returns PCI power state suitable for given device and given system
1136 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
1143 ret = platform_pci_choose_state(dev);
1144 if (ret != PCI_POWER_ERROR)
1147 switch (state.event) {
1150 case PM_EVENT_FREEZE:
1151 case PM_EVENT_PRETHAW:
1152 /* REVISIT both freeze and pre-thaw "should" use D0 */
1153 case PM_EVENT_SUSPEND:
1154 case PM_EVENT_HIBERNATE:
1157 pci_info(dev, "unrecognized suspend event %d\n",
1163 EXPORT_SYMBOL(pci_choose_state);
1165 #define PCI_EXP_SAVE_REGS 7
1167 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1168 u16 cap, bool extended)
1170 struct pci_cap_saved_state *tmp;
1172 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1173 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1179 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1181 return _pci_find_saved_cap(dev, cap, false);
1184 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1186 return _pci_find_saved_cap(dev, cap, true);
1189 static int pci_save_pcie_state(struct pci_dev *dev)
1192 struct pci_cap_saved_state *save_state;
1195 if (!pci_is_pcie(dev))
1198 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1200 pci_err(dev, "buffer not found in %s\n", __func__);
1204 cap = (u16 *)&save_state->cap.data[0];
1205 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1206 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1207 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1208 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1209 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1210 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1211 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1216 static void pci_restore_pcie_state(struct pci_dev *dev)
1219 struct pci_cap_saved_state *save_state;
1222 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1226 cap = (u16 *)&save_state->cap.data[0];
1227 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1228 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1229 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1230 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1231 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1232 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1233 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1237 static int pci_save_pcix_state(struct pci_dev *dev)
1240 struct pci_cap_saved_state *save_state;
1242 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1246 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1248 pci_err(dev, "buffer not found in %s\n", __func__);
1252 pci_read_config_word(dev, pos + PCI_X_CMD,
1253 (u16 *)save_state->cap.data);
1258 static void pci_restore_pcix_state(struct pci_dev *dev)
1261 struct pci_cap_saved_state *save_state;
1264 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1265 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1266 if (!save_state || !pos)
1268 cap = (u16 *)&save_state->cap.data[0];
1270 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1275 * pci_save_state - save the PCI configuration space of a device before suspending
1276 * @dev: - PCI device that we're dealing with
1278 int pci_save_state(struct pci_dev *dev)
1281 /* XXX: 100% dword access ok here? */
1282 for (i = 0; i < 16; i++)
1283 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1284 dev->state_saved = true;
1286 i = pci_save_pcie_state(dev);
1290 i = pci_save_pcix_state(dev);
1294 pci_save_dpc_state(dev);
1295 return pci_save_vc_state(dev);
1297 EXPORT_SYMBOL(pci_save_state);
1299 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1300 u32 saved_val, int retry)
1304 pci_read_config_dword(pdev, offset, &val);
1305 if (val == saved_val)
1309 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1310 offset, val, saved_val);
1311 pci_write_config_dword(pdev, offset, saved_val);
1315 pci_read_config_dword(pdev, offset, &val);
1316 if (val == saved_val)
1323 static void pci_restore_config_space_range(struct pci_dev *pdev,
1324 int start, int end, int retry)
1328 for (index = end; index >= start; index--)
1329 pci_restore_config_dword(pdev, 4 * index,
1330 pdev->saved_config_space[index],
1334 static void pci_restore_config_space(struct pci_dev *pdev)
1336 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1337 pci_restore_config_space_range(pdev, 10, 15, 0);
1338 /* Restore BARs before the command register. */
1339 pci_restore_config_space_range(pdev, 4, 9, 10);
1340 pci_restore_config_space_range(pdev, 0, 3, 0);
1342 pci_restore_config_space_range(pdev, 0, 15, 0);
1346 static void pci_restore_rebar_state(struct pci_dev *pdev)
1348 unsigned int pos, nbars, i;
1351 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1355 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1356 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
1357 PCI_REBAR_CTRL_NBAR_SHIFT;
1359 for (i = 0; i < nbars; i++, pos += 8) {
1360 struct resource *res;
1363 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1364 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1365 res = pdev->resource + bar_idx;
1366 size = order_base_2((resource_size(res) >> 20) | 1) - 1;
1367 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1368 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
1369 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1374 * pci_restore_state - Restore the saved state of a PCI device
1375 * @dev: - PCI device that we're dealing with
1377 void pci_restore_state(struct pci_dev *dev)
1379 if (!dev->state_saved)
1382 /* PCI Express register must be restored first */
1383 pci_restore_pcie_state(dev);
1384 pci_restore_pasid_state(dev);
1385 pci_restore_pri_state(dev);
1386 pci_restore_ats_state(dev);
1387 pci_restore_vc_state(dev);
1388 pci_restore_rebar_state(dev);
1389 pci_restore_dpc_state(dev);
1391 pci_cleanup_aer_error_status_regs(dev);
1393 pci_restore_config_space(dev);
1395 pci_restore_pcix_state(dev);
1396 pci_restore_msi_state(dev);
1398 /* Restore ACS and IOV configuration state */
1399 pci_enable_acs(dev);
1400 pci_restore_iov_state(dev);
1402 dev->state_saved = false;
1404 EXPORT_SYMBOL(pci_restore_state);
1406 struct pci_saved_state {
1407 u32 config_space[16];
1408 struct pci_cap_saved_data cap[0];
1412 * pci_store_saved_state - Allocate and return an opaque struct containing
1413 * the device saved state.
1414 * @dev: PCI device that we're dealing with
1416 * Return NULL if no state or error.
1418 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1420 struct pci_saved_state *state;
1421 struct pci_cap_saved_state *tmp;
1422 struct pci_cap_saved_data *cap;
1425 if (!dev->state_saved)
1428 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1430 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1431 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1433 state = kzalloc(size, GFP_KERNEL);
1437 memcpy(state->config_space, dev->saved_config_space,
1438 sizeof(state->config_space));
1441 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1442 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1443 memcpy(cap, &tmp->cap, len);
1444 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1446 /* Empty cap_save terminates list */
1450 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1453 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1454 * @dev: PCI device that we're dealing with
1455 * @state: Saved state returned from pci_store_saved_state()
1457 int pci_load_saved_state(struct pci_dev *dev,
1458 struct pci_saved_state *state)
1460 struct pci_cap_saved_data *cap;
1462 dev->state_saved = false;
1467 memcpy(dev->saved_config_space, state->config_space,
1468 sizeof(state->config_space));
1472 struct pci_cap_saved_state *tmp;
1474 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1475 if (!tmp || tmp->cap.size != cap->size)
1478 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1479 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1480 sizeof(struct pci_cap_saved_data) + cap->size);
1483 dev->state_saved = true;
1486 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1489 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1490 * and free the memory allocated for it.
1491 * @dev: PCI device that we're dealing with
1492 * @state: Pointer to saved state returned from pci_store_saved_state()
1494 int pci_load_and_free_saved_state(struct pci_dev *dev,
1495 struct pci_saved_state **state)
1497 int ret = pci_load_saved_state(dev, *state);
1502 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1504 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1506 return pci_enable_resources(dev, bars);
1509 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1512 struct pci_dev *bridge;
1516 err = pci_set_power_state(dev, PCI_D0);
1517 if (err < 0 && err != -EIO)
1520 bridge = pci_upstream_bridge(dev);
1522 pcie_aspm_powersave_config_link(bridge);
1524 err = pcibios_enable_device(dev, bars);
1527 pci_fixup_device(pci_fixup_enable, dev);
1529 if (dev->msi_enabled || dev->msix_enabled)
1532 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1534 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1535 if (cmd & PCI_COMMAND_INTX_DISABLE)
1536 pci_write_config_word(dev, PCI_COMMAND,
1537 cmd & ~PCI_COMMAND_INTX_DISABLE);
1544 * pci_reenable_device - Resume abandoned device
1545 * @dev: PCI device to be resumed
1547 * Note this function is a backend of pci_default_resume and is not supposed
1548 * to be called by normal code, write proper resume handler and use it instead.
1550 int pci_reenable_device(struct pci_dev *dev)
1552 if (pci_is_enabled(dev))
1553 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1556 EXPORT_SYMBOL(pci_reenable_device);
1558 static void pci_enable_bridge(struct pci_dev *dev)
1560 struct pci_dev *bridge;
1563 bridge = pci_upstream_bridge(dev);
1565 pci_enable_bridge(bridge);
1567 if (pci_is_enabled(dev)) {
1568 if (!dev->is_busmaster)
1569 pci_set_master(dev);
1573 retval = pci_enable_device(dev);
1575 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1577 pci_set_master(dev);
1580 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1582 struct pci_dev *bridge;
1587 * Power state could be unknown at this point, either due to a fresh
1588 * boot or a device removal call. So get the current power state
1589 * so that things like MSI message writing will behave as expected
1590 * (e.g. if the device really is in D0 at enable time).
1594 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1595 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1598 if (atomic_inc_return(&dev->enable_cnt) > 1)
1599 return 0; /* already enabled */
1601 bridge = pci_upstream_bridge(dev);
1603 pci_enable_bridge(bridge);
1605 /* only skip sriov related */
1606 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1607 if (dev->resource[i].flags & flags)
1609 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1610 if (dev->resource[i].flags & flags)
1613 err = do_pci_enable_device(dev, bars);
1615 atomic_dec(&dev->enable_cnt);
1620 * pci_enable_device_io - Initialize a device for use with IO space
1621 * @dev: PCI device to be initialized
1623 * Initialize device before it's used by a driver. Ask low-level code
1624 * to enable I/O resources. Wake up the device if it was suspended.
1625 * Beware, this function can fail.
1627 int pci_enable_device_io(struct pci_dev *dev)
1629 return pci_enable_device_flags(dev, IORESOURCE_IO);
1631 EXPORT_SYMBOL(pci_enable_device_io);
1634 * pci_enable_device_mem - Initialize a device for use with Memory space
1635 * @dev: PCI device to be initialized
1637 * Initialize device before it's used by a driver. Ask low-level code
1638 * to enable Memory resources. Wake up the device if it was suspended.
1639 * Beware, this function can fail.
1641 int pci_enable_device_mem(struct pci_dev *dev)
1643 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1645 EXPORT_SYMBOL(pci_enable_device_mem);
1648 * pci_enable_device - Initialize device before it's used by a driver.
1649 * @dev: PCI device to be initialized
1651 * Initialize device before it's used by a driver. Ask low-level code
1652 * to enable I/O and memory. Wake up the device if it was suspended.
1653 * Beware, this function can fail.
1655 * Note we don't actually enable the device many times if we call
1656 * this function repeatedly (we just increment the count).
1658 int pci_enable_device(struct pci_dev *dev)
1660 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1662 EXPORT_SYMBOL(pci_enable_device);
1665 * Managed PCI resources. This manages device on/off, intx/msi/msix
1666 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1667 * there's no need to track it separately. pci_devres is initialized
1668 * when a device is enabled using managed PCI device enable interface.
1671 unsigned int enabled:1;
1672 unsigned int pinned:1;
1673 unsigned int orig_intx:1;
1674 unsigned int restore_intx:1;
1679 static void pcim_release(struct device *gendev, void *res)
1681 struct pci_dev *dev = to_pci_dev(gendev);
1682 struct pci_devres *this = res;
1685 if (dev->msi_enabled)
1686 pci_disable_msi(dev);
1687 if (dev->msix_enabled)
1688 pci_disable_msix(dev);
1690 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1691 if (this->region_mask & (1 << i))
1692 pci_release_region(dev, i);
1697 if (this->restore_intx)
1698 pci_intx(dev, this->orig_intx);
1700 if (this->enabled && !this->pinned)
1701 pci_disable_device(dev);
1704 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1706 struct pci_devres *dr, *new_dr;
1708 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1712 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1715 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1718 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1720 if (pci_is_managed(pdev))
1721 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1726 * pcim_enable_device - Managed pci_enable_device()
1727 * @pdev: PCI device to be initialized
1729 * Managed pci_enable_device().
1731 int pcim_enable_device(struct pci_dev *pdev)
1733 struct pci_devres *dr;
1736 dr = get_pci_dr(pdev);
1742 rc = pci_enable_device(pdev);
1744 pdev->is_managed = 1;
1749 EXPORT_SYMBOL(pcim_enable_device);
1752 * pcim_pin_device - Pin managed PCI device
1753 * @pdev: PCI device to pin
1755 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1756 * driver detach. @pdev must have been enabled with
1757 * pcim_enable_device().
1759 void pcim_pin_device(struct pci_dev *pdev)
1761 struct pci_devres *dr;
1763 dr = find_pci_dr(pdev);
1764 WARN_ON(!dr || !dr->enabled);
1768 EXPORT_SYMBOL(pcim_pin_device);
1771 * pcibios_add_device - provide arch specific hooks when adding device dev
1772 * @dev: the PCI device being added
1774 * Permits the platform to provide architecture specific functionality when
1775 * devices are added. This is the default implementation. Architecture
1776 * implementations can override this.
1778 int __weak pcibios_add_device(struct pci_dev *dev)
1784 * pcibios_release_device - provide arch specific hooks when releasing device dev
1785 * @dev: the PCI device being released
1787 * Permits the platform to provide architecture specific functionality when
1788 * devices are released. This is the default implementation. Architecture
1789 * implementations can override this.
1791 void __weak pcibios_release_device(struct pci_dev *dev) {}
1794 * pcibios_disable_device - disable arch specific PCI resources for device dev
1795 * @dev: the PCI device to disable
1797 * Disables architecture specific PCI resources for the device. This
1798 * is the default implementation. Architecture implementations can
1801 void __weak pcibios_disable_device(struct pci_dev *dev) {}
1804 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1805 * @irq: ISA IRQ to penalize
1806 * @active: IRQ active or not
1808 * Permits the platform to provide architecture-specific functionality when
1809 * penalizing ISA IRQs. This is the default implementation. Architecture
1810 * implementations can override this.
1812 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1814 static void do_pci_disable_device(struct pci_dev *dev)
1818 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1819 if (pci_command & PCI_COMMAND_MASTER) {
1820 pci_command &= ~PCI_COMMAND_MASTER;
1821 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1824 pcibios_disable_device(dev);
1828 * pci_disable_enabled_device - Disable device without updating enable_cnt
1829 * @dev: PCI device to disable
1831 * NOTE: This function is a backend of PCI power management routines and is
1832 * not supposed to be called drivers.
1834 void pci_disable_enabled_device(struct pci_dev *dev)
1836 if (pci_is_enabled(dev))
1837 do_pci_disable_device(dev);
1841 * pci_disable_device - Disable PCI device after use
1842 * @dev: PCI device to be disabled
1844 * Signal to the system that the PCI device is not in use by the system
1845 * anymore. This only involves disabling PCI bus-mastering, if active.
1847 * Note we don't actually disable the device until all callers of
1848 * pci_enable_device() have called pci_disable_device().
1850 void pci_disable_device(struct pci_dev *dev)
1852 struct pci_devres *dr;
1854 dr = find_pci_dr(dev);
1858 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1859 "disabling already-disabled device");
1861 if (atomic_dec_return(&dev->enable_cnt) != 0)
1864 do_pci_disable_device(dev);
1866 dev->is_busmaster = 0;
1868 EXPORT_SYMBOL(pci_disable_device);
1871 * pcibios_set_pcie_reset_state - set reset state for device dev
1872 * @dev: the PCIe device reset
1873 * @state: Reset state to enter into
1876 * Sets the PCIe reset state for the device. This is the default
1877 * implementation. Architecture implementations can override this.
1879 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1880 enum pcie_reset_state state)
1886 * pci_set_pcie_reset_state - set reset state for device dev
1887 * @dev: the PCIe device reset
1888 * @state: Reset state to enter into
1891 * Sets the PCI reset state for the device.
1893 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1895 return pcibios_set_pcie_reset_state(dev, state);
1897 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1900 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
1901 * @dev: PCIe root port or event collector.
1903 void pcie_clear_root_pme_status(struct pci_dev *dev)
1905 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
1909 * pci_check_pme_status - Check if given device has generated PME.
1910 * @dev: Device to check.
1912 * Check the PME status of the device and if set, clear it and clear PME enable
1913 * (if set). Return 'true' if PME status and PME enable were both set or
1914 * 'false' otherwise.
1916 bool pci_check_pme_status(struct pci_dev *dev)
1925 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1926 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1927 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1930 /* Clear PME status. */
1931 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1932 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1933 /* Disable PME to avoid interrupt flood. */
1934 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1938 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1944 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1945 * @dev: Device to handle.
1946 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1948 * Check if @dev has generated PME and queue a resume request for it in that
1951 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1953 if (pme_poll_reset && dev->pme_poll)
1954 dev->pme_poll = false;
1956 if (pci_check_pme_status(dev)) {
1957 pci_wakeup_event(dev);
1958 pm_request_resume(&dev->dev);
1964 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1965 * @bus: Top bus of the subtree to walk.
1967 void pci_pme_wakeup_bus(struct pci_bus *bus)
1970 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1975 * pci_pme_capable - check the capability of PCI device to generate PME#
1976 * @dev: PCI device to handle.
1977 * @state: PCI state from which device will issue PME#.
1979 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1984 return !!(dev->pme_support & (1 << state));
1986 EXPORT_SYMBOL(pci_pme_capable);
1988 static void pci_pme_list_scan(struct work_struct *work)
1990 struct pci_pme_device *pme_dev, *n;
1992 mutex_lock(&pci_pme_list_mutex);
1993 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1994 if (pme_dev->dev->pme_poll) {
1995 struct pci_dev *bridge;
1997 bridge = pme_dev->dev->bus->self;
1999 * If bridge is in low power state, the
2000 * configuration space of subordinate devices
2001 * may be not accessible
2003 if (bridge && bridge->current_state != PCI_D0)
2005 pci_pme_wakeup(pme_dev->dev, NULL);
2007 list_del(&pme_dev->list);
2011 if (!list_empty(&pci_pme_list))
2012 queue_delayed_work(system_freezable_wq, &pci_pme_work,
2013 msecs_to_jiffies(PME_TIMEOUT));
2014 mutex_unlock(&pci_pme_list_mutex);
2017 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2021 if (!dev->pme_support)
2024 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2025 /* Clear PME_Status by writing 1 to it and enable PME# */
2026 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2028 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2030 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2034 * pci_pme_restore - Restore PME configuration after config space restore.
2035 * @dev: PCI device to update.
2037 void pci_pme_restore(struct pci_dev *dev)
2041 if (!dev->pme_support)
2044 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2045 if (dev->wakeup_prepared) {
2046 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2047 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2049 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2050 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2052 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2056 * pci_pme_active - enable or disable PCI device's PME# function
2057 * @dev: PCI device to handle.
2058 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2060 * The caller must verify that the device is capable of generating PME# before
2061 * calling this function with @enable equal to 'true'.
2063 void pci_pme_active(struct pci_dev *dev, bool enable)
2065 __pci_pme_active(dev, enable);
2068 * PCI (as opposed to PCIe) PME requires that the device have
2069 * its PME# line hooked up correctly. Not all hardware vendors
2070 * do this, so the PME never gets delivered and the device
2071 * remains asleep. The easiest way around this is to
2072 * periodically walk the list of suspended devices and check
2073 * whether any have their PME flag set. The assumption is that
2074 * we'll wake up often enough anyway that this won't be a huge
2075 * hit, and the power savings from the devices will still be a
2078 * Although PCIe uses in-band PME message instead of PME# line
2079 * to report PME, PME does not work for some PCIe devices in
2080 * reality. For example, there are devices that set their PME
2081 * status bits, but don't really bother to send a PME message;
2082 * there are PCI Express Root Ports that don't bother to
2083 * trigger interrupts when they receive PME messages from the
2084 * devices below. So PME poll is used for PCIe devices too.
2087 if (dev->pme_poll) {
2088 struct pci_pme_device *pme_dev;
2090 pme_dev = kmalloc(sizeof(struct pci_pme_device),
2093 pci_warn(dev, "can't enable PME#\n");
2097 mutex_lock(&pci_pme_list_mutex);
2098 list_add(&pme_dev->list, &pci_pme_list);
2099 if (list_is_singular(&pci_pme_list))
2100 queue_delayed_work(system_freezable_wq,
2102 msecs_to_jiffies(PME_TIMEOUT));
2103 mutex_unlock(&pci_pme_list_mutex);
2105 mutex_lock(&pci_pme_list_mutex);
2106 list_for_each_entry(pme_dev, &pci_pme_list, list) {
2107 if (pme_dev->dev == dev) {
2108 list_del(&pme_dev->list);
2113 mutex_unlock(&pci_pme_list_mutex);
2117 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2119 EXPORT_SYMBOL(pci_pme_active);
2122 * __pci_enable_wake - enable PCI device as wakeup event source
2123 * @dev: PCI device affected
2124 * @state: PCI state from which device will issue wakeup events
2125 * @enable: True to enable event generation; false to disable
2127 * This enables the device as a wakeup event source, or disables it.
2128 * When such events involves platform-specific hooks, those hooks are
2129 * called automatically by this routine.
2131 * Devices with legacy power management (no standard PCI PM capabilities)
2132 * always require such platform hooks.
2135 * 0 is returned on success
2136 * -EINVAL is returned if device is not supposed to wake up the system
2137 * Error code depending on the platform is returned if both the platform and
2138 * the native mechanism fail to enable the generation of wake-up events
2140 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2145 * Bridges that are not power-manageable directly only signal
2146 * wakeup on behalf of subordinate devices which is set up
2147 * elsewhere, so skip them. However, bridges that are
2148 * power-manageable may signal wakeup for themselves (for example,
2149 * on a hotplug event) and they need to be covered here.
2151 if (!pci_power_manageable(dev))
2154 /* Don't do the same thing twice in a row for one device. */
2155 if (!!enable == !!dev->wakeup_prepared)
2159 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2160 * Anderson we should be doing PME# wake enable followed by ACPI wake
2161 * enable. To disable wake-up we call the platform first, for symmetry.
2167 if (pci_pme_capable(dev, state))
2168 pci_pme_active(dev, true);
2171 error = platform_pci_set_wakeup(dev, true);
2175 dev->wakeup_prepared = true;
2177 platform_pci_set_wakeup(dev, false);
2178 pci_pme_active(dev, false);
2179 dev->wakeup_prepared = false;
2186 * pci_enable_wake - change wakeup settings for a PCI device
2187 * @pci_dev: Target device
2188 * @state: PCI state from which device will issue wakeup events
2189 * @enable: Whether or not to enable event generation
2191 * If @enable is set, check device_may_wakeup() for the device before calling
2192 * __pci_enable_wake() for it.
2194 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2196 if (enable && !device_may_wakeup(&pci_dev->dev))
2199 return __pci_enable_wake(pci_dev, state, enable);
2201 EXPORT_SYMBOL(pci_enable_wake);
2204 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2205 * @dev: PCI device to prepare
2206 * @enable: True to enable wake-up event generation; false to disable
2208 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2209 * and this function allows them to set that up cleanly - pci_enable_wake()
2210 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2211 * ordering constraints.
2213 * This function only returns error code if the device is not allowed to wake
2214 * up the system from sleep or it is not capable of generating PME# from both
2215 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2217 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2219 return pci_pme_capable(dev, PCI_D3cold) ?
2220 pci_enable_wake(dev, PCI_D3cold, enable) :
2221 pci_enable_wake(dev, PCI_D3hot, enable);
2223 EXPORT_SYMBOL(pci_wake_from_d3);
2226 * pci_target_state - find an appropriate low power state for a given PCI dev
2228 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2230 * Use underlying platform code to find a supported low power state for @dev.
2231 * If the platform can't manage @dev, return the deepest state from which it
2232 * can generate wake events, based on any available PME info.
2234 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2236 pci_power_t target_state = PCI_D3hot;
2238 if (platform_pci_power_manageable(dev)) {
2240 * Call the platform to find the target state for the device.
2242 pci_power_t state = platform_pci_choose_state(dev);
2245 case PCI_POWER_ERROR:
2250 if (pci_no_d1d2(dev))
2252 /* else: fall through */
2254 target_state = state;
2257 return target_state;
2261 target_state = PCI_D0;
2264 * If the device is in D3cold even though it's not power-manageable by
2265 * the platform, it may have been powered down by non-standard means.
2266 * Best to let it slumber.
2268 if (dev->current_state == PCI_D3cold)
2269 target_state = PCI_D3cold;
2273 * Find the deepest state from which the device can generate
2276 if (dev->pme_support) {
2278 && !(dev->pme_support & (1 << target_state)))
2283 return target_state;
2287 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2288 * @dev: Device to handle.
2290 * Choose the power state appropriate for the device depending on whether
2291 * it can wake up the system and/or is power manageable by the platform
2292 * (PCI_D3hot is the default) and put the device into that state.
2294 int pci_prepare_to_sleep(struct pci_dev *dev)
2296 bool wakeup = device_may_wakeup(&dev->dev);
2297 pci_power_t target_state = pci_target_state(dev, wakeup);
2300 if (target_state == PCI_POWER_ERROR)
2303 pci_enable_wake(dev, target_state, wakeup);
2305 error = pci_set_power_state(dev, target_state);
2308 pci_enable_wake(dev, target_state, false);
2312 EXPORT_SYMBOL(pci_prepare_to_sleep);
2315 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2316 * @dev: Device to handle.
2318 * Disable device's system wake-up capability and put it into D0.
2320 int pci_back_from_sleep(struct pci_dev *dev)
2322 pci_enable_wake(dev, PCI_D0, false);
2323 return pci_set_power_state(dev, PCI_D0);
2325 EXPORT_SYMBOL(pci_back_from_sleep);
2328 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2329 * @dev: PCI device being suspended.
2331 * Prepare @dev to generate wake-up events at run time and put it into a low
2334 int pci_finish_runtime_suspend(struct pci_dev *dev)
2336 pci_power_t target_state;
2339 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2340 if (target_state == PCI_POWER_ERROR)
2343 dev->runtime_d3cold = target_state == PCI_D3cold;
2345 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2347 error = pci_set_power_state(dev, target_state);
2350 pci_enable_wake(dev, target_state, false);
2351 dev->runtime_d3cold = false;
2358 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2359 * @dev: Device to check.
2361 * Return true if the device itself is capable of generating wake-up events
2362 * (through the platform or using the native PCIe PME) or if the device supports
2363 * PME and one of its upstream bridges can generate wake-up events.
2365 bool pci_dev_run_wake(struct pci_dev *dev)
2367 struct pci_bus *bus = dev->bus;
2369 if (!dev->pme_support)
2372 /* PME-capable in principle, but not from the target power state */
2373 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2376 if (device_can_wakeup(&dev->dev))
2379 while (bus->parent) {
2380 struct pci_dev *bridge = bus->self;
2382 if (device_can_wakeup(&bridge->dev))
2388 /* We have reached the root bus. */
2390 return device_can_wakeup(bus->bridge);
2394 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2397 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2398 * @pci_dev: Device to check.
2400 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2401 * reconfigured due to wakeup settings difference between system and runtime
2402 * suspend and the current power state of it is suitable for the upcoming
2403 * (system) transition.
2405 * If the device is not configured for system wakeup, disable PME for it before
2406 * returning 'true' to prevent it from waking up the system unnecessarily.
2408 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2410 struct device *dev = &pci_dev->dev;
2411 bool wakeup = device_may_wakeup(dev);
2413 if (!pm_runtime_suspended(dev)
2414 || pci_target_state(pci_dev, wakeup) != pci_dev->current_state
2415 || platform_pci_need_resume(pci_dev))
2419 * At this point the device is good to go unless it's been configured
2420 * to generate PME at the runtime suspend time, but it is not supposed
2421 * to wake up the system. In that case, simply disable PME for it
2422 * (it will have to be re-enabled on exit from system resume).
2424 * If the device's power state is D3cold and the platform check above
2425 * hasn't triggered, the device's configuration is suitable and we don't
2426 * need to manipulate it at all.
2428 spin_lock_irq(&dev->power.lock);
2430 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2432 __pci_pme_active(pci_dev, false);
2434 spin_unlock_irq(&dev->power.lock);
2439 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2440 * @pci_dev: Device to handle.
2442 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2443 * it might have been disabled during the prepare phase of system suspend if
2444 * the device was not configured for system wakeup.
2446 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2448 struct device *dev = &pci_dev->dev;
2450 if (!pci_dev_run_wake(pci_dev))
2453 spin_lock_irq(&dev->power.lock);
2455 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2456 __pci_pme_active(pci_dev, true);
2458 spin_unlock_irq(&dev->power.lock);
2461 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2463 struct device *dev = &pdev->dev;
2464 struct device *parent = dev->parent;
2467 pm_runtime_get_sync(parent);
2468 pm_runtime_get_noresume(dev);
2470 * pdev->current_state is set to PCI_D3cold during suspending,
2471 * so wait until suspending completes
2473 pm_runtime_barrier(dev);
2475 * Only need to resume devices in D3cold, because config
2476 * registers are still accessible for devices suspended but
2479 if (pdev->current_state == PCI_D3cold)
2480 pm_runtime_resume(dev);
2483 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2485 struct device *dev = &pdev->dev;
2486 struct device *parent = dev->parent;
2488 pm_runtime_put(dev);
2490 pm_runtime_put_sync(parent);
2494 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2495 * @bridge: Bridge to check
2497 * This function checks if it is possible to move the bridge to D3.
2498 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2500 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2502 if (!pci_is_pcie(bridge))
2505 switch (pci_pcie_type(bridge)) {
2506 case PCI_EXP_TYPE_ROOT_PORT:
2507 case PCI_EXP_TYPE_UPSTREAM:
2508 case PCI_EXP_TYPE_DOWNSTREAM:
2509 if (pci_bridge_d3_disable)
2513 * Hotplug ports handled by firmware in System Management Mode
2514 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2516 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
2519 if (pci_bridge_d3_force)
2522 /* Even the oldest 2010 Thunderbolt controller supports D3. */
2523 if (bridge->is_thunderbolt)
2526 /* Platform might know better if the bridge supports D3 */
2527 if (platform_pci_bridge_d3(bridge))
2531 * Hotplug ports handled natively by the OS were not validated
2532 * by vendors for runtime D3 at least until 2018 because there
2533 * was no OS support.
2535 if (bridge->is_hotplug_bridge)
2539 * It should be safe to put PCIe ports from 2015 or newer
2542 if (dmi_get_bios_year() >= 2015)
2550 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2552 bool *d3cold_ok = data;
2554 if (/* The device needs to be allowed to go D3cold ... */
2555 dev->no_d3cold || !dev->d3cold_allowed ||
2557 /* ... and if it is wakeup capable to do so from D3cold. */
2558 (device_may_wakeup(&dev->dev) &&
2559 !pci_pme_capable(dev, PCI_D3cold)) ||
2561 /* If it is a bridge it must be allowed to go to D3. */
2562 !pci_power_manageable(dev))
2570 * pci_bridge_d3_update - Update bridge D3 capabilities
2571 * @dev: PCI device which is changed
2573 * Update upstream bridge PM capabilities accordingly depending on if the
2574 * device PM configuration was changed or the device is being removed. The
2575 * change is also propagated upstream.
2577 void pci_bridge_d3_update(struct pci_dev *dev)
2579 bool remove = !device_is_registered(&dev->dev);
2580 struct pci_dev *bridge;
2581 bool d3cold_ok = true;
2583 bridge = pci_upstream_bridge(dev);
2584 if (!bridge || !pci_bridge_d3_possible(bridge))
2588 * If D3 is currently allowed for the bridge, removing one of its
2589 * children won't change that.
2591 if (remove && bridge->bridge_d3)
2595 * If D3 is currently allowed for the bridge and a child is added or
2596 * changed, disallowance of D3 can only be caused by that child, so
2597 * we only need to check that single device, not any of its siblings.
2599 * If D3 is currently not allowed for the bridge, checking the device
2600 * first may allow us to skip checking its siblings.
2603 pci_dev_check_d3cold(dev, &d3cold_ok);
2606 * If D3 is currently not allowed for the bridge, this may be caused
2607 * either by the device being changed/removed or any of its siblings,
2608 * so we need to go through all children to find out if one of them
2609 * continues to block D3.
2611 if (d3cold_ok && !bridge->bridge_d3)
2612 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2615 if (bridge->bridge_d3 != d3cold_ok) {
2616 bridge->bridge_d3 = d3cold_ok;
2617 /* Propagate change to upstream bridges */
2618 pci_bridge_d3_update(bridge);
2623 * pci_d3cold_enable - Enable D3cold for device
2624 * @dev: PCI device to handle
2626 * This function can be used in drivers to enable D3cold from the device
2627 * they handle. It also updates upstream PCI bridge PM capabilities
2630 void pci_d3cold_enable(struct pci_dev *dev)
2632 if (dev->no_d3cold) {
2633 dev->no_d3cold = false;
2634 pci_bridge_d3_update(dev);
2637 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2640 * pci_d3cold_disable - Disable D3cold for device
2641 * @dev: PCI device to handle
2643 * This function can be used in drivers to disable D3cold from the device
2644 * they handle. It also updates upstream PCI bridge PM capabilities
2647 void pci_d3cold_disable(struct pci_dev *dev)
2649 if (!dev->no_d3cold) {
2650 dev->no_d3cold = true;
2651 pci_bridge_d3_update(dev);
2654 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2657 * pci_pm_init - Initialize PM functions of given PCI device
2658 * @dev: PCI device to handle.
2660 void pci_pm_init(struct pci_dev *dev)
2665 pm_runtime_forbid(&dev->dev);
2666 pm_runtime_set_active(&dev->dev);
2667 pm_runtime_enable(&dev->dev);
2668 device_enable_async_suspend(&dev->dev);
2669 dev->wakeup_prepared = false;
2672 dev->pme_support = 0;
2674 /* find PCI PM capability in list */
2675 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2678 /* Check device's ability to generate PME# */
2679 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2681 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2682 pci_err(dev, "unsupported PM cap regs version (%u)\n",
2683 pmc & PCI_PM_CAP_VER_MASK);
2688 dev->d3_delay = PCI_PM_D3_WAIT;
2689 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2690 dev->bridge_d3 = pci_bridge_d3_possible(dev);
2691 dev->d3cold_allowed = true;
2693 dev->d1_support = false;
2694 dev->d2_support = false;
2695 if (!pci_no_d1d2(dev)) {
2696 if (pmc & PCI_PM_CAP_D1)
2697 dev->d1_support = true;
2698 if (pmc & PCI_PM_CAP_D2)
2699 dev->d2_support = true;
2701 if (dev->d1_support || dev->d2_support)
2702 pci_printk(KERN_DEBUG, dev, "supports%s%s\n",
2703 dev->d1_support ? " D1" : "",
2704 dev->d2_support ? " D2" : "");
2707 pmc &= PCI_PM_CAP_PME_MASK;
2709 pci_printk(KERN_DEBUG, dev, "PME# supported from%s%s%s%s%s\n",
2710 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2711 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2712 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2713 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2714 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2715 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2716 dev->pme_poll = true;
2718 * Make device's PM flags reflect the wake-up capability, but
2719 * let the user space enable it to wake up the system as needed.
2721 device_set_wakeup_capable(&dev->dev, true);
2722 /* Disable the PME# generation functionality */
2723 pci_pme_active(dev, false);
2727 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2729 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
2733 case PCI_EA_P_VF_MEM:
2734 flags |= IORESOURCE_MEM;
2736 case PCI_EA_P_MEM_PREFETCH:
2737 case PCI_EA_P_VF_MEM_PREFETCH:
2738 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2741 flags |= IORESOURCE_IO;
2750 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2753 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2754 return &dev->resource[bei];
2755 #ifdef CONFIG_PCI_IOV
2756 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2757 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2758 return &dev->resource[PCI_IOV_RESOURCES +
2759 bei - PCI_EA_BEI_VF_BAR0];
2761 else if (bei == PCI_EA_BEI_ROM)
2762 return &dev->resource[PCI_ROM_RESOURCE];
2767 /* Read an Enhanced Allocation (EA) entry */
2768 static int pci_ea_read(struct pci_dev *dev, int offset)
2770 struct resource *res;
2771 int ent_size, ent_offset = offset;
2772 resource_size_t start, end;
2773 unsigned long flags;
2774 u32 dw0, bei, base, max_offset;
2776 bool support_64 = (sizeof(resource_size_t) >= 8);
2778 pci_read_config_dword(dev, ent_offset, &dw0);
2781 /* Entry size field indicates DWORDs after 1st */
2782 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2784 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2787 bei = (dw0 & PCI_EA_BEI) >> 4;
2788 prop = (dw0 & PCI_EA_PP) >> 8;
2791 * If the Property is in the reserved range, try the Secondary
2794 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2795 prop = (dw0 & PCI_EA_SP) >> 16;
2796 if (prop > PCI_EA_P_BRIDGE_IO)
2799 res = pci_ea_get_resource(dev, bei, prop);
2801 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
2805 flags = pci_ea_flags(dev, prop);
2807 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
2812 pci_read_config_dword(dev, ent_offset, &base);
2813 start = (base & PCI_EA_FIELD_MASK);
2816 /* Read MaxOffset */
2817 pci_read_config_dword(dev, ent_offset, &max_offset);
2820 /* Read Base MSBs (if 64-bit entry) */
2821 if (base & PCI_EA_IS_64) {
2824 pci_read_config_dword(dev, ent_offset, &base_upper);
2827 flags |= IORESOURCE_MEM_64;
2829 /* entry starts above 32-bit boundary, can't use */
2830 if (!support_64 && base_upper)
2834 start |= ((u64)base_upper << 32);
2837 end = start + (max_offset | 0x03);
2839 /* Read MaxOffset MSBs (if 64-bit entry) */
2840 if (max_offset & PCI_EA_IS_64) {
2841 u32 max_offset_upper;
2843 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2846 flags |= IORESOURCE_MEM_64;
2848 /* entry too big, can't use */
2849 if (!support_64 && max_offset_upper)
2853 end += ((u64)max_offset_upper << 32);
2857 pci_err(dev, "EA Entry crosses address boundary\n");
2861 if (ent_size != ent_offset - offset) {
2862 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
2863 ent_size, ent_offset - offset);
2867 res->name = pci_name(dev);
2872 if (bei <= PCI_EA_BEI_BAR5)
2873 pci_printk(KERN_DEBUG, dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2875 else if (bei == PCI_EA_BEI_ROM)
2876 pci_printk(KERN_DEBUG, dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2878 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2879 pci_printk(KERN_DEBUG, dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2880 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2882 pci_printk(KERN_DEBUG, dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2886 return offset + ent_size;
2889 /* Enhanced Allocation Initialization */
2890 void pci_ea_init(struct pci_dev *dev)
2897 /* find PCI EA capability in list */
2898 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2902 /* determine the number of entries */
2903 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2905 num_ent &= PCI_EA_NUM_ENT_MASK;
2907 offset = ea + PCI_EA_FIRST_ENT;
2909 /* Skip DWORD 2 for type 1 functions */
2910 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2913 /* parse each EA entry */
2914 for (i = 0; i < num_ent; ++i)
2915 offset = pci_ea_read(dev, offset);
2918 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2919 struct pci_cap_saved_state *new_cap)
2921 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2925 * _pci_add_cap_save_buffer - allocate buffer for saving given
2926 * capability registers
2927 * @dev: the PCI device
2928 * @cap: the capability to allocate the buffer for
2929 * @extended: Standard or Extended capability ID
2930 * @size: requested size of the buffer
2932 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2933 bool extended, unsigned int size)
2936 struct pci_cap_saved_state *save_state;
2939 pos = pci_find_ext_capability(dev, cap);
2941 pos = pci_find_capability(dev, cap);
2946 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2950 save_state->cap.cap_nr = cap;
2951 save_state->cap.cap_extended = extended;
2952 save_state->cap.size = size;
2953 pci_add_saved_cap(dev, save_state);
2958 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2960 return _pci_add_cap_save_buffer(dev, cap, false, size);
2963 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2965 return _pci_add_cap_save_buffer(dev, cap, true, size);
2969 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2970 * @dev: the PCI device
2972 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2976 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2977 PCI_EXP_SAVE_REGS * sizeof(u16));
2979 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
2981 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2983 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
2985 pci_allocate_vc_save_buffers(dev);
2988 void pci_free_cap_save_buffers(struct pci_dev *dev)
2990 struct pci_cap_saved_state *tmp;
2991 struct hlist_node *n;
2993 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2998 * pci_configure_ari - enable or disable ARI forwarding
2999 * @dev: the PCI device
3001 * If @dev and its upstream bridge both support ARI, enable ARI in the
3002 * bridge. Otherwise, disable ARI in the bridge.
3004 void pci_configure_ari(struct pci_dev *dev)
3007 struct pci_dev *bridge;
3009 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3012 bridge = dev->bus->self;
3016 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3017 if (!(cap & PCI_EXP_DEVCAP2_ARI))
3020 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3021 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3022 PCI_EXP_DEVCTL2_ARI);
3023 bridge->ari_enabled = 1;
3025 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3026 PCI_EXP_DEVCTL2_ARI);
3027 bridge->ari_enabled = 0;
3031 static int pci_acs_enable;
3034 * pci_request_acs - ask for ACS to be enabled if supported
3036 void pci_request_acs(void)
3041 static const char *disable_acs_redir_param;
3044 * pci_disable_acs_redir - disable ACS redirect capabilities
3045 * @dev: the PCI device
3047 * For only devices specified in the disable_acs_redir parameter.
3049 static void pci_disable_acs_redir(struct pci_dev *dev)
3056 if (!disable_acs_redir_param)
3059 p = disable_acs_redir_param;
3061 ret = pci_dev_str_match(dev, p, &p);
3063 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
3064 disable_acs_redir_param);
3067 } else if (ret == 1) {
3072 if (*p != ';' && *p != ',') {
3073 /* End of param or invalid format */
3082 if (!pci_dev_specific_disable_acs_redir(dev))
3085 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3087 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
3091 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
3093 /* P2P Request & Completion Redirect */
3094 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
3096 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
3098 pci_info(dev, "disabled ACS redirect\n");
3102 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
3103 * @dev: the PCI device
3105 static void pci_std_enable_acs(struct pci_dev *dev)
3111 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3115 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
3116 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
3118 /* Source Validation */
3119 ctrl |= (cap & PCI_ACS_SV);
3121 /* P2P Request Redirect */
3122 ctrl |= (cap & PCI_ACS_RR);
3124 /* P2P Completion Redirect */
3125 ctrl |= (cap & PCI_ACS_CR);
3127 /* Upstream Forwarding */
3128 ctrl |= (cap & PCI_ACS_UF);
3130 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
3134 * pci_enable_acs - enable ACS if hardware support it
3135 * @dev: the PCI device
3137 void pci_enable_acs(struct pci_dev *dev)
3139 if (!pci_acs_enable)
3140 goto disable_acs_redir;
3142 if (!pci_dev_specific_enable_acs(dev))
3143 goto disable_acs_redir;
3145 pci_std_enable_acs(dev);
3149 * Note: pci_disable_acs_redir() must be called even if ACS was not
3150 * enabled by the kernel because it may have been enabled by
3151 * platform firmware. So if we are told to disable it, we should
3152 * always disable it after setting the kernel's default
3155 pci_disable_acs_redir(dev);
3158 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3163 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
3168 * Except for egress control, capabilities are either required
3169 * or only required if controllable. Features missing from the
3170 * capability field can therefore be assumed as hard-wired enabled.
3172 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3173 acs_flags &= (cap | PCI_ACS_EC);
3175 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3176 return (ctrl & acs_flags) == acs_flags;
3180 * pci_acs_enabled - test ACS against required flags for a given device
3181 * @pdev: device to test
3182 * @acs_flags: required PCI ACS flags
3184 * Return true if the device supports the provided flags. Automatically
3185 * filters out flags that are not implemented on multifunction devices.
3187 * Note that this interface checks the effective ACS capabilities of the
3188 * device rather than the actual capabilities. For instance, most single
3189 * function endpoints are not required to support ACS because they have no
3190 * opportunity for peer-to-peer access. We therefore return 'true'
3191 * regardless of whether the device exposes an ACS capability. This makes
3192 * it much easier for callers of this function to ignore the actual type
3193 * or topology of the device when testing ACS support.
3195 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3199 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3204 * Conventional PCI and PCI-X devices never support ACS, either
3205 * effectively or actually. The shared bus topology implies that
3206 * any device on the bus can receive or snoop DMA.
3208 if (!pci_is_pcie(pdev))
3211 switch (pci_pcie_type(pdev)) {
3213 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3214 * but since their primary interface is PCI/X, we conservatively
3215 * handle them as we would a non-PCIe device.
3217 case PCI_EXP_TYPE_PCIE_BRIDGE:
3219 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3220 * applicable... must never implement an ACS Extended Capability...".
3221 * This seems arbitrary, but we take a conservative interpretation
3222 * of this statement.
3224 case PCI_EXP_TYPE_PCI_BRIDGE:
3225 case PCI_EXP_TYPE_RC_EC:
3228 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3229 * implement ACS in order to indicate their peer-to-peer capabilities,
3230 * regardless of whether they are single- or multi-function devices.
3232 case PCI_EXP_TYPE_DOWNSTREAM:
3233 case PCI_EXP_TYPE_ROOT_PORT:
3234 return pci_acs_flags_enabled(pdev, acs_flags);
3236 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3237 * implemented by the remaining PCIe types to indicate peer-to-peer
3238 * capabilities, but only when they are part of a multifunction
3239 * device. The footnote for section 6.12 indicates the specific
3240 * PCIe types included here.
3242 case PCI_EXP_TYPE_ENDPOINT:
3243 case PCI_EXP_TYPE_UPSTREAM:
3244 case PCI_EXP_TYPE_LEG_END:
3245 case PCI_EXP_TYPE_RC_END:
3246 if (!pdev->multifunction)
3249 return pci_acs_flags_enabled(pdev, acs_flags);
3253 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3254 * to single function devices with the exception of downstream ports.
3260 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
3261 * @start: starting downstream device
3262 * @end: ending upstream device or NULL to search to the root bus
3263 * @acs_flags: required flags
3265 * Walk up a device tree from start to end testing PCI ACS support. If
3266 * any step along the way does not support the required flags, return false.
3268 bool pci_acs_path_enabled(struct pci_dev *start,
3269 struct pci_dev *end, u16 acs_flags)
3271 struct pci_dev *pdev, *parent = start;
3276 if (!pci_acs_enabled(pdev, acs_flags))
3279 if (pci_is_root_bus(pdev->bus))
3280 return (end == NULL);
3282 parent = pdev->bus->self;
3283 } while (pdev != end);
3289 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3293 * Helper to find the position of the ctrl register for a BAR.
3294 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3295 * Returns -ENOENT if no ctrl register for the BAR could be found.
3297 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3299 unsigned int pos, nbars, i;
3302 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3306 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3307 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3308 PCI_REBAR_CTRL_NBAR_SHIFT;
3310 for (i = 0; i < nbars; i++, pos += 8) {
3313 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3314 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3323 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3325 * @bar: BAR to query
3327 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3328 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3330 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3335 pos = pci_rebar_find_pos(pdev, bar);
3339 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3340 return (cap & PCI_REBAR_CAP_SIZES) >> 4;
3344 * pci_rebar_get_current_size - get the current size of a BAR
3346 * @bar: BAR to set size to
3348 * Read the size of a BAR from the resizable BAR config.
3349 * Returns size if found or negative error code.
3351 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3356 pos = pci_rebar_find_pos(pdev, bar);
3360 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3361 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
3365 * pci_rebar_set_size - set a new size for a BAR
3367 * @bar: BAR to set size to
3368 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3370 * Set the new size of a BAR as defined in the spec.
3371 * Returns zero if resizing was successful, error code otherwise.
3373 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3378 pos = pci_rebar_find_pos(pdev, bar);
3382 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3383 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3384 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
3385 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3390 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3391 * @dev: the PCI device
3392 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3393 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3394 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3395 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3397 * Return 0 if all upstream bridges support AtomicOp routing, egress
3398 * blocking is disabled on all upstream ports, and the root port supports
3399 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3400 * AtomicOp completion), or negative otherwise.
3402 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3404 struct pci_bus *bus = dev->bus;
3405 struct pci_dev *bridge;
3408 if (!pci_is_pcie(dev))
3412 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3413 * AtomicOp requesters. For now, we only support endpoints as
3414 * requesters and root ports as completers. No endpoints as
3415 * completers, and no peer-to-peer.
3418 switch (pci_pcie_type(dev)) {
3419 case PCI_EXP_TYPE_ENDPOINT:
3420 case PCI_EXP_TYPE_LEG_END:
3421 case PCI_EXP_TYPE_RC_END:
3427 while (bus->parent) {
3430 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3432 switch (pci_pcie_type(bridge)) {
3433 /* Ensure switch ports support AtomicOp routing */
3434 case PCI_EXP_TYPE_UPSTREAM:
3435 case PCI_EXP_TYPE_DOWNSTREAM:
3436 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3440 /* Ensure root port supports all the sizes we care about */
3441 case PCI_EXP_TYPE_ROOT_PORT:
3442 if ((cap & cap_mask) != cap_mask)
3447 /* Ensure upstream ports don't block AtomicOps on egress */
3448 if (!bridge->has_secondary_link) {
3449 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3451 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3458 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3459 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3462 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3465 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3466 * @dev: the PCI device
3467 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3469 * Perform INTx swizzling for a device behind one level of bridge. This is
3470 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3471 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3472 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3473 * the PCI Express Base Specification, Revision 2.1)
3475 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3479 if (pci_ari_enabled(dev->bus))
3482 slot = PCI_SLOT(dev->devfn);
3484 return (((pin - 1) + slot) % 4) + 1;
3487 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3495 while (!pci_is_root_bus(dev->bus)) {
3496 pin = pci_swizzle_interrupt_pin(dev, pin);
3497 dev = dev->bus->self;
3504 * pci_common_swizzle - swizzle INTx all the way to root bridge
3505 * @dev: the PCI device
3506 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3508 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3509 * bridges all the way up to a PCI root bus.
3511 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3515 while (!pci_is_root_bus(dev->bus)) {
3516 pin = pci_swizzle_interrupt_pin(dev, pin);
3517 dev = dev->bus->self;
3520 return PCI_SLOT(dev->devfn);
3522 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3525 * pci_release_region - Release a PCI bar
3526 * @pdev: PCI device whose resources were previously reserved by pci_request_region
3527 * @bar: BAR to release
3529 * Releases the PCI I/O and memory resources previously reserved by a
3530 * successful call to pci_request_region. Call this function only
3531 * after all use of the PCI regions has ceased.
3533 void pci_release_region(struct pci_dev *pdev, int bar)
3535 struct pci_devres *dr;
3537 if (pci_resource_len(pdev, bar) == 0)
3539 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3540 release_region(pci_resource_start(pdev, bar),
3541 pci_resource_len(pdev, bar));
3542 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3543 release_mem_region(pci_resource_start(pdev, bar),
3544 pci_resource_len(pdev, bar));
3546 dr = find_pci_dr(pdev);
3548 dr->region_mask &= ~(1 << bar);
3550 EXPORT_SYMBOL(pci_release_region);
3553 * __pci_request_region - Reserved PCI I/O and memory resource
3554 * @pdev: PCI device whose resources are to be reserved
3555 * @bar: BAR to be reserved
3556 * @res_name: Name to be associated with resource.
3557 * @exclusive: whether the region access is exclusive or not
3559 * Mark the PCI region associated with PCI device @pdev BR @bar as
3560 * being reserved by owner @res_name. Do not access any
3561 * address inside the PCI regions unless this call returns
3564 * If @exclusive is set, then the region is marked so that userspace
3565 * is explicitly not allowed to map the resource via /dev/mem or
3566 * sysfs MMIO access.
3568 * Returns 0 on success, or %EBUSY on error. A warning
3569 * message is also printed on failure.
3571 static int __pci_request_region(struct pci_dev *pdev, int bar,
3572 const char *res_name, int exclusive)
3574 struct pci_devres *dr;
3576 if (pci_resource_len(pdev, bar) == 0)
3579 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3580 if (!request_region(pci_resource_start(pdev, bar),
3581 pci_resource_len(pdev, bar), res_name))
3583 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3584 if (!__request_mem_region(pci_resource_start(pdev, bar),
3585 pci_resource_len(pdev, bar), res_name,
3590 dr = find_pci_dr(pdev);
3592 dr->region_mask |= 1 << bar;
3597 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3598 &pdev->resource[bar]);
3603 * pci_request_region - Reserve PCI I/O and memory resource
3604 * @pdev: PCI device whose resources are to be reserved
3605 * @bar: BAR to be reserved
3606 * @res_name: Name to be associated with resource
3608 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3609 * being reserved by owner @res_name. Do not access any
3610 * address inside the PCI regions unless this call returns
3613 * Returns 0 on success, or %EBUSY on error. A warning
3614 * message is also printed on failure.
3616 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3618 return __pci_request_region(pdev, bar, res_name, 0);
3620 EXPORT_SYMBOL(pci_request_region);
3623 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3624 * @pdev: PCI device whose resources are to be reserved
3625 * @bar: BAR to be reserved
3626 * @res_name: Name to be associated with resource.
3628 * Mark the PCI region associated with PCI device @pdev BR @bar as
3629 * being reserved by owner @res_name. Do not access any
3630 * address inside the PCI regions unless this call returns
3633 * Returns 0 on success, or %EBUSY on error. A warning
3634 * message is also printed on failure.
3636 * The key difference that _exclusive makes it that userspace is
3637 * explicitly not allowed to map the resource via /dev/mem or
3640 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3641 const char *res_name)
3643 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3645 EXPORT_SYMBOL(pci_request_region_exclusive);
3648 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3649 * @pdev: PCI device whose resources were previously reserved
3650 * @bars: Bitmask of BARs to be released
3652 * Release selected PCI I/O and memory resources previously reserved.
3653 * Call this function only after all use of the PCI regions has ceased.
3655 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3659 for (i = 0; i < 6; i++)
3660 if (bars & (1 << i))
3661 pci_release_region(pdev, i);
3663 EXPORT_SYMBOL(pci_release_selected_regions);
3665 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3666 const char *res_name, int excl)
3670 for (i = 0; i < 6; i++)
3671 if (bars & (1 << i))
3672 if (__pci_request_region(pdev, i, res_name, excl))
3678 if (bars & (1 << i))
3679 pci_release_region(pdev, i);
3686 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3687 * @pdev: PCI device whose resources are to be reserved
3688 * @bars: Bitmask of BARs to be requested
3689 * @res_name: Name to be associated with resource
3691 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3692 const char *res_name)
3694 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3696 EXPORT_SYMBOL(pci_request_selected_regions);
3698 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3699 const char *res_name)
3701 return __pci_request_selected_regions(pdev, bars, res_name,
3702 IORESOURCE_EXCLUSIVE);
3704 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3707 * pci_release_regions - Release reserved PCI I/O and memory resources
3708 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3710 * Releases all PCI I/O and memory resources previously reserved by a
3711 * successful call to pci_request_regions. Call this function only
3712 * after all use of the PCI regions has ceased.
3715 void pci_release_regions(struct pci_dev *pdev)
3717 pci_release_selected_regions(pdev, (1 << 6) - 1);
3719 EXPORT_SYMBOL(pci_release_regions);
3722 * pci_request_regions - Reserved PCI I/O and memory resources
3723 * @pdev: PCI device whose resources are to be reserved
3724 * @res_name: Name to be associated with resource.
3726 * Mark all PCI regions associated with PCI device @pdev as
3727 * being reserved by owner @res_name. Do not access any
3728 * address inside the PCI regions unless this call returns
3731 * Returns 0 on success, or %EBUSY on error. A warning
3732 * message is also printed on failure.
3734 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3736 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3738 EXPORT_SYMBOL(pci_request_regions);
3741 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3742 * @pdev: PCI device whose resources are to be reserved
3743 * @res_name: Name to be associated with resource.
3745 * Mark all PCI regions associated with PCI device @pdev as
3746 * being reserved by owner @res_name. Do not access any
3747 * address inside the PCI regions unless this call returns
3750 * pci_request_regions_exclusive() will mark the region so that
3751 * /dev/mem and the sysfs MMIO access will not be allowed.
3753 * Returns 0 on success, or %EBUSY on error. A warning
3754 * message is also printed on failure.
3756 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3758 return pci_request_selected_regions_exclusive(pdev,
3759 ((1 << 6) - 1), res_name);
3761 EXPORT_SYMBOL(pci_request_regions_exclusive);
3764 * Record the PCI IO range (expressed as CPU physical address + size).
3765 * Return a negative value if an error has occured, zero otherwise
3767 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
3768 resource_size_t size)
3772 struct logic_pio_hwaddr *range;
3774 if (!size || addr + size < addr)
3777 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3781 range->fwnode = fwnode;
3783 range->hw_start = addr;
3784 range->flags = LOGIC_PIO_CPU_MMIO;
3786 ret = logic_pio_register_range(range);
3794 phys_addr_t pci_pio_to_address(unsigned long pio)
3796 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3799 if (pio >= MMIO_UPPER_LIMIT)
3802 address = logic_pio_to_hwaddr(pio);
3808 unsigned long __weak pci_address_to_pio(phys_addr_t address)
3811 return logic_pio_trans_cpuaddr(address);
3813 if (address > IO_SPACE_LIMIT)
3814 return (unsigned long)-1;
3816 return (unsigned long) address;
3821 * pci_remap_iospace - Remap the memory mapped I/O space
3822 * @res: Resource describing the I/O space
3823 * @phys_addr: physical address of range to be mapped
3825 * Remap the memory mapped I/O space described by the @res
3826 * and the CPU physical address @phys_addr into virtual address space.
3827 * Only architectures that have memory mapped IO functions defined
3828 * (and the PCI_IOBASE value defined) should call this function.
3830 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3832 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3833 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3835 if (!(res->flags & IORESOURCE_IO))
3838 if (res->end > IO_SPACE_LIMIT)
3841 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3842 pgprot_device(PAGE_KERNEL));
3844 /* this architecture does not have memory mapped I/O space,
3845 so this function should never be called */
3846 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3850 EXPORT_SYMBOL(pci_remap_iospace);
3853 * pci_unmap_iospace - Unmap the memory mapped I/O space
3854 * @res: resource to be unmapped
3856 * Unmap the CPU virtual address @res from virtual address space.
3857 * Only architectures that have memory mapped IO functions defined
3858 * (and the PCI_IOBASE value defined) should call this function.
3860 void pci_unmap_iospace(struct resource *res)
3862 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3863 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3865 unmap_kernel_range(vaddr, resource_size(res));
3868 EXPORT_SYMBOL(pci_unmap_iospace);
3870 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
3872 struct resource **res = ptr;
3874 pci_unmap_iospace(*res);
3878 * devm_pci_remap_iospace - Managed pci_remap_iospace()
3879 * @dev: Generic device to remap IO address for
3880 * @res: Resource describing the I/O space
3881 * @phys_addr: physical address of range to be mapped
3883 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
3886 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
3887 phys_addr_t phys_addr)
3889 const struct resource **ptr;
3892 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
3896 error = pci_remap_iospace(res, phys_addr);
3901 devres_add(dev, ptr);
3906 EXPORT_SYMBOL(devm_pci_remap_iospace);
3909 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
3910 * @dev: Generic device to remap IO address for
3911 * @offset: Resource address to map
3912 * @size: Size of map
3914 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
3917 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
3918 resource_size_t offset,
3919 resource_size_t size)
3921 void __iomem **ptr, *addr;
3923 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
3927 addr = pci_remap_cfgspace(offset, size);
3930 devres_add(dev, ptr);
3936 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
3939 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
3940 * @dev: generic device to handle the resource for
3941 * @res: configuration space resource to be handled
3943 * Checks that a resource is a valid memory region, requests the memory
3944 * region and ioremaps with pci_remap_cfgspace() API that ensures the
3945 * proper PCI configuration space memory attributes are guaranteed.
3947 * All operations are managed and will be undone on driver detach.
3949 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
3950 * on failure. Usage example::
3952 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3953 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
3955 * return PTR_ERR(base);
3957 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
3958 struct resource *res)
3960 resource_size_t size;
3962 void __iomem *dest_ptr;
3966 if (!res || resource_type(res) != IORESOURCE_MEM) {
3967 dev_err(dev, "invalid resource\n");
3968 return IOMEM_ERR_PTR(-EINVAL);
3971 size = resource_size(res);
3972 name = res->name ?: dev_name(dev);
3974 if (!devm_request_mem_region(dev, res->start, size, name)) {
3975 dev_err(dev, "can't request region for resource %pR\n", res);
3976 return IOMEM_ERR_PTR(-EBUSY);
3979 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
3981 dev_err(dev, "ioremap failed for resource %pR\n", res);
3982 devm_release_mem_region(dev, res->start, size);
3983 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
3988 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
3990 static void __pci_set_master(struct pci_dev *dev, bool enable)
3994 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3996 cmd = old_cmd | PCI_COMMAND_MASTER;
3998 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3999 if (cmd != old_cmd) {
4000 pci_dbg(dev, "%s bus mastering\n",
4001 enable ? "enabling" : "disabling");
4002 pci_write_config_word(dev, PCI_COMMAND, cmd);
4004 dev->is_busmaster = enable;
4008 * pcibios_setup - process "pci=" kernel boot arguments
4009 * @str: string used to pass in "pci=" kernel boot arguments
4011 * Process kernel boot arguments. This is the default implementation.
4012 * Architecture specific implementations can override this as necessary.
4014 char * __weak __init pcibios_setup(char *str)
4020 * pcibios_set_master - enable PCI bus-mastering for device dev
4021 * @dev: the PCI device to enable
4023 * Enables PCI bus-mastering for the device. This is the default
4024 * implementation. Architecture specific implementations can override
4025 * this if necessary.
4027 void __weak pcibios_set_master(struct pci_dev *dev)
4031 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4032 if (pci_is_pcie(dev))
4035 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4037 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4038 else if (lat > pcibios_max_latency)
4039 lat = pcibios_max_latency;
4043 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4047 * pci_set_master - enables bus-mastering for device dev
4048 * @dev: the PCI device to enable
4050 * Enables bus-mastering on the device and calls pcibios_set_master()
4051 * to do the needed arch specific settings.
4053 void pci_set_master(struct pci_dev *dev)
4055 __pci_set_master(dev, true);
4056 pcibios_set_master(dev);
4058 EXPORT_SYMBOL(pci_set_master);
4061 * pci_clear_master - disables bus-mastering for device dev
4062 * @dev: the PCI device to disable
4064 void pci_clear_master(struct pci_dev *dev)
4066 __pci_set_master(dev, false);
4068 EXPORT_SYMBOL(pci_clear_master);
4071 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4072 * @dev: the PCI device for which MWI is to be enabled
4074 * Helper function for pci_set_mwi.
4075 * Originally copied from drivers/net/acenic.c.
4076 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4078 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4080 int pci_set_cacheline_size(struct pci_dev *dev)
4084 if (!pci_cache_line_size)
4087 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4088 equal to or multiple of the right value. */
4089 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4090 if (cacheline_size >= pci_cache_line_size &&
4091 (cacheline_size % pci_cache_line_size) == 0)
4094 /* Write the correct value. */
4095 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4097 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4098 if (cacheline_size == pci_cache_line_size)
4101 pci_printk(KERN_DEBUG, dev, "cache line size of %d is not supported\n",
4102 pci_cache_line_size << 2);
4106 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4109 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4110 * @dev: the PCI device for which MWI is enabled
4112 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4114 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4116 int pci_set_mwi(struct pci_dev *dev)
4118 #ifdef PCI_DISABLE_MWI
4124 rc = pci_set_cacheline_size(dev);
4128 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4129 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4130 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4131 cmd |= PCI_COMMAND_INVALIDATE;
4132 pci_write_config_word(dev, PCI_COMMAND, cmd);
4137 EXPORT_SYMBOL(pci_set_mwi);
4140 * pcim_set_mwi - a device-managed pci_set_mwi()
4141 * @dev: the PCI device for which MWI is enabled
4143 * Managed pci_set_mwi().
4145 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4147 int pcim_set_mwi(struct pci_dev *dev)
4149 struct pci_devres *dr;
4151 dr = find_pci_dr(dev);
4156 return pci_set_mwi(dev);
4158 EXPORT_SYMBOL(pcim_set_mwi);
4161 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4162 * @dev: the PCI device for which MWI is enabled
4164 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4165 * Callers are not required to check the return value.
4167 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4169 int pci_try_set_mwi(struct pci_dev *dev)
4171 #ifdef PCI_DISABLE_MWI
4174 return pci_set_mwi(dev);
4177 EXPORT_SYMBOL(pci_try_set_mwi);
4180 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4181 * @dev: the PCI device to disable
4183 * Disables PCI Memory-Write-Invalidate transaction on the device
4185 void pci_clear_mwi(struct pci_dev *dev)
4187 #ifndef PCI_DISABLE_MWI
4190 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4191 if (cmd & PCI_COMMAND_INVALIDATE) {
4192 cmd &= ~PCI_COMMAND_INVALIDATE;
4193 pci_write_config_word(dev, PCI_COMMAND, cmd);
4197 EXPORT_SYMBOL(pci_clear_mwi);
4200 * pci_intx - enables/disables PCI INTx for device dev
4201 * @pdev: the PCI device to operate on
4202 * @enable: boolean: whether to enable or disable PCI INTx
4204 * Enables/disables PCI INTx for device dev
4206 void pci_intx(struct pci_dev *pdev, int enable)
4208 u16 pci_command, new;
4210 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4213 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4215 new = pci_command | PCI_COMMAND_INTX_DISABLE;
4217 if (new != pci_command) {
4218 struct pci_devres *dr;
4220 pci_write_config_word(pdev, PCI_COMMAND, new);
4222 dr = find_pci_dr(pdev);
4223 if (dr && !dr->restore_intx) {
4224 dr->restore_intx = 1;
4225 dr->orig_intx = !enable;
4229 EXPORT_SYMBOL_GPL(pci_intx);
4231 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4233 struct pci_bus *bus = dev->bus;
4234 bool mask_updated = true;
4235 u32 cmd_status_dword;
4236 u16 origcmd, newcmd;
4237 unsigned long flags;
4241 * We do a single dword read to retrieve both command and status.
4242 * Document assumptions that make this possible.
4244 BUILD_BUG_ON(PCI_COMMAND % 4);
4245 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4247 raw_spin_lock_irqsave(&pci_lock, flags);
4249 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4251 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4254 * Check interrupt status register to see whether our device
4255 * triggered the interrupt (when masking) or the next IRQ is
4256 * already pending (when unmasking).
4258 if (mask != irq_pending) {
4259 mask_updated = false;
4263 origcmd = cmd_status_dword;
4264 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4266 newcmd |= PCI_COMMAND_INTX_DISABLE;
4267 if (newcmd != origcmd)
4268 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4271 raw_spin_unlock_irqrestore(&pci_lock, flags);
4273 return mask_updated;
4277 * pci_check_and_mask_intx - mask INTx on pending interrupt
4278 * @dev: the PCI device to operate on
4280 * Check if the device dev has its INTx line asserted, mask it and
4281 * return true in that case. False is returned if no interrupt was
4284 bool pci_check_and_mask_intx(struct pci_dev *dev)
4286 return pci_check_and_set_intx_mask(dev, true);
4288 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4291 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4292 * @dev: the PCI device to operate on
4294 * Check if the device dev has its INTx line asserted, unmask it if not
4295 * and return true. False is returned and the mask remains active if
4296 * there was still an interrupt pending.
4298 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4300 return pci_check_and_set_intx_mask(dev, false);
4302 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4305 * pci_wait_for_pending_transaction - waits for pending transaction
4306 * @dev: the PCI device to operate on
4308 * Return 0 if transaction is pending 1 otherwise.
4310 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4312 if (!pci_is_pcie(dev))
4315 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4316 PCI_EXP_DEVSTA_TRPND);
4318 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4320 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
4326 * After reset, the device should not silently discard config
4327 * requests, but it may still indicate that it needs more time by
4328 * responding to them with CRS completions. The Root Port will
4329 * generally synthesize ~0 data to complete the read (except when
4330 * CRS SV is enabled and the read was for the Vendor ID; in that
4331 * case it synthesizes 0x0001 data).
4333 * Wait for the device to return a non-CRS completion. Read the
4334 * Command register instead of Vendor ID so we don't have to
4335 * contend with the CRS SV value.
4337 pci_read_config_dword(dev, PCI_COMMAND, &id);
4339 if (delay > timeout) {
4340 pci_warn(dev, "not ready %dms after %s; giving up\n",
4341 delay - 1, reset_type);
4346 pci_info(dev, "not ready %dms after %s; waiting\n",
4347 delay - 1, reset_type);
4351 pci_read_config_dword(dev, PCI_COMMAND, &id);
4355 pci_info(dev, "ready %dms after %s\n", delay - 1,
4362 * pcie_has_flr - check if a device supports function level resets
4363 * @dev: device to check
4365 * Returns true if the device advertises support for PCIe function level
4368 bool pcie_has_flr(struct pci_dev *dev)
4372 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4375 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
4376 return cap & PCI_EXP_DEVCAP_FLR;
4378 EXPORT_SYMBOL_GPL(pcie_has_flr);
4381 * pcie_flr - initiate a PCIe function level reset
4382 * @dev: device to reset
4384 * Initiate a function level reset on @dev. The caller should ensure the
4385 * device supports FLR before calling this function, e.g. by using the
4386 * pcie_has_flr() helper.
4388 int pcie_flr(struct pci_dev *dev)
4390 if (!pci_wait_for_pending_transaction(dev))
4391 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4393 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4396 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4397 * 100ms, but may silently discard requests while the FLR is in
4398 * progress. Wait 100ms before trying to access the device.
4402 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4404 EXPORT_SYMBOL_GPL(pcie_flr);
4406 static int pci_af_flr(struct pci_dev *dev, int probe)
4411 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4415 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4418 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4419 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4426 * Wait for Transaction Pending bit to clear. A word-aligned test
4427 * is used, so we use the conrol offset rather than status and shift
4428 * the test bit to match.
4430 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4431 PCI_AF_STATUS_TP << 8))
4432 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4434 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4437 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4438 * updated 27 July 2006; a device must complete an FLR within
4439 * 100ms, but may silently discard requests while the FLR is in
4440 * progress. Wait 100ms before trying to access the device.
4444 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4448 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4449 * @dev: Device to reset.
4450 * @probe: If set, only check if the device can be reset this way.
4452 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4453 * unset, it will be reinitialized internally when going from PCI_D3hot to
4454 * PCI_D0. If that's the case and the device is not in a low-power state
4455 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4457 * NOTE: This causes the caller to sleep for twice the device power transition
4458 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4459 * by default (i.e. unless the @dev's d3_delay field has a different value).
4460 * Moreover, only devices in D0 can be reset by this function.
4462 static int pci_pm_reset(struct pci_dev *dev, int probe)
4466 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4469 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4470 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4476 if (dev->current_state != PCI_D0)
4479 csr &= ~PCI_PM_CTRL_STATE_MASK;
4481 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4482 pci_dev_d3_sleep(dev);
4484 csr &= ~PCI_PM_CTRL_STATE_MASK;
4486 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4487 pci_dev_d3_sleep(dev);
4489 return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS);
4492 * pcie_wait_for_link - Wait until link is active or inactive
4493 * @pdev: Bridge device
4494 * @active: waiting for active or inactive?
4496 * Use this to wait till link becomes active or inactive.
4498 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4505 * Some controllers might not implement link active reporting. In this
4506 * case, we wait for 1000 + 100 ms.
4508 if (!pdev->link_active_reporting) {
4514 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4515 * after which we should expect an link active if the reset was
4516 * successful. If so, software must wait a minimum 100ms before sending
4517 * configuration requests to devices downstream this port.
4519 * If the link fails to activate, either the device was physically
4520 * removed or the link is permanently failed.
4525 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4526 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4536 else if (ret != active)
4537 pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n",
4538 active ? "set" : "cleared");
4539 return ret == active;
4542 void pci_reset_secondary_bus(struct pci_dev *dev)
4546 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4547 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4548 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4551 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4552 * this to 2ms to ensure that we meet the minimum requirement.
4556 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
4557 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4560 * Trhfa for conventional PCI is 2^25 clock cycles.
4561 * Assuming a minimum 33MHz clock this results in a 1s
4562 * delay before we can consider subordinate devices to
4563 * be re-initialized. PCIe has some ways to shorten this,
4564 * but we don't make use of them yet.
4569 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4571 pci_reset_secondary_bus(dev);
4575 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
4576 * @dev: Bridge device
4578 * Use the bridge control register to assert reset on the secondary bus.
4579 * Devices on the secondary bus are left in power-on state.
4581 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
4583 pcibios_reset_secondary_bus(dev);
4585 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
4587 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
4589 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4591 struct pci_dev *pdev;
4593 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4594 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4597 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4604 return pci_bridge_secondary_bus_reset(dev->bus->self);
4607 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
4611 if (!hotplug || !try_module_get(hotplug->owner))
4614 if (hotplug->ops->reset_slot)
4615 rc = hotplug->ops->reset_slot(hotplug, probe);
4617 module_put(hotplug->owner);
4622 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
4624 struct pci_dev *pdev;
4626 if (dev->subordinate || !dev->slot ||
4627 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4630 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4631 if (pdev != dev && pdev->slot == dev->slot)
4634 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
4637 static void pci_dev_lock(struct pci_dev *dev)
4639 pci_cfg_access_lock(dev);
4640 /* block PM suspend, driver probe, etc. */
4641 device_lock(&dev->dev);
4644 /* Return 1 on successful lock, 0 on contention */
4645 static int pci_dev_trylock(struct pci_dev *dev)
4647 if (pci_cfg_access_trylock(dev)) {
4648 if (device_trylock(&dev->dev))
4650 pci_cfg_access_unlock(dev);
4656 static void pci_dev_unlock(struct pci_dev *dev)
4658 device_unlock(&dev->dev);
4659 pci_cfg_access_unlock(dev);
4662 static void pci_dev_save_and_disable(struct pci_dev *dev)
4664 const struct pci_error_handlers *err_handler =
4665 dev->driver ? dev->driver->err_handler : NULL;
4668 * dev->driver->err_handler->reset_prepare() is protected against
4669 * races with ->remove() by the device lock, which must be held by
4672 if (err_handler && err_handler->reset_prepare)
4673 err_handler->reset_prepare(dev);
4676 * Wake-up device prior to save. PM registers default to D0 after
4677 * reset and a simple register restore doesn't reliably return
4678 * to a non-D0 state anyway.
4680 pci_set_power_state(dev, PCI_D0);
4682 pci_save_state(dev);
4684 * Disable the device by clearing the Command register, except for
4685 * INTx-disable which is set. This not only disables MMIO and I/O port
4686 * BARs, but also prevents the device from being Bus Master, preventing
4687 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4688 * compliant devices, INTx-disable prevents legacy interrupts.
4690 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4693 static void pci_dev_restore(struct pci_dev *dev)
4695 const struct pci_error_handlers *err_handler =
4696 dev->driver ? dev->driver->err_handler : NULL;
4698 pci_restore_state(dev);
4701 * dev->driver->err_handler->reset_done() is protected against
4702 * races with ->remove() by the device lock, which must be held by
4705 if (err_handler && err_handler->reset_done)
4706 err_handler->reset_done(dev);
4710 * __pci_reset_function_locked - reset a PCI device function while holding
4711 * the @dev mutex lock.
4712 * @dev: PCI device to reset
4714 * Some devices allow an individual function to be reset without affecting
4715 * other functions in the same device. The PCI device must be responsive
4716 * to PCI config space in order to use this function.
4718 * The device function is presumed to be unused and the caller is holding
4719 * the device mutex lock when this function is called.
4720 * Resetting the device will make the contents of PCI configuration space
4721 * random, so any caller of this must be prepared to reinitialise the
4722 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4725 * Returns 0 if the device function was successfully reset or negative if the
4726 * device doesn't support resetting a single function.
4728 int __pci_reset_function_locked(struct pci_dev *dev)
4735 * A reset method returns -ENOTTY if it doesn't support this device
4736 * and we should try the next method.
4738 * If it returns 0 (success), we're finished. If it returns any
4739 * other error, we're also finished: this indicates that further
4740 * reset mechanisms might be broken on the device.
4742 rc = pci_dev_specific_reset(dev, 0);
4745 if (pcie_has_flr(dev)) {
4750 rc = pci_af_flr(dev, 0);
4753 rc = pci_pm_reset(dev, 0);
4756 rc = pci_dev_reset_slot_function(dev, 0);
4759 return pci_parent_bus_reset(dev, 0);
4761 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4764 * pci_probe_reset_function - check whether the device can be safely reset
4765 * @dev: PCI device to reset
4767 * Some devices allow an individual function to be reset without affecting
4768 * other functions in the same device. The PCI device must be responsive
4769 * to PCI config space in order to use this function.
4771 * Returns 0 if the device function can be reset or negative if the
4772 * device doesn't support resetting a single function.
4774 int pci_probe_reset_function(struct pci_dev *dev)
4780 rc = pci_dev_specific_reset(dev, 1);
4783 if (pcie_has_flr(dev))
4785 rc = pci_af_flr(dev, 1);
4788 rc = pci_pm_reset(dev, 1);
4791 rc = pci_dev_reset_slot_function(dev, 1);
4795 return pci_parent_bus_reset(dev, 1);
4799 * pci_reset_function - quiesce and reset a PCI device function
4800 * @dev: PCI device to reset
4802 * Some devices allow an individual function to be reset without affecting
4803 * other functions in the same device. The PCI device must be responsive
4804 * to PCI config space in order to use this function.
4806 * This function does not just reset the PCI portion of a device, but
4807 * clears all the state associated with the device. This function differs
4808 * from __pci_reset_function_locked() in that it saves and restores device state
4809 * over the reset and takes the PCI device lock.
4811 * Returns 0 if the device function was successfully reset or negative if the
4812 * device doesn't support resetting a single function.
4814 int pci_reset_function(struct pci_dev *dev)
4822 pci_dev_save_and_disable(dev);
4824 rc = __pci_reset_function_locked(dev);
4826 pci_dev_restore(dev);
4827 pci_dev_unlock(dev);
4831 EXPORT_SYMBOL_GPL(pci_reset_function);
4834 * pci_reset_function_locked - quiesce and reset a PCI device function
4835 * @dev: PCI device to reset
4837 * Some devices allow an individual function to be reset without affecting
4838 * other functions in the same device. The PCI device must be responsive
4839 * to PCI config space in order to use this function.
4841 * This function does not just reset the PCI portion of a device, but
4842 * clears all the state associated with the device. This function differs
4843 * from __pci_reset_function_locked() in that it saves and restores device state
4844 * over the reset. It also differs from pci_reset_function() in that it
4845 * requires the PCI device lock to be held.
4847 * Returns 0 if the device function was successfully reset or negative if the
4848 * device doesn't support resetting a single function.
4850 int pci_reset_function_locked(struct pci_dev *dev)
4857 pci_dev_save_and_disable(dev);
4859 rc = __pci_reset_function_locked(dev);
4861 pci_dev_restore(dev);
4865 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
4868 * pci_try_reset_function - quiesce and reset a PCI device function
4869 * @dev: PCI device to reset
4871 * Same as above, except return -EAGAIN if unable to lock device.
4873 int pci_try_reset_function(struct pci_dev *dev)
4880 if (!pci_dev_trylock(dev))
4883 pci_dev_save_and_disable(dev);
4884 rc = __pci_reset_function_locked(dev);
4885 pci_dev_restore(dev);
4886 pci_dev_unlock(dev);
4890 EXPORT_SYMBOL_GPL(pci_try_reset_function);
4892 /* Do any devices on or below this bus prevent a bus reset? */
4893 static bool pci_bus_resetable(struct pci_bus *bus)
4895 struct pci_dev *dev;
4898 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4901 list_for_each_entry(dev, &bus->devices, bus_list) {
4902 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4903 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4910 /* Lock devices from the top of the tree down */
4911 static void pci_bus_lock(struct pci_bus *bus)
4913 struct pci_dev *dev;
4915 list_for_each_entry(dev, &bus->devices, bus_list) {
4917 if (dev->subordinate)
4918 pci_bus_lock(dev->subordinate);
4922 /* Unlock devices from the bottom of the tree up */
4923 static void pci_bus_unlock(struct pci_bus *bus)
4925 struct pci_dev *dev;
4927 list_for_each_entry(dev, &bus->devices, bus_list) {
4928 if (dev->subordinate)
4929 pci_bus_unlock(dev->subordinate);
4930 pci_dev_unlock(dev);
4934 /* Return 1 on successful lock, 0 on contention */
4935 static int pci_bus_trylock(struct pci_bus *bus)
4937 struct pci_dev *dev;
4939 list_for_each_entry(dev, &bus->devices, bus_list) {
4940 if (!pci_dev_trylock(dev))
4942 if (dev->subordinate) {
4943 if (!pci_bus_trylock(dev->subordinate)) {
4944 pci_dev_unlock(dev);
4952 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
4953 if (dev->subordinate)
4954 pci_bus_unlock(dev->subordinate);
4955 pci_dev_unlock(dev);
4960 /* Do any devices on or below this slot prevent a bus reset? */
4961 static bool pci_slot_resetable(struct pci_slot *slot)
4963 struct pci_dev *dev;
4965 if (slot->bus->self &&
4966 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4969 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4970 if (!dev->slot || dev->slot != slot)
4972 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4973 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4980 /* Lock devices from the top of the tree down */
4981 static void pci_slot_lock(struct pci_slot *slot)
4983 struct pci_dev *dev;
4985 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4986 if (!dev->slot || dev->slot != slot)
4989 if (dev->subordinate)
4990 pci_bus_lock(dev->subordinate);
4994 /* Unlock devices from the bottom of the tree up */
4995 static void pci_slot_unlock(struct pci_slot *slot)
4997 struct pci_dev *dev;
4999 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5000 if (!dev->slot || dev->slot != slot)
5002 if (dev->subordinate)
5003 pci_bus_unlock(dev->subordinate);
5004 pci_dev_unlock(dev);
5008 /* Return 1 on successful lock, 0 on contention */
5009 static int pci_slot_trylock(struct pci_slot *slot)
5011 struct pci_dev *dev;
5013 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5014 if (!dev->slot || dev->slot != slot)
5016 if (!pci_dev_trylock(dev))
5018 if (dev->subordinate) {
5019 if (!pci_bus_trylock(dev->subordinate)) {
5020 pci_dev_unlock(dev);
5028 list_for_each_entry_continue_reverse(dev,
5029 &slot->bus->devices, bus_list) {
5030 if (!dev->slot || dev->slot != slot)
5032 if (dev->subordinate)
5033 pci_bus_unlock(dev->subordinate);
5034 pci_dev_unlock(dev);
5039 /* Save and disable devices from the top of the tree down */
5040 static void pci_bus_save_and_disable(struct pci_bus *bus)
5042 struct pci_dev *dev;
5044 list_for_each_entry(dev, &bus->devices, bus_list) {
5046 pci_dev_save_and_disable(dev);
5047 pci_dev_unlock(dev);
5048 if (dev->subordinate)
5049 pci_bus_save_and_disable(dev->subordinate);
5054 * Restore devices from top of the tree down - parent bridges need to be
5055 * restored before we can get to subordinate devices.
5057 static void pci_bus_restore(struct pci_bus *bus)
5059 struct pci_dev *dev;
5061 list_for_each_entry(dev, &bus->devices, bus_list) {
5063 pci_dev_restore(dev);
5064 pci_dev_unlock(dev);
5065 if (dev->subordinate)
5066 pci_bus_restore(dev->subordinate);
5070 /* Save and disable devices from the top of the tree down */
5071 static void pci_slot_save_and_disable(struct pci_slot *slot)
5073 struct pci_dev *dev;
5075 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5076 if (!dev->slot || dev->slot != slot)
5078 pci_dev_save_and_disable(dev);
5079 if (dev->subordinate)
5080 pci_bus_save_and_disable(dev->subordinate);
5085 * Restore devices from top of the tree down - parent bridges need to be
5086 * restored before we can get to subordinate devices.
5088 static void pci_slot_restore(struct pci_slot *slot)
5090 struct pci_dev *dev;
5092 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5093 if (!dev->slot || dev->slot != slot)
5096 pci_dev_restore(dev);
5097 pci_dev_unlock(dev);
5098 if (dev->subordinate)
5099 pci_bus_restore(dev->subordinate);
5103 static int pci_slot_reset(struct pci_slot *slot, int probe)
5107 if (!slot || !pci_slot_resetable(slot))
5111 pci_slot_lock(slot);
5115 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5118 pci_slot_unlock(slot);
5124 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5125 * @slot: PCI slot to probe
5127 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5129 int pci_probe_reset_slot(struct pci_slot *slot)
5131 return pci_slot_reset(slot, 1);
5133 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5136 * __pci_reset_slot - Try to reset a PCI slot
5137 * @slot: PCI slot to reset
5139 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5140 * independent of other slots. For instance, some slots may support slot power
5141 * control. In the case of a 1:1 bus to slot architecture, this function may
5142 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5143 * Generally a slot reset should be attempted before a bus reset. All of the
5144 * function of the slot and any subordinate buses behind the slot are reset
5145 * through this function. PCI config space of all devices in the slot and
5146 * behind the slot is saved before and restored after reset.
5148 * Same as above except return -EAGAIN if the slot cannot be locked
5150 static int __pci_reset_slot(struct pci_slot *slot)
5154 rc = pci_slot_reset(slot, 1);
5158 pci_slot_save_and_disable(slot);
5160 if (pci_slot_trylock(slot)) {
5162 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
5163 pci_slot_unlock(slot);
5167 pci_slot_restore(slot);
5172 static int pci_bus_reset(struct pci_bus *bus, int probe)
5176 if (!bus->self || !pci_bus_resetable(bus))
5186 ret = pci_bridge_secondary_bus_reset(bus->self);
5188 pci_bus_unlock(bus);
5194 * pci_bus_error_reset - reset the bridge's subordinate bus
5195 * @bridge: The parent device that connects to the bus to reset
5197 * This function will first try to reset the slots on this bus if the method is
5198 * available. If slot reset fails or is not available, this will fall back to a
5199 * secondary bus reset.
5201 int pci_bus_error_reset(struct pci_dev *bridge)
5203 struct pci_bus *bus = bridge->subordinate;
5204 struct pci_slot *slot;
5209 mutex_lock(&pci_slot_mutex);
5210 if (list_empty(&bus->slots))
5213 list_for_each_entry(slot, &bus->slots, list)
5214 if (pci_probe_reset_slot(slot))
5217 list_for_each_entry(slot, &bus->slots, list)
5218 if (pci_slot_reset(slot, 0))
5221 mutex_unlock(&pci_slot_mutex);
5224 mutex_unlock(&pci_slot_mutex);
5225 return pci_bus_reset(bridge->subordinate, 0);
5229 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5230 * @bus: PCI bus to probe
5232 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5234 int pci_probe_reset_bus(struct pci_bus *bus)
5236 return pci_bus_reset(bus, 1);
5238 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
5241 * __pci_reset_bus - Try to reset a PCI bus
5242 * @bus: top level PCI bus to reset
5244 * Same as above except return -EAGAIN if the bus cannot be locked
5246 static int __pci_reset_bus(struct pci_bus *bus)
5250 rc = pci_bus_reset(bus, 1);
5254 pci_bus_save_and_disable(bus);
5256 if (pci_bus_trylock(bus)) {
5258 rc = pci_bridge_secondary_bus_reset(bus->self);
5259 pci_bus_unlock(bus);
5263 pci_bus_restore(bus);
5269 * pci_reset_bus - Try to reset a PCI bus
5270 * @pdev: top level PCI device to reset via slot/bus
5272 * Same as above except return -EAGAIN if the bus cannot be locked
5274 int pci_reset_bus(struct pci_dev *pdev)
5276 return (!pci_probe_reset_slot(pdev->slot)) ?
5277 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
5279 EXPORT_SYMBOL_GPL(pci_reset_bus);
5282 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5283 * @dev: PCI device to query
5285 * Returns mmrbc: maximum designed memory read count in bytes
5286 * or appropriate error value.
5288 int pcix_get_max_mmrbc(struct pci_dev *dev)
5293 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5297 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5300 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5302 EXPORT_SYMBOL(pcix_get_max_mmrbc);
5305 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5306 * @dev: PCI device to query
5308 * Returns mmrbc: maximum memory read count in bytes
5309 * or appropriate error value.
5311 int pcix_get_mmrbc(struct pci_dev *dev)
5316 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5320 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5323 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5325 EXPORT_SYMBOL(pcix_get_mmrbc);
5328 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5329 * @dev: PCI device to query
5330 * @mmrbc: maximum memory read count in bytes
5331 * valid values are 512, 1024, 2048, 4096
5333 * If possible sets maximum memory read byte count, some bridges have erratas
5334 * that prevent this.
5336 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5342 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5345 v = ffs(mmrbc) - 10;
5347 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5351 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5354 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5357 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5360 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5362 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5365 cmd &= ~PCI_X_CMD_MAX_READ;
5367 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5372 EXPORT_SYMBOL(pcix_set_mmrbc);
5375 * pcie_get_readrq - get PCI Express read request size
5376 * @dev: PCI device to query
5378 * Returns maximum memory read request in bytes
5379 * or appropriate error value.
5381 int pcie_get_readrq(struct pci_dev *dev)
5385 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5387 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5389 EXPORT_SYMBOL(pcie_get_readrq);
5392 * pcie_set_readrq - set PCI Express maximum memory read request
5393 * @dev: PCI device to query
5394 * @rq: maximum memory read count in bytes
5395 * valid values are 128, 256, 512, 1024, 2048, 4096
5397 * If possible sets maximum memory read request in bytes
5399 int pcie_set_readrq(struct pci_dev *dev, int rq)
5403 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5407 * If using the "performance" PCIe config, we clamp the
5408 * read rq size to the max packet size to prevent the
5409 * host bridge generating requests larger than we can
5412 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5413 int mps = pcie_get_mps(dev);
5419 v = (ffs(rq) - 8) << 12;
5421 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5422 PCI_EXP_DEVCTL_READRQ, v);
5424 EXPORT_SYMBOL(pcie_set_readrq);
5427 * pcie_get_mps - get PCI Express maximum payload size
5428 * @dev: PCI device to query
5430 * Returns maximum payload size in bytes
5432 int pcie_get_mps(struct pci_dev *dev)
5436 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5438 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5440 EXPORT_SYMBOL(pcie_get_mps);
5443 * pcie_set_mps - set PCI Express maximum payload size
5444 * @dev: PCI device to query
5445 * @mps: maximum payload size in bytes
5446 * valid values are 128, 256, 512, 1024, 2048, 4096
5448 * If possible sets maximum payload size
5450 int pcie_set_mps(struct pci_dev *dev, int mps)
5454 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
5458 if (v > dev->pcie_mpss)
5462 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5463 PCI_EXP_DEVCTL_PAYLOAD, v);
5465 EXPORT_SYMBOL(pcie_set_mps);
5468 * pcie_bandwidth_available - determine minimum link settings of a PCIe
5469 * device and its bandwidth limitation
5470 * @dev: PCI device to query
5471 * @limiting_dev: storage for device causing the bandwidth limitation
5472 * @speed: storage for speed of limiting device
5473 * @width: storage for width of limiting device
5475 * Walk up the PCI device chain and find the point where the minimum
5476 * bandwidth is available. Return the bandwidth available there and (if
5477 * limiting_dev, speed, and width pointers are supplied) information about
5478 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
5481 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
5482 enum pci_bus_speed *speed,
5483 enum pcie_link_width *width)
5486 enum pci_bus_speed next_speed;
5487 enum pcie_link_width next_width;
5491 *speed = PCI_SPEED_UNKNOWN;
5493 *width = PCIE_LNK_WIDTH_UNKNOWN;
5498 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
5500 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
5501 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
5502 PCI_EXP_LNKSTA_NLW_SHIFT;
5504 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
5506 /* Check if current device limits the total bandwidth */
5507 if (!bw || next_bw <= bw) {
5511 *limiting_dev = dev;
5513 *speed = next_speed;
5515 *width = next_width;
5518 dev = pci_upstream_bridge(dev);
5523 EXPORT_SYMBOL(pcie_bandwidth_available);
5526 * pcie_get_speed_cap - query for the PCI device's link speed capability
5527 * @dev: PCI device to query
5529 * Query the PCI device speed capability. Return the maximum link speed
5530 * supported by the device.
5532 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
5534 u32 lnkcap2, lnkcap;
5537 * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link
5538 * Speeds Vector in Link Capabilities 2 when supported, falling
5539 * back to Max Link Speed in Link Capabilities otherwise.
5541 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
5542 if (lnkcap2) { /* PCIe r3.0-compliant */
5543 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
5544 return PCIE_SPEED_16_0GT;
5545 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
5546 return PCIE_SPEED_8_0GT;
5547 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
5548 return PCIE_SPEED_5_0GT;
5549 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
5550 return PCIE_SPEED_2_5GT;
5551 return PCI_SPEED_UNKNOWN;
5554 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5556 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
5557 return PCIE_SPEED_16_0GT;
5558 else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
5559 return PCIE_SPEED_8_0GT;
5560 else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
5561 return PCIE_SPEED_5_0GT;
5562 else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
5563 return PCIE_SPEED_2_5GT;
5566 return PCI_SPEED_UNKNOWN;
5568 EXPORT_SYMBOL(pcie_get_speed_cap);
5571 * pcie_get_width_cap - query for the PCI device's link width capability
5572 * @dev: PCI device to query
5574 * Query the PCI device width capability. Return the maximum link width
5575 * supported by the device.
5577 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
5581 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5583 return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
5585 return PCIE_LNK_WIDTH_UNKNOWN;
5587 EXPORT_SYMBOL(pcie_get_width_cap);
5590 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
5592 * @speed: storage for link speed
5593 * @width: storage for link width
5595 * Calculate a PCI device's link bandwidth by querying for its link speed
5596 * and width, multiplying them, and applying encoding overhead. The result
5597 * is in Mb/s, i.e., megabits/second of raw bandwidth.
5599 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
5600 enum pcie_link_width *width)
5602 *speed = pcie_get_speed_cap(dev);
5603 *width = pcie_get_width_cap(dev);
5605 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
5608 return *width * PCIE_SPEED2MBS_ENC(*speed);
5612 * __pcie_print_link_status - Report the PCI device's link speed and width
5613 * @dev: PCI device to query
5614 * @verbose: Print info even when enough bandwidth is available
5616 * If the available bandwidth at the device is less than the device is
5617 * capable of, report the device's maximum possible bandwidth and the
5618 * upstream link that limits its performance. If @verbose, always print
5619 * the available bandwidth, even if the device isn't constrained.
5621 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
5623 enum pcie_link_width width, width_cap;
5624 enum pci_bus_speed speed, speed_cap;
5625 struct pci_dev *limiting_dev = NULL;
5626 u32 bw_avail, bw_cap;
5628 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
5629 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
5631 if (bw_avail >= bw_cap && verbose)
5632 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
5633 bw_cap / 1000, bw_cap % 1000,
5634 PCIE_SPEED2STR(speed_cap), width_cap);
5635 else if (bw_avail < bw_cap)
5636 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
5637 bw_avail / 1000, bw_avail % 1000,
5638 PCIE_SPEED2STR(speed), width,
5639 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
5640 bw_cap / 1000, bw_cap % 1000,
5641 PCIE_SPEED2STR(speed_cap), width_cap);
5645 * pcie_print_link_status - Report the PCI device's link speed and width
5646 * @dev: PCI device to query
5648 * Report the available bandwidth at the device.
5650 void pcie_print_link_status(struct pci_dev *dev)
5652 __pcie_print_link_status(dev, true);
5654 EXPORT_SYMBOL(pcie_print_link_status);
5657 * pci_select_bars - Make BAR mask from the type of resource
5658 * @dev: the PCI device for which BAR mask is made
5659 * @flags: resource type mask to be selected
5661 * This helper routine makes bar mask from the type of resource.
5663 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
5666 for (i = 0; i < PCI_NUM_RESOURCES; i++)
5667 if (pci_resource_flags(dev, i) & flags)
5671 EXPORT_SYMBOL(pci_select_bars);
5673 /* Some architectures require additional programming to enable VGA */
5674 static arch_set_vga_state_t arch_set_vga_state;
5676 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
5678 arch_set_vga_state = func; /* NULL disables */
5681 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
5682 unsigned int command_bits, u32 flags)
5684 if (arch_set_vga_state)
5685 return arch_set_vga_state(dev, decode, command_bits,
5691 * pci_set_vga_state - set VGA decode state on device and parents if requested
5692 * @dev: the PCI device
5693 * @decode: true = enable decoding, false = disable decoding
5694 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
5695 * @flags: traverse ancestors and change bridges
5696 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
5698 int pci_set_vga_state(struct pci_dev *dev, bool decode,
5699 unsigned int command_bits, u32 flags)
5701 struct pci_bus *bus;
5702 struct pci_dev *bridge;
5706 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
5708 /* ARCH specific VGA enables */
5709 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
5713 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
5714 pci_read_config_word(dev, PCI_COMMAND, &cmd);
5716 cmd |= command_bits;
5718 cmd &= ~command_bits;
5719 pci_write_config_word(dev, PCI_COMMAND, cmd);
5722 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
5729 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
5732 cmd |= PCI_BRIDGE_CTL_VGA;
5734 cmd &= ~PCI_BRIDGE_CTL_VGA;
5735 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
5744 * pci_add_dma_alias - Add a DMA devfn alias for a device
5745 * @dev: the PCI device for which alias is added
5746 * @devfn: alias slot and function
5748 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
5749 * which is used to program permissible bus-devfn source addresses for DMA
5750 * requests in an IOMMU. These aliases factor into IOMMU group creation
5751 * and are useful for devices generating DMA requests beyond or different
5752 * from their logical bus-devfn. Examples include device quirks where the
5753 * device simply uses the wrong devfn, as well as non-transparent bridges
5754 * where the alias may be a proxy for devices in another domain.
5756 * IOMMU group creation is performed during device discovery or addition,
5757 * prior to any potential DMA mapping and therefore prior to driver probing
5758 * (especially for userspace assigned devices where IOMMU group definition
5759 * cannot be left as a userspace activity). DMA aliases should therefore
5760 * be configured via quirks, such as the PCI fixup header quirk.
5762 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
5764 if (!dev->dma_alias_mask)
5765 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
5766 sizeof(long), GFP_KERNEL);
5767 if (!dev->dma_alias_mask) {
5768 pci_warn(dev, "Unable to allocate DMA alias mask\n");
5772 set_bit(devfn, dev->dma_alias_mask);
5773 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
5774 PCI_SLOT(devfn), PCI_FUNC(devfn));
5777 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
5779 return (dev1->dma_alias_mask &&
5780 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
5781 (dev2->dma_alias_mask &&
5782 test_bit(dev1->devfn, dev2->dma_alias_mask));
5785 bool pci_device_is_present(struct pci_dev *pdev)
5789 if (pci_dev_is_disconnected(pdev))
5791 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
5793 EXPORT_SYMBOL_GPL(pci_device_is_present);
5795 void pci_ignore_hotplug(struct pci_dev *dev)
5797 struct pci_dev *bridge = dev->bus->self;
5799 dev->ignore_hotplug = 1;
5800 /* Propagate the "ignore hotplug" setting to the parent bridge. */
5802 bridge->ignore_hotplug = 1;
5804 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
5806 resource_size_t __weak pcibios_default_alignment(void)
5811 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
5812 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
5813 static DEFINE_SPINLOCK(resource_alignment_lock);
5816 * pci_specified_resource_alignment - get resource alignment specified by user.
5817 * @dev: the PCI device to get
5818 * @resize: whether or not to change resources' size when reassigning alignment
5820 * RETURNS: Resource alignment if it is specified.
5821 * Zero if it is not specified.
5823 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
5826 int align_order, count;
5827 resource_size_t align = pcibios_default_alignment();
5831 spin_lock(&resource_alignment_lock);
5832 p = resource_alignment_param;
5835 if (pci_has_flag(PCI_PROBE_ONLY)) {
5837 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
5843 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
5850 ret = pci_dev_str_match(dev, p, &p);
5853 if (align_order == -1)
5856 align = 1 << align_order;
5858 } else if (ret < 0) {
5859 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
5864 if (*p != ';' && *p != ',') {
5865 /* End of param or invalid format */
5871 spin_unlock(&resource_alignment_lock);
5875 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
5876 resource_size_t align, bool resize)
5878 struct resource *r = &dev->resource[bar];
5879 resource_size_t size;
5881 if (!(r->flags & IORESOURCE_MEM))
5884 if (r->flags & IORESOURCE_PCI_FIXED) {
5885 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
5886 bar, r, (unsigned long long)align);
5890 size = resource_size(r);
5895 * Increase the alignment of the resource. There are two ways we
5898 * 1) Increase the size of the resource. BARs are aligned on their
5899 * size, so when we reallocate space for this resource, we'll
5900 * allocate it with the larger alignment. This also prevents
5901 * assignment of any other BARs inside the alignment region, so
5902 * if we're requesting page alignment, this means no other BARs
5903 * will share the page.
5905 * The disadvantage is that this makes the resource larger than
5906 * the hardware BAR, which may break drivers that compute things
5907 * based on the resource size, e.g., to find registers at a
5908 * fixed offset before the end of the BAR.
5910 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
5911 * set r->start to the desired alignment. By itself this
5912 * doesn't prevent other BARs being put inside the alignment
5913 * region, but if we realign *every* resource of every device in
5914 * the system, none of them will share an alignment region.
5916 * When the user has requested alignment for only some devices via
5917 * the "pci=resource_alignment" argument, "resize" is true and we
5918 * use the first method. Otherwise we assume we're aligning all
5919 * devices and we use the second.
5922 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
5923 bar, r, (unsigned long long)align);
5929 r->flags &= ~IORESOURCE_SIZEALIGN;
5930 r->flags |= IORESOURCE_STARTALIGN;
5932 r->end = r->start + size - 1;
5934 r->flags |= IORESOURCE_UNSET;
5938 * This function disables memory decoding and releases memory resources
5939 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5940 * It also rounds up size to specified alignment.
5941 * Later on, the kernel will assign page-aligned memory resource back
5944 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
5948 resource_size_t align;
5950 bool resize = false;
5953 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
5954 * 3.4.1.11. Their resources are allocated from the space
5955 * described by the VF BARx register in the PF's SR-IOV capability.
5956 * We can't influence their alignment here.
5961 /* check if specified PCI is target device to reassign */
5962 align = pci_specified_resource_alignment(dev, &resize);
5966 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
5967 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
5968 pci_warn(dev, "Can't reassign resources to host bridge\n");
5972 pci_read_config_word(dev, PCI_COMMAND, &command);
5973 command &= ~PCI_COMMAND_MEMORY;
5974 pci_write_config_word(dev, PCI_COMMAND, command);
5976 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
5977 pci_request_resource_alignment(dev, i, align, resize);
5980 * Need to disable bridge's resource window,
5981 * to enable the kernel to reassign new resource
5984 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
5985 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
5986 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
5987 r = &dev->resource[i];
5988 if (!(r->flags & IORESOURCE_MEM))
5990 r->flags |= IORESOURCE_UNSET;
5991 r->end = resource_size(r) - 1;
5994 pci_disable_bridge_window(dev);
5998 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
6000 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
6001 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
6002 spin_lock(&resource_alignment_lock);
6003 strncpy(resource_alignment_param, buf, count);
6004 resource_alignment_param[count] = '\0';
6005 spin_unlock(&resource_alignment_lock);
6009 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
6012 spin_lock(&resource_alignment_lock);
6013 count = snprintf(buf, size, "%s", resource_alignment_param);
6014 spin_unlock(&resource_alignment_lock);
6018 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
6020 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
6023 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
6024 const char *buf, size_t count)
6026 return pci_set_resource_alignment_param(buf, count);
6029 static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
6030 pci_resource_alignment_store);
6032 static int __init pci_resource_alignment_sysfs_init(void)
6034 return bus_create_file(&pci_bus_type,
6035 &bus_attr_resource_alignment);
6037 late_initcall(pci_resource_alignment_sysfs_init);
6039 static void pci_no_domains(void)
6041 #ifdef CONFIG_PCI_DOMAINS
6042 pci_domains_supported = 0;
6046 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6047 static atomic_t __domain_nr = ATOMIC_INIT(-1);
6049 static int pci_get_new_domain_nr(void)
6051 return atomic_inc_return(&__domain_nr);
6054 static int of_pci_bus_find_domain_nr(struct device *parent)
6056 static int use_dt_domains = -1;
6060 domain = of_get_pci_domain_nr(parent->of_node);
6062 * Check DT domain and use_dt_domains values.
6064 * If DT domain property is valid (domain >= 0) and
6065 * use_dt_domains != 0, the DT assignment is valid since this means
6066 * we have not previously allocated a domain number by using
6067 * pci_get_new_domain_nr(); we should also update use_dt_domains to
6068 * 1, to indicate that we have just assigned a domain number from
6071 * If DT domain property value is not valid (ie domain < 0), and we
6072 * have not previously assigned a domain number from DT
6073 * (use_dt_domains != 1) we should assign a domain number by
6076 * pci_get_new_domain_nr()
6078 * API and update the use_dt_domains value to keep track of method we
6079 * are using to assign domain numbers (use_dt_domains = 0).
6081 * All other combinations imply we have a platform that is trying
6082 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
6083 * which is a recipe for domain mishandling and it is prevented by
6084 * invalidating the domain value (domain = -1) and printing a
6085 * corresponding error.
6087 if (domain >= 0 && use_dt_domains) {
6089 } else if (domain < 0 && use_dt_domains != 1) {
6091 domain = pci_get_new_domain_nr();
6094 pr_err("Node %pOF has ", parent->of_node);
6095 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
6102 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
6104 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
6105 acpi_pci_bus_find_domain_nr(bus);
6110 * pci_ext_cfg_avail - can we access extended PCI config space?
6112 * Returns 1 if we can access PCI extended config space (offsets
6113 * greater than 0xff). This is the default implementation. Architecture
6114 * implementations can override this.
6116 int __weak pci_ext_cfg_avail(void)
6121 void __weak pci_fixup_cardbus(struct pci_bus *bus)
6124 EXPORT_SYMBOL(pci_fixup_cardbus);
6126 static int __init pci_setup(char *str)
6129 char *k = strchr(str, ',');
6132 if (*str && (str = pcibios_setup(str)) && *str) {
6133 if (!strcmp(str, "nomsi")) {
6135 } else if (!strncmp(str, "noats", 5)) {
6136 pr_info("PCIe: ATS is disabled\n");
6137 pcie_ats_disabled = true;
6138 } else if (!strcmp(str, "noaer")) {
6140 } else if (!strcmp(str, "earlydump")) {
6141 pci_early_dump = true;
6142 } else if (!strncmp(str, "realloc=", 8)) {
6143 pci_realloc_get_opt(str + 8);
6144 } else if (!strncmp(str, "realloc", 7)) {
6145 pci_realloc_get_opt("on");
6146 } else if (!strcmp(str, "nodomains")) {
6148 } else if (!strncmp(str, "noari", 5)) {
6149 pcie_ari_disabled = true;
6150 } else if (!strncmp(str, "cbiosize=", 9)) {
6151 pci_cardbus_io_size = memparse(str + 9, &str);
6152 } else if (!strncmp(str, "cbmemsize=", 10)) {
6153 pci_cardbus_mem_size = memparse(str + 10, &str);
6154 } else if (!strncmp(str, "resource_alignment=", 19)) {
6155 pci_set_resource_alignment_param(str + 19,
6157 } else if (!strncmp(str, "ecrc=", 5)) {
6158 pcie_ecrc_get_policy(str + 5);
6159 } else if (!strncmp(str, "hpiosize=", 9)) {
6160 pci_hotplug_io_size = memparse(str + 9, &str);
6161 } else if (!strncmp(str, "hpmemsize=", 10)) {
6162 pci_hotplug_mem_size = memparse(str + 10, &str);
6163 } else if (!strncmp(str, "hpbussize=", 10)) {
6164 pci_hotplug_bus_size =
6165 simple_strtoul(str + 10, &str, 0);
6166 if (pci_hotplug_bus_size > 0xff)
6167 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
6168 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
6169 pcie_bus_config = PCIE_BUS_TUNE_OFF;
6170 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
6171 pcie_bus_config = PCIE_BUS_SAFE;
6172 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
6173 pcie_bus_config = PCIE_BUS_PERFORMANCE;
6174 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
6175 pcie_bus_config = PCIE_BUS_PEER2PEER;
6176 } else if (!strncmp(str, "pcie_scan_all", 13)) {
6177 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
6178 } else if (!strncmp(str, "disable_acs_redir=", 18)) {
6179 disable_acs_redir_param = str + 18;
6181 printk(KERN_ERR "PCI: Unknown option `%s'\n",
6189 early_param("pci", pci_setup);