1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
17 #include <linux/of_pci.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pci-ats.h>
33 #include <asm/setup.h>
35 #include <linux/aer.h>
38 DEFINE_MUTEX(pci_slot_mutex);
40 const char *pci_power_names[] = {
41 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
43 EXPORT_SYMBOL_GPL(pci_power_names);
45 int isa_dma_bridge_buggy;
46 EXPORT_SYMBOL(isa_dma_bridge_buggy);
49 EXPORT_SYMBOL(pci_pci_problems);
51 unsigned int pci_pm_d3_delay;
53 static void pci_pme_list_scan(struct work_struct *work);
55 static LIST_HEAD(pci_pme_list);
56 static DEFINE_MUTEX(pci_pme_list_mutex);
57 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
59 struct pci_pme_device {
60 struct list_head list;
64 #define PME_TIMEOUT 1000 /* How long between PME checks */
66 static void pci_dev_d3_sleep(struct pci_dev *dev)
68 unsigned int delay = dev->d3_delay;
70 if (delay < pci_pm_d3_delay)
71 delay = pci_pm_d3_delay;
77 #ifdef CONFIG_PCI_DOMAINS
78 int pci_domains_supported = 1;
81 #define DEFAULT_CARDBUS_IO_SIZE (256)
82 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
83 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
84 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
85 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
87 #define DEFAULT_HOTPLUG_IO_SIZE (256)
88 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
89 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
90 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
91 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
93 #define DEFAULT_HOTPLUG_BUS_SIZE 1
94 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
96 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
99 * The default CLS is used if arch didn't set CLS explicitly and not
100 * all pci devices agree on the same value. Arch can override either
101 * the dfl or actual value as it sees fit. Don't forget this is
102 * measured in 32-bit words, not bytes.
104 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
105 u8 pci_cache_line_size;
108 * If we set up a device for bus mastering, we need to check the latency
109 * timer as certain BIOSes forget to set it properly.
111 unsigned int pcibios_max_latency = 255;
113 /* If set, the PCIe ARI capability will not be used. */
114 static bool pcie_ari_disabled;
116 /* If set, the PCIe ATS capability will not be used. */
117 static bool pcie_ats_disabled;
119 /* If set, the PCI config space of each device is printed during boot. */
122 bool pci_ats_disabled(void)
124 return pcie_ats_disabled;
127 /* Disable bridge_d3 for all PCIe ports */
128 static bool pci_bridge_d3_disable;
129 /* Force bridge_d3 for all PCIe ports */
130 static bool pci_bridge_d3_force;
132 static int __init pcie_port_pm_setup(char *str)
134 if (!strcmp(str, "off"))
135 pci_bridge_d3_disable = true;
136 else if (!strcmp(str, "force"))
137 pci_bridge_d3_force = true;
140 __setup("pcie_port_pm=", pcie_port_pm_setup);
142 /* Time to wait after a reset for device to become responsive */
143 #define PCIE_RESET_READY_POLL_MS 60000
146 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
147 * @bus: pointer to PCI bus structure to search
149 * Given a PCI bus, returns the highest PCI bus number present in the set
150 * including the given PCI bus and its list of child PCI buses.
152 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
155 unsigned char max, n;
157 max = bus->busn_res.end;
158 list_for_each_entry(tmp, &bus->children, node) {
159 n = pci_bus_max_busnr(tmp);
165 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
167 #ifdef CONFIG_HAS_IOMEM
168 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
170 struct resource *res = &pdev->resource[bar];
173 * Make sure the BAR is actually a memory resource, not an IO resource
175 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
176 pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
179 return ioremap_nocache(res->start, resource_size(res));
181 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
183 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
186 * Make sure the BAR is actually a memory resource, not an IO resource
188 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
192 return ioremap_wc(pci_resource_start(pdev, bar),
193 pci_resource_len(pdev, bar));
195 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
199 * pci_dev_str_match_path - test if a path string matches a device
200 * @dev: the PCI device to test
201 * @path: string to match the device against
202 * @endptr: pointer to the string after the match
204 * Test if a string (typically from a kernel parameter) formatted as a
205 * path of device/function addresses matches a PCI device. The string must
208 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
210 * A path for a device can be obtained using 'lspci -t'. Using a path
211 * is more robust against bus renumbering than using only a single bus,
212 * device and function address.
214 * Returns 1 if the string matches the device, 0 if it does not and
215 * a negative error code if it fails to parse the string.
217 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
221 int seg, bus, slot, func;
225 *endptr = strchrnul(path, ';');
227 wpath = kmemdup_nul(path, *endptr - path, GFP_KERNEL);
232 p = strrchr(wpath, '/');
235 ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
241 if (dev->devfn != PCI_DEVFN(slot, func)) {
247 * Note: we don't need to get a reference to the upstream
248 * bridge because we hold a reference to the top level
249 * device which should hold a reference to the bridge,
252 dev = pci_upstream_bridge(dev);
261 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
265 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
272 ret = (seg == pci_domain_nr(dev->bus) &&
273 bus == dev->bus->number &&
274 dev->devfn == PCI_DEVFN(slot, func));
282 * pci_dev_str_match - test if a string matches a device
283 * @dev: the PCI device to test
284 * @p: string to match the device against
285 * @endptr: pointer to the string after the match
287 * Test if a string (typically from a kernel parameter) matches a specified
288 * PCI device. The string may be of one of the following formats:
290 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
291 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
293 * The first format specifies a PCI bus/device/function address which
294 * may change if new hardware is inserted, if motherboard firmware changes,
295 * or due to changes caused in kernel parameters. If the domain is
296 * left unspecified, it is taken to be 0. In order to be robust against
297 * bus renumbering issues, a path of PCI device/function numbers may be used
298 * to address the specific device. The path for a device can be determined
299 * through the use of 'lspci -t'.
301 * The second format matches devices using IDs in the configuration
302 * space which may match multiple devices in the system. A value of 0
303 * for any field will match all devices. (Note: this differs from
304 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
305 * legacy reasons and convenience so users don't have to specify
306 * FFFFFFFFs on the command line.)
308 * Returns 1 if the string matches the device, 0 if it does not and
309 * a negative error code if the string cannot be parsed.
311 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
316 unsigned short vendor, device, subsystem_vendor, subsystem_device;
318 if (strncmp(p, "pci:", 4) == 0) {
319 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
321 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
322 &subsystem_vendor, &subsystem_device, &count);
324 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
328 subsystem_vendor = 0;
329 subsystem_device = 0;
334 if ((!vendor || vendor == dev->vendor) &&
335 (!device || device == dev->device) &&
336 (!subsystem_vendor ||
337 subsystem_vendor == dev->subsystem_vendor) &&
338 (!subsystem_device ||
339 subsystem_device == dev->subsystem_device))
343 * PCI Bus, Device, Function IDs are specified
344 * (optionally, may include a path of devfns following it)
346 ret = pci_dev_str_match_path(dev, p, &p);
361 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
362 u8 pos, int cap, int *ttl)
367 pci_bus_read_config_byte(bus, devfn, pos, &pos);
373 pci_bus_read_config_word(bus, devfn, pos, &ent);
385 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
388 int ttl = PCI_FIND_CAP_TTL;
390 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
393 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
395 return __pci_find_next_cap(dev->bus, dev->devfn,
396 pos + PCI_CAP_LIST_NEXT, cap);
398 EXPORT_SYMBOL_GPL(pci_find_next_capability);
400 static int __pci_bus_find_cap_start(struct pci_bus *bus,
401 unsigned int devfn, u8 hdr_type)
405 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
406 if (!(status & PCI_STATUS_CAP_LIST))
410 case PCI_HEADER_TYPE_NORMAL:
411 case PCI_HEADER_TYPE_BRIDGE:
412 return PCI_CAPABILITY_LIST;
413 case PCI_HEADER_TYPE_CARDBUS:
414 return PCI_CB_CAPABILITY_LIST;
421 * pci_find_capability - query for devices' capabilities
422 * @dev: PCI device to query
423 * @cap: capability code
425 * Tell if a device supports a given PCI capability.
426 * Returns the address of the requested capability structure within the
427 * device's PCI configuration space or 0 in case the device does not
428 * support it. Possible values for @cap include:
430 * %PCI_CAP_ID_PM Power Management
431 * %PCI_CAP_ID_AGP Accelerated Graphics Port
432 * %PCI_CAP_ID_VPD Vital Product Data
433 * %PCI_CAP_ID_SLOTID Slot Identification
434 * %PCI_CAP_ID_MSI Message Signalled Interrupts
435 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
436 * %PCI_CAP_ID_PCIX PCI-X
437 * %PCI_CAP_ID_EXP PCI Express
439 int pci_find_capability(struct pci_dev *dev, int cap)
443 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
445 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
449 EXPORT_SYMBOL(pci_find_capability);
452 * pci_bus_find_capability - query for devices' capabilities
453 * @bus: the PCI bus to query
454 * @devfn: PCI device to query
455 * @cap: capability code
457 * Like pci_find_capability() but works for PCI devices that do not have a
458 * pci_dev structure set up yet.
460 * Returns the address of the requested capability structure within the
461 * device's PCI configuration space or 0 in case the device does not
464 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
469 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
471 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
473 pos = __pci_find_next_cap(bus, devfn, pos, cap);
477 EXPORT_SYMBOL(pci_bus_find_capability);
480 * pci_find_next_ext_capability - Find an extended capability
481 * @dev: PCI device to query
482 * @start: address at which to start looking (0 to start at beginning of list)
483 * @cap: capability code
485 * Returns the address of the next matching extended capability structure
486 * within the device's PCI configuration space or 0 if the device does
487 * not support it. Some capabilities can occur several times, e.g., the
488 * vendor-specific capability, and this provides a way to find them all.
490 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
494 int pos = PCI_CFG_SPACE_SIZE;
496 /* minimum 8 bytes per capability */
497 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
499 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
505 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
509 * If we have no capabilities, this is indicated by cap ID,
510 * cap version and next pointer all being 0.
516 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
519 pos = PCI_EXT_CAP_NEXT(header);
520 if (pos < PCI_CFG_SPACE_SIZE)
523 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
529 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
532 * pci_find_ext_capability - Find an extended capability
533 * @dev: PCI device to query
534 * @cap: capability code
536 * Returns the address of the requested extended capability structure
537 * within the device's PCI configuration space or 0 if the device does
538 * not support it. Possible values for @cap include:
540 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
541 * %PCI_EXT_CAP_ID_VC Virtual Channel
542 * %PCI_EXT_CAP_ID_DSN Device Serial Number
543 * %PCI_EXT_CAP_ID_PWR Power Budgeting
545 int pci_find_ext_capability(struct pci_dev *dev, int cap)
547 return pci_find_next_ext_capability(dev, 0, cap);
549 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
551 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
553 int rc, ttl = PCI_FIND_CAP_TTL;
556 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
557 mask = HT_3BIT_CAP_MASK;
559 mask = HT_5BIT_CAP_MASK;
561 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
562 PCI_CAP_ID_HT, &ttl);
564 rc = pci_read_config_byte(dev, pos + 3, &cap);
565 if (rc != PCIBIOS_SUCCESSFUL)
568 if ((cap & mask) == ht_cap)
571 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
572 pos + PCI_CAP_LIST_NEXT,
573 PCI_CAP_ID_HT, &ttl);
579 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
580 * @dev: PCI device to query
581 * @pos: Position from which to continue searching
582 * @ht_cap: Hypertransport capability code
584 * To be used in conjunction with pci_find_ht_capability() to search for
585 * all capabilities matching @ht_cap. @pos should always be a value returned
586 * from pci_find_ht_capability().
588 * NB. To be 100% safe against broken PCI devices, the caller should take
589 * steps to avoid an infinite loop.
591 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
593 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
595 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
598 * pci_find_ht_capability - query a device's Hypertransport capabilities
599 * @dev: PCI device to query
600 * @ht_cap: Hypertransport capability code
602 * Tell if a device supports a given Hypertransport capability.
603 * Returns an address within the device's PCI configuration space
604 * or 0 in case the device does not support the request capability.
605 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
606 * which has a Hypertransport capability matching @ht_cap.
608 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
612 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
614 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
618 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
621 * pci_find_parent_resource - return resource region of parent bus of given
623 * @dev: PCI device structure contains resources to be searched
624 * @res: child resource record for which parent is sought
626 * For given resource region of given device, return the resource region of
627 * parent bus the given region is contained in.
629 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
630 struct resource *res)
632 const struct pci_bus *bus = dev->bus;
636 pci_bus_for_each_resource(bus, r, i) {
639 if (resource_contains(r, res)) {
642 * If the window is prefetchable but the BAR is
643 * not, the allocator made a mistake.
645 if (r->flags & IORESOURCE_PREFETCH &&
646 !(res->flags & IORESOURCE_PREFETCH))
650 * If we're below a transparent bridge, there may
651 * be both a positively-decoded aperture and a
652 * subtractively-decoded region that contain the BAR.
653 * We want the positively-decoded one, so this depends
654 * on pci_bus_for_each_resource() giving us those
662 EXPORT_SYMBOL(pci_find_parent_resource);
665 * pci_find_resource - Return matching PCI device resource
666 * @dev: PCI device to query
667 * @res: Resource to look for
669 * Goes over standard PCI resources (BARs) and checks if the given resource
670 * is partially or fully contained in any of them. In that case the
671 * matching resource is returned, %NULL otherwise.
673 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
677 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
678 struct resource *r = &dev->resource[i];
680 if (r->start && resource_contains(r, res))
686 EXPORT_SYMBOL(pci_find_resource);
689 * pci_find_pcie_root_port - return PCIe Root Port
690 * @dev: PCI device to query
692 * Traverse up the parent chain and return the PCIe Root Port PCI Device
693 * for a given PCI Device.
695 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
697 struct pci_dev *bridge, *highest_pcie_bridge = dev;
699 bridge = pci_upstream_bridge(dev);
700 while (bridge && pci_is_pcie(bridge)) {
701 highest_pcie_bridge = bridge;
702 bridge = pci_upstream_bridge(bridge);
705 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
708 return highest_pcie_bridge;
710 EXPORT_SYMBOL(pci_find_pcie_root_port);
713 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
714 * @dev: the PCI device to operate on
715 * @pos: config space offset of status word
716 * @mask: mask of bit(s) to care about in status word
718 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
720 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
724 /* Wait for Transaction Pending bit clean */
725 for (i = 0; i < 4; i++) {
728 msleep((1 << (i - 1)) * 100);
730 pci_read_config_word(dev, pos, &status);
731 if (!(status & mask))
739 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
740 * @dev: PCI device to have its BARs restored
742 * Restore the BAR values for a given device, so as to make it
743 * accessible by its driver.
745 static void pci_restore_bars(struct pci_dev *dev)
749 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
750 pci_update_resource(dev, i);
753 static const struct pci_platform_pm_ops *pci_platform_pm;
755 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
757 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
758 !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
760 pci_platform_pm = ops;
764 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
766 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
769 static inline int platform_pci_set_power_state(struct pci_dev *dev,
772 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
775 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
777 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
780 static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
782 if (pci_platform_pm && pci_platform_pm->refresh_state)
783 pci_platform_pm->refresh_state(dev);
786 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
788 return pci_platform_pm ?
789 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
792 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
794 return pci_platform_pm ?
795 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
798 static inline bool platform_pci_need_resume(struct pci_dev *dev)
800 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
803 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
805 return pci_platform_pm ? pci_platform_pm->bridge_d3(dev) : false;
809 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
811 * @dev: PCI device to handle.
812 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
815 * -EINVAL if the requested state is invalid.
816 * -EIO if device does not support PCI PM or its PM capabilities register has a
817 * wrong version, or device doesn't support the requested state.
818 * 0 if device already is in the requested state.
819 * 0 if device's power state has been successfully changed.
821 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
824 bool need_restore = false;
826 /* Check if we're already there */
827 if (dev->current_state == state)
833 if (state < PCI_D0 || state > PCI_D3hot)
837 * Validate current state:
838 * Can enter D0 from any state, but if we can only go deeper
839 * to sleep if we're already in a low power state
841 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
842 && dev->current_state > state) {
843 pci_err(dev, "invalid power transition (from state %d to %d)\n",
844 dev->current_state, state);
848 /* Check if this device supports the desired state */
849 if ((state == PCI_D1 && !dev->d1_support)
850 || (state == PCI_D2 && !dev->d2_support))
853 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
856 * If we're (effectively) in D3, force entire word to 0.
857 * This doesn't affect PME_Status, disables PME_En, and
858 * sets PowerState to 0.
860 switch (dev->current_state) {
864 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
869 case PCI_UNKNOWN: /* Boot-up */
870 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
871 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
873 /* Fall-through - force to D0 */
879 /* Enter specified state */
880 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
883 * Mandatory power management transition delays; see PCI PM 1.1
886 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
887 pci_dev_d3_sleep(dev);
888 else if (state == PCI_D2 || dev->current_state == PCI_D2)
889 udelay(PCI_PM_D2_DELAY);
891 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
892 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
893 if (dev->current_state != state)
894 pci_info_ratelimited(dev, "Refused to change power state, currently in D%d\n",
898 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
899 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
900 * from D3hot to D0 _may_ perform an internal reset, thereby
901 * going to "D0 Uninitialized" rather than "D0 Initialized".
902 * For example, at least some versions of the 3c905B and the
903 * 3c556B exhibit this behaviour.
905 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
906 * devices in a D3hot state at boot. Consequently, we need to
907 * restore at least the BARs so that the device will be
908 * accessible to its driver.
911 pci_restore_bars(dev);
914 pcie_aspm_pm_state_change(dev->bus->self);
920 * pci_update_current_state - Read power state of given device and cache it
921 * @dev: PCI device to handle.
922 * @state: State to cache in case the device doesn't have the PM capability
924 * The power state is read from the PMCSR register, which however is
925 * inaccessible in D3cold. The platform firmware is therefore queried first
926 * to detect accessibility of the register. In case the platform firmware
927 * reports an incorrect state or the device isn't power manageable by the
928 * platform at all, we try to detect D3cold by testing accessibility of the
929 * vendor ID in config space.
931 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
933 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
934 !pci_device_is_present(dev)) {
935 dev->current_state = PCI_D3cold;
936 } else if (dev->pm_cap) {
939 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
940 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
942 dev->current_state = state;
947 * pci_refresh_power_state - Refresh the given device's power state data
948 * @dev: Target PCI device.
950 * Ask the platform to refresh the devices power state information and invoke
951 * pci_update_current_state() to update its current PCI power state.
953 void pci_refresh_power_state(struct pci_dev *dev)
955 if (platform_pci_power_manageable(dev))
956 platform_pci_refresh_power_state(dev);
958 pci_update_current_state(dev, dev->current_state);
962 * pci_power_up - Put the given device into D0 forcibly
963 * @dev: PCI device to power up
965 void pci_power_up(struct pci_dev *dev)
967 if (platform_pci_power_manageable(dev))
968 platform_pci_set_power_state(dev, PCI_D0);
970 pci_raw_set_power_state(dev, PCI_D0);
971 pci_update_current_state(dev, PCI_D0);
975 * pci_platform_power_transition - Use platform to change device power state
976 * @dev: PCI device to handle.
977 * @state: State to put the device into.
979 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
983 if (platform_pci_power_manageable(dev)) {
984 error = platform_pci_set_power_state(dev, state);
986 pci_update_current_state(dev, state);
990 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
991 dev->current_state = PCI_D0;
997 * pci_wakeup - Wake up a PCI device
998 * @pci_dev: Device to handle.
999 * @ign: ignored parameter
1001 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
1003 pci_wakeup_event(pci_dev);
1004 pm_request_resume(&pci_dev->dev);
1009 * pci_wakeup_bus - Walk given bus and wake up devices on it
1010 * @bus: Top bus of the subtree to walk.
1012 void pci_wakeup_bus(struct pci_bus *bus)
1015 pci_walk_bus(bus, pci_wakeup, NULL);
1019 * __pci_start_power_transition - Start power transition of a PCI device
1020 * @dev: PCI device to handle.
1021 * @state: State to put the device into.
1023 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
1025 if (state == PCI_D0) {
1026 pci_platform_power_transition(dev, PCI_D0);
1028 * Mandatory power management transition delays, see
1029 * PCI Express Base Specification Revision 2.0 Section
1030 * 6.6.1: Conventional Reset. Do not delay for
1031 * devices powered on/off by corresponding bridge,
1032 * because have already delayed for the bridge.
1034 if (dev->runtime_d3cold) {
1035 if (dev->d3cold_delay && !dev->imm_ready)
1036 msleep(dev->d3cold_delay);
1038 * When powering on a bridge from D3cold, the
1039 * whole hierarchy may be powered on into
1040 * D0uninitialized state, resume them to give
1041 * them a chance to suspend again
1043 pci_wakeup_bus(dev->subordinate);
1049 * __pci_dev_set_current_state - Set current state of a PCI device
1050 * @dev: Device to handle
1051 * @data: pointer to state to be set
1053 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1055 pci_power_t state = *(pci_power_t *)data;
1057 dev->current_state = state;
1062 * pci_bus_set_current_state - Walk given bus and set current state of devices
1063 * @bus: Top bus of the subtree to walk.
1064 * @state: state to be set
1066 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1069 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1073 * __pci_complete_power_transition - Complete power transition of a PCI device
1074 * @dev: PCI device to handle.
1075 * @state: State to put the device into.
1077 * This function should not be called directly by device drivers.
1079 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
1083 if (state <= PCI_D0)
1085 ret = pci_platform_power_transition(dev, state);
1086 /* Power off the bridge may power off the whole hierarchy */
1087 if (!ret && state == PCI_D3cold)
1088 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1091 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
1094 * pci_set_power_state - Set the power state of a PCI device
1095 * @dev: PCI device to handle.
1096 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1098 * Transition a device to a new power state, using the platform firmware and/or
1099 * the device's PCI PM registers.
1102 * -EINVAL if the requested state is invalid.
1103 * -EIO if device does not support PCI PM or its PM capabilities register has a
1104 * wrong version, or device doesn't support the requested state.
1105 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1106 * 0 if device already is in the requested state.
1107 * 0 if the transition is to D3 but D3 is not supported.
1108 * 0 if device's power state has been successfully changed.
1110 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1114 /* Bound the state we're entering */
1115 if (state > PCI_D3cold)
1117 else if (state < PCI_D0)
1119 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1122 * If the device or the parent bridge do not support PCI
1123 * PM, ignore the request if we're doing anything other
1124 * than putting it into D0 (which would only happen on
1129 /* Check if we're already there */
1130 if (dev->current_state == state)
1133 __pci_start_power_transition(dev, state);
1136 * This device is quirked not to be put into D3, so don't put it in
1139 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1143 * To put device in D3cold, we put device into D3hot in native
1144 * way, then put device into D3cold with platform ops
1146 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
1149 if (!__pci_complete_power_transition(dev, state))
1154 EXPORT_SYMBOL(pci_set_power_state);
1157 * pci_choose_state - Choose the power state of a PCI device
1158 * @dev: PCI device to be suspended
1159 * @state: target sleep state for the whole system. This is the value
1160 * that is passed to suspend() function.
1162 * Returns PCI power state suitable for given device and given system
1165 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
1172 ret = platform_pci_choose_state(dev);
1173 if (ret != PCI_POWER_ERROR)
1176 switch (state.event) {
1179 case PM_EVENT_FREEZE:
1180 case PM_EVENT_PRETHAW:
1181 /* REVISIT both freeze and pre-thaw "should" use D0 */
1182 case PM_EVENT_SUSPEND:
1183 case PM_EVENT_HIBERNATE:
1186 pci_info(dev, "unrecognized suspend event %d\n",
1192 EXPORT_SYMBOL(pci_choose_state);
1194 #define PCI_EXP_SAVE_REGS 7
1196 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1197 u16 cap, bool extended)
1199 struct pci_cap_saved_state *tmp;
1201 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1202 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1208 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1210 return _pci_find_saved_cap(dev, cap, false);
1213 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1215 return _pci_find_saved_cap(dev, cap, true);
1218 static int pci_save_pcie_state(struct pci_dev *dev)
1221 struct pci_cap_saved_state *save_state;
1224 if (!pci_is_pcie(dev))
1227 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1229 pci_err(dev, "buffer not found in %s\n", __func__);
1233 cap = (u16 *)&save_state->cap.data[0];
1234 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1235 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1236 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1237 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1238 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1239 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1240 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1245 static void pci_restore_pcie_state(struct pci_dev *dev)
1248 struct pci_cap_saved_state *save_state;
1251 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1255 cap = (u16 *)&save_state->cap.data[0];
1256 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1257 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1258 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1259 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1260 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1261 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1262 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1265 static int pci_save_pcix_state(struct pci_dev *dev)
1268 struct pci_cap_saved_state *save_state;
1270 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1274 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1276 pci_err(dev, "buffer not found in %s\n", __func__);
1280 pci_read_config_word(dev, pos + PCI_X_CMD,
1281 (u16 *)save_state->cap.data);
1286 static void pci_restore_pcix_state(struct pci_dev *dev)
1289 struct pci_cap_saved_state *save_state;
1292 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1293 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1294 if (!save_state || !pos)
1296 cap = (u16 *)&save_state->cap.data[0];
1298 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1301 static void pci_save_ltr_state(struct pci_dev *dev)
1304 struct pci_cap_saved_state *save_state;
1307 if (!pci_is_pcie(dev))
1310 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1314 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1316 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1320 cap = (u16 *)&save_state->cap.data[0];
1321 pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++);
1322 pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++);
1325 static void pci_restore_ltr_state(struct pci_dev *dev)
1327 struct pci_cap_saved_state *save_state;
1331 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1332 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1333 if (!save_state || !ltr)
1336 cap = (u16 *)&save_state->cap.data[0];
1337 pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++);
1338 pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++);
1342 * pci_save_state - save the PCI configuration space of a device before
1344 * @dev: PCI device that we're dealing with
1346 int pci_save_state(struct pci_dev *dev)
1349 /* XXX: 100% dword access ok here? */
1350 for (i = 0; i < 16; i++)
1351 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1352 dev->state_saved = true;
1354 i = pci_save_pcie_state(dev);
1358 i = pci_save_pcix_state(dev);
1362 pci_save_ltr_state(dev);
1363 pci_save_dpc_state(dev);
1364 return pci_save_vc_state(dev);
1366 EXPORT_SYMBOL(pci_save_state);
1368 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1369 u32 saved_val, int retry, bool force)
1373 pci_read_config_dword(pdev, offset, &val);
1374 if (!force && val == saved_val)
1378 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1379 offset, val, saved_val);
1380 pci_write_config_dword(pdev, offset, saved_val);
1384 pci_read_config_dword(pdev, offset, &val);
1385 if (val == saved_val)
1392 static void pci_restore_config_space_range(struct pci_dev *pdev,
1393 int start, int end, int retry,
1398 for (index = end; index >= start; index--)
1399 pci_restore_config_dword(pdev, 4 * index,
1400 pdev->saved_config_space[index],
1404 static void pci_restore_config_space(struct pci_dev *pdev)
1406 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1407 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1408 /* Restore BARs before the command register. */
1409 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1410 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1411 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1412 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1415 * Force rewriting of prefetch registers to avoid S3 resume
1416 * issues on Intel PCI bridges that occur when these
1417 * registers are not explicitly written.
1419 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1420 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1422 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1426 static void pci_restore_rebar_state(struct pci_dev *pdev)
1428 unsigned int pos, nbars, i;
1431 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1435 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1436 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
1437 PCI_REBAR_CTRL_NBAR_SHIFT;
1439 for (i = 0; i < nbars; i++, pos += 8) {
1440 struct resource *res;
1443 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1444 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1445 res = pdev->resource + bar_idx;
1446 size = ilog2(resource_size(res)) - 20;
1447 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1448 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
1449 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1454 * pci_restore_state - Restore the saved state of a PCI device
1455 * @dev: PCI device that we're dealing with
1457 void pci_restore_state(struct pci_dev *dev)
1459 if (!dev->state_saved)
1463 * Restore max latencies (in the LTR capability) before enabling
1464 * LTR itself (in the PCIe capability).
1466 pci_restore_ltr_state(dev);
1468 pci_restore_pcie_state(dev);
1469 pci_restore_pasid_state(dev);
1470 pci_restore_pri_state(dev);
1471 pci_restore_ats_state(dev);
1472 pci_restore_vc_state(dev);
1473 pci_restore_rebar_state(dev);
1474 pci_restore_dpc_state(dev);
1476 pci_cleanup_aer_error_status_regs(dev);
1478 pci_restore_config_space(dev);
1480 pci_restore_pcix_state(dev);
1481 pci_restore_msi_state(dev);
1483 /* Restore ACS and IOV configuration state */
1484 pci_enable_acs(dev);
1485 pci_restore_iov_state(dev);
1487 dev->state_saved = false;
1489 EXPORT_SYMBOL(pci_restore_state);
1491 struct pci_saved_state {
1492 u32 config_space[16];
1493 struct pci_cap_saved_data cap[0];
1497 * pci_store_saved_state - Allocate and return an opaque struct containing
1498 * the device saved state.
1499 * @dev: PCI device that we're dealing with
1501 * Return NULL if no state or error.
1503 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1505 struct pci_saved_state *state;
1506 struct pci_cap_saved_state *tmp;
1507 struct pci_cap_saved_data *cap;
1510 if (!dev->state_saved)
1513 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1515 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1516 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1518 state = kzalloc(size, GFP_KERNEL);
1522 memcpy(state->config_space, dev->saved_config_space,
1523 sizeof(state->config_space));
1526 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1527 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1528 memcpy(cap, &tmp->cap, len);
1529 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1531 /* Empty cap_save terminates list */
1535 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1538 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1539 * @dev: PCI device that we're dealing with
1540 * @state: Saved state returned from pci_store_saved_state()
1542 int pci_load_saved_state(struct pci_dev *dev,
1543 struct pci_saved_state *state)
1545 struct pci_cap_saved_data *cap;
1547 dev->state_saved = false;
1552 memcpy(dev->saved_config_space, state->config_space,
1553 sizeof(state->config_space));
1557 struct pci_cap_saved_state *tmp;
1559 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1560 if (!tmp || tmp->cap.size != cap->size)
1563 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1564 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1565 sizeof(struct pci_cap_saved_data) + cap->size);
1568 dev->state_saved = true;
1571 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1574 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1575 * and free the memory allocated for it.
1576 * @dev: PCI device that we're dealing with
1577 * @state: Pointer to saved state returned from pci_store_saved_state()
1579 int pci_load_and_free_saved_state(struct pci_dev *dev,
1580 struct pci_saved_state **state)
1582 int ret = pci_load_saved_state(dev, *state);
1587 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1589 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1591 return pci_enable_resources(dev, bars);
1594 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1597 struct pci_dev *bridge;
1601 err = pci_set_power_state(dev, PCI_D0);
1602 if (err < 0 && err != -EIO)
1605 bridge = pci_upstream_bridge(dev);
1607 pcie_aspm_powersave_config_link(bridge);
1609 err = pcibios_enable_device(dev, bars);
1612 pci_fixup_device(pci_fixup_enable, dev);
1614 if (dev->msi_enabled || dev->msix_enabled)
1617 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1619 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1620 if (cmd & PCI_COMMAND_INTX_DISABLE)
1621 pci_write_config_word(dev, PCI_COMMAND,
1622 cmd & ~PCI_COMMAND_INTX_DISABLE);
1629 * pci_reenable_device - Resume abandoned device
1630 * @dev: PCI device to be resumed
1632 * NOTE: This function is a backend of pci_default_resume() and is not supposed
1633 * to be called by normal code, write proper resume handler and use it instead.
1635 int pci_reenable_device(struct pci_dev *dev)
1637 if (pci_is_enabled(dev))
1638 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1641 EXPORT_SYMBOL(pci_reenable_device);
1643 static void pci_enable_bridge(struct pci_dev *dev)
1645 struct pci_dev *bridge;
1648 bridge = pci_upstream_bridge(dev);
1650 pci_enable_bridge(bridge);
1652 if (pci_is_enabled(dev)) {
1653 if (!dev->is_busmaster)
1654 pci_set_master(dev);
1658 retval = pci_enable_device(dev);
1660 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1662 pci_set_master(dev);
1665 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1667 struct pci_dev *bridge;
1672 * Power state could be unknown at this point, either due to a fresh
1673 * boot or a device removal call. So get the current power state
1674 * so that things like MSI message writing will behave as expected
1675 * (e.g. if the device really is in D0 at enable time).
1679 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1680 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1683 if (atomic_inc_return(&dev->enable_cnt) > 1)
1684 return 0; /* already enabled */
1686 bridge = pci_upstream_bridge(dev);
1688 pci_enable_bridge(bridge);
1690 /* only skip sriov related */
1691 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1692 if (dev->resource[i].flags & flags)
1694 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1695 if (dev->resource[i].flags & flags)
1698 err = do_pci_enable_device(dev, bars);
1700 atomic_dec(&dev->enable_cnt);
1705 * pci_enable_device_io - Initialize a device for use with IO space
1706 * @dev: PCI device to be initialized
1708 * Initialize device before it's used by a driver. Ask low-level code
1709 * to enable I/O resources. Wake up the device if it was suspended.
1710 * Beware, this function can fail.
1712 int pci_enable_device_io(struct pci_dev *dev)
1714 return pci_enable_device_flags(dev, IORESOURCE_IO);
1716 EXPORT_SYMBOL(pci_enable_device_io);
1719 * pci_enable_device_mem - Initialize a device for use with Memory space
1720 * @dev: PCI device to be initialized
1722 * Initialize device before it's used by a driver. Ask low-level code
1723 * to enable Memory resources. Wake up the device if it was suspended.
1724 * Beware, this function can fail.
1726 int pci_enable_device_mem(struct pci_dev *dev)
1728 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1730 EXPORT_SYMBOL(pci_enable_device_mem);
1733 * pci_enable_device - Initialize device before it's used by a driver.
1734 * @dev: PCI device to be initialized
1736 * Initialize device before it's used by a driver. Ask low-level code
1737 * to enable I/O and memory. Wake up the device if it was suspended.
1738 * Beware, this function can fail.
1740 * Note we don't actually enable the device many times if we call
1741 * this function repeatedly (we just increment the count).
1743 int pci_enable_device(struct pci_dev *dev)
1745 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1747 EXPORT_SYMBOL(pci_enable_device);
1750 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
1751 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
1752 * there's no need to track it separately. pci_devres is initialized
1753 * when a device is enabled using managed PCI device enable interface.
1756 unsigned int enabled:1;
1757 unsigned int pinned:1;
1758 unsigned int orig_intx:1;
1759 unsigned int restore_intx:1;
1764 static void pcim_release(struct device *gendev, void *res)
1766 struct pci_dev *dev = to_pci_dev(gendev);
1767 struct pci_devres *this = res;
1770 if (dev->msi_enabled)
1771 pci_disable_msi(dev);
1772 if (dev->msix_enabled)
1773 pci_disable_msix(dev);
1775 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1776 if (this->region_mask & (1 << i))
1777 pci_release_region(dev, i);
1782 if (this->restore_intx)
1783 pci_intx(dev, this->orig_intx);
1785 if (this->enabled && !this->pinned)
1786 pci_disable_device(dev);
1789 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1791 struct pci_devres *dr, *new_dr;
1793 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1797 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1800 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1803 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1805 if (pci_is_managed(pdev))
1806 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1811 * pcim_enable_device - Managed pci_enable_device()
1812 * @pdev: PCI device to be initialized
1814 * Managed pci_enable_device().
1816 int pcim_enable_device(struct pci_dev *pdev)
1818 struct pci_devres *dr;
1821 dr = get_pci_dr(pdev);
1827 rc = pci_enable_device(pdev);
1829 pdev->is_managed = 1;
1834 EXPORT_SYMBOL(pcim_enable_device);
1837 * pcim_pin_device - Pin managed PCI device
1838 * @pdev: PCI device to pin
1840 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1841 * driver detach. @pdev must have been enabled with
1842 * pcim_enable_device().
1844 void pcim_pin_device(struct pci_dev *pdev)
1846 struct pci_devres *dr;
1848 dr = find_pci_dr(pdev);
1849 WARN_ON(!dr || !dr->enabled);
1853 EXPORT_SYMBOL(pcim_pin_device);
1856 * pcibios_add_device - provide arch specific hooks when adding device dev
1857 * @dev: the PCI device being added
1859 * Permits the platform to provide architecture specific functionality when
1860 * devices are added. This is the default implementation. Architecture
1861 * implementations can override this.
1863 int __weak pcibios_add_device(struct pci_dev *dev)
1869 * pcibios_release_device - provide arch specific hooks when releasing
1871 * @dev: the PCI device being released
1873 * Permits the platform to provide architecture specific functionality when
1874 * devices are released. This is the default implementation. Architecture
1875 * implementations can override this.
1877 void __weak pcibios_release_device(struct pci_dev *dev) {}
1880 * pcibios_disable_device - disable arch specific PCI resources for device dev
1881 * @dev: the PCI device to disable
1883 * Disables architecture specific PCI resources for the device. This
1884 * is the default implementation. Architecture implementations can
1887 void __weak pcibios_disable_device(struct pci_dev *dev) {}
1890 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1891 * @irq: ISA IRQ to penalize
1892 * @active: IRQ active or not
1894 * Permits the platform to provide architecture-specific functionality when
1895 * penalizing ISA IRQs. This is the default implementation. Architecture
1896 * implementations can override this.
1898 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1900 static void do_pci_disable_device(struct pci_dev *dev)
1904 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1905 if (pci_command & PCI_COMMAND_MASTER) {
1906 pci_command &= ~PCI_COMMAND_MASTER;
1907 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1910 pcibios_disable_device(dev);
1914 * pci_disable_enabled_device - Disable device without updating enable_cnt
1915 * @dev: PCI device to disable
1917 * NOTE: This function is a backend of PCI power management routines and is
1918 * not supposed to be called drivers.
1920 void pci_disable_enabled_device(struct pci_dev *dev)
1922 if (pci_is_enabled(dev))
1923 do_pci_disable_device(dev);
1927 * pci_disable_device - Disable PCI device after use
1928 * @dev: PCI device to be disabled
1930 * Signal to the system that the PCI device is not in use by the system
1931 * anymore. This only involves disabling PCI bus-mastering, if active.
1933 * Note we don't actually disable the device until all callers of
1934 * pci_enable_device() have called pci_disable_device().
1936 void pci_disable_device(struct pci_dev *dev)
1938 struct pci_devres *dr;
1940 dr = find_pci_dr(dev);
1944 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1945 "disabling already-disabled device");
1947 if (atomic_dec_return(&dev->enable_cnt) != 0)
1950 do_pci_disable_device(dev);
1952 dev->is_busmaster = 0;
1954 EXPORT_SYMBOL(pci_disable_device);
1957 * pcibios_set_pcie_reset_state - set reset state for device dev
1958 * @dev: the PCIe device reset
1959 * @state: Reset state to enter into
1961 * Set the PCIe reset state for the device. This is the default
1962 * implementation. Architecture implementations can override this.
1964 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1965 enum pcie_reset_state state)
1971 * pci_set_pcie_reset_state - set reset state for device dev
1972 * @dev: the PCIe device reset
1973 * @state: Reset state to enter into
1975 * Sets the PCI reset state for the device.
1977 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1979 return pcibios_set_pcie_reset_state(dev, state);
1981 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1984 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
1985 * @dev: PCIe root port or event collector.
1987 void pcie_clear_root_pme_status(struct pci_dev *dev)
1989 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
1993 * pci_check_pme_status - Check if given device has generated PME.
1994 * @dev: Device to check.
1996 * Check the PME status of the device and if set, clear it and clear PME enable
1997 * (if set). Return 'true' if PME status and PME enable were both set or
1998 * 'false' otherwise.
2000 bool pci_check_pme_status(struct pci_dev *dev)
2009 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2010 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2011 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2014 /* Clear PME status. */
2015 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2016 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2017 /* Disable PME to avoid interrupt flood. */
2018 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2022 pci_write_config_word(dev, pmcsr_pos, pmcsr);
2028 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2029 * @dev: Device to handle.
2030 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2032 * Check if @dev has generated PME and queue a resume request for it in that
2035 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2037 if (pme_poll_reset && dev->pme_poll)
2038 dev->pme_poll = false;
2040 if (pci_check_pme_status(dev)) {
2041 pci_wakeup_event(dev);
2042 pm_request_resume(&dev->dev);
2048 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2049 * @bus: Top bus of the subtree to walk.
2051 void pci_pme_wakeup_bus(struct pci_bus *bus)
2054 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2059 * pci_pme_capable - check the capability of PCI device to generate PME#
2060 * @dev: PCI device to handle.
2061 * @state: PCI state from which device will issue PME#.
2063 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2068 return !!(dev->pme_support & (1 << state));
2070 EXPORT_SYMBOL(pci_pme_capable);
2072 static void pci_pme_list_scan(struct work_struct *work)
2074 struct pci_pme_device *pme_dev, *n;
2076 mutex_lock(&pci_pme_list_mutex);
2077 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
2078 if (pme_dev->dev->pme_poll) {
2079 struct pci_dev *bridge;
2081 bridge = pme_dev->dev->bus->self;
2083 * If bridge is in low power state, the
2084 * configuration space of subordinate devices
2085 * may be not accessible
2087 if (bridge && bridge->current_state != PCI_D0)
2090 * If the device is in D3cold it should not be
2093 if (pme_dev->dev->current_state == PCI_D3cold)
2096 pci_pme_wakeup(pme_dev->dev, NULL);
2098 list_del(&pme_dev->list);
2102 if (!list_empty(&pci_pme_list))
2103 queue_delayed_work(system_freezable_wq, &pci_pme_work,
2104 msecs_to_jiffies(PME_TIMEOUT));
2105 mutex_unlock(&pci_pme_list_mutex);
2108 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2112 if (!dev->pme_support)
2115 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2116 /* Clear PME_Status by writing 1 to it and enable PME# */
2117 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2119 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2121 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2125 * pci_pme_restore - Restore PME configuration after config space restore.
2126 * @dev: PCI device to update.
2128 void pci_pme_restore(struct pci_dev *dev)
2132 if (!dev->pme_support)
2135 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2136 if (dev->wakeup_prepared) {
2137 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2138 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2140 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2141 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2143 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2147 * pci_pme_active - enable or disable PCI device's PME# function
2148 * @dev: PCI device to handle.
2149 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2151 * The caller must verify that the device is capable of generating PME# before
2152 * calling this function with @enable equal to 'true'.
2154 void pci_pme_active(struct pci_dev *dev, bool enable)
2156 __pci_pme_active(dev, enable);
2159 * PCI (as opposed to PCIe) PME requires that the device have
2160 * its PME# line hooked up correctly. Not all hardware vendors
2161 * do this, so the PME never gets delivered and the device
2162 * remains asleep. The easiest way around this is to
2163 * periodically walk the list of suspended devices and check
2164 * whether any have their PME flag set. The assumption is that
2165 * we'll wake up often enough anyway that this won't be a huge
2166 * hit, and the power savings from the devices will still be a
2169 * Although PCIe uses in-band PME message instead of PME# line
2170 * to report PME, PME does not work for some PCIe devices in
2171 * reality. For example, there are devices that set their PME
2172 * status bits, but don't really bother to send a PME message;
2173 * there are PCI Express Root Ports that don't bother to
2174 * trigger interrupts when they receive PME messages from the
2175 * devices below. So PME poll is used for PCIe devices too.
2178 if (dev->pme_poll) {
2179 struct pci_pme_device *pme_dev;
2181 pme_dev = kmalloc(sizeof(struct pci_pme_device),
2184 pci_warn(dev, "can't enable PME#\n");
2188 mutex_lock(&pci_pme_list_mutex);
2189 list_add(&pme_dev->list, &pci_pme_list);
2190 if (list_is_singular(&pci_pme_list))
2191 queue_delayed_work(system_freezable_wq,
2193 msecs_to_jiffies(PME_TIMEOUT));
2194 mutex_unlock(&pci_pme_list_mutex);
2196 mutex_lock(&pci_pme_list_mutex);
2197 list_for_each_entry(pme_dev, &pci_pme_list, list) {
2198 if (pme_dev->dev == dev) {
2199 list_del(&pme_dev->list);
2204 mutex_unlock(&pci_pme_list_mutex);
2208 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2210 EXPORT_SYMBOL(pci_pme_active);
2213 * __pci_enable_wake - enable PCI device as wakeup event source
2214 * @dev: PCI device affected
2215 * @state: PCI state from which device will issue wakeup events
2216 * @enable: True to enable event generation; false to disable
2218 * This enables the device as a wakeup event source, or disables it.
2219 * When such events involves platform-specific hooks, those hooks are
2220 * called automatically by this routine.
2222 * Devices with legacy power management (no standard PCI PM capabilities)
2223 * always require such platform hooks.
2226 * 0 is returned on success
2227 * -EINVAL is returned if device is not supposed to wake up the system
2228 * Error code depending on the platform is returned if both the platform and
2229 * the native mechanism fail to enable the generation of wake-up events
2231 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2236 * Bridges that are not power-manageable directly only signal
2237 * wakeup on behalf of subordinate devices which is set up
2238 * elsewhere, so skip them. However, bridges that are
2239 * power-manageable may signal wakeup for themselves (for example,
2240 * on a hotplug event) and they need to be covered here.
2242 if (!pci_power_manageable(dev))
2245 /* Don't do the same thing twice in a row for one device. */
2246 if (!!enable == !!dev->wakeup_prepared)
2250 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2251 * Anderson we should be doing PME# wake enable followed by ACPI wake
2252 * enable. To disable wake-up we call the platform first, for symmetry.
2258 if (pci_pme_capable(dev, state))
2259 pci_pme_active(dev, true);
2262 error = platform_pci_set_wakeup(dev, true);
2266 dev->wakeup_prepared = true;
2268 platform_pci_set_wakeup(dev, false);
2269 pci_pme_active(dev, false);
2270 dev->wakeup_prepared = false;
2277 * pci_enable_wake - change wakeup settings for a PCI device
2278 * @pci_dev: Target device
2279 * @state: PCI state from which device will issue wakeup events
2280 * @enable: Whether or not to enable event generation
2282 * If @enable is set, check device_may_wakeup() for the device before calling
2283 * __pci_enable_wake() for it.
2285 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2287 if (enable && !device_may_wakeup(&pci_dev->dev))
2290 return __pci_enable_wake(pci_dev, state, enable);
2292 EXPORT_SYMBOL(pci_enable_wake);
2295 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2296 * @dev: PCI device to prepare
2297 * @enable: True to enable wake-up event generation; false to disable
2299 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2300 * and this function allows them to set that up cleanly - pci_enable_wake()
2301 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2302 * ordering constraints.
2304 * This function only returns error code if the device is not allowed to wake
2305 * up the system from sleep or it is not capable of generating PME# from both
2306 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2308 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2310 return pci_pme_capable(dev, PCI_D3cold) ?
2311 pci_enable_wake(dev, PCI_D3cold, enable) :
2312 pci_enable_wake(dev, PCI_D3hot, enable);
2314 EXPORT_SYMBOL(pci_wake_from_d3);
2317 * pci_target_state - find an appropriate low power state for a given PCI dev
2319 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2321 * Use underlying platform code to find a supported low power state for @dev.
2322 * If the platform can't manage @dev, return the deepest state from which it
2323 * can generate wake events, based on any available PME info.
2325 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2327 pci_power_t target_state = PCI_D3hot;
2329 if (platform_pci_power_manageable(dev)) {
2331 * Call the platform to find the target state for the device.
2333 pci_power_t state = platform_pci_choose_state(dev);
2336 case PCI_POWER_ERROR:
2341 if (pci_no_d1d2(dev))
2343 /* else, fall through */
2345 target_state = state;
2348 return target_state;
2352 target_state = PCI_D0;
2355 * If the device is in D3cold even though it's not power-manageable by
2356 * the platform, it may have been powered down by non-standard means.
2357 * Best to let it slumber.
2359 if (dev->current_state == PCI_D3cold)
2360 target_state = PCI_D3cold;
2364 * Find the deepest state from which the device can generate
2367 if (dev->pme_support) {
2369 && !(dev->pme_support & (1 << target_state)))
2374 return target_state;
2378 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2379 * into a sleep state
2380 * @dev: Device to handle.
2382 * Choose the power state appropriate for the device depending on whether
2383 * it can wake up the system and/or is power manageable by the platform
2384 * (PCI_D3hot is the default) and put the device into that state.
2386 int pci_prepare_to_sleep(struct pci_dev *dev)
2388 bool wakeup = device_may_wakeup(&dev->dev);
2389 pci_power_t target_state = pci_target_state(dev, wakeup);
2392 if (target_state == PCI_POWER_ERROR)
2395 pci_enable_wake(dev, target_state, wakeup);
2397 error = pci_set_power_state(dev, target_state);
2400 pci_enable_wake(dev, target_state, false);
2404 EXPORT_SYMBOL(pci_prepare_to_sleep);
2407 * pci_back_from_sleep - turn PCI device on during system-wide transition
2408 * into working state
2409 * @dev: Device to handle.
2411 * Disable device's system wake-up capability and put it into D0.
2413 int pci_back_from_sleep(struct pci_dev *dev)
2415 pci_enable_wake(dev, PCI_D0, false);
2416 return pci_set_power_state(dev, PCI_D0);
2418 EXPORT_SYMBOL(pci_back_from_sleep);
2421 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2422 * @dev: PCI device being suspended.
2424 * Prepare @dev to generate wake-up events at run time and put it into a low
2427 int pci_finish_runtime_suspend(struct pci_dev *dev)
2429 pci_power_t target_state;
2432 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2433 if (target_state == PCI_POWER_ERROR)
2436 dev->runtime_d3cold = target_state == PCI_D3cold;
2438 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2440 error = pci_set_power_state(dev, target_state);
2443 pci_enable_wake(dev, target_state, false);
2444 dev->runtime_d3cold = false;
2451 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2452 * @dev: Device to check.
2454 * Return true if the device itself is capable of generating wake-up events
2455 * (through the platform or using the native PCIe PME) or if the device supports
2456 * PME and one of its upstream bridges can generate wake-up events.
2458 bool pci_dev_run_wake(struct pci_dev *dev)
2460 struct pci_bus *bus = dev->bus;
2462 if (!dev->pme_support)
2465 /* PME-capable in principle, but not from the target power state */
2466 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2469 if (device_can_wakeup(&dev->dev))
2472 while (bus->parent) {
2473 struct pci_dev *bridge = bus->self;
2475 if (device_can_wakeup(&bridge->dev))
2481 /* We have reached the root bus. */
2483 return device_can_wakeup(bus->bridge);
2487 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2490 * pci_dev_need_resume - Check if it is necessary to resume the device.
2491 * @pci_dev: Device to check.
2493 * Return 'true' if the device is not runtime-suspended or it has to be
2494 * reconfigured due to wakeup settings difference between system and runtime
2495 * suspend, or the current power state of it is not suitable for the upcoming
2496 * (system-wide) transition.
2498 bool pci_dev_need_resume(struct pci_dev *pci_dev)
2500 struct device *dev = &pci_dev->dev;
2501 pci_power_t target_state;
2503 if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2506 target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2509 * If the earlier platform check has not triggered, D3cold is just power
2510 * removal on top of D3hot, so no need to resume the device in that
2513 return target_state != pci_dev->current_state &&
2514 target_state != PCI_D3cold &&
2515 pci_dev->current_state != PCI_D3hot;
2519 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2520 * @pci_dev: Device to check.
2522 * If the device is suspended and it is not configured for system wakeup,
2523 * disable PME for it to prevent it from waking up the system unnecessarily.
2525 * Note that if the device's power state is D3cold and the platform check in
2526 * pci_dev_need_resume() has not triggered, the device's configuration need not
2529 void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2531 struct device *dev = &pci_dev->dev;
2533 spin_lock_irq(&dev->power.lock);
2535 if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2536 pci_dev->current_state < PCI_D3cold)
2537 __pci_pme_active(pci_dev, false);
2539 spin_unlock_irq(&dev->power.lock);
2543 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2544 * @pci_dev: Device to handle.
2546 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2547 * it might have been disabled during the prepare phase of system suspend if
2548 * the device was not configured for system wakeup.
2550 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2552 struct device *dev = &pci_dev->dev;
2554 if (!pci_dev_run_wake(pci_dev))
2557 spin_lock_irq(&dev->power.lock);
2559 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2560 __pci_pme_active(pci_dev, true);
2562 spin_unlock_irq(&dev->power.lock);
2565 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2567 struct device *dev = &pdev->dev;
2568 struct device *parent = dev->parent;
2571 pm_runtime_get_sync(parent);
2572 pm_runtime_get_noresume(dev);
2574 * pdev->current_state is set to PCI_D3cold during suspending,
2575 * so wait until suspending completes
2577 pm_runtime_barrier(dev);
2579 * Only need to resume devices in D3cold, because config
2580 * registers are still accessible for devices suspended but
2583 if (pdev->current_state == PCI_D3cold)
2584 pm_runtime_resume(dev);
2587 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2589 struct device *dev = &pdev->dev;
2590 struct device *parent = dev->parent;
2592 pm_runtime_put(dev);
2594 pm_runtime_put_sync(parent);
2597 static const struct dmi_system_id bridge_d3_blacklist[] = {
2601 * Gigabyte X299 root port is not marked as hotplug capable
2602 * which allows Linux to power manage it. However, this
2603 * confuses the BIOS SMI handler so don't power manage root
2604 * ports on that system.
2606 .ident = "X299 DESIGNARE EX-CF",
2608 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
2609 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2617 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2618 * @bridge: Bridge to check
2620 * This function checks if it is possible to move the bridge to D3.
2621 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2623 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2625 if (!pci_is_pcie(bridge))
2628 switch (pci_pcie_type(bridge)) {
2629 case PCI_EXP_TYPE_ROOT_PORT:
2630 case PCI_EXP_TYPE_UPSTREAM:
2631 case PCI_EXP_TYPE_DOWNSTREAM:
2632 if (pci_bridge_d3_disable)
2636 * Hotplug ports handled by firmware in System Management Mode
2637 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2639 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
2642 if (pci_bridge_d3_force)
2645 /* Even the oldest 2010 Thunderbolt controller supports D3. */
2646 if (bridge->is_thunderbolt)
2649 /* Platform might know better if the bridge supports D3 */
2650 if (platform_pci_bridge_d3(bridge))
2654 * Hotplug ports handled natively by the OS were not validated
2655 * by vendors for runtime D3 at least until 2018 because there
2656 * was no OS support.
2658 if (bridge->is_hotplug_bridge)
2661 if (dmi_check_system(bridge_d3_blacklist))
2665 * It should be safe to put PCIe ports from 2015 or newer
2668 if (dmi_get_bios_year() >= 2015)
2676 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2678 bool *d3cold_ok = data;
2680 if (/* The device needs to be allowed to go D3cold ... */
2681 dev->no_d3cold || !dev->d3cold_allowed ||
2683 /* ... and if it is wakeup capable to do so from D3cold. */
2684 (device_may_wakeup(&dev->dev) &&
2685 !pci_pme_capable(dev, PCI_D3cold)) ||
2687 /* If it is a bridge it must be allowed to go to D3. */
2688 !pci_power_manageable(dev))
2696 * pci_bridge_d3_update - Update bridge D3 capabilities
2697 * @dev: PCI device which is changed
2699 * Update upstream bridge PM capabilities accordingly depending on if the
2700 * device PM configuration was changed or the device is being removed. The
2701 * change is also propagated upstream.
2703 void pci_bridge_d3_update(struct pci_dev *dev)
2705 bool remove = !device_is_registered(&dev->dev);
2706 struct pci_dev *bridge;
2707 bool d3cold_ok = true;
2709 bridge = pci_upstream_bridge(dev);
2710 if (!bridge || !pci_bridge_d3_possible(bridge))
2714 * If D3 is currently allowed for the bridge, removing one of its
2715 * children won't change that.
2717 if (remove && bridge->bridge_d3)
2721 * If D3 is currently allowed for the bridge and a child is added or
2722 * changed, disallowance of D3 can only be caused by that child, so
2723 * we only need to check that single device, not any of its siblings.
2725 * If D3 is currently not allowed for the bridge, checking the device
2726 * first may allow us to skip checking its siblings.
2729 pci_dev_check_d3cold(dev, &d3cold_ok);
2732 * If D3 is currently not allowed for the bridge, this may be caused
2733 * either by the device being changed/removed or any of its siblings,
2734 * so we need to go through all children to find out if one of them
2735 * continues to block D3.
2737 if (d3cold_ok && !bridge->bridge_d3)
2738 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2741 if (bridge->bridge_d3 != d3cold_ok) {
2742 bridge->bridge_d3 = d3cold_ok;
2743 /* Propagate change to upstream bridges */
2744 pci_bridge_d3_update(bridge);
2749 * pci_d3cold_enable - Enable D3cold for device
2750 * @dev: PCI device to handle
2752 * This function can be used in drivers to enable D3cold from the device
2753 * they handle. It also updates upstream PCI bridge PM capabilities
2756 void pci_d3cold_enable(struct pci_dev *dev)
2758 if (dev->no_d3cold) {
2759 dev->no_d3cold = false;
2760 pci_bridge_d3_update(dev);
2763 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2766 * pci_d3cold_disable - Disable D3cold for device
2767 * @dev: PCI device to handle
2769 * This function can be used in drivers to disable D3cold from the device
2770 * they handle. It also updates upstream PCI bridge PM capabilities
2773 void pci_d3cold_disable(struct pci_dev *dev)
2775 if (!dev->no_d3cold) {
2776 dev->no_d3cold = true;
2777 pci_bridge_d3_update(dev);
2780 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2783 * pci_pm_init - Initialize PM functions of given PCI device
2784 * @dev: PCI device to handle.
2786 void pci_pm_init(struct pci_dev *dev)
2792 pm_runtime_forbid(&dev->dev);
2793 pm_runtime_set_active(&dev->dev);
2794 pm_runtime_enable(&dev->dev);
2795 device_enable_async_suspend(&dev->dev);
2796 dev->wakeup_prepared = false;
2799 dev->pme_support = 0;
2801 /* find PCI PM capability in list */
2802 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2805 /* Check device's ability to generate PME# */
2806 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2808 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2809 pci_err(dev, "unsupported PM cap regs version (%u)\n",
2810 pmc & PCI_PM_CAP_VER_MASK);
2815 dev->d3_delay = PCI_PM_D3_WAIT;
2816 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2817 dev->bridge_d3 = pci_bridge_d3_possible(dev);
2818 dev->d3cold_allowed = true;
2820 dev->d1_support = false;
2821 dev->d2_support = false;
2822 if (!pci_no_d1d2(dev)) {
2823 if (pmc & PCI_PM_CAP_D1)
2824 dev->d1_support = true;
2825 if (pmc & PCI_PM_CAP_D2)
2826 dev->d2_support = true;
2828 if (dev->d1_support || dev->d2_support)
2829 pci_info(dev, "supports%s%s\n",
2830 dev->d1_support ? " D1" : "",
2831 dev->d2_support ? " D2" : "");
2834 pmc &= PCI_PM_CAP_PME_MASK;
2836 pci_info(dev, "PME# supported from%s%s%s%s%s\n",
2837 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2838 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2839 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2840 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2841 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2842 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2843 dev->pme_poll = true;
2845 * Make device's PM flags reflect the wake-up capability, but
2846 * let the user space enable it to wake up the system as needed.
2848 device_set_wakeup_capable(&dev->dev, true);
2849 /* Disable the PME# generation functionality */
2850 pci_pme_active(dev, false);
2853 pci_read_config_word(dev, PCI_STATUS, &status);
2854 if (status & PCI_STATUS_IMM_READY)
2858 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2860 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
2864 case PCI_EA_P_VF_MEM:
2865 flags |= IORESOURCE_MEM;
2867 case PCI_EA_P_MEM_PREFETCH:
2868 case PCI_EA_P_VF_MEM_PREFETCH:
2869 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2872 flags |= IORESOURCE_IO;
2881 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2884 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2885 return &dev->resource[bei];
2886 #ifdef CONFIG_PCI_IOV
2887 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2888 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2889 return &dev->resource[PCI_IOV_RESOURCES +
2890 bei - PCI_EA_BEI_VF_BAR0];
2892 else if (bei == PCI_EA_BEI_ROM)
2893 return &dev->resource[PCI_ROM_RESOURCE];
2898 /* Read an Enhanced Allocation (EA) entry */
2899 static int pci_ea_read(struct pci_dev *dev, int offset)
2901 struct resource *res;
2902 int ent_size, ent_offset = offset;
2903 resource_size_t start, end;
2904 unsigned long flags;
2905 u32 dw0, bei, base, max_offset;
2907 bool support_64 = (sizeof(resource_size_t) >= 8);
2909 pci_read_config_dword(dev, ent_offset, &dw0);
2912 /* Entry size field indicates DWORDs after 1st */
2913 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2915 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2918 bei = (dw0 & PCI_EA_BEI) >> 4;
2919 prop = (dw0 & PCI_EA_PP) >> 8;
2922 * If the Property is in the reserved range, try the Secondary
2925 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2926 prop = (dw0 & PCI_EA_SP) >> 16;
2927 if (prop > PCI_EA_P_BRIDGE_IO)
2930 res = pci_ea_get_resource(dev, bei, prop);
2932 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
2936 flags = pci_ea_flags(dev, prop);
2938 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
2943 pci_read_config_dword(dev, ent_offset, &base);
2944 start = (base & PCI_EA_FIELD_MASK);
2947 /* Read MaxOffset */
2948 pci_read_config_dword(dev, ent_offset, &max_offset);
2951 /* Read Base MSBs (if 64-bit entry) */
2952 if (base & PCI_EA_IS_64) {
2955 pci_read_config_dword(dev, ent_offset, &base_upper);
2958 flags |= IORESOURCE_MEM_64;
2960 /* entry starts above 32-bit boundary, can't use */
2961 if (!support_64 && base_upper)
2965 start |= ((u64)base_upper << 32);
2968 end = start + (max_offset | 0x03);
2970 /* Read MaxOffset MSBs (if 64-bit entry) */
2971 if (max_offset & PCI_EA_IS_64) {
2972 u32 max_offset_upper;
2974 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2977 flags |= IORESOURCE_MEM_64;
2979 /* entry too big, can't use */
2980 if (!support_64 && max_offset_upper)
2984 end += ((u64)max_offset_upper << 32);
2988 pci_err(dev, "EA Entry crosses address boundary\n");
2992 if (ent_size != ent_offset - offset) {
2993 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
2994 ent_size, ent_offset - offset);
2998 res->name = pci_name(dev);
3003 if (bei <= PCI_EA_BEI_BAR5)
3004 pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3006 else if (bei == PCI_EA_BEI_ROM)
3007 pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3009 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3010 pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3011 bei - PCI_EA_BEI_VF_BAR0, res, prop);
3013 pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3017 return offset + ent_size;
3020 /* Enhanced Allocation Initialization */
3021 void pci_ea_init(struct pci_dev *dev)
3028 /* find PCI EA capability in list */
3029 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3033 /* determine the number of entries */
3034 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3036 num_ent &= PCI_EA_NUM_ENT_MASK;
3038 offset = ea + PCI_EA_FIRST_ENT;
3040 /* Skip DWORD 2 for type 1 functions */
3041 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3044 /* parse each EA entry */
3045 for (i = 0; i < num_ent; ++i)
3046 offset = pci_ea_read(dev, offset);
3049 static void pci_add_saved_cap(struct pci_dev *pci_dev,
3050 struct pci_cap_saved_state *new_cap)
3052 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
3056 * _pci_add_cap_save_buffer - allocate buffer for saving given
3057 * capability registers
3058 * @dev: the PCI device
3059 * @cap: the capability to allocate the buffer for
3060 * @extended: Standard or Extended capability ID
3061 * @size: requested size of the buffer
3063 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3064 bool extended, unsigned int size)
3067 struct pci_cap_saved_state *save_state;
3070 pos = pci_find_ext_capability(dev, cap);
3072 pos = pci_find_capability(dev, cap);
3077 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
3081 save_state->cap.cap_nr = cap;
3082 save_state->cap.cap_extended = extended;
3083 save_state->cap.size = size;
3084 pci_add_saved_cap(dev, save_state);
3089 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3091 return _pci_add_cap_save_buffer(dev, cap, false, size);
3094 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3096 return _pci_add_cap_save_buffer(dev, cap, true, size);
3100 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3101 * @dev: the PCI device
3103 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3107 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3108 PCI_EXP_SAVE_REGS * sizeof(u16));
3110 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3112 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3114 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3116 error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3119 pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3121 pci_allocate_vc_save_buffers(dev);
3124 void pci_free_cap_save_buffers(struct pci_dev *dev)
3126 struct pci_cap_saved_state *tmp;
3127 struct hlist_node *n;
3129 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3134 * pci_configure_ari - enable or disable ARI forwarding
3135 * @dev: the PCI device
3137 * If @dev and its upstream bridge both support ARI, enable ARI in the
3138 * bridge. Otherwise, disable ARI in the bridge.
3140 void pci_configure_ari(struct pci_dev *dev)
3143 struct pci_dev *bridge;
3145 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3148 bridge = dev->bus->self;
3152 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3153 if (!(cap & PCI_EXP_DEVCAP2_ARI))
3156 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3157 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3158 PCI_EXP_DEVCTL2_ARI);
3159 bridge->ari_enabled = 1;
3161 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3162 PCI_EXP_DEVCTL2_ARI);
3163 bridge->ari_enabled = 0;
3167 static int pci_acs_enable;
3170 * pci_request_acs - ask for ACS to be enabled if supported
3172 void pci_request_acs(void)
3177 static const char *disable_acs_redir_param;
3180 * pci_disable_acs_redir - disable ACS redirect capabilities
3181 * @dev: the PCI device
3183 * For only devices specified in the disable_acs_redir parameter.
3185 static void pci_disable_acs_redir(struct pci_dev *dev)
3192 if (!disable_acs_redir_param)
3195 p = disable_acs_redir_param;
3197 ret = pci_dev_str_match(dev, p, &p);
3199 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
3200 disable_acs_redir_param);
3203 } else if (ret == 1) {
3208 if (*p != ';' && *p != ',') {
3209 /* End of param or invalid format */
3218 if (!pci_dev_specific_disable_acs_redir(dev))
3221 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3223 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
3227 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
3229 /* P2P Request & Completion Redirect */
3230 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
3232 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
3234 pci_info(dev, "disabled ACS redirect\n");
3238 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
3239 * @dev: the PCI device
3241 static void pci_std_enable_acs(struct pci_dev *dev)
3247 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3251 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
3252 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
3254 /* Source Validation */
3255 ctrl |= (cap & PCI_ACS_SV);
3257 /* P2P Request Redirect */
3258 ctrl |= (cap & PCI_ACS_RR);
3260 /* P2P Completion Redirect */
3261 ctrl |= (cap & PCI_ACS_CR);
3263 /* Upstream Forwarding */
3264 ctrl |= (cap & PCI_ACS_UF);
3266 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
3270 * pci_enable_acs - enable ACS if hardware support it
3271 * @dev: the PCI device
3273 void pci_enable_acs(struct pci_dev *dev)
3275 if (!pci_acs_enable)
3276 goto disable_acs_redir;
3278 if (!pci_dev_specific_enable_acs(dev))
3279 goto disable_acs_redir;
3281 pci_std_enable_acs(dev);
3285 * Note: pci_disable_acs_redir() must be called even if ACS was not
3286 * enabled by the kernel because it may have been enabled by
3287 * platform firmware. So if we are told to disable it, we should
3288 * always disable it after setting the kernel's default
3291 pci_disable_acs_redir(dev);
3294 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3299 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
3304 * Except for egress control, capabilities are either required
3305 * or only required if controllable. Features missing from the
3306 * capability field can therefore be assumed as hard-wired enabled.
3308 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3309 acs_flags &= (cap | PCI_ACS_EC);
3311 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3312 return (ctrl & acs_flags) == acs_flags;
3316 * pci_acs_enabled - test ACS against required flags for a given device
3317 * @pdev: device to test
3318 * @acs_flags: required PCI ACS flags
3320 * Return true if the device supports the provided flags. Automatically
3321 * filters out flags that are not implemented on multifunction devices.
3323 * Note that this interface checks the effective ACS capabilities of the
3324 * device rather than the actual capabilities. For instance, most single
3325 * function endpoints are not required to support ACS because they have no
3326 * opportunity for peer-to-peer access. We therefore return 'true'
3327 * regardless of whether the device exposes an ACS capability. This makes
3328 * it much easier for callers of this function to ignore the actual type
3329 * or topology of the device when testing ACS support.
3331 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3335 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3340 * Conventional PCI and PCI-X devices never support ACS, either
3341 * effectively or actually. The shared bus topology implies that
3342 * any device on the bus can receive or snoop DMA.
3344 if (!pci_is_pcie(pdev))
3347 switch (pci_pcie_type(pdev)) {
3349 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3350 * but since their primary interface is PCI/X, we conservatively
3351 * handle them as we would a non-PCIe device.
3353 case PCI_EXP_TYPE_PCIE_BRIDGE:
3355 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3356 * applicable... must never implement an ACS Extended Capability...".
3357 * This seems arbitrary, but we take a conservative interpretation
3358 * of this statement.
3360 case PCI_EXP_TYPE_PCI_BRIDGE:
3361 case PCI_EXP_TYPE_RC_EC:
3364 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3365 * implement ACS in order to indicate their peer-to-peer capabilities,
3366 * regardless of whether they are single- or multi-function devices.
3368 case PCI_EXP_TYPE_DOWNSTREAM:
3369 case PCI_EXP_TYPE_ROOT_PORT:
3370 return pci_acs_flags_enabled(pdev, acs_flags);
3372 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3373 * implemented by the remaining PCIe types to indicate peer-to-peer
3374 * capabilities, but only when they are part of a multifunction
3375 * device. The footnote for section 6.12 indicates the specific
3376 * PCIe types included here.
3378 case PCI_EXP_TYPE_ENDPOINT:
3379 case PCI_EXP_TYPE_UPSTREAM:
3380 case PCI_EXP_TYPE_LEG_END:
3381 case PCI_EXP_TYPE_RC_END:
3382 if (!pdev->multifunction)
3385 return pci_acs_flags_enabled(pdev, acs_flags);
3389 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3390 * to single function devices with the exception of downstream ports.
3396 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
3397 * @start: starting downstream device
3398 * @end: ending upstream device or NULL to search to the root bus
3399 * @acs_flags: required flags
3401 * Walk up a device tree from start to end testing PCI ACS support. If
3402 * any step along the way does not support the required flags, return false.
3404 bool pci_acs_path_enabled(struct pci_dev *start,
3405 struct pci_dev *end, u16 acs_flags)
3407 struct pci_dev *pdev, *parent = start;
3412 if (!pci_acs_enabled(pdev, acs_flags))
3415 if (pci_is_root_bus(pdev->bus))
3416 return (end == NULL);
3418 parent = pdev->bus->self;
3419 } while (pdev != end);
3425 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3429 * Helper to find the position of the ctrl register for a BAR.
3430 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3431 * Returns -ENOENT if no ctrl register for the BAR could be found.
3433 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3435 unsigned int pos, nbars, i;
3438 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3442 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3443 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3444 PCI_REBAR_CTRL_NBAR_SHIFT;
3446 for (i = 0; i < nbars; i++, pos += 8) {
3449 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3450 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3459 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3461 * @bar: BAR to query
3463 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3464 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3466 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3471 pos = pci_rebar_find_pos(pdev, bar);
3475 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3476 return (cap & PCI_REBAR_CAP_SIZES) >> 4;
3480 * pci_rebar_get_current_size - get the current size of a BAR
3482 * @bar: BAR to set size to
3484 * Read the size of a BAR from the resizable BAR config.
3485 * Returns size if found or negative error code.
3487 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3492 pos = pci_rebar_find_pos(pdev, bar);
3496 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3497 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
3501 * pci_rebar_set_size - set a new size for a BAR
3503 * @bar: BAR to set size to
3504 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3506 * Set the new size of a BAR as defined in the spec.
3507 * Returns zero if resizing was successful, error code otherwise.
3509 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3514 pos = pci_rebar_find_pos(pdev, bar);
3518 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3519 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3520 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
3521 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3526 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3527 * @dev: the PCI device
3528 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3529 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3530 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3531 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3533 * Return 0 if all upstream bridges support AtomicOp routing, egress
3534 * blocking is disabled on all upstream ports, and the root port supports
3535 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3536 * AtomicOp completion), or negative otherwise.
3538 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3540 struct pci_bus *bus = dev->bus;
3541 struct pci_dev *bridge;
3544 if (!pci_is_pcie(dev))
3548 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3549 * AtomicOp requesters. For now, we only support endpoints as
3550 * requesters and root ports as completers. No endpoints as
3551 * completers, and no peer-to-peer.
3554 switch (pci_pcie_type(dev)) {
3555 case PCI_EXP_TYPE_ENDPOINT:
3556 case PCI_EXP_TYPE_LEG_END:
3557 case PCI_EXP_TYPE_RC_END:
3563 while (bus->parent) {
3566 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3568 switch (pci_pcie_type(bridge)) {
3569 /* Ensure switch ports support AtomicOp routing */
3570 case PCI_EXP_TYPE_UPSTREAM:
3571 case PCI_EXP_TYPE_DOWNSTREAM:
3572 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3576 /* Ensure root port supports all the sizes we care about */
3577 case PCI_EXP_TYPE_ROOT_PORT:
3578 if ((cap & cap_mask) != cap_mask)
3583 /* Ensure upstream ports don't block AtomicOps on egress */
3584 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3585 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3587 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3594 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3595 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3598 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3601 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3602 * @dev: the PCI device
3603 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3605 * Perform INTx swizzling for a device behind one level of bridge. This is
3606 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3607 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3608 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3609 * the PCI Express Base Specification, Revision 2.1)
3611 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3615 if (pci_ari_enabled(dev->bus))
3618 slot = PCI_SLOT(dev->devfn);
3620 return (((pin - 1) + slot) % 4) + 1;
3623 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3631 while (!pci_is_root_bus(dev->bus)) {
3632 pin = pci_swizzle_interrupt_pin(dev, pin);
3633 dev = dev->bus->self;
3640 * pci_common_swizzle - swizzle INTx all the way to root bridge
3641 * @dev: the PCI device
3642 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3644 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3645 * bridges all the way up to a PCI root bus.
3647 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3651 while (!pci_is_root_bus(dev->bus)) {
3652 pin = pci_swizzle_interrupt_pin(dev, pin);
3653 dev = dev->bus->self;
3656 return PCI_SLOT(dev->devfn);
3658 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3661 * pci_release_region - Release a PCI bar
3662 * @pdev: PCI device whose resources were previously reserved by
3663 * pci_request_region()
3664 * @bar: BAR to release
3666 * Releases the PCI I/O and memory resources previously reserved by a
3667 * successful call to pci_request_region(). Call this function only
3668 * after all use of the PCI regions has ceased.
3670 void pci_release_region(struct pci_dev *pdev, int bar)
3672 struct pci_devres *dr;
3674 if (pci_resource_len(pdev, bar) == 0)
3676 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3677 release_region(pci_resource_start(pdev, bar),
3678 pci_resource_len(pdev, bar));
3679 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3680 release_mem_region(pci_resource_start(pdev, bar),
3681 pci_resource_len(pdev, bar));
3683 dr = find_pci_dr(pdev);
3685 dr->region_mask &= ~(1 << bar);
3687 EXPORT_SYMBOL(pci_release_region);
3690 * __pci_request_region - Reserved PCI I/O and memory resource
3691 * @pdev: PCI device whose resources are to be reserved
3692 * @bar: BAR to be reserved
3693 * @res_name: Name to be associated with resource.
3694 * @exclusive: whether the region access is exclusive or not
3696 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3697 * being reserved by owner @res_name. Do not access any
3698 * address inside the PCI regions unless this call returns
3701 * If @exclusive is set, then the region is marked so that userspace
3702 * is explicitly not allowed to map the resource via /dev/mem or
3703 * sysfs MMIO access.
3705 * Returns 0 on success, or %EBUSY on error. A warning
3706 * message is also printed on failure.
3708 static int __pci_request_region(struct pci_dev *pdev, int bar,
3709 const char *res_name, int exclusive)
3711 struct pci_devres *dr;
3713 if (pci_resource_len(pdev, bar) == 0)
3716 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3717 if (!request_region(pci_resource_start(pdev, bar),
3718 pci_resource_len(pdev, bar), res_name))
3720 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3721 if (!__request_mem_region(pci_resource_start(pdev, bar),
3722 pci_resource_len(pdev, bar), res_name,
3727 dr = find_pci_dr(pdev);
3729 dr->region_mask |= 1 << bar;
3734 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3735 &pdev->resource[bar]);
3740 * pci_request_region - Reserve PCI I/O and memory resource
3741 * @pdev: PCI device whose resources are to be reserved
3742 * @bar: BAR to be reserved
3743 * @res_name: Name to be associated with resource
3745 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3746 * being reserved by owner @res_name. Do not access any
3747 * address inside the PCI regions unless this call returns
3750 * Returns 0 on success, or %EBUSY on error. A warning
3751 * message is also printed on failure.
3753 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3755 return __pci_request_region(pdev, bar, res_name, 0);
3757 EXPORT_SYMBOL(pci_request_region);
3760 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3761 * @pdev: PCI device whose resources were previously reserved
3762 * @bars: Bitmask of BARs to be released
3764 * Release selected PCI I/O and memory resources previously reserved.
3765 * Call this function only after all use of the PCI regions has ceased.
3767 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3771 for (i = 0; i < 6; i++)
3772 if (bars & (1 << i))
3773 pci_release_region(pdev, i);
3775 EXPORT_SYMBOL(pci_release_selected_regions);
3777 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3778 const char *res_name, int excl)
3782 for (i = 0; i < 6; i++)
3783 if (bars & (1 << i))
3784 if (__pci_request_region(pdev, i, res_name, excl))
3790 if (bars & (1 << i))
3791 pci_release_region(pdev, i);
3798 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3799 * @pdev: PCI device whose resources are to be reserved
3800 * @bars: Bitmask of BARs to be requested
3801 * @res_name: Name to be associated with resource
3803 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3804 const char *res_name)
3806 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3808 EXPORT_SYMBOL(pci_request_selected_regions);
3810 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3811 const char *res_name)
3813 return __pci_request_selected_regions(pdev, bars, res_name,
3814 IORESOURCE_EXCLUSIVE);
3816 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3819 * pci_release_regions - Release reserved PCI I/O and memory resources
3820 * @pdev: PCI device whose resources were previously reserved by
3821 * pci_request_regions()
3823 * Releases all PCI I/O and memory resources previously reserved by a
3824 * successful call to pci_request_regions(). Call this function only
3825 * after all use of the PCI regions has ceased.
3828 void pci_release_regions(struct pci_dev *pdev)
3830 pci_release_selected_regions(pdev, (1 << 6) - 1);
3832 EXPORT_SYMBOL(pci_release_regions);
3835 * pci_request_regions - Reserve PCI I/O and memory resources
3836 * @pdev: PCI device whose resources are to be reserved
3837 * @res_name: Name to be associated with resource.
3839 * Mark all PCI regions associated with PCI device @pdev as
3840 * being reserved by owner @res_name. Do not access any
3841 * address inside the PCI regions unless this call returns
3844 * Returns 0 on success, or %EBUSY on error. A warning
3845 * message is also printed on failure.
3847 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3849 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3851 EXPORT_SYMBOL(pci_request_regions);
3854 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
3855 * @pdev: PCI device whose resources are to be reserved
3856 * @res_name: Name to be associated with resource.
3858 * Mark all PCI regions associated with PCI device @pdev as being reserved
3859 * by owner @res_name. Do not access any address inside the PCI regions
3860 * unless this call returns successfully.
3862 * pci_request_regions_exclusive() will mark the region so that /dev/mem
3863 * and the sysfs MMIO access will not be allowed.
3865 * Returns 0 on success, or %EBUSY on error. A warning message is also
3866 * printed on failure.
3868 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3870 return pci_request_selected_regions_exclusive(pdev,
3871 ((1 << 6) - 1), res_name);
3873 EXPORT_SYMBOL(pci_request_regions_exclusive);
3876 * Record the PCI IO range (expressed as CPU physical address + size).
3877 * Return a negative value if an error has occurred, zero otherwise
3879 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
3880 resource_size_t size)
3884 struct logic_pio_hwaddr *range;
3886 if (!size || addr + size < addr)
3889 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3893 range->fwnode = fwnode;
3895 range->hw_start = addr;
3896 range->flags = LOGIC_PIO_CPU_MMIO;
3898 ret = logic_pio_register_range(range);
3906 phys_addr_t pci_pio_to_address(unsigned long pio)
3908 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3911 if (pio >= MMIO_UPPER_LIMIT)
3914 address = logic_pio_to_hwaddr(pio);
3920 unsigned long __weak pci_address_to_pio(phys_addr_t address)
3923 return logic_pio_trans_cpuaddr(address);
3925 if (address > IO_SPACE_LIMIT)
3926 return (unsigned long)-1;
3928 return (unsigned long) address;
3933 * pci_remap_iospace - Remap the memory mapped I/O space
3934 * @res: Resource describing the I/O space
3935 * @phys_addr: physical address of range to be mapped
3937 * Remap the memory mapped I/O space described by the @res and the CPU
3938 * physical address @phys_addr into virtual address space. Only
3939 * architectures that have memory mapped IO functions defined (and the
3940 * PCI_IOBASE value defined) should call this function.
3942 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3944 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3945 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3947 if (!(res->flags & IORESOURCE_IO))
3950 if (res->end > IO_SPACE_LIMIT)
3953 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3954 pgprot_device(PAGE_KERNEL));
3957 * This architecture does not have memory mapped I/O space,
3958 * so this function should never be called
3960 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3964 EXPORT_SYMBOL(pci_remap_iospace);
3967 * pci_unmap_iospace - Unmap the memory mapped I/O space
3968 * @res: resource to be unmapped
3970 * Unmap the CPU virtual address @res from virtual address space. Only
3971 * architectures that have memory mapped IO functions defined (and the
3972 * PCI_IOBASE value defined) should call this function.
3974 void pci_unmap_iospace(struct resource *res)
3976 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3977 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3979 unmap_kernel_range(vaddr, resource_size(res));
3982 EXPORT_SYMBOL(pci_unmap_iospace);
3984 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
3986 struct resource **res = ptr;
3988 pci_unmap_iospace(*res);
3992 * devm_pci_remap_iospace - Managed pci_remap_iospace()
3993 * @dev: Generic device to remap IO address for
3994 * @res: Resource describing the I/O space
3995 * @phys_addr: physical address of range to be mapped
3997 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4000 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4001 phys_addr_t phys_addr)
4003 const struct resource **ptr;
4006 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4010 error = pci_remap_iospace(res, phys_addr);
4015 devres_add(dev, ptr);
4020 EXPORT_SYMBOL(devm_pci_remap_iospace);
4023 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4024 * @dev: Generic device to remap IO address for
4025 * @offset: Resource address to map
4026 * @size: Size of map
4028 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4031 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4032 resource_size_t offset,
4033 resource_size_t size)
4035 void __iomem **ptr, *addr;
4037 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4041 addr = pci_remap_cfgspace(offset, size);
4044 devres_add(dev, ptr);
4050 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4053 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4054 * @dev: generic device to handle the resource for
4055 * @res: configuration space resource to be handled
4057 * Checks that a resource is a valid memory region, requests the memory
4058 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4059 * proper PCI configuration space memory attributes are guaranteed.
4061 * All operations are managed and will be undone on driver detach.
4063 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4064 * on failure. Usage example::
4066 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4067 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4069 * return PTR_ERR(base);
4071 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4072 struct resource *res)
4074 resource_size_t size;
4076 void __iomem *dest_ptr;
4080 if (!res || resource_type(res) != IORESOURCE_MEM) {
4081 dev_err(dev, "invalid resource\n");
4082 return IOMEM_ERR_PTR(-EINVAL);
4085 size = resource_size(res);
4086 name = res->name ?: dev_name(dev);
4088 if (!devm_request_mem_region(dev, res->start, size, name)) {
4089 dev_err(dev, "can't request region for resource %pR\n", res);
4090 return IOMEM_ERR_PTR(-EBUSY);
4093 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4095 dev_err(dev, "ioremap failed for resource %pR\n", res);
4096 devm_release_mem_region(dev, res->start, size);
4097 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4102 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4104 static void __pci_set_master(struct pci_dev *dev, bool enable)
4108 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4110 cmd = old_cmd | PCI_COMMAND_MASTER;
4112 cmd = old_cmd & ~PCI_COMMAND_MASTER;
4113 if (cmd != old_cmd) {
4114 pci_dbg(dev, "%s bus mastering\n",
4115 enable ? "enabling" : "disabling");
4116 pci_write_config_word(dev, PCI_COMMAND, cmd);
4118 dev->is_busmaster = enable;
4122 * pcibios_setup - process "pci=" kernel boot arguments
4123 * @str: string used to pass in "pci=" kernel boot arguments
4125 * Process kernel boot arguments. This is the default implementation.
4126 * Architecture specific implementations can override this as necessary.
4128 char * __weak __init pcibios_setup(char *str)
4134 * pcibios_set_master - enable PCI bus-mastering for device dev
4135 * @dev: the PCI device to enable
4137 * Enables PCI bus-mastering for the device. This is the default
4138 * implementation. Architecture specific implementations can override
4139 * this if necessary.
4141 void __weak pcibios_set_master(struct pci_dev *dev)
4145 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4146 if (pci_is_pcie(dev))
4149 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4151 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4152 else if (lat > pcibios_max_latency)
4153 lat = pcibios_max_latency;
4157 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4161 * pci_set_master - enables bus-mastering for device dev
4162 * @dev: the PCI device to enable
4164 * Enables bus-mastering on the device and calls pcibios_set_master()
4165 * to do the needed arch specific settings.
4167 void pci_set_master(struct pci_dev *dev)
4169 __pci_set_master(dev, true);
4170 pcibios_set_master(dev);
4172 EXPORT_SYMBOL(pci_set_master);
4175 * pci_clear_master - disables bus-mastering for device dev
4176 * @dev: the PCI device to disable
4178 void pci_clear_master(struct pci_dev *dev)
4180 __pci_set_master(dev, false);
4182 EXPORT_SYMBOL(pci_clear_master);
4185 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4186 * @dev: the PCI device for which MWI is to be enabled
4188 * Helper function for pci_set_mwi.
4189 * Originally copied from drivers/net/acenic.c.
4190 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4192 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4194 int pci_set_cacheline_size(struct pci_dev *dev)
4198 if (!pci_cache_line_size)
4201 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4202 equal to or multiple of the right value. */
4203 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4204 if (cacheline_size >= pci_cache_line_size &&
4205 (cacheline_size % pci_cache_line_size) == 0)
4208 /* Write the correct value. */
4209 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4211 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4212 if (cacheline_size == pci_cache_line_size)
4215 pci_info(dev, "cache line size of %d is not supported\n",
4216 pci_cache_line_size << 2);
4220 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4223 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4224 * @dev: the PCI device for which MWI is enabled
4226 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4228 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4230 int pci_set_mwi(struct pci_dev *dev)
4232 #ifdef PCI_DISABLE_MWI
4238 rc = pci_set_cacheline_size(dev);
4242 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4243 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4244 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4245 cmd |= PCI_COMMAND_INVALIDATE;
4246 pci_write_config_word(dev, PCI_COMMAND, cmd);
4251 EXPORT_SYMBOL(pci_set_mwi);
4254 * pcim_set_mwi - a device-managed pci_set_mwi()
4255 * @dev: the PCI device for which MWI is enabled
4257 * Managed pci_set_mwi().
4259 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4261 int pcim_set_mwi(struct pci_dev *dev)
4263 struct pci_devres *dr;
4265 dr = find_pci_dr(dev);
4270 return pci_set_mwi(dev);
4272 EXPORT_SYMBOL(pcim_set_mwi);
4275 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4276 * @dev: the PCI device for which MWI is enabled
4278 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4279 * Callers are not required to check the return value.
4281 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4283 int pci_try_set_mwi(struct pci_dev *dev)
4285 #ifdef PCI_DISABLE_MWI
4288 return pci_set_mwi(dev);
4291 EXPORT_SYMBOL(pci_try_set_mwi);
4294 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4295 * @dev: the PCI device to disable
4297 * Disables PCI Memory-Write-Invalidate transaction on the device
4299 void pci_clear_mwi(struct pci_dev *dev)
4301 #ifndef PCI_DISABLE_MWI
4304 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4305 if (cmd & PCI_COMMAND_INVALIDATE) {
4306 cmd &= ~PCI_COMMAND_INVALIDATE;
4307 pci_write_config_word(dev, PCI_COMMAND, cmd);
4311 EXPORT_SYMBOL(pci_clear_mwi);
4314 * pci_intx - enables/disables PCI INTx for device dev
4315 * @pdev: the PCI device to operate on
4316 * @enable: boolean: whether to enable or disable PCI INTx
4318 * Enables/disables PCI INTx for device @pdev
4320 void pci_intx(struct pci_dev *pdev, int enable)
4322 u16 pci_command, new;
4324 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4327 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4329 new = pci_command | PCI_COMMAND_INTX_DISABLE;
4331 if (new != pci_command) {
4332 struct pci_devres *dr;
4334 pci_write_config_word(pdev, PCI_COMMAND, new);
4336 dr = find_pci_dr(pdev);
4337 if (dr && !dr->restore_intx) {
4338 dr->restore_intx = 1;
4339 dr->orig_intx = !enable;
4343 EXPORT_SYMBOL_GPL(pci_intx);
4345 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4347 struct pci_bus *bus = dev->bus;
4348 bool mask_updated = true;
4349 u32 cmd_status_dword;
4350 u16 origcmd, newcmd;
4351 unsigned long flags;
4355 * We do a single dword read to retrieve both command and status.
4356 * Document assumptions that make this possible.
4358 BUILD_BUG_ON(PCI_COMMAND % 4);
4359 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4361 raw_spin_lock_irqsave(&pci_lock, flags);
4363 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4365 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4368 * Check interrupt status register to see whether our device
4369 * triggered the interrupt (when masking) or the next IRQ is
4370 * already pending (when unmasking).
4372 if (mask != irq_pending) {
4373 mask_updated = false;
4377 origcmd = cmd_status_dword;
4378 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4380 newcmd |= PCI_COMMAND_INTX_DISABLE;
4381 if (newcmd != origcmd)
4382 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4385 raw_spin_unlock_irqrestore(&pci_lock, flags);
4387 return mask_updated;
4391 * pci_check_and_mask_intx - mask INTx on pending interrupt
4392 * @dev: the PCI device to operate on
4394 * Check if the device dev has its INTx line asserted, mask it and return
4395 * true in that case. False is returned if no interrupt was pending.
4397 bool pci_check_and_mask_intx(struct pci_dev *dev)
4399 return pci_check_and_set_intx_mask(dev, true);
4401 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4404 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4405 * @dev: the PCI device to operate on
4407 * Check if the device dev has its INTx line asserted, unmask it if not and
4408 * return true. False is returned and the mask remains active if there was
4409 * still an interrupt pending.
4411 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4413 return pci_check_and_set_intx_mask(dev, false);
4415 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4418 * pci_wait_for_pending_transaction - wait for pending transaction
4419 * @dev: the PCI device to operate on
4421 * Return 0 if transaction is pending 1 otherwise.
4423 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4425 if (!pci_is_pcie(dev))
4428 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4429 PCI_EXP_DEVSTA_TRPND);
4431 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4433 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
4439 * After reset, the device should not silently discard config
4440 * requests, but it may still indicate that it needs more time by
4441 * responding to them with CRS completions. The Root Port will
4442 * generally synthesize ~0 data to complete the read (except when
4443 * CRS SV is enabled and the read was for the Vendor ID; in that
4444 * case it synthesizes 0x0001 data).
4446 * Wait for the device to return a non-CRS completion. Read the
4447 * Command register instead of Vendor ID so we don't have to
4448 * contend with the CRS SV value.
4450 pci_read_config_dword(dev, PCI_COMMAND, &id);
4452 if (delay > timeout) {
4453 pci_warn(dev, "not ready %dms after %s; giving up\n",
4454 delay - 1, reset_type);
4459 pci_info(dev, "not ready %dms after %s; waiting\n",
4460 delay - 1, reset_type);
4464 pci_read_config_dword(dev, PCI_COMMAND, &id);
4468 pci_info(dev, "ready %dms after %s\n", delay - 1,
4475 * pcie_has_flr - check if a device supports function level resets
4476 * @dev: device to check
4478 * Returns true if the device advertises support for PCIe function level
4481 bool pcie_has_flr(struct pci_dev *dev)
4485 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4488 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
4489 return cap & PCI_EXP_DEVCAP_FLR;
4491 EXPORT_SYMBOL_GPL(pcie_has_flr);
4494 * pcie_flr - initiate a PCIe function level reset
4495 * @dev: device to reset
4497 * Initiate a function level reset on @dev. The caller should ensure the
4498 * device supports FLR before calling this function, e.g. by using the
4499 * pcie_has_flr() helper.
4501 int pcie_flr(struct pci_dev *dev)
4503 if (!pci_wait_for_pending_transaction(dev))
4504 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4506 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4512 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4513 * 100ms, but may silently discard requests while the FLR is in
4514 * progress. Wait 100ms before trying to access the device.
4518 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4520 EXPORT_SYMBOL_GPL(pcie_flr);
4522 static int pci_af_flr(struct pci_dev *dev, int probe)
4527 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4531 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4534 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4535 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4542 * Wait for Transaction Pending bit to clear. A word-aligned test
4543 * is used, so we use the control offset rather than status and shift
4544 * the test bit to match.
4546 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4547 PCI_AF_STATUS_TP << 8))
4548 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4550 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4556 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4557 * updated 27 July 2006; a device must complete an FLR within
4558 * 100ms, but may silently discard requests while the FLR is in
4559 * progress. Wait 100ms before trying to access the device.
4563 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4567 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4568 * @dev: Device to reset.
4569 * @probe: If set, only check if the device can be reset this way.
4571 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4572 * unset, it will be reinitialized internally when going from PCI_D3hot to
4573 * PCI_D0. If that's the case and the device is not in a low-power state
4574 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4576 * NOTE: This causes the caller to sleep for twice the device power transition
4577 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4578 * by default (i.e. unless the @dev's d3_delay field has a different value).
4579 * Moreover, only devices in D0 can be reset by this function.
4581 static int pci_pm_reset(struct pci_dev *dev, int probe)
4585 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4588 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4589 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4595 if (dev->current_state != PCI_D0)
4598 csr &= ~PCI_PM_CTRL_STATE_MASK;
4600 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4601 pci_dev_d3_sleep(dev);
4603 csr &= ~PCI_PM_CTRL_STATE_MASK;
4605 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4606 pci_dev_d3_sleep(dev);
4608 return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS);
4611 * pcie_wait_for_link - Wait until link is active or inactive
4612 * @pdev: Bridge device
4613 * @active: waiting for active or inactive?
4615 * Use this to wait till link becomes active or inactive.
4617 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4624 * Some controllers might not implement link active reporting. In this
4625 * case, we wait for 1000 + 100 ms.
4627 if (!pdev->link_active_reporting) {
4633 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4634 * after which we should expect an link active if the reset was
4635 * successful. If so, software must wait a minimum 100ms before sending
4636 * configuration requests to devices downstream this port.
4638 * If the link fails to activate, either the device was physically
4639 * removed or the link is permanently failed.
4644 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4645 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4655 else if (ret != active)
4656 pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n",
4657 active ? "set" : "cleared");
4658 return ret == active;
4661 void pci_reset_secondary_bus(struct pci_dev *dev)
4665 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4666 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4667 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4670 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4671 * this to 2ms to ensure that we meet the minimum requirement.
4675 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
4676 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4679 * Trhfa for conventional PCI is 2^25 clock cycles.
4680 * Assuming a minimum 33MHz clock this results in a 1s
4681 * delay before we can consider subordinate devices to
4682 * be re-initialized. PCIe has some ways to shorten this,
4683 * but we don't make use of them yet.
4688 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4690 pci_reset_secondary_bus(dev);
4694 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
4695 * @dev: Bridge device
4697 * Use the bridge control register to assert reset on the secondary bus.
4698 * Devices on the secondary bus are left in power-on state.
4700 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
4702 pcibios_reset_secondary_bus(dev);
4704 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
4706 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
4708 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4710 struct pci_dev *pdev;
4712 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4713 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4716 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4723 return pci_bridge_secondary_bus_reset(dev->bus->self);
4726 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
4730 if (!hotplug || !try_module_get(hotplug->owner))
4733 if (hotplug->ops->reset_slot)
4734 rc = hotplug->ops->reset_slot(hotplug, probe);
4736 module_put(hotplug->owner);
4741 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
4743 struct pci_dev *pdev;
4745 if (dev->subordinate || !dev->slot ||
4746 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4749 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4750 if (pdev != dev && pdev->slot == dev->slot)
4753 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
4756 static void pci_dev_lock(struct pci_dev *dev)
4758 pci_cfg_access_lock(dev);
4759 /* block PM suspend, driver probe, etc. */
4760 device_lock(&dev->dev);
4763 /* Return 1 on successful lock, 0 on contention */
4764 static int pci_dev_trylock(struct pci_dev *dev)
4766 if (pci_cfg_access_trylock(dev)) {
4767 if (device_trylock(&dev->dev))
4769 pci_cfg_access_unlock(dev);
4775 static void pci_dev_unlock(struct pci_dev *dev)
4777 device_unlock(&dev->dev);
4778 pci_cfg_access_unlock(dev);
4781 static void pci_dev_save_and_disable(struct pci_dev *dev)
4783 const struct pci_error_handlers *err_handler =
4784 dev->driver ? dev->driver->err_handler : NULL;
4787 * dev->driver->err_handler->reset_prepare() is protected against
4788 * races with ->remove() by the device lock, which must be held by
4791 if (err_handler && err_handler->reset_prepare)
4792 err_handler->reset_prepare(dev);
4795 * Wake-up device prior to save. PM registers default to D0 after
4796 * reset and a simple register restore doesn't reliably return
4797 * to a non-D0 state anyway.
4799 pci_set_power_state(dev, PCI_D0);
4801 pci_save_state(dev);
4803 * Disable the device by clearing the Command register, except for
4804 * INTx-disable which is set. This not only disables MMIO and I/O port
4805 * BARs, but also prevents the device from being Bus Master, preventing
4806 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4807 * compliant devices, INTx-disable prevents legacy interrupts.
4809 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4812 static void pci_dev_restore(struct pci_dev *dev)
4814 const struct pci_error_handlers *err_handler =
4815 dev->driver ? dev->driver->err_handler : NULL;
4817 pci_restore_state(dev);
4820 * dev->driver->err_handler->reset_done() is protected against
4821 * races with ->remove() by the device lock, which must be held by
4824 if (err_handler && err_handler->reset_done)
4825 err_handler->reset_done(dev);
4829 * __pci_reset_function_locked - reset a PCI device function while holding
4830 * the @dev mutex lock.
4831 * @dev: PCI device to reset
4833 * Some devices allow an individual function to be reset without affecting
4834 * other functions in the same device. The PCI device must be responsive
4835 * to PCI config space in order to use this function.
4837 * The device function is presumed to be unused and the caller is holding
4838 * the device mutex lock when this function is called.
4840 * Resetting the device will make the contents of PCI configuration space
4841 * random, so any caller of this must be prepared to reinitialise the
4842 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4845 * Returns 0 if the device function was successfully reset or negative if the
4846 * device doesn't support resetting a single function.
4848 int __pci_reset_function_locked(struct pci_dev *dev)
4855 * A reset method returns -ENOTTY if it doesn't support this device
4856 * and we should try the next method.
4858 * If it returns 0 (success), we're finished. If it returns any
4859 * other error, we're also finished: this indicates that further
4860 * reset mechanisms might be broken on the device.
4862 rc = pci_dev_specific_reset(dev, 0);
4865 if (pcie_has_flr(dev)) {
4870 rc = pci_af_flr(dev, 0);
4873 rc = pci_pm_reset(dev, 0);
4876 rc = pci_dev_reset_slot_function(dev, 0);
4879 return pci_parent_bus_reset(dev, 0);
4881 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4884 * pci_probe_reset_function - check whether the device can be safely reset
4885 * @dev: PCI device to reset
4887 * Some devices allow an individual function to be reset without affecting
4888 * other functions in the same device. The PCI device must be responsive
4889 * to PCI config space in order to use this function.
4891 * Returns 0 if the device function can be reset or negative if the
4892 * device doesn't support resetting a single function.
4894 int pci_probe_reset_function(struct pci_dev *dev)
4900 rc = pci_dev_specific_reset(dev, 1);
4903 if (pcie_has_flr(dev))
4905 rc = pci_af_flr(dev, 1);
4908 rc = pci_pm_reset(dev, 1);
4911 rc = pci_dev_reset_slot_function(dev, 1);
4915 return pci_parent_bus_reset(dev, 1);
4919 * pci_reset_function - quiesce and reset a PCI device function
4920 * @dev: PCI device to reset
4922 * Some devices allow an individual function to be reset without affecting
4923 * other functions in the same device. The PCI device must be responsive
4924 * to PCI config space in order to use this function.
4926 * This function does not just reset the PCI portion of a device, but
4927 * clears all the state associated with the device. This function differs
4928 * from __pci_reset_function_locked() in that it saves and restores device state
4929 * over the reset and takes the PCI device lock.
4931 * Returns 0 if the device function was successfully reset or negative if the
4932 * device doesn't support resetting a single function.
4934 int pci_reset_function(struct pci_dev *dev)
4942 pci_dev_save_and_disable(dev);
4944 rc = __pci_reset_function_locked(dev);
4946 pci_dev_restore(dev);
4947 pci_dev_unlock(dev);
4951 EXPORT_SYMBOL_GPL(pci_reset_function);
4954 * pci_reset_function_locked - quiesce and reset a PCI device function
4955 * @dev: PCI device to reset
4957 * Some devices allow an individual function to be reset without affecting
4958 * other functions in the same device. The PCI device must be responsive
4959 * to PCI config space in order to use this function.
4961 * This function does not just reset the PCI portion of a device, but
4962 * clears all the state associated with the device. This function differs
4963 * from __pci_reset_function_locked() in that it saves and restores device state
4964 * over the reset. It also differs from pci_reset_function() in that it
4965 * requires the PCI device lock to be held.
4967 * Returns 0 if the device function was successfully reset or negative if the
4968 * device doesn't support resetting a single function.
4970 int pci_reset_function_locked(struct pci_dev *dev)
4977 pci_dev_save_and_disable(dev);
4979 rc = __pci_reset_function_locked(dev);
4981 pci_dev_restore(dev);
4985 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
4988 * pci_try_reset_function - quiesce and reset a PCI device function
4989 * @dev: PCI device to reset
4991 * Same as above, except return -EAGAIN if unable to lock device.
4993 int pci_try_reset_function(struct pci_dev *dev)
5000 if (!pci_dev_trylock(dev))
5003 pci_dev_save_and_disable(dev);
5004 rc = __pci_reset_function_locked(dev);
5005 pci_dev_restore(dev);
5006 pci_dev_unlock(dev);
5010 EXPORT_SYMBOL_GPL(pci_try_reset_function);
5012 /* Do any devices on or below this bus prevent a bus reset? */
5013 static bool pci_bus_resetable(struct pci_bus *bus)
5015 struct pci_dev *dev;
5018 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5021 list_for_each_entry(dev, &bus->devices, bus_list) {
5022 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5023 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5030 /* Lock devices from the top of the tree down */
5031 static void pci_bus_lock(struct pci_bus *bus)
5033 struct pci_dev *dev;
5035 list_for_each_entry(dev, &bus->devices, bus_list) {
5037 if (dev->subordinate)
5038 pci_bus_lock(dev->subordinate);
5042 /* Unlock devices from the bottom of the tree up */
5043 static void pci_bus_unlock(struct pci_bus *bus)
5045 struct pci_dev *dev;
5047 list_for_each_entry(dev, &bus->devices, bus_list) {
5048 if (dev->subordinate)
5049 pci_bus_unlock(dev->subordinate);
5050 pci_dev_unlock(dev);
5054 /* Return 1 on successful lock, 0 on contention */
5055 static int pci_bus_trylock(struct pci_bus *bus)
5057 struct pci_dev *dev;
5059 list_for_each_entry(dev, &bus->devices, bus_list) {
5060 if (!pci_dev_trylock(dev))
5062 if (dev->subordinate) {
5063 if (!pci_bus_trylock(dev->subordinate)) {
5064 pci_dev_unlock(dev);
5072 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5073 if (dev->subordinate)
5074 pci_bus_unlock(dev->subordinate);
5075 pci_dev_unlock(dev);
5080 /* Do any devices on or below this slot prevent a bus reset? */
5081 static bool pci_slot_resetable(struct pci_slot *slot)
5083 struct pci_dev *dev;
5085 if (slot->bus->self &&
5086 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5089 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5090 if (!dev->slot || dev->slot != slot)
5092 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5093 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5100 /* Lock devices from the top of the tree down */
5101 static void pci_slot_lock(struct pci_slot *slot)
5103 struct pci_dev *dev;
5105 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5106 if (!dev->slot || dev->slot != slot)
5109 if (dev->subordinate)
5110 pci_bus_lock(dev->subordinate);
5114 /* Unlock devices from the bottom of the tree up */
5115 static void pci_slot_unlock(struct pci_slot *slot)
5117 struct pci_dev *dev;
5119 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5120 if (!dev->slot || dev->slot != slot)
5122 if (dev->subordinate)
5123 pci_bus_unlock(dev->subordinate);
5124 pci_dev_unlock(dev);
5128 /* Return 1 on successful lock, 0 on contention */
5129 static int pci_slot_trylock(struct pci_slot *slot)
5131 struct pci_dev *dev;
5133 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5134 if (!dev->slot || dev->slot != slot)
5136 if (!pci_dev_trylock(dev))
5138 if (dev->subordinate) {
5139 if (!pci_bus_trylock(dev->subordinate)) {
5140 pci_dev_unlock(dev);
5148 list_for_each_entry_continue_reverse(dev,
5149 &slot->bus->devices, bus_list) {
5150 if (!dev->slot || dev->slot != slot)
5152 if (dev->subordinate)
5153 pci_bus_unlock(dev->subordinate);
5154 pci_dev_unlock(dev);
5160 * Save and disable devices from the top of the tree down while holding
5161 * the @dev mutex lock for the entire tree.
5163 static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5165 struct pci_dev *dev;
5167 list_for_each_entry(dev, &bus->devices, bus_list) {
5168 pci_dev_save_and_disable(dev);
5169 if (dev->subordinate)
5170 pci_bus_save_and_disable_locked(dev->subordinate);
5175 * Restore devices from top of the tree down while holding @dev mutex lock
5176 * for the entire tree. Parent bridges need to be restored before we can
5177 * get to subordinate devices.
5179 static void pci_bus_restore_locked(struct pci_bus *bus)
5181 struct pci_dev *dev;
5183 list_for_each_entry(dev, &bus->devices, bus_list) {
5184 pci_dev_restore(dev);
5185 if (dev->subordinate)
5186 pci_bus_restore_locked(dev->subordinate);
5191 * Save and disable devices from the top of the tree down while holding
5192 * the @dev mutex lock for the entire tree.
5194 static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
5196 struct pci_dev *dev;
5198 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5199 if (!dev->slot || dev->slot != slot)
5201 pci_dev_save_and_disable(dev);
5202 if (dev->subordinate)
5203 pci_bus_save_and_disable_locked(dev->subordinate);
5208 * Restore devices from top of the tree down while holding @dev mutex lock
5209 * for the entire tree. Parent bridges need to be restored before we can
5210 * get to subordinate devices.
5212 static void pci_slot_restore_locked(struct pci_slot *slot)
5214 struct pci_dev *dev;
5216 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5217 if (!dev->slot || dev->slot != slot)
5219 pci_dev_restore(dev);
5220 if (dev->subordinate)
5221 pci_bus_restore_locked(dev->subordinate);
5225 static int pci_slot_reset(struct pci_slot *slot, int probe)
5229 if (!slot || !pci_slot_resetable(slot))
5233 pci_slot_lock(slot);
5237 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5240 pci_slot_unlock(slot);
5246 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5247 * @slot: PCI slot to probe
5249 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5251 int pci_probe_reset_slot(struct pci_slot *slot)
5253 return pci_slot_reset(slot, 1);
5255 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5258 * __pci_reset_slot - Try to reset a PCI slot
5259 * @slot: PCI slot to reset
5261 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5262 * independent of other slots. For instance, some slots may support slot power
5263 * control. In the case of a 1:1 bus to slot architecture, this function may
5264 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5265 * Generally a slot reset should be attempted before a bus reset. All of the
5266 * function of the slot and any subordinate buses behind the slot are reset
5267 * through this function. PCI config space of all devices in the slot and
5268 * behind the slot is saved before and restored after reset.
5270 * Same as above except return -EAGAIN if the slot cannot be locked
5272 static int __pci_reset_slot(struct pci_slot *slot)
5276 rc = pci_slot_reset(slot, 1);
5280 if (pci_slot_trylock(slot)) {
5281 pci_slot_save_and_disable_locked(slot);
5283 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
5284 pci_slot_restore_locked(slot);
5285 pci_slot_unlock(slot);
5292 static int pci_bus_reset(struct pci_bus *bus, int probe)
5296 if (!bus->self || !pci_bus_resetable(bus))
5306 ret = pci_bridge_secondary_bus_reset(bus->self);
5308 pci_bus_unlock(bus);
5314 * pci_bus_error_reset - reset the bridge's subordinate bus
5315 * @bridge: The parent device that connects to the bus to reset
5317 * This function will first try to reset the slots on this bus if the method is
5318 * available. If slot reset fails or is not available, this will fall back to a
5319 * secondary bus reset.
5321 int pci_bus_error_reset(struct pci_dev *bridge)
5323 struct pci_bus *bus = bridge->subordinate;
5324 struct pci_slot *slot;
5329 mutex_lock(&pci_slot_mutex);
5330 if (list_empty(&bus->slots))
5333 list_for_each_entry(slot, &bus->slots, list)
5334 if (pci_probe_reset_slot(slot))
5337 list_for_each_entry(slot, &bus->slots, list)
5338 if (pci_slot_reset(slot, 0))
5341 mutex_unlock(&pci_slot_mutex);
5344 mutex_unlock(&pci_slot_mutex);
5345 return pci_bus_reset(bridge->subordinate, 0);
5349 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5350 * @bus: PCI bus to probe
5352 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5354 int pci_probe_reset_bus(struct pci_bus *bus)
5356 return pci_bus_reset(bus, 1);
5358 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
5361 * __pci_reset_bus - Try to reset a PCI bus
5362 * @bus: top level PCI bus to reset
5364 * Same as above except return -EAGAIN if the bus cannot be locked
5366 static int __pci_reset_bus(struct pci_bus *bus)
5370 rc = pci_bus_reset(bus, 1);
5374 if (pci_bus_trylock(bus)) {
5375 pci_bus_save_and_disable_locked(bus);
5377 rc = pci_bridge_secondary_bus_reset(bus->self);
5378 pci_bus_restore_locked(bus);
5379 pci_bus_unlock(bus);
5387 * pci_reset_bus - Try to reset a PCI bus
5388 * @pdev: top level PCI device to reset via slot/bus
5390 * Same as above except return -EAGAIN if the bus cannot be locked
5392 int pci_reset_bus(struct pci_dev *pdev)
5394 return (!pci_probe_reset_slot(pdev->slot)) ?
5395 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
5397 EXPORT_SYMBOL_GPL(pci_reset_bus);
5400 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5401 * @dev: PCI device to query
5403 * Returns mmrbc: maximum designed memory read count in bytes or
5404 * appropriate error value.
5406 int pcix_get_max_mmrbc(struct pci_dev *dev)
5411 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5415 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5418 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5420 EXPORT_SYMBOL(pcix_get_max_mmrbc);
5423 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5424 * @dev: PCI device to query
5426 * Returns mmrbc: maximum memory read count in bytes or appropriate error
5429 int pcix_get_mmrbc(struct pci_dev *dev)
5434 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5438 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5441 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5443 EXPORT_SYMBOL(pcix_get_mmrbc);
5446 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5447 * @dev: PCI device to query
5448 * @mmrbc: maximum memory read count in bytes
5449 * valid values are 512, 1024, 2048, 4096
5451 * If possible sets maximum memory read byte count, some bridges have errata
5452 * that prevent this.
5454 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5460 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5463 v = ffs(mmrbc) - 10;
5465 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5469 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5472 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5475 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5478 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5480 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5483 cmd &= ~PCI_X_CMD_MAX_READ;
5485 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5490 EXPORT_SYMBOL(pcix_set_mmrbc);
5493 * pcie_get_readrq - get PCI Express read request size
5494 * @dev: PCI device to query
5496 * Returns maximum memory read request in bytes or appropriate error value.
5498 int pcie_get_readrq(struct pci_dev *dev)
5502 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5504 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5506 EXPORT_SYMBOL(pcie_get_readrq);
5509 * pcie_set_readrq - set PCI Express maximum memory read request
5510 * @dev: PCI device to query
5511 * @rq: maximum memory read count in bytes
5512 * valid values are 128, 256, 512, 1024, 2048, 4096
5514 * If possible sets maximum memory read request in bytes
5516 int pcie_set_readrq(struct pci_dev *dev, int rq)
5520 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5524 * If using the "performance" PCIe config, we clamp the read rq
5525 * size to the max packet size to keep the host bridge from
5526 * generating requests larger than we can cope with.
5528 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5529 int mps = pcie_get_mps(dev);
5535 v = (ffs(rq) - 8) << 12;
5537 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5538 PCI_EXP_DEVCTL_READRQ, v);
5540 EXPORT_SYMBOL(pcie_set_readrq);
5543 * pcie_get_mps - get PCI Express maximum payload size
5544 * @dev: PCI device to query
5546 * Returns maximum payload size in bytes
5548 int pcie_get_mps(struct pci_dev *dev)
5552 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5554 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5556 EXPORT_SYMBOL(pcie_get_mps);
5559 * pcie_set_mps - set PCI Express maximum payload size
5560 * @dev: PCI device to query
5561 * @mps: maximum payload size in bytes
5562 * valid values are 128, 256, 512, 1024, 2048, 4096
5564 * If possible sets maximum payload size
5566 int pcie_set_mps(struct pci_dev *dev, int mps)
5570 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
5574 if (v > dev->pcie_mpss)
5578 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5579 PCI_EXP_DEVCTL_PAYLOAD, v);
5581 EXPORT_SYMBOL(pcie_set_mps);
5584 * pcie_bandwidth_available - determine minimum link settings of a PCIe
5585 * device and its bandwidth limitation
5586 * @dev: PCI device to query
5587 * @limiting_dev: storage for device causing the bandwidth limitation
5588 * @speed: storage for speed of limiting device
5589 * @width: storage for width of limiting device
5591 * Walk up the PCI device chain and find the point where the minimum
5592 * bandwidth is available. Return the bandwidth available there and (if
5593 * limiting_dev, speed, and width pointers are supplied) information about
5594 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
5597 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
5598 enum pci_bus_speed *speed,
5599 enum pcie_link_width *width)
5602 enum pci_bus_speed next_speed;
5603 enum pcie_link_width next_width;
5607 *speed = PCI_SPEED_UNKNOWN;
5609 *width = PCIE_LNK_WIDTH_UNKNOWN;
5614 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
5616 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
5617 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
5618 PCI_EXP_LNKSTA_NLW_SHIFT;
5620 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
5622 /* Check if current device limits the total bandwidth */
5623 if (!bw || next_bw <= bw) {
5627 *limiting_dev = dev;
5629 *speed = next_speed;
5631 *width = next_width;
5634 dev = pci_upstream_bridge(dev);
5639 EXPORT_SYMBOL(pcie_bandwidth_available);
5642 * pcie_get_speed_cap - query for the PCI device's link speed capability
5643 * @dev: PCI device to query
5645 * Query the PCI device speed capability. Return the maximum link speed
5646 * supported by the device.
5648 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
5650 u32 lnkcap2, lnkcap;
5653 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
5654 * implementation note there recommends using the Supported Link
5655 * Speeds Vector in Link Capabilities 2 when supported.
5657 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
5658 * should use the Supported Link Speeds field in Link Capabilities,
5659 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
5661 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
5662 if (lnkcap2) { /* PCIe r3.0-compliant */
5663 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB)
5664 return PCIE_SPEED_32_0GT;
5665 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
5666 return PCIE_SPEED_16_0GT;
5667 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
5668 return PCIE_SPEED_8_0GT;
5669 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
5670 return PCIE_SPEED_5_0GT;
5671 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
5672 return PCIE_SPEED_2_5GT;
5673 return PCI_SPEED_UNKNOWN;
5676 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5677 if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
5678 return PCIE_SPEED_5_0GT;
5679 else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
5680 return PCIE_SPEED_2_5GT;
5682 return PCI_SPEED_UNKNOWN;
5684 EXPORT_SYMBOL(pcie_get_speed_cap);
5687 * pcie_get_width_cap - query for the PCI device's link width capability
5688 * @dev: PCI device to query
5690 * Query the PCI device width capability. Return the maximum link width
5691 * supported by the device.
5693 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
5697 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5699 return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
5701 return PCIE_LNK_WIDTH_UNKNOWN;
5703 EXPORT_SYMBOL(pcie_get_width_cap);
5706 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
5708 * @speed: storage for link speed
5709 * @width: storage for link width
5711 * Calculate a PCI device's link bandwidth by querying for its link speed
5712 * and width, multiplying them, and applying encoding overhead. The result
5713 * is in Mb/s, i.e., megabits/second of raw bandwidth.
5715 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
5716 enum pcie_link_width *width)
5718 *speed = pcie_get_speed_cap(dev);
5719 *width = pcie_get_width_cap(dev);
5721 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
5724 return *width * PCIE_SPEED2MBS_ENC(*speed);
5728 * __pcie_print_link_status - Report the PCI device's link speed and width
5729 * @dev: PCI device to query
5730 * @verbose: Print info even when enough bandwidth is available
5732 * If the available bandwidth at the device is less than the device is
5733 * capable of, report the device's maximum possible bandwidth and the
5734 * upstream link that limits its performance. If @verbose, always print
5735 * the available bandwidth, even if the device isn't constrained.
5737 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
5739 enum pcie_link_width width, width_cap;
5740 enum pci_bus_speed speed, speed_cap;
5741 struct pci_dev *limiting_dev = NULL;
5742 u32 bw_avail, bw_cap;
5744 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
5745 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
5747 if (bw_avail >= bw_cap && verbose)
5748 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
5749 bw_cap / 1000, bw_cap % 1000,
5750 PCIE_SPEED2STR(speed_cap), width_cap);
5751 else if (bw_avail < bw_cap)
5752 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
5753 bw_avail / 1000, bw_avail % 1000,
5754 PCIE_SPEED2STR(speed), width,
5755 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
5756 bw_cap / 1000, bw_cap % 1000,
5757 PCIE_SPEED2STR(speed_cap), width_cap);
5761 * pcie_print_link_status - Report the PCI device's link speed and width
5762 * @dev: PCI device to query
5764 * Report the available bandwidth at the device.
5766 void pcie_print_link_status(struct pci_dev *dev)
5768 __pcie_print_link_status(dev, true);
5770 EXPORT_SYMBOL(pcie_print_link_status);
5773 * pci_select_bars - Make BAR mask from the type of resource
5774 * @dev: the PCI device for which BAR mask is made
5775 * @flags: resource type mask to be selected
5777 * This helper routine makes bar mask from the type of resource.
5779 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
5782 for (i = 0; i < PCI_NUM_RESOURCES; i++)
5783 if (pci_resource_flags(dev, i) & flags)
5787 EXPORT_SYMBOL(pci_select_bars);
5789 /* Some architectures require additional programming to enable VGA */
5790 static arch_set_vga_state_t arch_set_vga_state;
5792 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
5794 arch_set_vga_state = func; /* NULL disables */
5797 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
5798 unsigned int command_bits, u32 flags)
5800 if (arch_set_vga_state)
5801 return arch_set_vga_state(dev, decode, command_bits,
5807 * pci_set_vga_state - set VGA decode state on device and parents if requested
5808 * @dev: the PCI device
5809 * @decode: true = enable decoding, false = disable decoding
5810 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
5811 * @flags: traverse ancestors and change bridges
5812 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
5814 int pci_set_vga_state(struct pci_dev *dev, bool decode,
5815 unsigned int command_bits, u32 flags)
5817 struct pci_bus *bus;
5818 struct pci_dev *bridge;
5822 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
5824 /* ARCH specific VGA enables */
5825 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
5829 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
5830 pci_read_config_word(dev, PCI_COMMAND, &cmd);
5832 cmd |= command_bits;
5834 cmd &= ~command_bits;
5835 pci_write_config_word(dev, PCI_COMMAND, cmd);
5838 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
5845 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
5848 cmd |= PCI_BRIDGE_CTL_VGA;
5850 cmd &= ~PCI_BRIDGE_CTL_VGA;
5851 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
5860 * pci_add_dma_alias - Add a DMA devfn alias for a device
5861 * @dev: the PCI device for which alias is added
5862 * @devfn: alias slot and function
5864 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
5865 * which is used to program permissible bus-devfn source addresses for DMA
5866 * requests in an IOMMU. These aliases factor into IOMMU group creation
5867 * and are useful for devices generating DMA requests beyond or different
5868 * from their logical bus-devfn. Examples include device quirks where the
5869 * device simply uses the wrong devfn, as well as non-transparent bridges
5870 * where the alias may be a proxy for devices in another domain.
5872 * IOMMU group creation is performed during device discovery or addition,
5873 * prior to any potential DMA mapping and therefore prior to driver probing
5874 * (especially for userspace assigned devices where IOMMU group definition
5875 * cannot be left as a userspace activity). DMA aliases should therefore
5876 * be configured via quirks, such as the PCI fixup header quirk.
5878 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
5880 if (!dev->dma_alias_mask)
5881 dev->dma_alias_mask = bitmap_zalloc(U8_MAX, GFP_KERNEL);
5882 if (!dev->dma_alias_mask) {
5883 pci_warn(dev, "Unable to allocate DMA alias mask\n");
5887 set_bit(devfn, dev->dma_alias_mask);
5888 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
5889 PCI_SLOT(devfn), PCI_FUNC(devfn));
5892 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
5894 return (dev1->dma_alias_mask &&
5895 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
5896 (dev2->dma_alias_mask &&
5897 test_bit(dev1->devfn, dev2->dma_alias_mask));
5900 bool pci_device_is_present(struct pci_dev *pdev)
5904 if (pci_dev_is_disconnected(pdev))
5906 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
5908 EXPORT_SYMBOL_GPL(pci_device_is_present);
5910 void pci_ignore_hotplug(struct pci_dev *dev)
5912 struct pci_dev *bridge = dev->bus->self;
5914 dev->ignore_hotplug = 1;
5915 /* Propagate the "ignore hotplug" setting to the parent bridge. */
5917 bridge->ignore_hotplug = 1;
5919 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
5921 resource_size_t __weak pcibios_default_alignment(void)
5927 * Arches that don't want to expose struct resource to userland as-is in
5928 * sysfs and /proc can implement their own pci_resource_to_user().
5930 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
5931 const struct resource *rsrc,
5932 resource_size_t *start, resource_size_t *end)
5934 *start = rsrc->start;
5938 static char *resource_alignment_param;
5939 static DEFINE_SPINLOCK(resource_alignment_lock);
5942 * pci_specified_resource_alignment - get resource alignment specified by user.
5943 * @dev: the PCI device to get
5944 * @resize: whether or not to change resources' size when reassigning alignment
5946 * RETURNS: Resource alignment if it is specified.
5947 * Zero if it is not specified.
5949 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
5952 int align_order, count;
5953 resource_size_t align = pcibios_default_alignment();
5957 spin_lock(&resource_alignment_lock);
5958 p = resource_alignment_param;
5961 if (pci_has_flag(PCI_PROBE_ONLY)) {
5963 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
5969 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
5976 ret = pci_dev_str_match(dev, p, &p);
5979 if (align_order == -1)
5982 align = 1 << align_order;
5984 } else if (ret < 0) {
5985 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
5990 if (*p != ';' && *p != ',') {
5991 /* End of param or invalid format */
5997 spin_unlock(&resource_alignment_lock);
6001 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6002 resource_size_t align, bool resize)
6004 struct resource *r = &dev->resource[bar];
6005 resource_size_t size;
6007 if (!(r->flags & IORESOURCE_MEM))
6010 if (r->flags & IORESOURCE_PCI_FIXED) {
6011 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
6012 bar, r, (unsigned long long)align);
6016 size = resource_size(r);
6021 * Increase the alignment of the resource. There are two ways we
6024 * 1) Increase the size of the resource. BARs are aligned on their
6025 * size, so when we reallocate space for this resource, we'll
6026 * allocate it with the larger alignment. This also prevents
6027 * assignment of any other BARs inside the alignment region, so
6028 * if we're requesting page alignment, this means no other BARs
6029 * will share the page.
6031 * The disadvantage is that this makes the resource larger than
6032 * the hardware BAR, which may break drivers that compute things
6033 * based on the resource size, e.g., to find registers at a
6034 * fixed offset before the end of the BAR.
6036 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6037 * set r->start to the desired alignment. By itself this
6038 * doesn't prevent other BARs being put inside the alignment
6039 * region, but if we realign *every* resource of every device in
6040 * the system, none of them will share an alignment region.
6042 * When the user has requested alignment for only some devices via
6043 * the "pci=resource_alignment" argument, "resize" is true and we
6044 * use the first method. Otherwise we assume we're aligning all
6045 * devices and we use the second.
6048 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
6049 bar, r, (unsigned long long)align);
6055 r->flags &= ~IORESOURCE_SIZEALIGN;
6056 r->flags |= IORESOURCE_STARTALIGN;
6058 r->end = r->start + size - 1;
6060 r->flags |= IORESOURCE_UNSET;
6064 * This function disables memory decoding and releases memory resources
6065 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6066 * It also rounds up size to specified alignment.
6067 * Later on, the kernel will assign page-aligned memory resource back
6070 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6074 resource_size_t align;
6076 bool resize = false;
6079 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6080 * 3.4.1.11. Their resources are allocated from the space
6081 * described by the VF BARx register in the PF's SR-IOV capability.
6082 * We can't influence their alignment here.
6087 /* check if specified PCI is target device to reassign */
6088 align = pci_specified_resource_alignment(dev, &resize);
6092 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6093 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6094 pci_warn(dev, "Can't reassign resources to host bridge\n");
6098 pci_read_config_word(dev, PCI_COMMAND, &command);
6099 command &= ~PCI_COMMAND_MEMORY;
6100 pci_write_config_word(dev, PCI_COMMAND, command);
6102 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
6103 pci_request_resource_alignment(dev, i, align, resize);
6106 * Need to disable bridge's resource window,
6107 * to enable the kernel to reassign new resource
6110 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6111 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6112 r = &dev->resource[i];
6113 if (!(r->flags & IORESOURCE_MEM))
6115 r->flags |= IORESOURCE_UNSET;
6116 r->end = resource_size(r) - 1;
6119 pci_disable_bridge_window(dev);
6123 static ssize_t resource_alignment_show(struct bus_type *bus, char *buf)
6127 spin_lock(&resource_alignment_lock);
6128 if (resource_alignment_param)
6129 count = snprintf(buf, PAGE_SIZE, "%s", resource_alignment_param);
6130 spin_unlock(&resource_alignment_lock);
6133 * When set by the command line, resource_alignment_param will not
6134 * have a trailing line feed, which is ugly. So conditionally add
6137 if (count >= 2 && buf[count - 2] != '\n' && count < PAGE_SIZE - 1) {
6138 buf[count - 1] = '\n';
6145 static ssize_t resource_alignment_store(struct bus_type *bus,
6146 const char *buf, size_t count)
6148 char *param = kstrndup(buf, count, GFP_KERNEL);
6153 spin_lock(&resource_alignment_lock);
6154 kfree(resource_alignment_param);
6155 resource_alignment_param = param;
6156 spin_unlock(&resource_alignment_lock);
6160 static BUS_ATTR_RW(resource_alignment);
6162 static int __init pci_resource_alignment_sysfs_init(void)
6164 return bus_create_file(&pci_bus_type,
6165 &bus_attr_resource_alignment);
6167 late_initcall(pci_resource_alignment_sysfs_init);
6169 static void pci_no_domains(void)
6171 #ifdef CONFIG_PCI_DOMAINS
6172 pci_domains_supported = 0;
6176 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6177 static atomic_t __domain_nr = ATOMIC_INIT(-1);
6179 static int pci_get_new_domain_nr(void)
6181 return atomic_inc_return(&__domain_nr);
6184 static int of_pci_bus_find_domain_nr(struct device *parent)
6186 static int use_dt_domains = -1;
6190 domain = of_get_pci_domain_nr(parent->of_node);
6193 * Check DT domain and use_dt_domains values.
6195 * If DT domain property is valid (domain >= 0) and
6196 * use_dt_domains != 0, the DT assignment is valid since this means
6197 * we have not previously allocated a domain number by using
6198 * pci_get_new_domain_nr(); we should also update use_dt_domains to
6199 * 1, to indicate that we have just assigned a domain number from
6202 * If DT domain property value is not valid (ie domain < 0), and we
6203 * have not previously assigned a domain number from DT
6204 * (use_dt_domains != 1) we should assign a domain number by
6207 * pci_get_new_domain_nr()
6209 * API and update the use_dt_domains value to keep track of method we
6210 * are using to assign domain numbers (use_dt_domains = 0).
6212 * All other combinations imply we have a platform that is trying
6213 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
6214 * which is a recipe for domain mishandling and it is prevented by
6215 * invalidating the domain value (domain = -1) and printing a
6216 * corresponding error.
6218 if (domain >= 0 && use_dt_domains) {
6220 } else if (domain < 0 && use_dt_domains != 1) {
6222 domain = pci_get_new_domain_nr();
6225 pr_err("Node %pOF has ", parent->of_node);
6226 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
6233 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
6235 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
6236 acpi_pci_bus_find_domain_nr(bus);
6241 * pci_ext_cfg_avail - can we access extended PCI config space?
6243 * Returns 1 if we can access PCI extended config space (offsets
6244 * greater than 0xff). This is the default implementation. Architecture
6245 * implementations can override this.
6247 int __weak pci_ext_cfg_avail(void)
6252 void __weak pci_fixup_cardbus(struct pci_bus *bus)
6255 EXPORT_SYMBOL(pci_fixup_cardbus);
6257 static int __init pci_setup(char *str)
6260 char *k = strchr(str, ',');
6263 if (*str && (str = pcibios_setup(str)) && *str) {
6264 if (!strcmp(str, "nomsi")) {
6266 } else if (!strncmp(str, "noats", 5)) {
6267 pr_info("PCIe: ATS is disabled\n");
6268 pcie_ats_disabled = true;
6269 } else if (!strcmp(str, "noaer")) {
6271 } else if (!strcmp(str, "earlydump")) {
6272 pci_early_dump = true;
6273 } else if (!strncmp(str, "realloc=", 8)) {
6274 pci_realloc_get_opt(str + 8);
6275 } else if (!strncmp(str, "realloc", 7)) {
6276 pci_realloc_get_opt("on");
6277 } else if (!strcmp(str, "nodomains")) {
6279 } else if (!strncmp(str, "noari", 5)) {
6280 pcie_ari_disabled = true;
6281 } else if (!strncmp(str, "cbiosize=", 9)) {
6282 pci_cardbus_io_size = memparse(str + 9, &str);
6283 } else if (!strncmp(str, "cbmemsize=", 10)) {
6284 pci_cardbus_mem_size = memparse(str + 10, &str);
6285 } else if (!strncmp(str, "resource_alignment=", 19)) {
6286 resource_alignment_param = str + 19;
6287 } else if (!strncmp(str, "ecrc=", 5)) {
6288 pcie_ecrc_get_policy(str + 5);
6289 } else if (!strncmp(str, "hpiosize=", 9)) {
6290 pci_hotplug_io_size = memparse(str + 9, &str);
6291 } else if (!strncmp(str, "hpmemsize=", 10)) {
6292 pci_hotplug_mem_size = memparse(str + 10, &str);
6293 } else if (!strncmp(str, "hpbussize=", 10)) {
6294 pci_hotplug_bus_size =
6295 simple_strtoul(str + 10, &str, 0);
6296 if (pci_hotplug_bus_size > 0xff)
6297 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
6298 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
6299 pcie_bus_config = PCIE_BUS_TUNE_OFF;
6300 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
6301 pcie_bus_config = PCIE_BUS_SAFE;
6302 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
6303 pcie_bus_config = PCIE_BUS_PERFORMANCE;
6304 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
6305 pcie_bus_config = PCIE_BUS_PEER2PEER;
6306 } else if (!strncmp(str, "pcie_scan_all", 13)) {
6307 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
6308 } else if (!strncmp(str, "disable_acs_redir=", 18)) {
6309 disable_acs_redir_param = str + 18;
6311 pr_err("PCI: Unknown option `%s'\n", str);
6318 early_param("pci", pci_setup);
6321 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6322 * in pci_setup(), above, to point to data in the __initdata section which
6323 * will be freed after the init sequence is complete. We can't allocate memory
6324 * in pci_setup() because some architectures do not have any memory allocation
6325 * service available during an early_param() call. So we allocate memory and
6326 * copy the variable here before the init section is freed.
6329 static int __init pci_realloc_setup_params(void)
6331 resource_alignment_param = kstrdup(resource_alignment_param,
6333 disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
6337 pure_initcall(pci_realloc_setup_params);