1 # SPDX-License-Identifier: GPL-2.0
3 # PCI Express Port Bus Configuration
6 bool "PCI Express Port Bus support"
8 This enables PCI Express Port Bus support. Users can then enable
9 support for Native Hot-Plug, Advanced Error Reporting, Power
10 Management Events, and Downstream Port Containment.
13 # Include service Kconfig here
15 config HOTPLUG_PCI_PCIE
16 bool "PCI Express Hotplug driver"
17 depends on HOTPLUG_PCI && PCIEPORTBUS
19 Say Y here if you have a motherboard that supports PCI Express Native
25 bool "PCI Express Advanced Error Reporting support"
26 depends on PCIEPORTBUS
30 This enables PCI Express Root Port Advanced Error Reporting
31 (AER) driver support. Error reporting messages sent to Root
32 Port will be handled by PCI Express AER driver.
35 tristate "PCI Express error injection support"
38 This enables PCI Express Root Port Advanced Error Reporting
39 (AER) software error injector.
41 Debugging AER code is quite difficult because it is hard
42 to trigger various real hardware errors. Software-based
43 error injection can fake almost all kinds of errors with the
44 help of a user space helper tool aer-inject, which can be
46 http://www.kernel.org/pub/linux/utils/pci/aer-inject/
52 bool "PCI Express ECRC settings control"
55 Used to override firmware/bios settings for PCI Express ECRC
56 (transaction layer end-to-end CRC checking).
64 bool "PCI Express ASPM control" if EXPERT
67 This enables OS control over PCI Express ASPM (Active State
68 Power Management) and Clock Power Management. ASPM supports
71 ASPM is initially set up by the firmware. With this option enabled,
72 Linux can modify this state in order to disable ASPM on known-bad
73 hardware or configurations and enable it when known-safe.
75 ASPM can be disabled or enabled at runtime via
76 /sys/module/pcie_aspm/parameters/policy
81 bool "Debug PCI Express ASPM"
84 This enables PCI Express ASPM debug support. It will add per-device
85 interface to control ASPM.
88 prompt "Default ASPM policy"
89 default PCIEASPM_DEFAULT
92 config PCIEASPM_DEFAULT
96 Use the BIOS defaults for PCI Express ASPM.
98 config PCIEASPM_POWERSAVE
102 Enable PCI Express ASPM L0s and L1 where possible, even if the
105 config PCIEASPM_POWER_SUPERSAVE
106 bool "Power Supersave"
109 Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where
110 possible. This would result in higher power savings while staying in L1
111 where the components support it.
113 config PCIEASPM_PERFORMANCE
117 Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
122 depends on PCIEPORTBUS && PM
125 bool "PCI Express Downstream Port Containment support"
126 depends on PCIEPORTBUS && PCIEAER
128 This enables PCI Express Downstream Port Containment (DPC)
129 driver support. DPC events from Root and Downstream ports
130 will be handled by the DPC driver. If your system doesn't
131 have this capability or you do not want to use this feature,
132 it is safe to answer N.
135 bool "PCI Express Precision Time Measurement support"
137 This enables PCI Express Precision Time Measurement (PTM)
140 This is only useful if you have devices that support PTM, but it
141 is safe to enable even if you don't.
144 bool "PCI Express Bandwidth Change Notification"
145 depends on PCIEPORTBUS
147 This enables PCI Express Bandwidth Change Notification. If
148 you know link width or rate changes occur only to correct
149 unreliable links, you may answer Y.