1 # SPDX-License-Identifier: GPL-2.0
3 # PCI Express Port Bus Configuration
6 bool "PCI Express Port Bus support"
9 This enables PCI Express Port Bus support. Users can then enable
10 support for Native Hot-Plug, Advanced Error Reporting, Power
11 Management Events, and Downstream Port Containment.
14 # Include service Kconfig here
16 config HOTPLUG_PCI_PCIE
17 bool "PCI Express Hotplug driver"
18 depends on HOTPLUG_PCI && PCIEPORTBUS
20 Say Y here if you have a motherboard that supports PCI Express Native
26 bool "PCI Express Advanced Error Reporting support"
27 depends on PCIEPORTBUS
31 This enables PCI Express Root Port Advanced Error Reporting
32 (AER) driver support. Error reporting messages sent to Root
33 Port will be handled by PCI Express AER driver.
36 tristate "PCI Express error injection support"
39 This enables PCI Express Root Port Advanced Error Reporting
40 (AER) software error injector.
42 Debugging AER code is quite difficult because it is hard
43 to trigger various real hardware errors. Software-based
44 error injection can fake almost all kinds of errors with the
45 help of a user space helper tool aer-inject, which can be
47 http://www.kernel.org/pub/linux/utils/pci/aer-inject/
53 bool "PCI Express ECRC settings control"
56 Used to override firmware/bios settings for PCI Express ECRC
57 (transaction layer end-to-end CRC checking).
65 bool "PCI Express ASPM control" if EXPERT
69 This enables OS control over PCI Express ASPM (Active State
70 Power Management) and Clock Power Management. ASPM supports
73 ASPM is initially set up by the firmware. With this option enabled,
74 Linux can modify this state in order to disable ASPM on known-bad
75 hardware or configurations and enable it when known-safe.
77 ASPM can be disabled or enabled at runtime via
78 /sys/module/pcie_aspm/parameters/policy
83 bool "Debug PCI Express ASPM"
86 This enables PCI Express ASPM debug support. It will add per-device
87 interface to control ASPM.
90 prompt "Default ASPM policy"
91 default PCIEASPM_DEFAULT
94 config PCIEASPM_DEFAULT
98 Use the BIOS defaults for PCI Express ASPM.
100 config PCIEASPM_POWERSAVE
104 Enable PCI Express ASPM L0s and L1 where possible, even if the
107 config PCIEASPM_POWER_SUPERSAVE
108 bool "Power Supersave"
111 Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where
112 possible. This would result in higher power savings while staying in L1
113 where the components support it.
115 config PCIEASPM_PERFORMANCE
119 Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
124 depends on PCIEPORTBUS && PM
127 bool "PCI Express Downstream Port Containment support"
128 depends on PCIEPORTBUS && PCIEAER
130 This enables PCI Express Downstream Port Containment (DPC)
131 driver support. DPC events from Root and Downstream ports
132 will be handled by the DPC driver. If your system doesn't
133 have this capability or you do not want to use this feature,
134 it is safe to answer N.
137 bool "PCI Express Precision Time Measurement support"
139 This enables PCI Express Precision Time Measurement (PTM)
142 This is only useful if you have devices that support PTM, but it
143 is safe to enable even if you don't.
146 bool "PCI Express Bandwidth Change Notification"
147 depends on PCIEPORTBUS
149 This enables PCI Express Bandwidth Change Notification. If
150 you know link width or rate changes occur only to correct
151 unreliable links, you may answer Y.