1 // SPDX-License-Identifier: GPL-2.0
3 * Enable PCIe link L0s/L1 state and Clock Power Management
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/pci_regs.h>
15 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/slab.h>
19 #include <linux/jiffies.h>
20 #include <linux/delay.h>
21 #include <linux/pci-aspm.h>
24 #ifdef MODULE_PARAM_PREFIX
25 #undef MODULE_PARAM_PREFIX
27 #define MODULE_PARAM_PREFIX "pcie_aspm."
29 /* Note: those are not register definitions */
30 #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
31 #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
32 #define ASPM_STATE_L1 (4) /* L1 state */
33 #define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
34 #define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
35 #define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
36 #define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
37 #define ASPM_STATE_L1_SS_PCIPM (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM)
38 #define ASPM_STATE_L1_2_MASK (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM)
39 #define ASPM_STATE_L1SS (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\
41 #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
42 #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
46 u32 l0s; /* L0s latency (nsec) */
47 u32 l1; /* L1 latency (nsec) */
50 struct pcie_link_state {
51 struct pci_dev *pdev; /* Upstream component of the Link */
52 struct pci_dev *downstream; /* Downstream component, function 0 */
53 struct pcie_link_state *root; /* pointer to the root port link */
54 struct pcie_link_state *parent; /* pointer to the parent Link state */
55 struct list_head sibling; /* node in link_list */
58 u32 aspm_support:7; /* Supported ASPM state */
59 u32 aspm_enabled:7; /* Enabled ASPM state */
60 u32 aspm_capable:7; /* Capable ASPM state with latency */
61 u32 aspm_default:7; /* Default ASPM state by BIOS */
62 u32 aspm_disable:7; /* Disabled ASPM state */
65 u32 clkpm_capable:1; /* Clock PM capable? */
66 u32 clkpm_enabled:1; /* Current Clock PM state */
67 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
70 struct aspm_latency latency_up; /* Upstream direction exit latency */
71 struct aspm_latency latency_dw; /* Downstream direction exit latency */
73 * Endpoint acceptable latencies. A pcie downstream port only
74 * has one slot under it, so at most there are 8 functions.
76 struct aspm_latency acceptable[8];
78 /* L1 PM Substate info */
80 u32 up_cap_ptr; /* L1SS cap ptr in upstream dev */
81 u32 dw_cap_ptr; /* L1SS cap ptr in downstream dev */
82 u32 ctl1; /* value to be programmed in ctl1 */
83 u32 ctl2; /* value to be programmed in ctl2 */
87 static int aspm_disabled, aspm_force;
88 static bool aspm_support_enabled = true;
89 static DEFINE_MUTEX(aspm_lock);
90 static LIST_HEAD(link_list);
92 #define POLICY_DEFAULT 0 /* BIOS default setting */
93 #define POLICY_PERFORMANCE 1 /* high performance */
94 #define POLICY_POWERSAVE 2 /* high power saving */
95 #define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */
97 #ifdef CONFIG_PCIEASPM_PERFORMANCE
98 static int aspm_policy = POLICY_PERFORMANCE;
99 #elif defined CONFIG_PCIEASPM_POWERSAVE
100 static int aspm_policy = POLICY_POWERSAVE;
101 #elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
102 static int aspm_policy = POLICY_POWER_SUPERSAVE;
104 static int aspm_policy;
107 static const char *policy_str[] = {
108 [POLICY_DEFAULT] = "default",
109 [POLICY_PERFORMANCE] = "performance",
110 [POLICY_POWERSAVE] = "powersave",
111 [POLICY_POWER_SUPERSAVE] = "powersupersave"
114 #define LINK_RETRAIN_TIMEOUT HZ
116 static int policy_to_aspm_state(struct pcie_link_state *link)
118 switch (aspm_policy) {
119 case POLICY_PERFORMANCE:
120 /* Disable ASPM and Clock PM */
122 case POLICY_POWERSAVE:
123 /* Enable ASPM L0s/L1 */
124 return (ASPM_STATE_L0S | ASPM_STATE_L1);
125 case POLICY_POWER_SUPERSAVE:
126 /* Enable Everything */
127 return ASPM_STATE_ALL;
129 return link->aspm_default;
134 static int policy_to_clkpm_state(struct pcie_link_state *link)
136 switch (aspm_policy) {
137 case POLICY_PERFORMANCE:
138 /* Disable ASPM and Clock PM */
140 case POLICY_POWERSAVE:
141 case POLICY_POWER_SUPERSAVE:
142 /* Enable Clock PM */
145 return link->clkpm_default;
150 static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
152 struct pci_dev *child;
153 struct pci_bus *linkbus = link->pdev->subordinate;
154 u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
156 list_for_each_entry(child, &linkbus->devices, bus_list)
157 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
158 PCI_EXP_LNKCTL_CLKREQ_EN,
160 link->clkpm_enabled = !!enable;
163 static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
165 /* Don't enable Clock PM if the link is not Clock PM capable */
166 if (!link->clkpm_capable)
168 /* Need nothing if the specified equals to current state */
169 if (link->clkpm_enabled == enable)
171 pcie_set_clkpm_nocheck(link, enable);
174 static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
176 int capable = 1, enabled = 1;
179 struct pci_dev *child;
180 struct pci_bus *linkbus = link->pdev->subordinate;
182 /* All functions should have the same cap and state, take the worst */
183 list_for_each_entry(child, &linkbus->devices, bus_list) {
184 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
185 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
190 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
191 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
194 link->clkpm_enabled = enabled;
195 link->clkpm_default = enabled;
196 link->clkpm_capable = (blacklist) ? 0 : capable;
199 static bool pcie_retrain_link(struct pcie_link_state *link)
201 struct pci_dev *parent = link->pdev;
202 unsigned long end_jiffies;
205 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
206 reg16 |= PCI_EXP_LNKCTL_RL;
207 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
208 if (parent->clear_retrain_link) {
210 * Due to an erratum in some devices the Retrain Link bit
211 * needs to be cleared again manually to allow the link
212 * training to succeed.
214 reg16 &= ~PCI_EXP_LNKCTL_RL;
215 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
218 /* Wait for link training end. Break out after waiting for timeout */
219 end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;
221 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
222 if (!(reg16 & PCI_EXP_LNKSTA_LT))
225 } while (time_before(jiffies, end_jiffies));
226 return !(reg16 & PCI_EXP_LNKSTA_LT);
230 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
231 * could use common clock. If they are, configure them to use the
232 * common clock. That will reduce the ASPM state exit latency.
234 static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
237 u16 reg16, parent_reg, child_reg[8];
238 struct pci_dev *child, *parent = link->pdev;
239 struct pci_bus *linkbus = parent->subordinate;
241 * All functions of a slot should have the same Slot Clock
242 * Configuration, so just check one function
244 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
245 BUG_ON(!pci_is_pcie(child));
247 /* Check downstream component if bit Slot Clock Configuration is 1 */
248 pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
249 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
252 /* Check upstream component if bit Slot Clock Configuration is 1 */
253 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
254 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
257 /* Port might be already in common clock mode */
258 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
259 if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
260 bool consistent = true;
262 list_for_each_entry(child, &linkbus->devices, bus_list) {
263 pcie_capability_read_word(child, PCI_EXP_LNKCTL,
265 if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
272 pci_warn(parent, "ASPM: current common clock configuration is broken, reconfiguring\n");
275 /* Configure downstream component, all functions */
276 list_for_each_entry(child, &linkbus->devices, bus_list) {
277 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
278 child_reg[PCI_FUNC(child->devfn)] = reg16;
280 reg16 |= PCI_EXP_LNKCTL_CCC;
282 reg16 &= ~PCI_EXP_LNKCTL_CCC;
283 pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
286 /* Configure upstream component */
287 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
290 reg16 |= PCI_EXP_LNKCTL_CCC;
292 reg16 &= ~PCI_EXP_LNKCTL_CCC;
293 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
295 if (pcie_retrain_link(link))
298 /* Training failed. Restore common clock configurations */
299 pci_err(parent, "ASPM: Could not configure common clock\n");
300 list_for_each_entry(child, &linkbus->devices, bus_list)
301 pcie_capability_write_word(child, PCI_EXP_LNKCTL,
302 child_reg[PCI_FUNC(child->devfn)]);
303 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
306 /* Convert L0s latency encoding to ns */
307 static u32 calc_l0s_latency(u32 encoding)
310 return (5 * 1000); /* > 4us */
311 return (64 << encoding);
314 /* Convert L0s acceptable latency encoding to ns */
315 static u32 calc_l0s_acceptable(u32 encoding)
319 return (64 << encoding);
322 /* Convert L1 latency encoding to ns */
323 static u32 calc_l1_latency(u32 encoding)
326 return (65 * 1000); /* > 64us */
327 return (1000 << encoding);
330 /* Convert L1 acceptable latency encoding to ns */
331 static u32 calc_l1_acceptable(u32 encoding)
335 return (1000 << encoding);
338 /* Convert L1SS T_pwr encoding to usec */
339 static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
349 pci_err(pdev, "%s: Invalid T_PwrOn scale: %u\n", __func__, scale);
353 static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
355 u32 threshold_ns = threshold_us * 1000;
357 /* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
358 if (threshold_ns < 32) {
360 *value = threshold_ns;
361 } else if (threshold_ns < 1024) {
363 *value = threshold_ns >> 5;
364 } else if (threshold_ns < 32768) {
366 *value = threshold_ns >> 10;
367 } else if (threshold_ns < 1048576) {
369 *value = threshold_ns >> 15;
370 } else if (threshold_ns < 33554432) {
372 *value = threshold_ns >> 20;
375 *value = threshold_ns >> 25;
379 struct aspm_register_info {
382 u32 latency_encoding_l0s;
383 u32 latency_encoding_l1;
392 static void pcie_get_aspm_reg(struct pci_dev *pdev,
393 struct aspm_register_info *info)
398 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32);
399 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
400 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
401 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
402 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16);
403 info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
405 /* Read L1 PM substate capabilities */
406 info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0;
407 info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
408 if (!info->l1ss_cap_ptr)
410 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CAP,
412 if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) {
418 * If we don't have LTR for the entire path from the Root Complex
419 * to this device, we can't use ASPM L1.2 because it relies on the
420 * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18.
423 info->l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;
425 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1,
427 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2,
431 static void pcie_aspm_check_latency(struct pci_dev *endpoint)
433 u32 latency, l1_switch_latency = 0;
434 struct aspm_latency *acceptable;
435 struct pcie_link_state *link;
437 /* Device not in D0 doesn't need latency check */
438 if ((endpoint->current_state != PCI_D0) &&
439 (endpoint->current_state != PCI_UNKNOWN))
442 link = endpoint->bus->self->link_state;
443 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
446 /* Check upstream direction L0s latency */
447 if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
448 (link->latency_up.l0s > acceptable->l0s))
449 link->aspm_capable &= ~ASPM_STATE_L0S_UP;
451 /* Check downstream direction L0s latency */
452 if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
453 (link->latency_dw.l0s > acceptable->l0s))
454 link->aspm_capable &= ~ASPM_STATE_L0S_DW;
457 * Every switch on the path to root complex need 1
458 * more microsecond for L1. Spec doesn't mention L0s.
460 * The exit latencies for L1 substates are not advertised
461 * by a device. Since the spec also doesn't mention a way
462 * to determine max latencies introduced by enabling L1
463 * substates on the components, it is not clear how to do
464 * a L1 substate exit latency check. We assume that the
465 * L1 exit latencies advertised by a device include L1
466 * substate latencies (and hence do not do any check).
468 latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
469 if ((link->aspm_capable & ASPM_STATE_L1) &&
470 (latency + l1_switch_latency > acceptable->l1))
471 link->aspm_capable &= ~ASPM_STATE_L1;
472 l1_switch_latency += 1000;
479 * The L1 PM substate capability is only implemented in function 0 in a
480 * multi function device.
482 static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
484 struct pci_dev *child;
486 list_for_each_entry(child, &linkbus->devices, bus_list)
487 if (PCI_FUNC(child->devfn) == 0)
492 /* Calculate L1.2 PM substate timing parameters */
493 static void aspm_calc_l1ss_info(struct pcie_link_state *link,
494 struct aspm_register_info *upreg,
495 struct aspm_register_info *dwreg)
497 u32 val1, val2, scale1, scale2;
498 u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
500 link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr;
501 link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr;
502 link->l1ss.ctl1 = link->l1ss.ctl2 = 0;
504 if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
507 /* Choose the greater of the two Port Common_Mode_Restore_Times */
508 val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
509 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
510 t_common_mode = max(val1, val2);
512 /* Choose the greater of the two Port T_POWER_ON times */
513 val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
514 scale1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
515 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
516 scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
518 if (calc_l1ss_pwron(link->pdev, scale1, val1) >
519 calc_l1ss_pwron(link->downstream, scale2, val2)) {
520 link->l1ss.ctl2 |= scale1 | (val1 << 3);
521 t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1);
523 link->l1ss.ctl2 |= scale2 | (val2 << 3);
524 t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2);
528 * Set LTR_L1.2_THRESHOLD to the time required to transition the
529 * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
530 * downstream devices report (via LTR) that they can tolerate at
531 * least that much latency.
533 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
534 * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at
537 l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
538 encode_l12_threshold(l1_2_threshold, &scale, &value);
539 link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
542 static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
544 struct pci_dev *child = link->downstream, *parent = link->pdev;
545 struct pci_bus *linkbus = parent->subordinate;
546 struct aspm_register_info upreg, dwreg;
549 /* Set enabled/disable so that we will disable ASPM later */
550 link->aspm_enabled = ASPM_STATE_ALL;
551 link->aspm_disable = ASPM_STATE_ALL;
555 /* Get upstream/downstream components' register state */
556 pcie_get_aspm_reg(parent, &upreg);
557 pcie_get_aspm_reg(child, &dwreg);
560 * If ASPM not supported, don't mess with the clocks and link,
563 if (!(upreg.support & dwreg.support))
566 /* Configure common clock before checking latencies */
567 pcie_aspm_configure_common_clock(link);
570 * Re-read upstream/downstream components' register state
571 * after clock configuration
573 pcie_get_aspm_reg(parent, &upreg);
574 pcie_get_aspm_reg(child, &dwreg);
579 * Note that we must not enable L0s in either direction on a
580 * given link unless components on both sides of the link each
583 if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S)
584 link->aspm_support |= ASPM_STATE_L0S;
585 if (dwreg.enabled & PCIE_LINK_STATE_L0S)
586 link->aspm_enabled |= ASPM_STATE_L0S_UP;
587 if (upreg.enabled & PCIE_LINK_STATE_L0S)
588 link->aspm_enabled |= ASPM_STATE_L0S_DW;
589 link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);
590 link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);
593 if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1)
594 link->aspm_support |= ASPM_STATE_L1;
595 if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
596 link->aspm_enabled |= ASPM_STATE_L1;
597 link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
598 link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
600 /* Setup L1 substate */
601 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
602 link->aspm_support |= ASPM_STATE_L1_1;
603 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
604 link->aspm_support |= ASPM_STATE_L1_2;
605 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
606 link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
607 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
608 link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
610 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
611 link->aspm_enabled |= ASPM_STATE_L1_1;
612 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
613 link->aspm_enabled |= ASPM_STATE_L1_2;
614 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
615 link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
616 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
617 link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
619 if (link->aspm_support & ASPM_STATE_L1SS)
620 aspm_calc_l1ss_info(link, &upreg, &dwreg);
622 /* Save default state */
623 link->aspm_default = link->aspm_enabled;
625 /* Setup initial capable state. Will be updated later */
626 link->aspm_capable = link->aspm_support;
628 * If the downstream component has pci bridge function, don't
631 list_for_each_entry(child, &linkbus->devices, bus_list) {
632 if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) {
633 link->aspm_disable = ASPM_STATE_ALL;
638 /* Get and check endpoint acceptable latencies */
639 list_for_each_entry(child, &linkbus->devices, bus_list) {
641 struct aspm_latency *acceptable =
642 &link->acceptable[PCI_FUNC(child->devfn)];
644 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
645 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
648 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
649 /* Calculate endpoint L0s acceptable latency */
650 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
651 acceptable->l0s = calc_l0s_acceptable(encoding);
652 /* Calculate endpoint L1 acceptable latency */
653 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
654 acceptable->l1 = calc_l1_acceptable(encoding);
656 pcie_aspm_check_latency(child);
660 static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
665 pci_read_config_dword(pdev, pos, &val);
668 pci_write_config_dword(pdev, pos, val);
671 /* Configure the ASPM L1 substates */
672 static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
675 struct pci_dev *child = link->downstream, *parent = link->pdev;
676 u32 up_cap_ptr = link->l1ss.up_cap_ptr;
677 u32 dw_cap_ptr = link->l1ss.dw_cap_ptr;
679 enable_req = (link->aspm_enabled ^ state) & state;
682 * Here are the rules specified in the PCIe spec for enabling L1SS:
683 * - When enabling L1.x, enable bit at parent first, then at child
684 * - When disabling L1.x, disable bit at child first, then at parent
685 * - When enabling ASPM L1.x, need to disable L1
686 * (at child followed by parent).
687 * - The ASPM/PCIPM L1.2 must be disabled while programming timing
690 * To keep it simple, disable all L1SS bits first, and later enable
694 /* Disable all L1 substates */
695 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
696 PCI_L1SS_CTL1_L1SS_MASK, 0);
697 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
698 PCI_L1SS_CTL1_L1SS_MASK, 0);
700 * If needed, disable L1, and it gets enabled later
701 * in pcie_config_aspm_link().
703 if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) {
704 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
705 PCI_EXP_LNKCTL_ASPM_L1, 0);
706 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
707 PCI_EXP_LNKCTL_ASPM_L1, 0);
710 if (enable_req & ASPM_STATE_L1_2_MASK) {
712 /* Program T_POWER_ON times in both ports */
713 pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2,
715 pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2,
718 /* Program Common_Mode_Restore_Time in upstream device */
719 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
720 PCI_L1SS_CTL1_CM_RESTORE_TIME,
723 /* Program LTR_L1.2_THRESHOLD time in both ports */
724 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
725 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
726 PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
728 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
729 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
730 PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
735 if (state & ASPM_STATE_L1_1)
736 val |= PCI_L1SS_CTL1_ASPM_L1_1;
737 if (state & ASPM_STATE_L1_2)
738 val |= PCI_L1SS_CTL1_ASPM_L1_2;
739 if (state & ASPM_STATE_L1_1_PCIPM)
740 val |= PCI_L1SS_CTL1_PCIPM_L1_1;
741 if (state & ASPM_STATE_L1_2_PCIPM)
742 val |= PCI_L1SS_CTL1_PCIPM_L1_2;
744 /* Enable what we need to enable */
745 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
746 PCI_L1SS_CAP_L1_PM_SS, val);
747 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
748 PCI_L1SS_CAP_L1_PM_SS, val);
751 static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
753 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
754 PCI_EXP_LNKCTL_ASPMC, val);
757 static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
759 u32 upstream = 0, dwstream = 0;
760 struct pci_dev *child = link->downstream, *parent = link->pdev;
761 struct pci_bus *linkbus = parent->subordinate;
763 /* Enable only the states that were not explicitly disabled */
764 state &= (link->aspm_capable & ~link->aspm_disable);
766 /* Can't enable any substates if L1 is not enabled */
767 if (!(state & ASPM_STATE_L1))
768 state &= ~ASPM_STATE_L1SS;
770 /* Spec says both ports must be in D0 before enabling PCI PM substates*/
771 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
772 state &= ~ASPM_STATE_L1_SS_PCIPM;
773 state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
776 /* Nothing to do if the link is already in the requested state */
777 if (link->aspm_enabled == state)
779 /* Convert ASPM state to upstream/downstream ASPM register state */
780 if (state & ASPM_STATE_L0S_UP)
781 dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
782 if (state & ASPM_STATE_L0S_DW)
783 upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
784 if (state & ASPM_STATE_L1) {
785 upstream |= PCI_EXP_LNKCTL_ASPM_L1;
786 dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
789 if (link->aspm_capable & ASPM_STATE_L1SS)
790 pcie_config_aspm_l1ss(link, state);
793 * Spec 2.0 suggests all functions should be configured the
794 * same setting for ASPM. Enabling ASPM L1 should be done in
795 * upstream component first and then downstream, and vice
796 * versa for disabling ASPM L1. Spec doesn't mention L0S.
798 if (state & ASPM_STATE_L1)
799 pcie_config_aspm_dev(parent, upstream);
800 list_for_each_entry(child, &linkbus->devices, bus_list)
801 pcie_config_aspm_dev(child, dwstream);
802 if (!(state & ASPM_STATE_L1))
803 pcie_config_aspm_dev(parent, upstream);
805 link->aspm_enabled = state;
808 static void pcie_config_aspm_path(struct pcie_link_state *link)
811 pcie_config_aspm_link(link, policy_to_aspm_state(link));
816 static void free_link_state(struct pcie_link_state *link)
818 link->pdev->link_state = NULL;
822 static int pcie_aspm_sanity_check(struct pci_dev *pdev)
824 struct pci_dev *child;
828 * Some functions in a slot might not all be PCIe functions,
829 * very strange. Disable ASPM for the whole slot
831 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
832 if (!pci_is_pcie(child))
836 * If ASPM is disabled then we're not going to change
837 * the BIOS state. It's safe to continue even if it's a
845 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
846 * RBER bit to determine if a function is 1.1 version device
848 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
849 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
850 pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
857 static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
859 struct pcie_link_state *link;
861 link = kzalloc(sizeof(*link), GFP_KERNEL);
865 INIT_LIST_HEAD(&link->sibling);
867 link->downstream = pci_function_0(pdev->subordinate);
870 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
871 * hierarchies. Note that some PCIe host implementations omit
872 * the root ports entirely, in which case a downstream port on
873 * a switch may become the root of the link state chain for all
874 * its subordinate endpoints.
876 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
877 pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
878 !pdev->bus->parent->self) {
881 struct pcie_link_state *parent;
883 parent = pdev->bus->parent->self->link_state;
889 link->parent = parent;
890 link->root = link->parent->root;
893 list_add(&link->sibling, &link_list);
894 pdev->link_state = link;
899 * pcie_aspm_init_link_state: Initiate PCI express link state.
900 * It is called after the pcie and its children devices are scanned.
901 * @pdev: the root port or switch downstream port
903 void pcie_aspm_init_link_state(struct pci_dev *pdev)
905 struct pcie_link_state *link;
906 int blacklist = !!pcie_aspm_sanity_check(pdev);
908 if (!aspm_support_enabled)
911 if (pdev->link_state)
915 * We allocate pcie_link_state for the component on the upstream
916 * end of a Link, so there's nothing to do unless this device has a
917 * Link on its secondary side.
919 if (!pdev->has_secondary_link)
922 /* VIA has a strange chipset, root port is under a bridge */
923 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
927 down_read(&pci_bus_sem);
928 if (list_empty(&pdev->subordinate->devices))
931 mutex_lock(&aspm_lock);
932 link = alloc_pcie_link_state(pdev);
936 * Setup initial ASPM state. Note that we need to configure
937 * upstream links also because capable state of them can be
938 * update through pcie_aspm_cap_init().
940 pcie_aspm_cap_init(link, blacklist);
942 /* Setup initial Clock PM state */
943 pcie_clkpm_cap_init(link, blacklist);
946 * At this stage drivers haven't had an opportunity to change the
947 * link policy setting. Enabling ASPM on broken hardware can cripple
948 * it even before the driver has had a chance to disable ASPM, so
949 * default to a safe level right now. If we're enabling ASPM beyond
950 * the BIOS's expectation, we'll do so once pci_enable_device() is
953 if (aspm_policy != POLICY_POWERSAVE &&
954 aspm_policy != POLICY_POWER_SUPERSAVE) {
955 pcie_config_aspm_path(link);
956 pcie_set_clkpm(link, policy_to_clkpm_state(link));
960 mutex_unlock(&aspm_lock);
962 up_read(&pci_bus_sem);
965 /* Recheck latencies and update aspm_capable for links under the root */
966 static void pcie_update_aspm_capable(struct pcie_link_state *root)
968 struct pcie_link_state *link;
969 BUG_ON(root->parent);
970 list_for_each_entry(link, &link_list, sibling) {
971 if (link->root != root)
973 link->aspm_capable = link->aspm_support;
975 list_for_each_entry(link, &link_list, sibling) {
976 struct pci_dev *child;
977 struct pci_bus *linkbus = link->pdev->subordinate;
978 if (link->root != root)
980 list_for_each_entry(child, &linkbus->devices, bus_list) {
981 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
982 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
984 pcie_aspm_check_latency(child);
989 /* @pdev: the endpoint device */
990 void pcie_aspm_exit_link_state(struct pci_dev *pdev)
992 struct pci_dev *parent = pdev->bus->self;
993 struct pcie_link_state *link, *root, *parent_link;
995 if (!parent || !parent->link_state)
998 down_read(&pci_bus_sem);
999 mutex_lock(&aspm_lock);
1001 * All PCIe functions are in one slot, remove one function will remove
1002 * the whole slot, so just wait until we are the last function left.
1004 if (!list_empty(&parent->subordinate->devices))
1007 link = parent->link_state;
1009 parent_link = link->parent;
1011 /* All functions are removed, so just disable ASPM for the link */
1012 pcie_config_aspm_link(link, 0);
1013 list_del(&link->sibling);
1014 /* Clock PM is for endpoint device */
1015 free_link_state(link);
1017 /* Recheck latencies and configure upstream links */
1019 pcie_update_aspm_capable(root);
1020 pcie_config_aspm_path(parent_link);
1023 mutex_unlock(&aspm_lock);
1024 up_read(&pci_bus_sem);
1027 /* @pdev: the root port or switch downstream port */
1028 void pcie_aspm_pm_state_change(struct pci_dev *pdev)
1030 struct pcie_link_state *link = pdev->link_state;
1032 if (aspm_disabled || !link)
1035 * Devices changed PM state, we should recheck if latency
1036 * meets all functions' requirement
1038 down_read(&pci_bus_sem);
1039 mutex_lock(&aspm_lock);
1040 pcie_update_aspm_capable(link->root);
1041 pcie_config_aspm_path(link);
1042 mutex_unlock(&aspm_lock);
1043 up_read(&pci_bus_sem);
1046 void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
1048 struct pcie_link_state *link = pdev->link_state;
1050 if (aspm_disabled || !link)
1053 if (aspm_policy != POLICY_POWERSAVE &&
1054 aspm_policy != POLICY_POWER_SUPERSAVE)
1057 down_read(&pci_bus_sem);
1058 mutex_lock(&aspm_lock);
1059 pcie_config_aspm_path(link);
1060 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1061 mutex_unlock(&aspm_lock);
1062 up_read(&pci_bus_sem);
1065 static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
1067 struct pci_dev *parent = pdev->bus->self;
1068 struct pcie_link_state *link;
1070 if (!pci_is_pcie(pdev))
1073 if (pdev->has_secondary_link)
1075 if (!parent || !parent->link_state)
1079 * A driver requested that ASPM be disabled on this device, but
1080 * if we don't have permission to manage ASPM (e.g., on ACPI
1081 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1082 * the _OSC method), we can't honor that request. Windows has
1083 * a similar mechanism using "PciASPMOptOut", which is also
1084 * ignored in this situation.
1086 if (aspm_disabled) {
1087 pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n");
1092 down_read(&pci_bus_sem);
1093 mutex_lock(&aspm_lock);
1094 link = parent->link_state;
1095 if (state & PCIE_LINK_STATE_L0S)
1096 link->aspm_disable |= ASPM_STATE_L0S;
1097 if (state & PCIE_LINK_STATE_L1)
1098 link->aspm_disable |= ASPM_STATE_L1;
1099 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1101 if (state & PCIE_LINK_STATE_CLKPM) {
1102 link->clkpm_capable = 0;
1103 pcie_set_clkpm(link, 0);
1105 mutex_unlock(&aspm_lock);
1107 up_read(&pci_bus_sem);
1112 int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1114 return __pci_disable_link_state(pdev, state, false);
1116 EXPORT_SYMBOL(pci_disable_link_state_locked);
1119 * pci_disable_link_state - Disable device's link state, so the link will
1120 * never enter specific states. Note that if the BIOS didn't grant ASPM
1121 * control to the OS, this does nothing because we can't touch the LNKCTL
1122 * register. Returns 0 or a negative errno.
1125 * @state: ASPM link state to disable
1127 int pci_disable_link_state(struct pci_dev *pdev, int state)
1129 return __pci_disable_link_state(pdev, state, true);
1131 EXPORT_SYMBOL(pci_disable_link_state);
1133 static int pcie_aspm_set_policy(const char *val,
1134 const struct kernel_param *kp)
1137 struct pcie_link_state *link;
1141 i = sysfs_match_string(policy_str, val);
1144 if (i == aspm_policy)
1147 down_read(&pci_bus_sem);
1148 mutex_lock(&aspm_lock);
1150 list_for_each_entry(link, &link_list, sibling) {
1151 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1152 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1154 mutex_unlock(&aspm_lock);
1155 up_read(&pci_bus_sem);
1159 static int pcie_aspm_get_policy(char *buffer, const struct kernel_param *kp)
1162 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
1163 if (i == aspm_policy)
1164 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
1166 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
1170 module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
1174 * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device.
1175 * @pdev: Target device.
1177 bool pcie_aspm_enabled(struct pci_dev *pdev)
1179 struct pci_dev *bridge = pci_upstream_bridge(pdev);
1185 mutex_lock(&aspm_lock);
1186 ret = bridge->link_state ? !!bridge->link_state->aspm_enabled : false;
1187 mutex_unlock(&aspm_lock);
1191 EXPORT_SYMBOL_GPL(pcie_aspm_enabled);
1193 #ifdef CONFIG_PCIEASPM_DEBUG
1194 static ssize_t link_state_show(struct device *dev,
1195 struct device_attribute *attr,
1198 struct pci_dev *pci_device = to_pci_dev(dev);
1199 struct pcie_link_state *link_state = pci_device->link_state;
1201 return sprintf(buf, "%d\n", link_state->aspm_enabled);
1204 static ssize_t link_state_store(struct device *dev,
1205 struct device_attribute *attr,
1209 struct pci_dev *pdev = to_pci_dev(dev);
1210 struct pcie_link_state *link, *root = pdev->link_state->root;
1216 if (kstrtouint(buf, 10, &state))
1218 if ((state & ~ASPM_STATE_ALL) != 0)
1221 down_read(&pci_bus_sem);
1222 mutex_lock(&aspm_lock);
1223 list_for_each_entry(link, &link_list, sibling) {
1224 if (link->root != root)
1226 pcie_config_aspm_link(link, state);
1228 mutex_unlock(&aspm_lock);
1229 up_read(&pci_bus_sem);
1233 static ssize_t clk_ctl_show(struct device *dev,
1234 struct device_attribute *attr,
1237 struct pci_dev *pci_device = to_pci_dev(dev);
1238 struct pcie_link_state *link_state = pci_device->link_state;
1240 return sprintf(buf, "%d\n", link_state->clkpm_enabled);
1243 static ssize_t clk_ctl_store(struct device *dev,
1244 struct device_attribute *attr,
1248 struct pci_dev *pdev = to_pci_dev(dev);
1251 if (strtobool(buf, &state))
1254 down_read(&pci_bus_sem);
1255 mutex_lock(&aspm_lock);
1256 pcie_set_clkpm_nocheck(pdev->link_state, state);
1257 mutex_unlock(&aspm_lock);
1258 up_read(&pci_bus_sem);
1263 static DEVICE_ATTR_RW(link_state);
1264 static DEVICE_ATTR_RW(clk_ctl);
1266 static char power_group[] = "power";
1267 void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
1269 struct pcie_link_state *link_state = pdev->link_state;
1274 if (link_state->aspm_support)
1275 sysfs_add_file_to_group(&pdev->dev.kobj,
1276 &dev_attr_link_state.attr, power_group);
1277 if (link_state->clkpm_capable)
1278 sysfs_add_file_to_group(&pdev->dev.kobj,
1279 &dev_attr_clk_ctl.attr, power_group);
1282 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
1284 struct pcie_link_state *link_state = pdev->link_state;
1289 if (link_state->aspm_support)
1290 sysfs_remove_file_from_group(&pdev->dev.kobj,
1291 &dev_attr_link_state.attr, power_group);
1292 if (link_state->clkpm_capable)
1293 sysfs_remove_file_from_group(&pdev->dev.kobj,
1294 &dev_attr_clk_ctl.attr, power_group);
1298 static int __init pcie_aspm_disable(char *str)
1300 if (!strcmp(str, "off")) {
1301 aspm_policy = POLICY_DEFAULT;
1303 aspm_support_enabled = false;
1304 printk(KERN_INFO "PCIe ASPM is disabled\n");
1305 } else if (!strcmp(str, "force")) {
1307 printk(KERN_INFO "PCIe ASPM is forcibly enabled\n");
1312 __setup("pcie_aspm=", pcie_aspm_disable);
1314 void pcie_no_aspm(void)
1317 * Disabling ASPM is intended to prevent the kernel from modifying
1318 * existing hardware state, not to clear existing state. To that end:
1319 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
1320 * (b) prevent userspace from changing policy
1323 aspm_policy = POLICY_DEFAULT;
1328 bool pcie_aspm_support_enabled(void)
1330 return aspm_support_enabled;
1332 EXPORT_SYMBOL(pcie_aspm_support_enabled);