2 * File: drivers/pci/pcie/aspm.c
3 * Enabling PCIe link L0s/L1 state and Clock Power Management
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/pci_regs.h>
15 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/slab.h>
19 #include <linux/jiffies.h>
20 #include <linux/delay.h>
21 #include <linux/pci-aspm.h>
24 #ifdef MODULE_PARAM_PREFIX
25 #undef MODULE_PARAM_PREFIX
27 #define MODULE_PARAM_PREFIX "pcie_aspm."
29 /* Note: those are not register definitions */
30 #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
31 #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
32 #define ASPM_STATE_L1 (4) /* L1 state */
33 #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
34 #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1)
37 u32 l0s; /* L0s latency (nsec) */
38 u32 l1; /* L1 latency (nsec) */
41 struct pcie_link_state {
42 struct pci_dev *pdev; /* Upstream component of the Link */
43 struct pcie_link_state *root; /* pointer to the root port link */
44 struct pcie_link_state *parent; /* pointer to the parent Link state */
45 struct list_head sibling; /* node in link_list */
46 struct list_head children; /* list of child link states */
47 struct list_head link; /* node in parent's children list */
50 u32 aspm_support:3; /* Supported ASPM state */
51 u32 aspm_enabled:3; /* Enabled ASPM state */
52 u32 aspm_capable:3; /* Capable ASPM state with latency */
53 u32 aspm_default:3; /* Default ASPM state by BIOS */
54 u32 aspm_disable:3; /* Disabled ASPM state */
57 u32 clkpm_capable:1; /* Clock PM capable? */
58 u32 clkpm_enabled:1; /* Current Clock PM state */
59 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
62 struct aspm_latency latency_up; /* Upstream direction exit latency */
63 struct aspm_latency latency_dw; /* Downstream direction exit latency */
65 * Endpoint acceptable latencies. A pcie downstream port only
66 * has one slot under it, so at most there are 8 functions.
68 struct aspm_latency acceptable[8];
71 static int aspm_disabled, aspm_force;
72 static bool aspm_support_enabled = true;
73 static DEFINE_MUTEX(aspm_lock);
74 static LIST_HEAD(link_list);
76 #define POLICY_DEFAULT 0 /* BIOS default setting */
77 #define POLICY_PERFORMANCE 1 /* high performance */
78 #define POLICY_POWERSAVE 2 /* high power saving */
80 #ifdef CONFIG_PCIEASPM_PERFORMANCE
81 static int aspm_policy = POLICY_PERFORMANCE;
82 #elif defined CONFIG_PCIEASPM_POWERSAVE
83 static int aspm_policy = POLICY_POWERSAVE;
85 static int aspm_policy;
88 static const char *policy_str[] = {
89 [POLICY_DEFAULT] = "default",
90 [POLICY_PERFORMANCE] = "performance",
91 [POLICY_POWERSAVE] = "powersave"
94 #define LINK_RETRAIN_TIMEOUT HZ
96 static int policy_to_aspm_state(struct pcie_link_state *link)
98 switch (aspm_policy) {
99 case POLICY_PERFORMANCE:
100 /* Disable ASPM and Clock PM */
102 case POLICY_POWERSAVE:
103 /* Enable ASPM L0s/L1 */
104 return ASPM_STATE_ALL;
106 return link->aspm_default;
111 static int policy_to_clkpm_state(struct pcie_link_state *link)
113 switch (aspm_policy) {
114 case POLICY_PERFORMANCE:
115 /* Disable ASPM and Clock PM */
117 case POLICY_POWERSAVE:
118 /* Disable Clock PM */
121 return link->clkpm_default;
126 static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
128 struct pci_dev *child;
129 struct pci_bus *linkbus = link->pdev->subordinate;
130 u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
132 list_for_each_entry(child, &linkbus->devices, bus_list)
133 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
134 PCI_EXP_LNKCTL_CLKREQ_EN,
136 link->clkpm_enabled = !!enable;
139 static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
141 /* Don't enable Clock PM if the link is not Clock PM capable */
142 if (!link->clkpm_capable)
144 /* Need nothing if the specified equals to current state */
145 if (link->clkpm_enabled == enable)
147 pcie_set_clkpm_nocheck(link, enable);
150 static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
152 int capable = 1, enabled = 1;
155 struct pci_dev *child;
156 struct pci_bus *linkbus = link->pdev->subordinate;
158 /* All functions should have the same cap and state, take the worst */
159 list_for_each_entry(child, &linkbus->devices, bus_list) {
160 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
161 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
166 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
167 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
170 link->clkpm_enabled = enabled;
171 link->clkpm_default = enabled;
172 link->clkpm_capable = (blacklist) ? 0 : capable;
176 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
177 * could use common clock. If they are, configure them to use the
178 * common clock. That will reduce the ASPM state exit latency.
180 static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
183 u16 reg16, parent_reg, child_reg[8];
184 unsigned long start_jiffies;
185 struct pci_dev *child, *parent = link->pdev;
186 struct pci_bus *linkbus = parent->subordinate;
188 * All functions of a slot should have the same Slot Clock
189 * Configuration, so just check one function
191 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
192 BUG_ON(!pci_is_pcie(child));
194 /* Check downstream component if bit Slot Clock Configuration is 1 */
195 pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
196 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
199 /* Check upstream component if bit Slot Clock Configuration is 1 */
200 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
201 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
204 /* Configure downstream component, all functions */
205 list_for_each_entry(child, &linkbus->devices, bus_list) {
206 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
207 child_reg[PCI_FUNC(child->devfn)] = reg16;
209 reg16 |= PCI_EXP_LNKCTL_CCC;
211 reg16 &= ~PCI_EXP_LNKCTL_CCC;
212 pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
215 /* Configure upstream component */
216 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
219 reg16 |= PCI_EXP_LNKCTL_CCC;
221 reg16 &= ~PCI_EXP_LNKCTL_CCC;
222 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
225 reg16 |= PCI_EXP_LNKCTL_RL;
226 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
228 /* Wait for link training end. Break out after waiting for timeout */
229 start_jiffies = jiffies;
231 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
232 if (!(reg16 & PCI_EXP_LNKSTA_LT))
234 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
238 if (!(reg16 & PCI_EXP_LNKSTA_LT))
241 /* Training failed. Restore common clock configurations */
242 dev_err(&parent->dev, "ASPM: Could not configure common clock\n");
243 list_for_each_entry(child, &linkbus->devices, bus_list)
244 pcie_capability_write_word(child, PCI_EXP_LNKCTL,
245 child_reg[PCI_FUNC(child->devfn)]);
246 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
249 /* Convert L0s latency encoding to ns */
250 static u32 calc_l0s_latency(u32 encoding)
253 return (5 * 1000); /* > 4us */
254 return (64 << encoding);
257 /* Convert L0s acceptable latency encoding to ns */
258 static u32 calc_l0s_acceptable(u32 encoding)
262 return (64 << encoding);
265 /* Convert L1 latency encoding to ns */
266 static u32 calc_l1_latency(u32 encoding)
269 return (65 * 1000); /* > 64us */
270 return (1000 << encoding);
273 /* Convert L1 acceptable latency encoding to ns */
274 static u32 calc_l1_acceptable(u32 encoding)
278 return (1000 << encoding);
281 struct aspm_register_info {
284 u32 latency_encoding_l0s;
285 u32 latency_encoding_l1;
288 static void pcie_get_aspm_reg(struct pci_dev *pdev,
289 struct aspm_register_info *info)
294 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32);
295 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
296 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
297 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
298 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16);
299 info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
302 static void pcie_aspm_check_latency(struct pci_dev *endpoint)
304 u32 latency, l1_switch_latency = 0;
305 struct aspm_latency *acceptable;
306 struct pcie_link_state *link;
308 /* Device not in D0 doesn't need latency check */
309 if ((endpoint->current_state != PCI_D0) &&
310 (endpoint->current_state != PCI_UNKNOWN))
313 link = endpoint->bus->self->link_state;
314 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
317 /* Check upstream direction L0s latency */
318 if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
319 (link->latency_up.l0s > acceptable->l0s))
320 link->aspm_capable &= ~ASPM_STATE_L0S_UP;
322 /* Check downstream direction L0s latency */
323 if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
324 (link->latency_dw.l0s > acceptable->l0s))
325 link->aspm_capable &= ~ASPM_STATE_L0S_DW;
328 * Every switch on the path to root complex need 1
329 * more microsecond for L1. Spec doesn't mention L0s.
331 latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
332 if ((link->aspm_capable & ASPM_STATE_L1) &&
333 (latency + l1_switch_latency > acceptable->l1))
334 link->aspm_capable &= ~ASPM_STATE_L1;
335 l1_switch_latency += 1000;
341 static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
343 struct pci_dev *child, *parent = link->pdev;
344 struct pci_bus *linkbus = parent->subordinate;
345 struct aspm_register_info upreg, dwreg;
348 /* Set enabled/disable so that we will disable ASPM later */
349 link->aspm_enabled = ASPM_STATE_ALL;
350 link->aspm_disable = ASPM_STATE_ALL;
354 /* Get upstream/downstream components' register state */
355 pcie_get_aspm_reg(parent, &upreg);
356 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
357 pcie_get_aspm_reg(child, &dwreg);
360 * If ASPM not supported, don't mess with the clocks and link,
363 if (!(upreg.support & dwreg.support))
366 /* Configure common clock before checking latencies */
367 pcie_aspm_configure_common_clock(link);
370 * Re-read upstream/downstream components' register state
371 * after clock configuration
373 pcie_get_aspm_reg(parent, &upreg);
374 pcie_get_aspm_reg(child, &dwreg);
379 * Note that we must not enable L0s in either direction on a
380 * given link unless components on both sides of the link each
383 if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S)
384 link->aspm_support |= ASPM_STATE_L0S;
385 if (dwreg.enabled & PCIE_LINK_STATE_L0S)
386 link->aspm_enabled |= ASPM_STATE_L0S_UP;
387 if (upreg.enabled & PCIE_LINK_STATE_L0S)
388 link->aspm_enabled |= ASPM_STATE_L0S_DW;
389 link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);
390 link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);
393 if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1)
394 link->aspm_support |= ASPM_STATE_L1;
395 if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
396 link->aspm_enabled |= ASPM_STATE_L1;
397 link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
398 link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
400 /* Save default state */
401 link->aspm_default = link->aspm_enabled;
403 /* Setup initial capable state. Will be updated later */
404 link->aspm_capable = link->aspm_support;
406 * If the downstream component has pci bridge function, don't
409 list_for_each_entry(child, &linkbus->devices, bus_list) {
410 if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) {
411 link->aspm_disable = ASPM_STATE_ALL;
416 /* Get and check endpoint acceptable latencies */
417 list_for_each_entry(child, &linkbus->devices, bus_list) {
419 struct aspm_latency *acceptable =
420 &link->acceptable[PCI_FUNC(child->devfn)];
422 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
423 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
426 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
427 /* Calculate endpoint L0s acceptable latency */
428 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
429 acceptable->l0s = calc_l0s_acceptable(encoding);
430 /* Calculate endpoint L1 acceptable latency */
431 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
432 acceptable->l1 = calc_l1_acceptable(encoding);
434 pcie_aspm_check_latency(child);
438 static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
440 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
441 PCI_EXP_LNKCTL_ASPMC, val);
444 static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
446 u32 upstream = 0, dwstream = 0;
447 struct pci_dev *child, *parent = link->pdev;
448 struct pci_bus *linkbus = parent->subordinate;
450 /* Nothing to do if the link is already in the requested state */
451 state &= (link->aspm_capable & ~link->aspm_disable);
452 if (link->aspm_enabled == state)
454 /* Convert ASPM state to upstream/downstream ASPM register state */
455 if (state & ASPM_STATE_L0S_UP)
456 dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
457 if (state & ASPM_STATE_L0S_DW)
458 upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
459 if (state & ASPM_STATE_L1) {
460 upstream |= PCI_EXP_LNKCTL_ASPM_L1;
461 dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
464 * Spec 2.0 suggests all functions should be configured the
465 * same setting for ASPM. Enabling ASPM L1 should be done in
466 * upstream component first and then downstream, and vice
467 * versa for disabling ASPM L1. Spec doesn't mention L0S.
469 if (state & ASPM_STATE_L1)
470 pcie_config_aspm_dev(parent, upstream);
471 list_for_each_entry(child, &linkbus->devices, bus_list)
472 pcie_config_aspm_dev(child, dwstream);
473 if (!(state & ASPM_STATE_L1))
474 pcie_config_aspm_dev(parent, upstream);
476 link->aspm_enabled = state;
479 static void pcie_config_aspm_path(struct pcie_link_state *link)
482 pcie_config_aspm_link(link, policy_to_aspm_state(link));
487 static void free_link_state(struct pcie_link_state *link)
489 link->pdev->link_state = NULL;
493 static int pcie_aspm_sanity_check(struct pci_dev *pdev)
495 struct pci_dev *child;
499 * Some functions in a slot might not all be PCIe functions,
500 * very strange. Disable ASPM for the whole slot
502 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
503 if (!pci_is_pcie(child))
507 * If ASPM is disabled then we're not going to change
508 * the BIOS state. It's safe to continue even if it's a
516 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
517 * RBER bit to determine if a function is 1.1 version device
519 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
520 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
521 dev_info(&child->dev, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
528 static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
530 struct pcie_link_state *link;
532 link = kzalloc(sizeof(*link), GFP_KERNEL);
536 INIT_LIST_HEAD(&link->sibling);
537 INIT_LIST_HEAD(&link->children);
538 INIT_LIST_HEAD(&link->link);
542 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
545 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
546 pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE) {
549 struct pcie_link_state *parent;
551 parent = pdev->bus->parent->self->link_state;
557 link->parent = parent;
558 link->root = link->parent->root;
559 list_add(&link->link, &parent->children);
562 list_add(&link->sibling, &link_list);
563 pdev->link_state = link;
568 * pcie_aspm_init_link_state: Initiate PCI express link state.
569 * It is called after the pcie and its children devices are scanned.
570 * @pdev: the root port or switch downstream port
572 void pcie_aspm_init_link_state(struct pci_dev *pdev)
574 struct pcie_link_state *link;
575 int blacklist = !!pcie_aspm_sanity_check(pdev);
577 if (!aspm_support_enabled)
580 if (pdev->link_state)
584 * We allocate pcie_link_state for the component on the upstream
585 * end of a Link, so there's nothing to do unless this device has a
586 * Link on its secondary side.
588 if (!pdev->has_secondary_link)
591 /* VIA has a strange chipset, root port is under a bridge */
592 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
596 down_read(&pci_bus_sem);
597 if (list_empty(&pdev->subordinate->devices))
600 mutex_lock(&aspm_lock);
601 link = alloc_pcie_link_state(pdev);
605 * Setup initial ASPM state. Note that we need to configure
606 * upstream links also because capable state of them can be
607 * update through pcie_aspm_cap_init().
609 pcie_aspm_cap_init(link, blacklist);
611 /* Setup initial Clock PM state */
612 pcie_clkpm_cap_init(link, blacklist);
615 * At this stage drivers haven't had an opportunity to change the
616 * link policy setting. Enabling ASPM on broken hardware can cripple
617 * it even before the driver has had a chance to disable ASPM, so
618 * default to a safe level right now. If we're enabling ASPM beyond
619 * the BIOS's expectation, we'll do so once pci_enable_device() is
622 if (aspm_policy != POLICY_POWERSAVE) {
623 pcie_config_aspm_path(link);
624 pcie_set_clkpm(link, policy_to_clkpm_state(link));
628 mutex_unlock(&aspm_lock);
630 up_read(&pci_bus_sem);
633 /* Recheck latencies and update aspm_capable for links under the root */
634 static void pcie_update_aspm_capable(struct pcie_link_state *root)
636 struct pcie_link_state *link;
637 BUG_ON(root->parent);
638 list_for_each_entry(link, &link_list, sibling) {
639 if (link->root != root)
641 link->aspm_capable = link->aspm_support;
643 list_for_each_entry(link, &link_list, sibling) {
644 struct pci_dev *child;
645 struct pci_bus *linkbus = link->pdev->subordinate;
646 if (link->root != root)
648 list_for_each_entry(child, &linkbus->devices, bus_list) {
649 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
650 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
652 pcie_aspm_check_latency(child);
657 /* @pdev: the endpoint device */
658 void pcie_aspm_exit_link_state(struct pci_dev *pdev)
660 struct pci_dev *parent = pdev->bus->self;
661 struct pcie_link_state *link, *root, *parent_link;
663 if (!parent || !parent->link_state)
666 down_read(&pci_bus_sem);
667 mutex_lock(&aspm_lock);
669 * All PCIe functions are in one slot, remove one function will remove
670 * the whole slot, so just wait until we are the last function left.
672 if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices))
675 link = parent->link_state;
677 parent_link = link->parent;
679 /* All functions are removed, so just disable ASPM for the link */
680 pcie_config_aspm_link(link, 0);
681 list_del(&link->sibling);
682 list_del(&link->link);
683 /* Clock PM is for endpoint device */
684 free_link_state(link);
686 /* Recheck latencies and configure upstream links */
688 pcie_update_aspm_capable(root);
689 pcie_config_aspm_path(parent_link);
692 mutex_unlock(&aspm_lock);
693 up_read(&pci_bus_sem);
696 /* @pdev: the root port or switch downstream port */
697 void pcie_aspm_pm_state_change(struct pci_dev *pdev)
699 struct pcie_link_state *link = pdev->link_state;
701 if (aspm_disabled || !link)
704 * Devices changed PM state, we should recheck if latency
705 * meets all functions' requirement
707 down_read(&pci_bus_sem);
708 mutex_lock(&aspm_lock);
709 pcie_update_aspm_capable(link->root);
710 pcie_config_aspm_path(link);
711 mutex_unlock(&aspm_lock);
712 up_read(&pci_bus_sem);
715 void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
717 struct pcie_link_state *link = pdev->link_state;
719 if (aspm_disabled || !link)
722 if (aspm_policy != POLICY_POWERSAVE)
725 down_read(&pci_bus_sem);
726 mutex_lock(&aspm_lock);
727 pcie_config_aspm_path(link);
728 pcie_set_clkpm(link, policy_to_clkpm_state(link));
729 mutex_unlock(&aspm_lock);
730 up_read(&pci_bus_sem);
733 static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
735 struct pci_dev *parent = pdev->bus->self;
736 struct pcie_link_state *link;
738 if (!pci_is_pcie(pdev))
741 if (pdev->has_secondary_link)
743 if (!parent || !parent->link_state)
747 * A driver requested that ASPM be disabled on this device, but
748 * if we don't have permission to manage ASPM (e.g., on ACPI
749 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
750 * the _OSC method), we can't honor that request. Windows has
751 * a similar mechanism using "PciASPMOptOut", which is also
752 * ignored in this situation.
755 dev_warn(&pdev->dev, "can't disable ASPM; OS doesn't have ASPM control\n");
760 down_read(&pci_bus_sem);
761 mutex_lock(&aspm_lock);
762 link = parent->link_state;
763 if (state & PCIE_LINK_STATE_L0S)
764 link->aspm_disable |= ASPM_STATE_L0S;
765 if (state & PCIE_LINK_STATE_L1)
766 link->aspm_disable |= ASPM_STATE_L1;
767 pcie_config_aspm_link(link, policy_to_aspm_state(link));
769 if (state & PCIE_LINK_STATE_CLKPM) {
770 link->clkpm_capable = 0;
771 pcie_set_clkpm(link, 0);
773 mutex_unlock(&aspm_lock);
775 up_read(&pci_bus_sem);
778 void pci_disable_link_state_locked(struct pci_dev *pdev, int state)
780 __pci_disable_link_state(pdev, state, false);
782 EXPORT_SYMBOL(pci_disable_link_state_locked);
785 * pci_disable_link_state - Disable device's link state, so the link will
786 * never enter specific states. Note that if the BIOS didn't grant ASPM
787 * control to the OS, this does nothing because we can't touch the LNKCTL
791 * @state: ASPM link state to disable
793 void pci_disable_link_state(struct pci_dev *pdev, int state)
795 __pci_disable_link_state(pdev, state, true);
797 EXPORT_SYMBOL(pci_disable_link_state);
799 static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp)
802 struct pcie_link_state *link;
806 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
807 if (!strncmp(val, policy_str[i], strlen(policy_str[i])))
809 if (i >= ARRAY_SIZE(policy_str))
811 if (i == aspm_policy)
814 down_read(&pci_bus_sem);
815 mutex_lock(&aspm_lock);
817 list_for_each_entry(link, &link_list, sibling) {
818 pcie_config_aspm_link(link, policy_to_aspm_state(link));
819 pcie_set_clkpm(link, policy_to_clkpm_state(link));
821 mutex_unlock(&aspm_lock);
822 up_read(&pci_bus_sem);
826 static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp)
829 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
830 if (i == aspm_policy)
831 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
833 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
837 module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
840 #ifdef CONFIG_PCIEASPM_DEBUG
841 static ssize_t link_state_show(struct device *dev,
842 struct device_attribute *attr,
845 struct pci_dev *pci_device = to_pci_dev(dev);
846 struct pcie_link_state *link_state = pci_device->link_state;
848 return sprintf(buf, "%d\n", link_state->aspm_enabled);
851 static ssize_t link_state_store(struct device *dev,
852 struct device_attribute *attr,
856 struct pci_dev *pdev = to_pci_dev(dev);
857 struct pcie_link_state *link, *root = pdev->link_state->root;
863 if (kstrtouint(buf, 10, &state))
865 if ((state & ~ASPM_STATE_ALL) != 0)
868 down_read(&pci_bus_sem);
869 mutex_lock(&aspm_lock);
870 list_for_each_entry(link, &link_list, sibling) {
871 if (link->root != root)
873 pcie_config_aspm_link(link, state);
875 mutex_unlock(&aspm_lock);
876 up_read(&pci_bus_sem);
880 static ssize_t clk_ctl_show(struct device *dev,
881 struct device_attribute *attr,
884 struct pci_dev *pci_device = to_pci_dev(dev);
885 struct pcie_link_state *link_state = pci_device->link_state;
887 return sprintf(buf, "%d\n", link_state->clkpm_enabled);
890 static ssize_t clk_ctl_store(struct device *dev,
891 struct device_attribute *attr,
895 struct pci_dev *pdev = to_pci_dev(dev);
898 if (strtobool(buf, &state))
901 down_read(&pci_bus_sem);
902 mutex_lock(&aspm_lock);
903 pcie_set_clkpm_nocheck(pdev->link_state, state);
904 mutex_unlock(&aspm_lock);
905 up_read(&pci_bus_sem);
910 static DEVICE_ATTR_RW(link_state);
911 static DEVICE_ATTR_RW(clk_ctl);
913 static char power_group[] = "power";
914 void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
916 struct pcie_link_state *link_state = pdev->link_state;
921 if (link_state->aspm_support)
922 sysfs_add_file_to_group(&pdev->dev.kobj,
923 &dev_attr_link_state.attr, power_group);
924 if (link_state->clkpm_capable)
925 sysfs_add_file_to_group(&pdev->dev.kobj,
926 &dev_attr_clk_ctl.attr, power_group);
929 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
931 struct pcie_link_state *link_state = pdev->link_state;
936 if (link_state->aspm_support)
937 sysfs_remove_file_from_group(&pdev->dev.kobj,
938 &dev_attr_link_state.attr, power_group);
939 if (link_state->clkpm_capable)
940 sysfs_remove_file_from_group(&pdev->dev.kobj,
941 &dev_attr_clk_ctl.attr, power_group);
945 static int __init pcie_aspm_disable(char *str)
947 if (!strcmp(str, "off")) {
948 aspm_policy = POLICY_DEFAULT;
950 aspm_support_enabled = false;
951 printk(KERN_INFO "PCIe ASPM is disabled\n");
952 } else if (!strcmp(str, "force")) {
954 printk(KERN_INFO "PCIe ASPM is forcibly enabled\n");
959 __setup("pcie_aspm=", pcie_aspm_disable);
961 void pcie_no_aspm(void)
964 * Disabling ASPM is intended to prevent the kernel from modifying
965 * existing hardware state, not to clear existing state. To that end:
966 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
967 * (b) prevent userspace from changing policy
970 aspm_policy = POLICY_DEFAULT;
975 bool pcie_aspm_support_enabled(void)
977 return aspm_support_enabled;
979 EXPORT_SYMBOL(pcie_aspm_support_enabled);