1 // SPDX-License-Identifier: GPL-2.0
3 * PCI detection and setup code
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/init.h>
10 #include <linux/of_device.h>
11 #include <linux/of_pci.h>
12 #include <linux/pci_hotplug.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/cpumask.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <linux/hypervisor.h>
19 #include <linux/irqdomain.h>
20 #include <linux/pm_runtime.h>
23 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
24 #define CARDBUS_RESERVE_BUSNR 3
26 static struct resource busn_resource = {
30 .flags = IORESOURCE_BUS,
33 /* Ugh. Need to stop exporting this to modules. */
34 LIST_HEAD(pci_root_buses);
35 EXPORT_SYMBOL(pci_root_buses);
37 static LIST_HEAD(pci_domain_busn_res_list);
39 struct pci_domain_busn_res {
40 struct list_head list;
45 static struct resource *get_pci_domain_busn_res(int domain_nr)
47 struct pci_domain_busn_res *r;
49 list_for_each_entry(r, &pci_domain_busn_res_list, list)
50 if (r->domain_nr == domain_nr)
53 r = kzalloc(sizeof(*r), GFP_KERNEL);
57 r->domain_nr = domain_nr;
60 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
62 list_add_tail(&r->list, &pci_domain_busn_res_list);
68 * Some device drivers need know if PCI is initiated.
69 * Basically, we think PCI is not initiated when there
70 * is no device to be found on the pci_bus_type.
72 int no_pci_devices(void)
77 dev = bus_find_next_device(&pci_bus_type, NULL);
78 no_devices = (dev == NULL);
82 EXPORT_SYMBOL(no_pci_devices);
87 static void release_pcibus_dev(struct device *dev)
89 struct pci_bus *pci_bus = to_pci_bus(dev);
91 put_device(pci_bus->bridge);
92 pci_bus_remove_resources(pci_bus);
93 pci_release_bus_of_node(pci_bus);
97 static struct class pcibus_class = {
99 .dev_release = &release_pcibus_dev,
100 .dev_groups = pcibus_groups,
103 static int __init pcibus_class_init(void)
105 return class_register(&pcibus_class);
107 postcore_initcall(pcibus_class_init);
109 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
111 u64 size = mask & maxbase; /* Find the significant bits */
116 * Get the lowest of them to find the decode size, and from that
119 size = size & ~(size-1);
122 * base == maxbase can be valid only if the BAR has already been
123 * programmed with all 1s.
125 if (base == maxbase && ((base | (size - 1)) & mask) != mask)
131 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
136 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
137 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
138 flags |= IORESOURCE_IO;
142 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
143 flags |= IORESOURCE_MEM;
144 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
145 flags |= IORESOURCE_PREFETCH;
147 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
149 case PCI_BASE_ADDRESS_MEM_TYPE_32:
151 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
152 /* 1M mem BAR treated as 32-bit BAR */
154 case PCI_BASE_ADDRESS_MEM_TYPE_64:
155 flags |= IORESOURCE_MEM_64;
158 /* mem unknown type treated as 32-bit BAR */
164 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
167 * pci_read_base - Read a PCI BAR
168 * @dev: the PCI device
169 * @type: type of the BAR
170 * @res: resource buffer to be filled in
171 * @pos: BAR position in the config space
173 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
175 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
176 struct resource *res, unsigned int pos)
178 u32 l = 0, sz = 0, mask;
179 u64 l64, sz64, mask64;
181 struct pci_bus_region region, inverted_region;
183 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
185 /* No printks while decoding is disabled! */
186 if (!dev->mmio_always_on) {
187 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
188 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
189 pci_write_config_word(dev, PCI_COMMAND,
190 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
194 res->name = pci_name(dev);
196 pci_read_config_dword(dev, pos, &l);
197 pci_write_config_dword(dev, pos, l | mask);
198 pci_read_config_dword(dev, pos, &sz);
199 pci_write_config_dword(dev, pos, l);
202 * All bits set in sz means the device isn't working properly.
203 * If the BAR isn't implemented, all bits must be 0. If it's a
204 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
207 if (sz == 0xffffffff)
211 * I don't know how l can have all bits set. Copied from old code.
212 * Maybe it fixes a bug on some ancient platform.
217 if (type == pci_bar_unknown) {
218 res->flags = decode_bar(dev, l);
219 res->flags |= IORESOURCE_SIZEALIGN;
220 if (res->flags & IORESOURCE_IO) {
221 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
222 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
223 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
225 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
226 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
227 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
230 if (l & PCI_ROM_ADDRESS_ENABLE)
231 res->flags |= IORESOURCE_ROM_ENABLE;
232 l64 = l & PCI_ROM_ADDRESS_MASK;
233 sz64 = sz & PCI_ROM_ADDRESS_MASK;
234 mask64 = PCI_ROM_ADDRESS_MASK;
237 if (res->flags & IORESOURCE_MEM_64) {
238 pci_read_config_dword(dev, pos + 4, &l);
239 pci_write_config_dword(dev, pos + 4, ~0);
240 pci_read_config_dword(dev, pos + 4, &sz);
241 pci_write_config_dword(dev, pos + 4, l);
243 l64 |= ((u64)l << 32);
244 sz64 |= ((u64)sz << 32);
245 mask64 |= ((u64)~0 << 32);
248 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
249 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
254 sz64 = pci_size(l64, sz64, mask64);
256 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
261 if (res->flags & IORESOURCE_MEM_64) {
262 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
263 && sz64 > 0x100000000ULL) {
264 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
267 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
268 pos, (unsigned long long)sz64);
272 if ((sizeof(pci_bus_addr_t) < 8) && l) {
273 /* Above 32-bit boundary; try to reallocate */
274 res->flags |= IORESOURCE_UNSET;
277 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
278 pos, (unsigned long long)l64);
284 region.end = l64 + sz64 - 1;
286 pcibios_bus_to_resource(dev->bus, res, ®ion);
287 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
290 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
291 * the corresponding resource address (the physical address used by
292 * the CPU. Converting that resource address back to a bus address
293 * should yield the original BAR value:
295 * resource_to_bus(bus_to_resource(A)) == A
297 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
298 * be claimed by the device.
300 if (inverted_region.start != region.start) {
301 res->flags |= IORESOURCE_UNSET;
303 res->end = region.end - region.start;
304 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
305 pos, (unsigned long long)region.start);
315 pci_info(dev, "reg 0x%x: %pR\n", pos, res);
317 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
320 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
322 unsigned int pos, reg;
324 if (dev->non_compliant_bars)
327 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
331 for (pos = 0; pos < howmany; pos++) {
332 struct resource *res = &dev->resource[pos];
333 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
334 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
338 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
339 dev->rom_base_reg = rom;
340 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
341 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
342 __pci_read_base(dev, pci_bar_mem32, res, rom);
346 static void pci_read_bridge_windows(struct pci_dev *bridge)
351 pci_read_config_word(bridge, PCI_IO_BASE, &io);
353 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
354 pci_read_config_word(bridge, PCI_IO_BASE, &io);
355 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
358 bridge->io_window = 1;
361 * DECchip 21050 pass 2 errata: the bridge may miss an address
362 * disconnect boundary by one PCI data phase. Workaround: do not
363 * use prefetching on this device.
365 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
368 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
370 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
372 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
373 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
378 bridge->pref_window = 1;
380 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
383 * Bridge claims to have a 64-bit prefetchable memory
384 * window; verify that the upper bits are actually
387 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
388 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
390 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
391 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
393 bridge->pref_64_window = 1;
397 static void pci_read_bridge_io(struct pci_bus *child)
399 struct pci_dev *dev = child->self;
400 u8 io_base_lo, io_limit_lo;
401 unsigned long io_mask, io_granularity, base, limit;
402 struct pci_bus_region region;
403 struct resource *res;
405 io_mask = PCI_IO_RANGE_MASK;
406 io_granularity = 0x1000;
407 if (dev->io_window_1k) {
408 /* Support 1K I/O space granularity */
409 io_mask = PCI_IO_1K_RANGE_MASK;
410 io_granularity = 0x400;
413 res = child->resource[0];
414 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
415 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
416 base = (io_base_lo & io_mask) << 8;
417 limit = (io_limit_lo & io_mask) << 8;
419 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
420 u16 io_base_hi, io_limit_hi;
422 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
423 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
424 base |= ((unsigned long) io_base_hi << 16);
425 limit |= ((unsigned long) io_limit_hi << 16);
429 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
431 region.end = limit + io_granularity - 1;
432 pcibios_bus_to_resource(dev->bus, res, ®ion);
433 pci_info(dev, " bridge window %pR\n", res);
437 static void pci_read_bridge_mmio(struct pci_bus *child)
439 struct pci_dev *dev = child->self;
440 u16 mem_base_lo, mem_limit_lo;
441 unsigned long base, limit;
442 struct pci_bus_region region;
443 struct resource *res;
445 res = child->resource[1];
446 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
447 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
448 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
449 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
451 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
453 region.end = limit + 0xfffff;
454 pcibios_bus_to_resource(dev->bus, res, ®ion);
455 pci_info(dev, " bridge window %pR\n", res);
459 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
461 struct pci_dev *dev = child->self;
462 u16 mem_base_lo, mem_limit_lo;
464 pci_bus_addr_t base, limit;
465 struct pci_bus_region region;
466 struct resource *res;
468 res = child->resource[2];
469 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
470 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
471 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
472 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
474 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
475 u32 mem_base_hi, mem_limit_hi;
477 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
478 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
481 * Some bridges set the base > limit by default, and some
482 * (broken) BIOSes do not initialize them. If we find
483 * this, just assume they are not being used.
485 if (mem_base_hi <= mem_limit_hi) {
486 base64 |= (u64) mem_base_hi << 32;
487 limit64 |= (u64) mem_limit_hi << 32;
491 base = (pci_bus_addr_t) base64;
492 limit = (pci_bus_addr_t) limit64;
494 if (base != base64) {
495 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
496 (unsigned long long) base64);
501 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
502 IORESOURCE_MEM | IORESOURCE_PREFETCH;
503 if (res->flags & PCI_PREF_RANGE_TYPE_64)
504 res->flags |= IORESOURCE_MEM_64;
506 region.end = limit + 0xfffff;
507 pcibios_bus_to_resource(dev->bus, res, ®ion);
508 pci_info(dev, " bridge window %pR\n", res);
512 void pci_read_bridge_bases(struct pci_bus *child)
514 struct pci_dev *dev = child->self;
515 struct resource *res;
518 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
521 pci_info(dev, "PCI bridge to %pR%s\n",
523 dev->transparent ? " (subtractive decode)" : "");
525 pci_bus_remove_resources(child);
526 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
527 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
529 pci_read_bridge_io(child);
530 pci_read_bridge_mmio(child);
531 pci_read_bridge_mmio_pref(child);
533 if (dev->transparent) {
534 pci_bus_for_each_resource(child->parent, res, i) {
535 if (res && res->flags) {
536 pci_bus_add_resource(child, res,
537 PCI_SUBTRACTIVE_DECODE);
538 pci_info(dev, " bridge window %pR (subtractive decode)\n",
545 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
549 b = kzalloc(sizeof(*b), GFP_KERNEL);
553 INIT_LIST_HEAD(&b->node);
554 INIT_LIST_HEAD(&b->children);
555 INIT_LIST_HEAD(&b->devices);
556 INIT_LIST_HEAD(&b->slots);
557 INIT_LIST_HEAD(&b->resources);
558 b->max_bus_speed = PCI_SPEED_UNKNOWN;
559 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
560 #ifdef CONFIG_PCI_DOMAINS_GENERIC
562 b->domain_nr = parent->domain_nr;
567 static void devm_pci_release_host_bridge_dev(struct device *dev)
569 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
571 if (bridge->release_fn)
572 bridge->release_fn(bridge);
574 pci_free_resource_list(&bridge->windows);
577 static void pci_release_host_bridge_dev(struct device *dev)
579 devm_pci_release_host_bridge_dev(dev);
580 kfree(to_pci_host_bridge(dev));
583 static void pci_init_host_bridge(struct pci_host_bridge *bridge)
585 INIT_LIST_HEAD(&bridge->windows);
586 INIT_LIST_HEAD(&bridge->dma_ranges);
589 * We assume we can manage these PCIe features. Some systems may
590 * reserve these for use by the platform itself, e.g., an ACPI BIOS
591 * may implement its own AER handling and use _OSC to prevent the
592 * OS from interfering.
594 bridge->native_aer = 1;
595 bridge->native_pcie_hotplug = 1;
596 bridge->native_shpc_hotplug = 1;
597 bridge->native_pme = 1;
598 bridge->native_ltr = 1;
601 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
603 struct pci_host_bridge *bridge;
605 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
609 pci_init_host_bridge(bridge);
610 bridge->dev.release = pci_release_host_bridge_dev;
614 EXPORT_SYMBOL(pci_alloc_host_bridge);
616 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
619 struct pci_host_bridge *bridge;
621 bridge = devm_kzalloc(dev, sizeof(*bridge) + priv, GFP_KERNEL);
625 pci_init_host_bridge(bridge);
626 bridge->dev.release = devm_pci_release_host_bridge_dev;
630 EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
632 void pci_free_host_bridge(struct pci_host_bridge *bridge)
634 pci_free_resource_list(&bridge->windows);
635 pci_free_resource_list(&bridge->dma_ranges);
639 EXPORT_SYMBOL(pci_free_host_bridge);
641 static const unsigned char pcix_bus_speed[] = {
642 PCI_SPEED_UNKNOWN, /* 0 */
643 PCI_SPEED_66MHz_PCIX, /* 1 */
644 PCI_SPEED_100MHz_PCIX, /* 2 */
645 PCI_SPEED_133MHz_PCIX, /* 3 */
646 PCI_SPEED_UNKNOWN, /* 4 */
647 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
648 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
649 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
650 PCI_SPEED_UNKNOWN, /* 8 */
651 PCI_SPEED_66MHz_PCIX_266, /* 9 */
652 PCI_SPEED_100MHz_PCIX_266, /* A */
653 PCI_SPEED_133MHz_PCIX_266, /* B */
654 PCI_SPEED_UNKNOWN, /* C */
655 PCI_SPEED_66MHz_PCIX_533, /* D */
656 PCI_SPEED_100MHz_PCIX_533, /* E */
657 PCI_SPEED_133MHz_PCIX_533 /* F */
660 const unsigned char pcie_link_speed[] = {
661 PCI_SPEED_UNKNOWN, /* 0 */
662 PCIE_SPEED_2_5GT, /* 1 */
663 PCIE_SPEED_5_0GT, /* 2 */
664 PCIE_SPEED_8_0GT, /* 3 */
665 PCIE_SPEED_16_0GT, /* 4 */
666 PCIE_SPEED_32_0GT, /* 5 */
667 PCI_SPEED_UNKNOWN, /* 6 */
668 PCI_SPEED_UNKNOWN, /* 7 */
669 PCI_SPEED_UNKNOWN, /* 8 */
670 PCI_SPEED_UNKNOWN, /* 9 */
671 PCI_SPEED_UNKNOWN, /* A */
672 PCI_SPEED_UNKNOWN, /* B */
673 PCI_SPEED_UNKNOWN, /* C */
674 PCI_SPEED_UNKNOWN, /* D */
675 PCI_SPEED_UNKNOWN, /* E */
676 PCI_SPEED_UNKNOWN /* F */
679 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
681 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
683 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
685 static unsigned char agp_speeds[] = {
693 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
699 else if (agpstat & 2)
701 else if (agpstat & 1)
713 return agp_speeds[index];
716 static void pci_set_bus_speed(struct pci_bus *bus)
718 struct pci_dev *bridge = bus->self;
721 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
723 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
727 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
728 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
730 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
731 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
734 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
737 enum pci_bus_speed max;
739 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
742 if (status & PCI_X_SSTATUS_533MHZ) {
743 max = PCI_SPEED_133MHz_PCIX_533;
744 } else if (status & PCI_X_SSTATUS_266MHZ) {
745 max = PCI_SPEED_133MHz_PCIX_266;
746 } else if (status & PCI_X_SSTATUS_133MHZ) {
747 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
748 max = PCI_SPEED_133MHz_PCIX_ECC;
750 max = PCI_SPEED_133MHz_PCIX;
752 max = PCI_SPEED_66MHz_PCIX;
755 bus->max_bus_speed = max;
756 bus->cur_bus_speed = pcix_bus_speed[
757 (status & PCI_X_SSTATUS_FREQ) >> 6];
762 if (pci_is_pcie(bridge)) {
766 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
767 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
768 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC);
770 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
771 pcie_update_link_speed(bus, linksta);
775 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
777 struct irq_domain *d;
780 * Any firmware interface that can resolve the msi_domain
781 * should be called from here.
783 d = pci_host_bridge_of_msi_domain(bus);
785 d = pci_host_bridge_acpi_msi_domain(bus);
787 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
789 * If no IRQ domain was found via the OF tree, try looking it up
790 * directly through the fwnode_handle.
793 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
796 d = irq_find_matching_fwnode(fwnode,
804 static void pci_set_bus_msi_domain(struct pci_bus *bus)
806 struct irq_domain *d;
810 * The bus can be a root bus, a subordinate bus, or a virtual bus
811 * created by an SR-IOV device. Walk up to the first bridge device
812 * found or derive the domain from the host bridge.
814 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
816 d = dev_get_msi_domain(&b->self->dev);
820 d = pci_host_bridge_msi_domain(b);
822 dev_set_msi_domain(&bus->dev, d);
825 static int pci_register_host_bridge(struct pci_host_bridge *bridge)
827 struct device *parent = bridge->dev.parent;
828 struct resource_entry *window, *n;
829 struct pci_bus *bus, *b;
830 resource_size_t offset;
831 LIST_HEAD(resources);
832 struct resource *res;
837 bus = pci_alloc_bus(NULL);
843 /* Temporarily move resources off the list */
844 list_splice_init(&bridge->windows, &resources);
845 bus->sysdata = bridge->sysdata;
846 bus->msi = bridge->msi;
847 bus->ops = bridge->ops;
848 bus->number = bus->busn_res.start = bridge->busnr;
849 #ifdef CONFIG_PCI_DOMAINS_GENERIC
850 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
853 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
855 /* Ignore it if we already got here via a different bridge */
856 dev_dbg(&b->dev, "bus already known\n");
861 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
864 err = pcibios_root_bridge_prepare(bridge);
868 err = device_register(&bridge->dev);
870 put_device(&bridge->dev);
872 bus->bridge = get_device(&bridge->dev);
873 device_enable_async_suspend(bus->bridge);
874 pci_set_bus_of_node(bus);
875 pci_set_bus_msi_domain(bus);
878 set_dev_node(bus->bridge, pcibus_to_node(bus));
880 bus->dev.class = &pcibus_class;
881 bus->dev.parent = bus->bridge;
883 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
884 name = dev_name(&bus->dev);
886 err = device_register(&bus->dev);
890 pcibios_add_bus(bus);
892 /* Create legacy_io and legacy_mem files for this bus */
893 pci_create_legacy_files(bus);
896 dev_info(parent, "PCI host bridge to bus %s\n", name);
898 pr_info("PCI host bridge to bus %s\n", name);
900 /* Add initial resources to the bus */
901 resource_list_for_each_entry_safe(window, n, &resources) {
902 list_move_tail(&window->node, &bridge->windows);
903 offset = window->offset;
906 if (res->flags & IORESOURCE_BUS)
907 pci_bus_insert_busn_res(bus, bus->number, res->end);
909 pci_bus_add_resource(bus, res, 0);
912 if (resource_type(res) == IORESOURCE_IO)
913 fmt = " (bus address [%#06llx-%#06llx])";
915 fmt = " (bus address [%#010llx-%#010llx])";
917 snprintf(addr, sizeof(addr), fmt,
918 (unsigned long long)(res->start - offset),
919 (unsigned long long)(res->end - offset));
923 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
926 down_write(&pci_bus_sem);
927 list_add_tail(&bus->node, &pci_root_buses);
928 up_write(&pci_bus_sem);
933 put_device(&bridge->dev);
934 device_unregister(&bridge->dev);
941 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
947 * If extended config space isn't accessible on a bridge's primary
948 * bus, we certainly can't access it on the secondary bus.
950 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
954 * PCIe Root Ports and switch ports are PCIe on both sides, so if
955 * extended config space is accessible on the primary, it's also
956 * accessible on the secondary.
958 if (pci_is_pcie(bridge) &&
959 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
960 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
961 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
965 * For the other bridge types:
966 * - PCI-to-PCI bridges
967 * - PCIe-to-PCI/PCI-X forward bridges
968 * - PCI/PCI-X-to-PCIe reverse bridges
969 * extended config space on the secondary side is only accessible
970 * if the bridge supports PCI-X Mode 2.
972 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
976 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
977 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
980 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
981 struct pci_dev *bridge, int busnr)
983 struct pci_bus *child;
987 /* Allocate a new bus and inherit stuff from the parent */
988 child = pci_alloc_bus(parent);
992 child->parent = parent;
993 child->ops = parent->ops;
994 child->msi = parent->msi;
995 child->sysdata = parent->sysdata;
996 child->bus_flags = parent->bus_flags;
999 * Initialize some portions of the bus device, but don't register
1000 * it now as the parent is not properly set up yet.
1002 child->dev.class = &pcibus_class;
1003 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
1005 /* Set up the primary, secondary and subordinate bus numbers */
1006 child->number = child->busn_res.start = busnr;
1007 child->primary = parent->busn_res.start;
1008 child->busn_res.end = 0xff;
1011 child->dev.parent = parent->bridge;
1015 child->self = bridge;
1016 child->bridge = get_device(&bridge->dev);
1017 child->dev.parent = child->bridge;
1018 pci_set_bus_of_node(child);
1019 pci_set_bus_speed(child);
1022 * Check whether extended config space is accessible on the child
1023 * bus. Note that we currently assume it is always accessible on
1026 if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1027 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1028 pci_info(child, "extended config space not accessible\n");
1031 /* Set up default resource pointers and names */
1032 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
1033 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1034 child->resource[i]->name = child->name;
1036 bridge->subordinate = child;
1039 pci_set_bus_msi_domain(child);
1040 ret = device_register(&child->dev);
1043 pcibios_add_bus(child);
1045 if (child->ops->add_bus) {
1046 ret = child->ops->add_bus(child);
1047 if (WARN_ON(ret < 0))
1048 dev_err(&child->dev, "failed to add bus: %d\n", ret);
1051 /* Create legacy_io and legacy_mem files for this bus */
1052 pci_create_legacy_files(child);
1057 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1060 struct pci_bus *child;
1062 child = pci_alloc_child_bus(parent, dev, busnr);
1064 down_write(&pci_bus_sem);
1065 list_add_tail(&child->node, &parent->children);
1066 up_write(&pci_bus_sem);
1070 EXPORT_SYMBOL(pci_add_new_bus);
1072 static void pci_enable_crs(struct pci_dev *pdev)
1076 /* Enable CRS Software Visibility if supported */
1077 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1078 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
1079 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1080 PCI_EXP_RTCTL_CRSSVE);
1083 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1084 unsigned int available_buses);
1086 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1087 * numbers from EA capability.
1089 * @sec: updated with secondary bus number from EA
1090 * @sub: updated with subordinate bus number from EA
1092 * If @dev is a bridge with EA capability, update @sec and @sub with
1093 * fixed bus numbers from the capability and return true. Otherwise,
1096 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1101 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1104 /* find PCI EA capability in list */
1105 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1109 offset = ea + PCI_EA_FIRST_ENT;
1110 pci_read_config_dword(dev, offset, &dw);
1111 *sec = dw & PCI_EA_SEC_BUS_MASK;
1112 *sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
1117 * pci_scan_bridge_extend() - Scan buses behind a bridge
1118 * @bus: Parent bus the bridge is on
1119 * @dev: Bridge itself
1120 * @max: Starting subordinate number of buses behind this bridge
1121 * @available_buses: Total number of buses available for this bridge and
1122 * the devices below. After the minimal bus space has
1123 * been allocated the remaining buses will be
1124 * distributed equally between hotplug-capable bridges.
1125 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1126 * that need to be reconfigured.
1128 * If it's a bridge, configure it and scan the bus behind it.
1129 * For CardBus bridges, we don't scan behind as the devices will
1130 * be handled by the bridge driver itself.
1132 * We need to process bridges in two passes -- first we scan those
1133 * already configured by the BIOS and after we are done with all of
1134 * them, we proceed to assigning numbers to the remaining buses in
1135 * order to avoid overlaps between old and new bus numbers.
1137 * Return: New subordinate number covering all buses behind this bridge.
1139 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1140 int max, unsigned int available_buses,
1143 struct pci_bus *child;
1144 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1145 u32 buses, i, j = 0;
1147 u8 primary, secondary, subordinate;
1150 u8 fixed_sec, fixed_sub;
1154 * Make sure the bridge is powered on to be able to access config
1155 * space of devices below it.
1157 pm_runtime_get_sync(&dev->dev);
1159 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1160 primary = buses & 0xFF;
1161 secondary = (buses >> 8) & 0xFF;
1162 subordinate = (buses >> 16) & 0xFF;
1164 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1165 secondary, subordinate, pass);
1167 if (!primary && (primary != bus->number) && secondary && subordinate) {
1168 pci_warn(dev, "Primary bus is hard wired to 0\n");
1169 primary = bus->number;
1172 /* Check if setup is sensible at all */
1174 (primary != bus->number || secondary <= bus->number ||
1175 secondary > subordinate)) {
1176 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1177 secondary, subordinate);
1182 * Disable Master-Abort Mode during probing to avoid reporting of
1183 * bus errors in some architectures.
1185 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1186 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1187 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1189 pci_enable_crs(dev);
1191 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1192 !is_cardbus && !broken) {
1196 * Bus already configured by firmware, process it in the
1197 * first pass and just note the configuration.
1203 * The bus might already exist for two reasons: Either we
1204 * are rescanning the bus or the bus is reachable through
1205 * more than one bridge. The second case can happen with
1206 * the i450NX chipset.
1208 child = pci_find_bus(pci_domain_nr(bus), secondary);
1210 child = pci_add_new_bus(bus, dev, secondary);
1213 child->primary = primary;
1214 pci_bus_insert_busn_res(child, secondary, subordinate);
1215 child->bridge_ctl = bctl;
1218 cmax = pci_scan_child_bus(child);
1219 if (cmax > subordinate)
1220 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1223 /* Subordinate should equal child->busn_res.end */
1224 if (subordinate > max)
1229 * We need to assign a number to this bus which we always
1230 * do in the second pass.
1233 if (pcibios_assign_all_busses() || broken || is_cardbus)
1236 * Temporarily disable forwarding of the
1237 * configuration cycles on all bridges in
1238 * this bus segment to avoid possible
1239 * conflicts in the second pass between two
1240 * bridges programmed with overlapping bus
1243 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1249 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1251 /* Read bus numbers from EA Capability (if present) */
1252 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1254 next_busnr = fixed_sec;
1256 next_busnr = max + 1;
1259 * Prevent assigning a bus number that already exists.
1260 * This can happen when a bridge is hot-plugged, so in this
1261 * case we only re-scan this bus.
1263 child = pci_find_bus(pci_domain_nr(bus), next_busnr);
1265 child = pci_add_new_bus(bus, dev, next_busnr);
1268 pci_bus_insert_busn_res(child, next_busnr,
1272 if (available_buses)
1275 buses = (buses & 0xff000000)
1276 | ((unsigned int)(child->primary) << 0)
1277 | ((unsigned int)(child->busn_res.start) << 8)
1278 | ((unsigned int)(child->busn_res.end) << 16);
1281 * yenta.c forces a secondary latency timer of 176.
1282 * Copy that behaviour here.
1285 buses &= ~0xff000000;
1286 buses |= CARDBUS_LATENCY_TIMER << 24;
1289 /* We need to blast all three values with a single write */
1290 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1293 child->bridge_ctl = bctl;
1294 max = pci_scan_child_bus_extend(child, available_buses);
1298 * For CardBus bridges, we leave 4 bus numbers as
1299 * cards with a PCI-to-PCI bridge can be inserted
1302 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1303 struct pci_bus *parent = bus;
1304 if (pci_find_bus(pci_domain_nr(bus),
1307 while (parent->parent) {
1308 if ((!pcibios_assign_all_busses()) &&
1309 (parent->busn_res.end > max) &&
1310 (parent->busn_res.end <= max+i)) {
1313 parent = parent->parent;
1318 * Often, there are two CardBus
1319 * bridges -- try to leave one
1320 * valid bus number for each one.
1330 * Set subordinate bus number to its real value.
1331 * If fixed subordinate bus number exists from EA
1332 * capability then use it.
1336 pci_bus_update_busn_res_end(child, max);
1337 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1340 sprintf(child->name,
1341 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1342 pci_domain_nr(bus), child->number);
1344 /* Check that all devices are accessible */
1345 while (bus->parent) {
1346 if ((child->busn_res.end > bus->busn_res.end) ||
1347 (child->number > bus->busn_res.end) ||
1348 (child->number < bus->number) ||
1349 (child->busn_res.end < bus->number)) {
1350 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1358 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1360 pm_runtime_put(&dev->dev);
1366 * pci_scan_bridge() - Scan buses behind a bridge
1367 * @bus: Parent bus the bridge is on
1368 * @dev: Bridge itself
1369 * @max: Starting subordinate number of buses behind this bridge
1370 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1371 * that need to be reconfigured.
1373 * If it's a bridge, configure it and scan the bus behind it.
1374 * For CardBus bridges, we don't scan behind as the devices will
1375 * be handled by the bridge driver itself.
1377 * We need to process bridges in two passes -- first we scan those
1378 * already configured by the BIOS and after we are done with all of
1379 * them, we proceed to assigning numbers to the remaining buses in
1380 * order to avoid overlaps between old and new bus numbers.
1382 * Return: New subordinate number covering all buses behind this bridge.
1384 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1386 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1388 EXPORT_SYMBOL(pci_scan_bridge);
1391 * Read interrupt line and base address registers.
1392 * The architecture-dependent code can tweak these, of course.
1394 static void pci_read_irq(struct pci_dev *dev)
1398 /* VFs are not allowed to use INTx, so skip the config reads */
1399 if (dev->is_virtfn) {
1405 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1408 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1412 void set_pcie_port_type(struct pci_dev *pdev)
1417 struct pci_dev *parent;
1419 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1423 pdev->pcie_cap = pos;
1424 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1425 pdev->pcie_flags_reg = reg16;
1426 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1427 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1429 parent = pci_upstream_bridge(pdev);
1434 * Some systems do not identify their upstream/downstream ports
1435 * correctly so detect impossible configurations here and correct
1436 * the port type accordingly.
1438 type = pci_pcie_type(pdev);
1439 if (type == PCI_EXP_TYPE_DOWNSTREAM) {
1441 * If pdev claims to be downstream port but the parent
1442 * device is also downstream port assume pdev is actually
1445 if (pcie_downstream_port(parent)) {
1446 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1447 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1448 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1450 } else if (type == PCI_EXP_TYPE_UPSTREAM) {
1452 * If pdev claims to be upstream port but the parent
1453 * device is also upstream port assume pdev is actually
1456 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1457 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1458 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1459 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1464 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1468 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1469 if (reg32 & PCI_EXP_SLTCAP_HPC)
1470 pdev->is_hotplug_bridge = 1;
1473 static void set_pcie_thunderbolt(struct pci_dev *dev)
1478 while ((vsec = pci_find_next_ext_capability(dev, vsec,
1479 PCI_EXT_CAP_ID_VNDR))) {
1480 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
1482 /* Is the device part of a Thunderbolt controller? */
1483 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
1484 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
1485 dev->is_thunderbolt = 1;
1491 static void set_pcie_untrusted(struct pci_dev *dev)
1493 struct pci_dev *parent;
1496 * If the upstream bridge is untrusted we treat this device
1497 * untrusted as well.
1499 parent = pci_upstream_bridge(dev);
1500 if (parent && parent->untrusted)
1501 dev->untrusted = true;
1505 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1508 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1509 * when forwarding a type1 configuration request the bridge must check that
1510 * the extended register address field is zero. The bridge is not permitted
1511 * to forward the transactions and must handle it as an Unsupported Request.
1512 * Some bridges do not follow this rule and simply drop the extended register
1513 * bits, resulting in the standard config space being aliased, every 256
1514 * bytes across the entire configuration space. Test for this condition by
1515 * comparing the first dword of each potential alias to the vendor/device ID.
1517 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1518 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1520 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1522 #ifdef CONFIG_PCI_QUIRKS
1526 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1528 for (pos = PCI_CFG_SPACE_SIZE;
1529 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1530 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1542 * pci_cfg_space_size - Get the configuration space size of the PCI device
1545 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1546 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1547 * access it. Maybe we don't have a way to generate extended config space
1548 * accesses, or the device is behind a reverse Express bridge. So we try
1549 * reading the dword at 0x100 which must either be 0 or a valid extended
1550 * capability header.
1552 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1555 int pos = PCI_CFG_SPACE_SIZE;
1557 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1558 return PCI_CFG_SPACE_SIZE;
1559 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1560 return PCI_CFG_SPACE_SIZE;
1562 return PCI_CFG_SPACE_EXP_SIZE;
1565 int pci_cfg_space_size(struct pci_dev *dev)
1571 #ifdef CONFIG_PCI_IOV
1573 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1574 * implement a PCIe capability and therefore must implement extended
1575 * config space. We can skip the NO_EXTCFG test below and the
1576 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1577 * the fact that the SR-IOV capability on the PF resides in extended
1578 * config space and must be accessible and non-aliased to have enabled
1579 * support for this VF. This is a micro performance optimization for
1580 * systems supporting many VFs.
1583 return PCI_CFG_SPACE_EXP_SIZE;
1586 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1587 return PCI_CFG_SPACE_SIZE;
1589 class = dev->class >> 8;
1590 if (class == PCI_CLASS_BRIDGE_HOST)
1591 return pci_cfg_space_size_ext(dev);
1593 if (pci_is_pcie(dev))
1594 return pci_cfg_space_size_ext(dev);
1596 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1598 return PCI_CFG_SPACE_SIZE;
1600 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1601 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1602 return pci_cfg_space_size_ext(dev);
1604 return PCI_CFG_SPACE_SIZE;
1607 static u32 pci_class(struct pci_dev *dev)
1611 #ifdef CONFIG_PCI_IOV
1613 return dev->physfn->sriov->class;
1615 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1619 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1621 #ifdef CONFIG_PCI_IOV
1622 if (dev->is_virtfn) {
1623 *vendor = dev->physfn->sriov->subsystem_vendor;
1624 *device = dev->physfn->sriov->subsystem_device;
1628 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1629 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1632 static u8 pci_hdr_type(struct pci_dev *dev)
1636 #ifdef CONFIG_PCI_IOV
1638 return dev->physfn->sriov->hdr_type;
1640 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1644 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1646 static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1649 * Disable the MSI hardware to avoid screaming interrupts
1650 * during boot. This is the power on reset default so
1651 * usually this should be a noop.
1653 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1655 pci_msi_set_enable(dev, 0);
1657 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1659 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1663 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1666 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1667 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1669 static int pci_intx_mask_broken(struct pci_dev *dev)
1671 u16 orig, toggle, new;
1673 pci_read_config_word(dev, PCI_COMMAND, &orig);
1674 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1675 pci_write_config_word(dev, PCI_COMMAND, toggle);
1676 pci_read_config_word(dev, PCI_COMMAND, &new);
1678 pci_write_config_word(dev, PCI_COMMAND, orig);
1681 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1682 * r2.3, so strictly speaking, a device is not *broken* if it's not
1683 * writable. But we'll live with the misnomer for now.
1690 static void early_dump_pci_device(struct pci_dev *pdev)
1695 pci_info(pdev, "config space:\n");
1697 for (i = 0; i < 256; i += 4)
1698 pci_read_config_dword(pdev, i, &value[i / 4]);
1700 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1705 * pci_setup_device - Fill in class and map information of a device
1706 * @dev: the device structure to fill
1708 * Initialize the device structure with information about the device's
1709 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1710 * Called at initialisation of the PCI subsystem and by CardBus services.
1711 * Returns 0 on success and negative if unknown type of device (not normal,
1712 * bridge or CardBus).
1714 int pci_setup_device(struct pci_dev *dev)
1720 struct pci_bus_region region;
1721 struct resource *res;
1723 hdr_type = pci_hdr_type(dev);
1725 dev->sysdata = dev->bus->sysdata;
1726 dev->dev.parent = dev->bus->bridge;
1727 dev->dev.bus = &pci_bus_type;
1728 dev->hdr_type = hdr_type & 0x7f;
1729 dev->multifunction = !!(hdr_type & 0x80);
1730 dev->error_state = pci_channel_io_normal;
1731 set_pcie_port_type(dev);
1733 pci_dev_assign_slot(dev);
1736 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1737 * set this higher, assuming the system even supports it.
1739 dev->dma_mask = 0xffffffff;
1741 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1742 dev->bus->number, PCI_SLOT(dev->devfn),
1743 PCI_FUNC(dev->devfn));
1745 class = pci_class(dev);
1747 dev->revision = class & 0xff;
1748 dev->class = class >> 8; /* upper 3 bytes */
1750 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
1751 dev->vendor, dev->device, dev->hdr_type, dev->class);
1754 early_dump_pci_device(dev);
1756 /* Need to have dev->class ready */
1757 dev->cfg_size = pci_cfg_space_size(dev);
1759 /* Need to have dev->cfg_size ready */
1760 set_pcie_thunderbolt(dev);
1762 set_pcie_untrusted(dev);
1764 /* "Unknown power state" */
1765 dev->current_state = PCI_UNKNOWN;
1767 /* Early fixups, before probing the BARs */
1768 pci_fixup_device(pci_fixup_early, dev);
1770 /* Device class may be changed after fixup */
1771 class = dev->class >> 8;
1773 if (dev->non_compliant_bars) {
1774 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1775 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1776 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1777 cmd &= ~PCI_COMMAND_IO;
1778 cmd &= ~PCI_COMMAND_MEMORY;
1779 pci_write_config_word(dev, PCI_COMMAND, cmd);
1783 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1785 switch (dev->hdr_type) { /* header type */
1786 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1787 if (class == PCI_CLASS_BRIDGE_PCI)
1790 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1792 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1795 * Do the ugly legacy mode stuff here rather than broken chip
1796 * quirk code. Legacy mode ATA controllers have fixed
1797 * addresses. These are not always echoed in BAR0-3, and
1798 * BAR0-3 in a few cases contain junk!
1800 if (class == PCI_CLASS_STORAGE_IDE) {
1802 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1803 if ((progif & 1) == 0) {
1804 region.start = 0x1F0;
1806 res = &dev->resource[0];
1807 res->flags = LEGACY_IO_RESOURCE;
1808 pcibios_bus_to_resource(dev->bus, res, ®ion);
1809 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1811 region.start = 0x3F6;
1813 res = &dev->resource[1];
1814 res->flags = LEGACY_IO_RESOURCE;
1815 pcibios_bus_to_resource(dev->bus, res, ®ion);
1816 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1819 if ((progif & 4) == 0) {
1820 region.start = 0x170;
1822 res = &dev->resource[2];
1823 res->flags = LEGACY_IO_RESOURCE;
1824 pcibios_bus_to_resource(dev->bus, res, ®ion);
1825 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1827 region.start = 0x376;
1829 res = &dev->resource[3];
1830 res->flags = LEGACY_IO_RESOURCE;
1831 pcibios_bus_to_resource(dev->bus, res, ®ion);
1832 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1838 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1840 * The PCI-to-PCI bridge spec requires that subtractive
1841 * decoding (i.e. transparent) bridge must have programming
1842 * interface code of 0x01.
1845 dev->transparent = ((dev->class & 0xff) == 1);
1846 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1847 pci_read_bridge_windows(dev);
1848 set_pcie_hotplug_bridge(dev);
1849 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1851 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1852 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1856 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1857 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1860 pci_read_bases(dev, 1, 0);
1861 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1862 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1865 default: /* unknown header */
1866 pci_err(dev, "unknown header type %02x, ignoring device\n",
1871 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1872 dev->class, dev->hdr_type);
1873 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1876 /* We found a fine healthy device, go go go... */
1880 static void pci_configure_mps(struct pci_dev *dev)
1882 struct pci_dev *bridge = pci_upstream_bridge(dev);
1883 int mps, mpss, p_mps, rc;
1885 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1888 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
1892 mps = pcie_get_mps(dev);
1893 p_mps = pcie_get_mps(bridge);
1898 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1899 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1900 mps, pci_name(bridge), p_mps);
1905 * Fancier MPS configuration is done later by
1906 * pcie_bus_configure_settings()
1908 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1911 mpss = 128 << dev->pcie_mpss;
1912 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
1913 pcie_set_mps(bridge, mpss);
1914 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
1915 mpss, p_mps, 128 << bridge->pcie_mpss);
1916 p_mps = pcie_get_mps(bridge);
1919 rc = pcie_set_mps(dev, p_mps);
1921 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1926 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
1930 int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
1932 struct pci_host_bridge *host;
1937 if (!pci_is_pcie(dev))
1940 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
1944 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
1947 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
1951 host = pci_find_host_bridge(dev->bus);
1956 * If some device in the hierarchy doesn't handle Extended Tags
1957 * correctly, make sure they're disabled.
1959 if (host->no_ext_tags) {
1960 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
1961 pci_info(dev, "disabling Extended Tags\n");
1962 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
1963 PCI_EXP_DEVCTL_EXT_TAG);
1968 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
1969 pci_info(dev, "enabling Extended Tags\n");
1970 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
1971 PCI_EXP_DEVCTL_EXT_TAG);
1977 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
1978 * @dev: PCI device to query
1980 * Returns true if the device has enabled relaxed ordering attribute.
1982 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
1986 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
1988 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
1990 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
1992 static void pci_configure_relaxed_ordering(struct pci_dev *dev)
1994 struct pci_dev *root;
1996 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
2000 if (!pcie_relaxed_ordering_enabled(dev))
2004 * For now, we only deal with Relaxed Ordering issues with Root
2005 * Ports. Peer-to-Peer DMA is another can of worms.
2007 root = pci_find_pcie_root_port(dev);
2011 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2012 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2013 PCI_EXP_DEVCTL_RELAX_EN);
2014 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2018 static void pci_configure_ltr(struct pci_dev *dev)
2020 #ifdef CONFIG_PCIEASPM
2021 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
2022 struct pci_dev *bridge;
2025 if (!pci_is_pcie(dev))
2028 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2029 if (!(cap & PCI_EXP_DEVCAP2_LTR))
2032 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2033 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2034 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2039 bridge = pci_upstream_bridge(dev);
2040 if (bridge && bridge->ltr_path)
2046 if (!host->native_ltr)
2050 * Software must not enable LTR in an Endpoint unless the Root
2051 * Complex and all intermediate Switches indicate support for LTR.
2052 * PCIe r4.0, sec 6.18.
2054 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
2055 ((bridge = pci_upstream_bridge(dev)) &&
2056 bridge->ltr_path)) {
2057 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2058 PCI_EXP_DEVCTL2_LTR_EN);
2064 static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2066 #ifdef CONFIG_PCI_PASID
2067 struct pci_dev *bridge;
2071 if (!pci_is_pcie(dev))
2074 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2075 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2078 pcie_type = pci_pcie_type(dev);
2079 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2080 pcie_type == PCI_EXP_TYPE_RC_END)
2081 dev->eetlp_prefix_path = 1;
2083 bridge = pci_upstream_bridge(dev);
2084 if (bridge && bridge->eetlp_prefix_path)
2085 dev->eetlp_prefix_path = 1;
2090 static void pci_configure_serr(struct pci_dev *dev)
2094 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2097 * A bridge will not forward ERR_ messages coming from an
2098 * endpoint unless SERR# forwarding is enabled.
2100 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2101 if (!(control & PCI_BRIDGE_CTL_SERR)) {
2102 control |= PCI_BRIDGE_CTL_SERR;
2103 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2108 static void pci_configure_device(struct pci_dev *dev)
2110 pci_configure_mps(dev);
2111 pci_configure_extended_tags(dev, NULL);
2112 pci_configure_relaxed_ordering(dev);
2113 pci_configure_ltr(dev);
2114 pci_configure_eetlp_prefix(dev);
2115 pci_configure_serr(dev);
2117 pci_acpi_program_hp_params(dev);
2120 static void pci_release_capabilities(struct pci_dev *dev)
2123 pci_vpd_release(dev);
2124 pci_iov_release(dev);
2125 pci_free_cap_save_buffers(dev);
2129 * pci_release_dev - Free a PCI device structure when all users of it are
2131 * @dev: device that's been disconnected
2133 * Will be called only by the device core when all users of this PCI device are
2136 static void pci_release_dev(struct device *dev)
2138 struct pci_dev *pci_dev;
2140 pci_dev = to_pci_dev(dev);
2141 pci_release_capabilities(pci_dev);
2142 pci_release_of_node(pci_dev);
2143 pcibios_release_device(pci_dev);
2144 pci_bus_put(pci_dev->bus);
2145 kfree(pci_dev->driver_override);
2146 bitmap_free(pci_dev->dma_alias_mask);
2150 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2152 struct pci_dev *dev;
2154 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2158 INIT_LIST_HEAD(&dev->bus_list);
2159 dev->dev.type = &pci_dev_type;
2160 dev->bus = pci_bus_get(bus);
2164 EXPORT_SYMBOL(pci_alloc_dev);
2166 static bool pci_bus_crs_vendor_id(u32 l)
2168 return (l & 0xffff) == 0x0001;
2171 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2176 if (!pci_bus_crs_vendor_id(*l))
2177 return true; /* not a CRS completion */
2180 return false; /* CRS, but caller doesn't want to wait */
2183 * We got the reserved Vendor ID that indicates a completion with
2184 * Configuration Request Retry Status (CRS). Retry until we get a
2185 * valid Vendor ID or we time out.
2187 while (pci_bus_crs_vendor_id(*l)) {
2188 if (delay > timeout) {
2189 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2190 pci_domain_nr(bus), bus->number,
2191 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2196 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2197 pci_domain_nr(bus), bus->number,
2198 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2203 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2208 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2209 pci_domain_nr(bus), bus->number,
2210 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2215 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2218 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2221 /* Some broken boards return 0 or ~0 if a slot is empty: */
2222 if (*l == 0xffffffff || *l == 0x00000000 ||
2223 *l == 0x0000ffff || *l == 0xffff0000)
2226 if (pci_bus_crs_vendor_id(*l))
2227 return pci_bus_wait_crs(bus, devfn, l, timeout);
2232 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2235 #ifdef CONFIG_PCI_QUIRKS
2236 struct pci_dev *bridge = bus->self;
2239 * Certain IDT switches have an issue where they improperly trigger
2240 * ACS Source Validation errors on completions for config reads.
2242 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2243 bridge->device == 0x80b5)
2244 return pci_idt_bus_quirk(bus, devfn, l, timeout);
2247 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2249 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2252 * Read the config data for a PCI device, sanity-check it,
2253 * and fill in the dev structure.
2255 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2257 struct pci_dev *dev;
2260 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2263 dev = pci_alloc_dev(bus);
2268 dev->vendor = l & 0xffff;
2269 dev->device = (l >> 16) & 0xffff;
2271 pci_set_of_node(dev);
2273 if (pci_setup_device(dev)) {
2274 pci_bus_put(dev->bus);
2282 void pcie_report_downtraining(struct pci_dev *dev)
2284 if (!pci_is_pcie(dev))
2287 /* Look from the device up to avoid downstream ports with no devices */
2288 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2289 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2290 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2293 /* Multi-function PCIe devices share the same link/status */
2294 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2297 /* Print link status only if the device is constrained by the fabric */
2298 __pcie_print_link_status(dev, false);
2301 static void pci_init_capabilities(struct pci_dev *dev)
2303 /* Enhanced Allocation */
2306 /* Setup MSI caps & disable MSI/MSI-X interrupts */
2307 pci_msi_setup_pci_dev(dev);
2309 /* Buffers for saving PCIe and PCI-X capabilities */
2310 pci_allocate_cap_save_buffers(dev);
2312 /* Power Management */
2315 /* Vital Product Data */
2318 /* Alternative Routing-ID Forwarding */
2319 pci_configure_ari(dev);
2321 /* Single Root I/O Virtualization */
2324 /* Address Translation Services */
2327 /* Enable ACS P2P upstream forwarding */
2328 pci_enable_acs(dev);
2330 /* Precision Time Measurement */
2333 /* Advanced Error Reporting */
2336 pcie_report_downtraining(dev);
2338 if (pci_probe_reset_function(dev) == 0)
2343 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2344 * devices. Firmware interfaces that can select the MSI domain on a
2345 * per-device basis should be called from here.
2347 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2349 struct irq_domain *d;
2352 * If a domain has been set through the pcibios_add_device()
2353 * callback, then this is the one (platform code knows best).
2355 d = dev_get_msi_domain(&dev->dev);
2360 * Let's see if we have a firmware interface able to provide
2363 d = pci_msi_get_device_domain(dev);
2370 static void pci_set_msi_domain(struct pci_dev *dev)
2372 struct irq_domain *d;
2375 * If the platform or firmware interfaces cannot supply a
2376 * device-specific MSI domain, then inherit the default domain
2377 * from the host bridge itself.
2379 d = pci_dev_msi_domain(dev);
2381 d = dev_get_msi_domain(&dev->bus->dev);
2383 dev_set_msi_domain(&dev->dev, d);
2386 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2390 pci_configure_device(dev);
2392 device_initialize(&dev->dev);
2393 dev->dev.release = pci_release_dev;
2395 set_dev_node(&dev->dev, pcibus_to_node(bus));
2396 dev->dev.dma_mask = &dev->dma_mask;
2397 dev->dev.dma_parms = &dev->dma_parms;
2398 dev->dev.coherent_dma_mask = 0xffffffffull;
2400 dma_set_max_seg_size(&dev->dev, 65536);
2401 dma_set_seg_boundary(&dev->dev, 0xffffffff);
2403 /* Fix up broken headers */
2404 pci_fixup_device(pci_fixup_header, dev);
2406 /* Moved out from quirk header fixup code */
2407 pci_reassigndev_resource_alignment(dev);
2409 /* Clear the state_saved flag */
2410 dev->state_saved = false;
2412 /* Initialize various capabilities */
2413 pci_init_capabilities(dev);
2416 * Add the device to our list of discovered devices
2417 * and the bus list for fixup functions, etc.
2419 down_write(&pci_bus_sem);
2420 list_add_tail(&dev->bus_list, &bus->devices);
2421 up_write(&pci_bus_sem);
2423 ret = pcibios_add_device(dev);
2426 /* Set up MSI IRQ domain */
2427 pci_set_msi_domain(dev);
2429 /* Notifier could use PCI capabilities */
2430 dev->match_driver = false;
2431 ret = device_add(&dev->dev);
2435 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2437 struct pci_dev *dev;
2439 dev = pci_get_slot(bus, devfn);
2445 dev = pci_scan_device(bus, devfn);
2449 pci_device_add(dev, bus);
2453 EXPORT_SYMBOL(pci_scan_single_device);
2455 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
2461 if (pci_ari_enabled(bus)) {
2464 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2468 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2469 next_fn = PCI_ARI_CAP_NFN(cap);
2471 return 0; /* protect against malformed list */
2476 /* dev may be NULL for non-contiguous multifunction devices */
2477 if (!dev || dev->multifunction)
2478 return (fn + 1) % 8;
2483 static int only_one_child(struct pci_bus *bus)
2485 struct pci_dev *bridge = bus->self;
2488 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2489 * we scan for all possible devices, not just Device 0.
2491 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2495 * A PCIe Downstream Port normally leads to a Link with only Device
2496 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2497 * only for Device 0 in that situation.
2499 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
2506 * pci_scan_slot - Scan a PCI slot on a bus for devices
2507 * @bus: PCI bus to scan
2508 * @devfn: slot number to scan (must have zero function)
2510 * Scan a PCI slot on the specified PCI bus for devices, adding
2511 * discovered devices to the @bus->devices list. New devices
2512 * will not have is_added set.
2514 * Returns the number of new devices found.
2516 int pci_scan_slot(struct pci_bus *bus, int devfn)
2518 unsigned fn, nr = 0;
2519 struct pci_dev *dev;
2521 if (only_one_child(bus) && (devfn > 0))
2522 return 0; /* Already scanned the entire slot */
2524 dev = pci_scan_single_device(bus, devfn);
2527 if (!pci_dev_is_added(dev))
2530 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2531 dev = pci_scan_single_device(bus, devfn + fn);
2533 if (!pci_dev_is_added(dev))
2535 dev->multifunction = 1;
2539 /* Only one slot has PCIe device */
2540 if (bus->self && nr)
2541 pcie_aspm_init_link_state(bus->self);
2545 EXPORT_SYMBOL(pci_scan_slot);
2547 static int pcie_find_smpss(struct pci_dev *dev, void *data)
2551 if (!pci_is_pcie(dev))
2555 * We don't have a way to change MPS settings on devices that have
2556 * drivers attached. A hot-added device might support only the minimum
2557 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2558 * where devices may be hot-added, we limit the fabric MPS to 128 so
2559 * hot-added devices will work correctly.
2561 * However, if we hot-add a device to a slot directly below a Root
2562 * Port, it's impossible for there to be other existing devices below
2563 * the port. We don't limit the MPS in this case because we can
2564 * reconfigure MPS on both the Root Port and the hot-added device,
2565 * and there are no other devices involved.
2567 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2569 if (dev->is_hotplug_bridge &&
2570 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2573 if (*smpss > dev->pcie_mpss)
2574 *smpss = dev->pcie_mpss;
2579 static void pcie_write_mps(struct pci_dev *dev, int mps)
2583 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2584 mps = 128 << dev->pcie_mpss;
2586 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2590 * For "Performance", the assumption is made that
2591 * downstream communication will never be larger than
2592 * the MRRS. So, the MPS only needs to be configured
2593 * for the upstream communication. This being the case,
2594 * walk from the top down and set the MPS of the child
2595 * to that of the parent bus.
2597 * Configure the device MPS with the smaller of the
2598 * device MPSS or the bridge MPS (which is assumed to be
2599 * properly configured at this point to the largest
2600 * allowable MPS based on its parent bus).
2602 mps = min(mps, pcie_get_mps(dev->bus->self));
2605 rc = pcie_set_mps(dev, mps);
2607 pci_err(dev, "Failed attempting to set the MPS\n");
2610 static void pcie_write_mrrs(struct pci_dev *dev)
2615 * In the "safe" case, do not configure the MRRS. There appear to be
2616 * issues with setting MRRS to 0 on a number of devices.
2618 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2622 * For max performance, the MRRS must be set to the largest supported
2623 * value. However, it cannot be configured larger than the MPS the
2624 * device or the bus can support. This should already be properly
2625 * configured by a prior call to pcie_write_mps().
2627 mrrs = pcie_get_mps(dev);
2630 * MRRS is a R/W register. Invalid values can be written, but a
2631 * subsequent read will verify if the value is acceptable or not.
2632 * If the MRRS value provided is not acceptable (e.g., too large),
2633 * shrink the value until it is acceptable to the HW.
2635 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2636 rc = pcie_set_readrq(dev, mrrs);
2640 pci_warn(dev, "Failed attempting to set the MRRS\n");
2645 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2648 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2652 if (!pci_is_pcie(dev))
2655 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2656 pcie_bus_config == PCIE_BUS_DEFAULT)
2659 mps = 128 << *(u8 *)data;
2660 orig_mps = pcie_get_mps(dev);
2662 pcie_write_mps(dev, mps);
2663 pcie_write_mrrs(dev);
2665 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2666 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2667 orig_mps, pcie_get_readrq(dev));
2673 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2674 * parents then children fashion. If this changes, then this code will not
2677 void pcie_bus_configure_settings(struct pci_bus *bus)
2684 if (!pci_is_pcie(bus->self))
2688 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2689 * to be aware of the MPS of the destination. To work around this,
2690 * simply force the MPS of the entire system to the smallest possible.
2692 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2695 if (pcie_bus_config == PCIE_BUS_SAFE) {
2696 smpss = bus->self->pcie_mpss;
2698 pcie_find_smpss(bus->self, &smpss);
2699 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2702 pcie_bus_configure_set(bus->self, &smpss);
2703 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2705 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2708 * Called after each bus is probed, but before its children are examined. This
2709 * is marked as __weak because multiple architectures define it.
2711 void __weak pcibios_fixup_bus(struct pci_bus *bus)
2713 /* nothing to do, expected to be removed in the future */
2717 * pci_scan_child_bus_extend() - Scan devices below a bus
2718 * @bus: Bus to scan for devices
2719 * @available_buses: Total number of buses available (%0 does not try to
2720 * extend beyond the minimal)
2722 * Scans devices below @bus including subordinate buses. Returns new
2723 * subordinate number including all the found devices. Passing
2724 * @available_buses causes the remaining bus space to be distributed
2725 * equally between hotplug-capable bridges to allow future extension of the
2728 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2729 unsigned int available_buses)
2731 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2732 unsigned int start = bus->busn_res.start;
2733 unsigned int devfn, fn, cmax, max = start;
2734 struct pci_dev *dev;
2737 dev_dbg(&bus->dev, "scanning bus\n");
2739 /* Go find them, Rover! */
2740 for (devfn = 0; devfn < 256; devfn += 8) {
2741 nr_devs = pci_scan_slot(bus, devfn);
2744 * The Jailhouse hypervisor may pass individual functions of a
2745 * multi-function device to a guest without passing function 0.
2746 * Look for them as well.
2748 if (jailhouse_paravirt() && nr_devs == 0) {
2749 for (fn = 1; fn < 8; fn++) {
2750 dev = pci_scan_single_device(bus, devfn + fn);
2752 dev->multifunction = 1;
2757 /* Reserve buses for SR-IOV capability */
2758 used_buses = pci_iov_bus_range(bus);
2762 * After performing arch-dependent fixup of the bus, look behind
2763 * all PCI-to-PCI bridges on this bus.
2765 if (!bus->is_added) {
2766 dev_dbg(&bus->dev, "fixups for bus\n");
2767 pcibios_fixup_bus(bus);
2772 * Calculate how many hotplug bridges and normal bridges there
2773 * are on this bus. We will distribute the additional available
2774 * buses between hotplug bridges.
2776 for_each_pci_bridge(dev, bus) {
2777 if (dev->is_hotplug_bridge)
2784 * Scan bridges that are already configured. We don't touch them
2785 * unless they are misconfigured (which will be done in the second
2788 for_each_pci_bridge(dev, bus) {
2790 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2793 * Reserve one bus for each bridge now to avoid extending
2794 * hotplug bridges too much during the second scan below.
2798 used_buses += cmax - max - 1;
2801 /* Scan bridges that need to be reconfigured */
2802 for_each_pci_bridge(dev, bus) {
2803 unsigned int buses = 0;
2805 if (!hotplug_bridges && normal_bridges == 1) {
2808 * There is only one bridge on the bus (upstream
2809 * port) so it gets all available buses which it
2810 * can then distribute to the possible hotplug
2813 buses = available_buses;
2814 } else if (dev->is_hotplug_bridge) {
2817 * Distribute the extra buses between hotplug
2820 buses = available_buses / hotplug_bridges;
2821 buses = min(buses, available_buses - used_buses + 1);
2825 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2826 /* One bus is already accounted so don't add it again */
2828 used_buses += max - cmax - 1;
2832 * Make sure a hotplug bridge has at least the minimum requested
2833 * number of buses but allow it to grow up to the maximum available
2834 * bus number of there is room.
2836 if (bus->self && bus->self->is_hotplug_bridge) {
2837 used_buses = max_t(unsigned int, available_buses,
2838 pci_hotplug_bus_size - 1);
2839 if (max - start < used_buses) {
2840 max = start + used_buses;
2842 /* Do not allocate more buses than we have room left */
2843 if (max > bus->busn_res.end)
2844 max = bus->busn_res.end;
2846 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2847 &bus->busn_res, max - start);
2852 * We've scanned the bus and so we know all about what's on
2853 * the other side of any bridges that may be on this bus plus
2856 * Return how far we've got finding sub-buses.
2858 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2863 * pci_scan_child_bus() - Scan devices below a bus
2864 * @bus: Bus to scan for devices
2866 * Scans devices below @bus including subordinate buses. Returns new
2867 * subordinate number including all the found devices.
2869 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2871 return pci_scan_child_bus_extend(bus, 0);
2873 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2876 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
2877 * @bridge: Host bridge to set up
2879 * Default empty implementation. Replace with an architecture-specific setup
2880 * routine, if necessary.
2882 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2887 void __weak pcibios_add_bus(struct pci_bus *bus)
2891 void __weak pcibios_remove_bus(struct pci_bus *bus)
2895 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2896 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2899 struct pci_host_bridge *bridge;
2901 bridge = pci_alloc_host_bridge(0);
2905 bridge->dev.parent = parent;
2907 list_splice_init(resources, &bridge->windows);
2908 bridge->sysdata = sysdata;
2909 bridge->busnr = bus;
2912 error = pci_register_host_bridge(bridge);
2922 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2924 int pci_host_probe(struct pci_host_bridge *bridge)
2926 struct pci_bus *bus, *child;
2929 ret = pci_scan_root_bus_bridge(bridge);
2931 dev_err(bridge->dev.parent, "Scanning root bridge failed");
2938 * We insert PCI resources into the iomem_resource and
2939 * ioport_resource trees in either pci_bus_claim_resources()
2940 * or pci_bus_assign_resources().
2942 if (pci_has_flag(PCI_PROBE_ONLY)) {
2943 pci_bus_claim_resources(bus);
2945 pci_bus_size_bridges(bus);
2946 pci_bus_assign_resources(bus);
2948 list_for_each_entry(child, &bus->children, node)
2949 pcie_bus_configure_settings(child);
2952 pci_bus_add_devices(bus);
2955 EXPORT_SYMBOL_GPL(pci_host_probe);
2957 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2959 struct resource *res = &b->busn_res;
2960 struct resource *parent_res, *conflict;
2964 res->flags = IORESOURCE_BUS;
2966 if (!pci_is_root_bus(b))
2967 parent_res = &b->parent->busn_res;
2969 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2970 res->flags |= IORESOURCE_PCI_FIXED;
2973 conflict = request_resource_conflict(parent_res, res);
2977 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2978 res, pci_is_root_bus(b) ? "domain " : "",
2979 parent_res, conflict->name, conflict);
2981 return conflict == NULL;
2984 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2986 struct resource *res = &b->busn_res;
2987 struct resource old_res = *res;
2988 resource_size_t size;
2991 if (res->start > bus_max)
2994 size = bus_max - res->start + 1;
2995 ret = adjust_resource(res, res->start, size);
2996 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
2997 &old_res, ret ? "can not be" : "is", bus_max);
2999 if (!ret && !res->parent)
3000 pci_bus_insert_busn_res(b, res->start, res->end);
3005 void pci_bus_release_busn_res(struct pci_bus *b)
3007 struct resource *res = &b->busn_res;
3010 if (!res->flags || !res->parent)
3013 ret = release_resource(res);
3014 dev_info(&b->dev, "busn_res: %pR %s released\n",
3015 res, ret ? "can not be" : "is");
3018 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3020 struct resource_entry *window;
3028 resource_list_for_each_entry(window, &bridge->windows)
3029 if (window->res->flags & IORESOURCE_BUS) {
3034 ret = pci_register_host_bridge(bridge);
3039 bus = bridge->busnr;
3043 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3045 pci_bus_insert_busn_res(b, bus, 255);
3048 max = pci_scan_child_bus(b);
3051 pci_bus_update_busn_res_end(b, max);
3055 EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3057 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3058 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3060 struct resource_entry *window;
3065 resource_list_for_each_entry(window, resources)
3066 if (window->res->flags & IORESOURCE_BUS) {
3071 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
3077 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3079 pci_bus_insert_busn_res(b, bus, 255);
3082 max = pci_scan_child_bus(b);
3085 pci_bus_update_busn_res_end(b, max);
3089 EXPORT_SYMBOL(pci_scan_root_bus);
3091 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
3094 LIST_HEAD(resources);
3097 pci_add_resource(&resources, &ioport_resource);
3098 pci_add_resource(&resources, &iomem_resource);
3099 pci_add_resource(&resources, &busn_resource);
3100 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3102 pci_scan_child_bus(b);
3104 pci_free_resource_list(&resources);
3108 EXPORT_SYMBOL(pci_scan_bus);
3111 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3112 * @bridge: PCI bridge for the bus to scan
3114 * Scan a PCI bus and child buses for new devices, add them,
3115 * and enable them, resizing bridge mmio/io resource if necessary
3116 * and possible. The caller must ensure the child devices are already
3117 * removed for resizing to occur.
3119 * Returns the max number of subordinate bus discovered.
3121 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
3124 struct pci_bus *bus = bridge->subordinate;
3126 max = pci_scan_child_bus(bus);
3128 pci_assign_unassigned_bridge_resources(bridge);
3130 pci_bus_add_devices(bus);
3136 * pci_rescan_bus - Scan a PCI bus for devices
3137 * @bus: PCI bus to scan
3139 * Scan a PCI bus and child buses for new devices, add them,
3142 * Returns the max number of subordinate bus discovered.
3144 unsigned int pci_rescan_bus(struct pci_bus *bus)
3148 max = pci_scan_child_bus(bus);
3149 pci_assign_unassigned_bus_resources(bus);
3150 pci_bus_add_devices(bus);
3154 EXPORT_SYMBOL_GPL(pci_rescan_bus);
3157 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3158 * routines should always be executed under this mutex.
3160 static DEFINE_MUTEX(pci_rescan_remove_lock);
3162 void pci_lock_rescan_remove(void)
3164 mutex_lock(&pci_rescan_remove_lock);
3166 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3168 void pci_unlock_rescan_remove(void)
3170 mutex_unlock(&pci_rescan_remove_lock);
3172 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3174 static int __init pci_sort_bf_cmp(const struct device *d_a,
3175 const struct device *d_b)
3177 const struct pci_dev *a = to_pci_dev(d_a);
3178 const struct pci_dev *b = to_pci_dev(d_b);
3180 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3181 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3183 if (a->bus->number < b->bus->number) return -1;
3184 else if (a->bus->number > b->bus->number) return 1;
3186 if (a->devfn < b->devfn) return -1;
3187 else if (a->devfn > b->devfn) return 1;
3192 void __init pci_sort_breadthfirst(void)
3194 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3197 int pci_hp_add_bridge(struct pci_dev *dev)
3199 struct pci_bus *parent = dev->bus;
3200 int busnr, start = parent->busn_res.start;
3201 unsigned int available_buses = 0;
3202 int end = parent->busn_res.end;
3204 for (busnr = start; busnr <= end; busnr++) {
3205 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3208 if (busnr-- > end) {
3209 pci_err(dev, "No bus number available for hot-added bridge\n");
3213 /* Scan bridges that are already configured */
3214 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3217 * Distribute the available bus numbers between hotplug-capable
3218 * bridges to make extending the chain later possible.
3220 available_buses = end - busnr;
3222 /* Scan bridges that need to be reconfigured */
3223 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3225 if (!dev->subordinate)
3230 EXPORT_SYMBOL_GPL(pci_hp_add_bridge);