1 // SPDX-License-Identifier: GPL-2.0
3 * PCI detection and setup code
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/init.h>
10 #include <linux/of_device.h>
11 #include <linux/of_pci.h>
12 #include <linux/pci_hotplug.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/cpumask.h>
16 #include <linux/pci-aspm.h>
17 #include <linux/aer.h>
18 #include <linux/acpi.h>
19 #include <linux/hypervisor.h>
20 #include <linux/irqdomain.h>
21 #include <linux/pm_runtime.h>
24 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
25 #define CARDBUS_RESERVE_BUSNR 3
27 static struct resource busn_resource = {
31 .flags = IORESOURCE_BUS,
34 /* Ugh. Need to stop exporting this to modules. */
35 LIST_HEAD(pci_root_buses);
36 EXPORT_SYMBOL(pci_root_buses);
38 static LIST_HEAD(pci_domain_busn_res_list);
40 struct pci_domain_busn_res {
41 struct list_head list;
46 static struct resource *get_pci_domain_busn_res(int domain_nr)
48 struct pci_domain_busn_res *r;
50 list_for_each_entry(r, &pci_domain_busn_res_list, list)
51 if (r->domain_nr == domain_nr)
54 r = kzalloc(sizeof(*r), GFP_KERNEL);
58 r->domain_nr = domain_nr;
61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
63 list_add_tail(&r->list, &pci_domain_busn_res_list);
68 static int find_anything(struct device *dev, void *data)
74 * Some device drivers need know if PCI is initiated.
75 * Basically, we think PCI is not initiated when there
76 * is no device to be found on the pci_bus_type.
78 int no_pci_devices(void)
83 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
84 no_devices = (dev == NULL);
88 EXPORT_SYMBOL(no_pci_devices);
93 static void release_pcibus_dev(struct device *dev)
95 struct pci_bus *pci_bus = to_pci_bus(dev);
97 put_device(pci_bus->bridge);
98 pci_bus_remove_resources(pci_bus);
99 pci_release_bus_of_node(pci_bus);
103 static struct class pcibus_class = {
105 .dev_release = &release_pcibus_dev,
106 .dev_groups = pcibus_groups,
109 static int __init pcibus_class_init(void)
111 return class_register(&pcibus_class);
113 postcore_initcall(pcibus_class_init);
115 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
117 u64 size = mask & maxbase; /* Find the significant bits */
122 * Get the lowest of them to find the decode size, and from that
125 size = (size & ~(size-1)) - 1;
128 * base == maxbase can be valid only if the BAR has already been
129 * programmed with all 1s.
131 if (base == maxbase && ((base | size) & mask) != mask)
137 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
142 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
143 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
144 flags |= IORESOURCE_IO;
148 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
149 flags |= IORESOURCE_MEM;
150 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
151 flags |= IORESOURCE_PREFETCH;
153 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
155 case PCI_BASE_ADDRESS_MEM_TYPE_32:
157 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
158 /* 1M mem BAR treated as 32-bit BAR */
160 case PCI_BASE_ADDRESS_MEM_TYPE_64:
161 flags |= IORESOURCE_MEM_64;
164 /* mem unknown type treated as 32-bit BAR */
170 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
173 * pci_read_base - Read a PCI BAR
174 * @dev: the PCI device
175 * @type: type of the BAR
176 * @res: resource buffer to be filled in
177 * @pos: BAR position in the config space
179 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
181 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
182 struct resource *res, unsigned int pos)
184 u32 l = 0, sz = 0, mask;
185 u64 l64, sz64, mask64;
187 struct pci_bus_region region, inverted_region;
189 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
191 /* No printks while decoding is disabled! */
192 if (!dev->mmio_always_on) {
193 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
194 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
195 pci_write_config_word(dev, PCI_COMMAND,
196 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
200 res->name = pci_name(dev);
202 pci_read_config_dword(dev, pos, &l);
203 pci_write_config_dword(dev, pos, l | mask);
204 pci_read_config_dword(dev, pos, &sz);
205 pci_write_config_dword(dev, pos, l);
208 * All bits set in sz means the device isn't working properly.
209 * If the BAR isn't implemented, all bits must be 0. If it's a
210 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
213 if (sz == 0xffffffff)
217 * I don't know how l can have all bits set. Copied from old code.
218 * Maybe it fixes a bug on some ancient platform.
223 if (type == pci_bar_unknown) {
224 res->flags = decode_bar(dev, l);
225 res->flags |= IORESOURCE_SIZEALIGN;
226 if (res->flags & IORESOURCE_IO) {
227 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
228 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
229 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
231 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
232 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
233 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
236 if (l & PCI_ROM_ADDRESS_ENABLE)
237 res->flags |= IORESOURCE_ROM_ENABLE;
238 l64 = l & PCI_ROM_ADDRESS_MASK;
239 sz64 = sz & PCI_ROM_ADDRESS_MASK;
240 mask64 = PCI_ROM_ADDRESS_MASK;
243 if (res->flags & IORESOURCE_MEM_64) {
244 pci_read_config_dword(dev, pos + 4, &l);
245 pci_write_config_dword(dev, pos + 4, ~0);
246 pci_read_config_dword(dev, pos + 4, &sz);
247 pci_write_config_dword(dev, pos + 4, l);
249 l64 |= ((u64)l << 32);
250 sz64 |= ((u64)sz << 32);
251 mask64 |= ((u64)~0 << 32);
254 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
255 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
260 sz64 = pci_size(l64, sz64, mask64);
262 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
267 if (res->flags & IORESOURCE_MEM_64) {
268 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
269 && sz64 > 0x100000000ULL) {
270 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
273 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
274 pos, (unsigned long long)sz64);
278 if ((sizeof(pci_bus_addr_t) < 8) && l) {
279 /* Above 32-bit boundary; try to reallocate */
280 res->flags |= IORESOURCE_UNSET;
283 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
284 pos, (unsigned long long)l64);
290 region.end = l64 + sz64;
292 pcibios_bus_to_resource(dev->bus, res, ®ion);
293 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
296 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
297 * the corresponding resource address (the physical address used by
298 * the CPU. Converting that resource address back to a bus address
299 * should yield the original BAR value:
301 * resource_to_bus(bus_to_resource(A)) == A
303 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
304 * be claimed by the device.
306 if (inverted_region.start != region.start) {
307 res->flags |= IORESOURCE_UNSET;
309 res->end = region.end - region.start;
310 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
311 pos, (unsigned long long)region.start);
321 pci_printk(KERN_DEBUG, dev, "reg 0x%x: %pR\n", pos, res);
323 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
326 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
328 unsigned int pos, reg;
330 if (dev->non_compliant_bars)
333 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
337 for (pos = 0; pos < howmany; pos++) {
338 struct resource *res = &dev->resource[pos];
339 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
340 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
344 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
345 dev->rom_base_reg = rom;
346 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
347 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
348 __pci_read_base(dev, pci_bar_mem32, res, rom);
352 static void pci_read_bridge_io(struct pci_bus *child)
354 struct pci_dev *dev = child->self;
355 u8 io_base_lo, io_limit_lo;
356 unsigned long io_mask, io_granularity, base, limit;
357 struct pci_bus_region region;
358 struct resource *res;
360 io_mask = PCI_IO_RANGE_MASK;
361 io_granularity = 0x1000;
362 if (dev->io_window_1k) {
363 /* Support 1K I/O space granularity */
364 io_mask = PCI_IO_1K_RANGE_MASK;
365 io_granularity = 0x400;
368 res = child->resource[0];
369 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
370 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
371 base = (io_base_lo & io_mask) << 8;
372 limit = (io_limit_lo & io_mask) << 8;
374 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
375 u16 io_base_hi, io_limit_hi;
377 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
378 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
379 base |= ((unsigned long) io_base_hi << 16);
380 limit |= ((unsigned long) io_limit_hi << 16);
384 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
386 region.end = limit + io_granularity - 1;
387 pcibios_bus_to_resource(dev->bus, res, ®ion);
388 pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res);
392 static void pci_read_bridge_mmio(struct pci_bus *child)
394 struct pci_dev *dev = child->self;
395 u16 mem_base_lo, mem_limit_lo;
396 unsigned long base, limit;
397 struct pci_bus_region region;
398 struct resource *res;
400 res = child->resource[1];
401 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
402 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
403 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
404 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
406 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
408 region.end = limit + 0xfffff;
409 pcibios_bus_to_resource(dev->bus, res, ®ion);
410 pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res);
414 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
416 struct pci_dev *dev = child->self;
417 u16 mem_base_lo, mem_limit_lo;
419 pci_bus_addr_t base, limit;
420 struct pci_bus_region region;
421 struct resource *res;
423 res = child->resource[2];
424 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
425 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
426 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
427 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
429 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
430 u32 mem_base_hi, mem_limit_hi;
432 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
433 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
436 * Some bridges set the base > limit by default, and some
437 * (broken) BIOSes do not initialize them. If we find
438 * this, just assume they are not being used.
440 if (mem_base_hi <= mem_limit_hi) {
441 base64 |= (u64) mem_base_hi << 32;
442 limit64 |= (u64) mem_limit_hi << 32;
446 base = (pci_bus_addr_t) base64;
447 limit = (pci_bus_addr_t) limit64;
449 if (base != base64) {
450 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
451 (unsigned long long) base64);
456 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
457 IORESOURCE_MEM | IORESOURCE_PREFETCH;
458 if (res->flags & PCI_PREF_RANGE_TYPE_64)
459 res->flags |= IORESOURCE_MEM_64;
461 region.end = limit + 0xfffff;
462 pcibios_bus_to_resource(dev->bus, res, ®ion);
463 pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res);
467 void pci_read_bridge_bases(struct pci_bus *child)
469 struct pci_dev *dev = child->self;
470 struct resource *res;
473 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
476 pci_info(dev, "PCI bridge to %pR%s\n",
478 dev->transparent ? " (subtractive decode)" : "");
480 pci_bus_remove_resources(child);
481 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
482 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
484 pci_read_bridge_io(child);
485 pci_read_bridge_mmio(child);
486 pci_read_bridge_mmio_pref(child);
488 if (dev->transparent) {
489 pci_bus_for_each_resource(child->parent, res, i) {
490 if (res && res->flags) {
491 pci_bus_add_resource(child, res,
492 PCI_SUBTRACTIVE_DECODE);
493 pci_printk(KERN_DEBUG, dev,
494 " bridge window %pR (subtractive decode)\n",
501 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
505 b = kzalloc(sizeof(*b), GFP_KERNEL);
509 INIT_LIST_HEAD(&b->node);
510 INIT_LIST_HEAD(&b->children);
511 INIT_LIST_HEAD(&b->devices);
512 INIT_LIST_HEAD(&b->slots);
513 INIT_LIST_HEAD(&b->resources);
514 b->max_bus_speed = PCI_SPEED_UNKNOWN;
515 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
516 #ifdef CONFIG_PCI_DOMAINS_GENERIC
518 b->domain_nr = parent->domain_nr;
523 static void devm_pci_release_host_bridge_dev(struct device *dev)
525 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
527 if (bridge->release_fn)
528 bridge->release_fn(bridge);
531 static void pci_release_host_bridge_dev(struct device *dev)
533 devm_pci_release_host_bridge_dev(dev);
534 pci_free_host_bridge(to_pci_host_bridge(dev));
537 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
539 struct pci_host_bridge *bridge;
541 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
545 INIT_LIST_HEAD(&bridge->windows);
546 bridge->dev.release = pci_release_host_bridge_dev;
549 * We assume we can manage these PCIe features. Some systems may
550 * reserve these for use by the platform itself, e.g., an ACPI BIOS
551 * may implement its own AER handling and use _OSC to prevent the
552 * OS from interfering.
554 bridge->native_aer = 1;
555 bridge->native_hotplug = 1;
556 bridge->native_pme = 1;
557 bridge->native_ltr = 1;
561 EXPORT_SYMBOL(pci_alloc_host_bridge);
563 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
566 struct pci_host_bridge *bridge;
568 bridge = devm_kzalloc(dev, sizeof(*bridge) + priv, GFP_KERNEL);
572 INIT_LIST_HEAD(&bridge->windows);
573 bridge->dev.release = devm_pci_release_host_bridge_dev;
577 EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
579 void pci_free_host_bridge(struct pci_host_bridge *bridge)
581 pci_free_resource_list(&bridge->windows);
585 EXPORT_SYMBOL(pci_free_host_bridge);
587 static const unsigned char pcix_bus_speed[] = {
588 PCI_SPEED_UNKNOWN, /* 0 */
589 PCI_SPEED_66MHz_PCIX, /* 1 */
590 PCI_SPEED_100MHz_PCIX, /* 2 */
591 PCI_SPEED_133MHz_PCIX, /* 3 */
592 PCI_SPEED_UNKNOWN, /* 4 */
593 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
594 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
595 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
596 PCI_SPEED_UNKNOWN, /* 8 */
597 PCI_SPEED_66MHz_PCIX_266, /* 9 */
598 PCI_SPEED_100MHz_PCIX_266, /* A */
599 PCI_SPEED_133MHz_PCIX_266, /* B */
600 PCI_SPEED_UNKNOWN, /* C */
601 PCI_SPEED_66MHz_PCIX_533, /* D */
602 PCI_SPEED_100MHz_PCIX_533, /* E */
603 PCI_SPEED_133MHz_PCIX_533 /* F */
606 const unsigned char pcie_link_speed[] = {
607 PCI_SPEED_UNKNOWN, /* 0 */
608 PCIE_SPEED_2_5GT, /* 1 */
609 PCIE_SPEED_5_0GT, /* 2 */
610 PCIE_SPEED_8_0GT, /* 3 */
611 PCIE_SPEED_16_0GT, /* 4 */
612 PCI_SPEED_UNKNOWN, /* 5 */
613 PCI_SPEED_UNKNOWN, /* 6 */
614 PCI_SPEED_UNKNOWN, /* 7 */
615 PCI_SPEED_UNKNOWN, /* 8 */
616 PCI_SPEED_UNKNOWN, /* 9 */
617 PCI_SPEED_UNKNOWN, /* A */
618 PCI_SPEED_UNKNOWN, /* B */
619 PCI_SPEED_UNKNOWN, /* C */
620 PCI_SPEED_UNKNOWN, /* D */
621 PCI_SPEED_UNKNOWN, /* E */
622 PCI_SPEED_UNKNOWN /* F */
625 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
627 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
629 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
631 static unsigned char agp_speeds[] = {
639 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
645 else if (agpstat & 2)
647 else if (agpstat & 1)
659 return agp_speeds[index];
662 static void pci_set_bus_speed(struct pci_bus *bus)
664 struct pci_dev *bridge = bus->self;
667 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
669 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
673 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
674 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
676 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
677 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
680 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
683 enum pci_bus_speed max;
685 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
688 if (status & PCI_X_SSTATUS_533MHZ) {
689 max = PCI_SPEED_133MHz_PCIX_533;
690 } else if (status & PCI_X_SSTATUS_266MHZ) {
691 max = PCI_SPEED_133MHz_PCIX_266;
692 } else if (status & PCI_X_SSTATUS_133MHZ) {
693 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
694 max = PCI_SPEED_133MHz_PCIX_ECC;
696 max = PCI_SPEED_133MHz_PCIX;
698 max = PCI_SPEED_66MHz_PCIX;
701 bus->max_bus_speed = max;
702 bus->cur_bus_speed = pcix_bus_speed[
703 (status & PCI_X_SSTATUS_FREQ) >> 6];
708 if (pci_is_pcie(bridge)) {
712 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
713 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
715 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
716 pcie_update_link_speed(bus, linksta);
720 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
722 struct irq_domain *d;
725 * Any firmware interface that can resolve the msi_domain
726 * should be called from here.
728 d = pci_host_bridge_of_msi_domain(bus);
730 d = pci_host_bridge_acpi_msi_domain(bus);
732 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
734 * If no IRQ domain was found via the OF tree, try looking it up
735 * directly through the fwnode_handle.
738 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
741 d = irq_find_matching_fwnode(fwnode,
749 static void pci_set_bus_msi_domain(struct pci_bus *bus)
751 struct irq_domain *d;
755 * The bus can be a root bus, a subordinate bus, or a virtual bus
756 * created by an SR-IOV device. Walk up to the first bridge device
757 * found or derive the domain from the host bridge.
759 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
761 d = dev_get_msi_domain(&b->self->dev);
765 d = pci_host_bridge_msi_domain(b);
767 dev_set_msi_domain(&bus->dev, d);
770 static int pci_register_host_bridge(struct pci_host_bridge *bridge)
772 struct device *parent = bridge->dev.parent;
773 struct resource_entry *window, *n;
774 struct pci_bus *bus, *b;
775 resource_size_t offset;
776 LIST_HEAD(resources);
777 struct resource *res;
782 bus = pci_alloc_bus(NULL);
788 /* Temporarily move resources off the list */
789 list_splice_init(&bridge->windows, &resources);
790 bus->sysdata = bridge->sysdata;
791 bus->msi = bridge->msi;
792 bus->ops = bridge->ops;
793 bus->number = bus->busn_res.start = bridge->busnr;
794 #ifdef CONFIG_PCI_DOMAINS_GENERIC
795 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
798 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
800 /* Ignore it if we already got here via a different bridge */
801 dev_dbg(&b->dev, "bus already known\n");
806 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
809 err = pcibios_root_bridge_prepare(bridge);
813 err = device_register(&bridge->dev);
815 put_device(&bridge->dev);
817 bus->bridge = get_device(&bridge->dev);
818 device_enable_async_suspend(bus->bridge);
819 pci_set_bus_of_node(bus);
820 pci_set_bus_msi_domain(bus);
823 set_dev_node(bus->bridge, pcibus_to_node(bus));
825 bus->dev.class = &pcibus_class;
826 bus->dev.parent = bus->bridge;
828 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
829 name = dev_name(&bus->dev);
831 err = device_register(&bus->dev);
835 pcibios_add_bus(bus);
837 /* Create legacy_io and legacy_mem files for this bus */
838 pci_create_legacy_files(bus);
841 dev_info(parent, "PCI host bridge to bus %s\n", name);
843 pr_info("PCI host bridge to bus %s\n", name);
845 /* Add initial resources to the bus */
846 resource_list_for_each_entry_safe(window, n, &resources) {
847 list_move_tail(&window->node, &bridge->windows);
848 offset = window->offset;
851 if (res->flags & IORESOURCE_BUS)
852 pci_bus_insert_busn_res(bus, bus->number, res->end);
854 pci_bus_add_resource(bus, res, 0);
857 if (resource_type(res) == IORESOURCE_IO)
858 fmt = " (bus address [%#06llx-%#06llx])";
860 fmt = " (bus address [%#010llx-%#010llx])";
862 snprintf(addr, sizeof(addr), fmt,
863 (unsigned long long)(res->start - offset),
864 (unsigned long long)(res->end - offset));
868 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
871 down_write(&pci_bus_sem);
872 list_add_tail(&bus->node, &pci_root_buses);
873 up_write(&pci_bus_sem);
878 put_device(&bridge->dev);
879 device_unregister(&bridge->dev);
886 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
887 struct pci_dev *bridge, int busnr)
889 struct pci_bus *child;
893 /* Allocate a new bus and inherit stuff from the parent */
894 child = pci_alloc_bus(parent);
898 child->parent = parent;
899 child->ops = parent->ops;
900 child->msi = parent->msi;
901 child->sysdata = parent->sysdata;
902 child->bus_flags = parent->bus_flags;
905 * Initialize some portions of the bus device, but don't register
906 * it now as the parent is not properly set up yet.
908 child->dev.class = &pcibus_class;
909 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
911 /* Set up the primary, secondary and subordinate bus numbers */
912 child->number = child->busn_res.start = busnr;
913 child->primary = parent->busn_res.start;
914 child->busn_res.end = 0xff;
917 child->dev.parent = parent->bridge;
921 child->self = bridge;
922 child->bridge = get_device(&bridge->dev);
923 child->dev.parent = child->bridge;
924 pci_set_bus_of_node(child);
925 pci_set_bus_speed(child);
927 /* Set up default resource pointers and names */
928 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
929 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
930 child->resource[i]->name = child->name;
932 bridge->subordinate = child;
935 pci_set_bus_msi_domain(child);
936 ret = device_register(&child->dev);
939 pcibios_add_bus(child);
941 if (child->ops->add_bus) {
942 ret = child->ops->add_bus(child);
943 if (WARN_ON(ret < 0))
944 dev_err(&child->dev, "failed to add bus: %d\n", ret);
947 /* Create legacy_io and legacy_mem files for this bus */
948 pci_create_legacy_files(child);
953 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
956 struct pci_bus *child;
958 child = pci_alloc_child_bus(parent, dev, busnr);
960 down_write(&pci_bus_sem);
961 list_add_tail(&child->node, &parent->children);
962 up_write(&pci_bus_sem);
966 EXPORT_SYMBOL(pci_add_new_bus);
968 static void pci_enable_crs(struct pci_dev *pdev)
972 /* Enable CRS Software Visibility if supported */
973 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
974 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
975 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
976 PCI_EXP_RTCTL_CRSSVE);
979 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
980 unsigned int available_buses);
983 * pci_scan_bridge_extend() - Scan buses behind a bridge
984 * @bus: Parent bus the bridge is on
985 * @dev: Bridge itself
986 * @max: Starting subordinate number of buses behind this bridge
987 * @available_buses: Total number of buses available for this bridge and
988 * the devices below. After the minimal bus space has
989 * been allocated the remaining buses will be
990 * distributed equally between hotplug-capable bridges.
991 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
992 * that need to be reconfigured.
994 * If it's a bridge, configure it and scan the bus behind it.
995 * For CardBus bridges, we don't scan behind as the devices will
996 * be handled by the bridge driver itself.
998 * We need to process bridges in two passes -- first we scan those
999 * already configured by the BIOS and after we are done with all of
1000 * them, we proceed to assigning numbers to the remaining buses in
1001 * order to avoid overlaps between old and new bus numbers.
1003 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1004 int max, unsigned int available_buses,
1007 struct pci_bus *child;
1008 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1009 u32 buses, i, j = 0;
1011 u8 primary, secondary, subordinate;
1015 * Make sure the bridge is powered on to be able to access config
1016 * space of devices below it.
1018 pm_runtime_get_sync(&dev->dev);
1020 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1021 primary = buses & 0xFF;
1022 secondary = (buses >> 8) & 0xFF;
1023 subordinate = (buses >> 16) & 0xFF;
1025 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1026 secondary, subordinate, pass);
1028 if (!primary && (primary != bus->number) && secondary && subordinate) {
1029 pci_warn(dev, "Primary bus is hard wired to 0\n");
1030 primary = bus->number;
1033 /* Check if setup is sensible at all */
1035 (primary != bus->number || secondary <= bus->number ||
1036 secondary > subordinate)) {
1037 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1038 secondary, subordinate);
1043 * Disable Master-Abort Mode during probing to avoid reporting of
1044 * bus errors in some architectures.
1046 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1047 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1048 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1050 pci_enable_crs(dev);
1052 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1053 !is_cardbus && !broken) {
1057 * Bus already configured by firmware, process it in the
1058 * first pass and just note the configuration.
1064 * The bus might already exist for two reasons: Either we
1065 * are rescanning the bus or the bus is reachable through
1066 * more than one bridge. The second case can happen with
1067 * the i450NX chipset.
1069 child = pci_find_bus(pci_domain_nr(bus), secondary);
1071 child = pci_add_new_bus(bus, dev, secondary);
1074 child->primary = primary;
1075 pci_bus_insert_busn_res(child, secondary, subordinate);
1076 child->bridge_ctl = bctl;
1079 cmax = pci_scan_child_bus(child);
1080 if (cmax > subordinate)
1081 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1084 /* Subordinate should equal child->busn_res.end */
1085 if (subordinate > max)
1090 * We need to assign a number to this bus which we always
1091 * do in the second pass.
1094 if (pcibios_assign_all_busses() || broken || is_cardbus)
1097 * Temporarily disable forwarding of the
1098 * configuration cycles on all bridges in
1099 * this bus segment to avoid possible
1100 * conflicts in the second pass between two
1101 * bridges programmed with overlapping bus
1104 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1110 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1113 * Prevent assigning a bus number that already exists.
1114 * This can happen when a bridge is hot-plugged, so in this
1115 * case we only re-scan this bus.
1117 child = pci_find_bus(pci_domain_nr(bus), max+1);
1119 child = pci_add_new_bus(bus, dev, max+1);
1122 pci_bus_insert_busn_res(child, max+1,
1126 if (available_buses)
1129 buses = (buses & 0xff000000)
1130 | ((unsigned int)(child->primary) << 0)
1131 | ((unsigned int)(child->busn_res.start) << 8)
1132 | ((unsigned int)(child->busn_res.end) << 16);
1135 * yenta.c forces a secondary latency timer of 176.
1136 * Copy that behaviour here.
1139 buses &= ~0xff000000;
1140 buses |= CARDBUS_LATENCY_TIMER << 24;
1143 /* We need to blast all three values with a single write */
1144 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1147 child->bridge_ctl = bctl;
1148 max = pci_scan_child_bus_extend(child, available_buses);
1152 * For CardBus bridges, we leave 4 bus numbers as
1153 * cards with a PCI-to-PCI bridge can be inserted
1156 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1157 struct pci_bus *parent = bus;
1158 if (pci_find_bus(pci_domain_nr(bus),
1161 while (parent->parent) {
1162 if ((!pcibios_assign_all_busses()) &&
1163 (parent->busn_res.end > max) &&
1164 (parent->busn_res.end <= max+i)) {
1167 parent = parent->parent;
1172 * Often, there are two CardBus
1173 * bridges -- try to leave one
1174 * valid bus number for each one.
1183 /* Set subordinate bus number to its real value */
1184 pci_bus_update_busn_res_end(child, max);
1185 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1188 sprintf(child->name,
1189 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1190 pci_domain_nr(bus), child->number);
1192 /* Has only triggered on CardBus, fixup is in yenta_socket */
1193 while (bus->parent) {
1194 if ((child->busn_res.end > bus->busn_res.end) ||
1195 (child->number > bus->busn_res.end) ||
1196 (child->number < bus->number) ||
1197 (child->busn_res.end < bus->number)) {
1198 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
1200 (bus->number > child->busn_res.end &&
1201 bus->busn_res.end < child->number) ?
1202 "wholly" : "partially",
1203 bus->self->transparent ? " transparent" : "",
1204 dev_name(&bus->dev),
1211 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1213 pm_runtime_put(&dev->dev);
1219 * pci_scan_bridge() - Scan buses behind a bridge
1220 * @bus: Parent bus the bridge is on
1221 * @dev: Bridge itself
1222 * @max: Starting subordinate number of buses behind this bridge
1223 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1224 * that need to be reconfigured.
1226 * If it's a bridge, configure it and scan the bus behind it.
1227 * For CardBus bridges, we don't scan behind as the devices will
1228 * be handled by the bridge driver itself.
1230 * We need to process bridges in two passes -- first we scan those
1231 * already configured by the BIOS and after we are done with all of
1232 * them, we proceed to assigning numbers to the remaining buses in
1233 * order to avoid overlaps between old and new bus numbers.
1235 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1237 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1239 EXPORT_SYMBOL(pci_scan_bridge);
1242 * Read interrupt line and base address registers.
1243 * The architecture-dependent code can tweak these, of course.
1245 static void pci_read_irq(struct pci_dev *dev)
1249 /* VFs are not allowed to use INTx, so skip the config reads */
1250 if (dev->is_virtfn) {
1256 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1259 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1263 void set_pcie_port_type(struct pci_dev *pdev)
1268 struct pci_dev *parent;
1270 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1274 pdev->pcie_cap = pos;
1275 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1276 pdev->pcie_flags_reg = reg16;
1277 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1278 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1281 * A Root Port or a PCI-to-PCIe bridge is always the upstream end
1282 * of a Link. No PCIe component has two Links. Two Links are
1283 * connected by a Switch that has a Port on each Link and internal
1284 * logic to connect the two Ports.
1286 type = pci_pcie_type(pdev);
1287 if (type == PCI_EXP_TYPE_ROOT_PORT ||
1288 type == PCI_EXP_TYPE_PCIE_BRIDGE)
1289 pdev->has_secondary_link = 1;
1290 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1291 type == PCI_EXP_TYPE_DOWNSTREAM) {
1292 parent = pci_upstream_bridge(pdev);
1295 * Usually there's an upstream device (Root Port or Switch
1296 * Downstream Port), but we can't assume one exists.
1298 if (parent && !parent->has_secondary_link)
1299 pdev->has_secondary_link = 1;
1303 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1307 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1308 if (reg32 & PCI_EXP_SLTCAP_HPC)
1309 pdev->is_hotplug_bridge = 1;
1312 static void set_pcie_thunderbolt(struct pci_dev *dev)
1317 while ((vsec = pci_find_next_ext_capability(dev, vsec,
1318 PCI_EXT_CAP_ID_VNDR))) {
1319 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
1321 /* Is the device part of a Thunderbolt controller? */
1322 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
1323 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
1324 dev->is_thunderbolt = 1;
1331 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1334 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1335 * when forwarding a type1 configuration request the bridge must check that
1336 * the extended register address field is zero. The bridge is not permitted
1337 * to forward the transactions and must handle it as an Unsupported Request.
1338 * Some bridges do not follow this rule and simply drop the extended register
1339 * bits, resulting in the standard config space being aliased, every 256
1340 * bytes across the entire configuration space. Test for this condition by
1341 * comparing the first dword of each potential alias to the vendor/device ID.
1343 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1344 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1346 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1348 #ifdef CONFIG_PCI_QUIRKS
1352 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1354 for (pos = PCI_CFG_SPACE_SIZE;
1355 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1356 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1368 * pci_cfg_space_size - Get the configuration space size of the PCI device
1371 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1372 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1373 * access it. Maybe we don't have a way to generate extended config space
1374 * accesses, or the device is behind a reverse Express bridge. So we try
1375 * reading the dword at 0x100 which must either be 0 or a valid extended
1376 * capability header.
1378 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1381 int pos = PCI_CFG_SPACE_SIZE;
1383 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1384 return PCI_CFG_SPACE_SIZE;
1385 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1386 return PCI_CFG_SPACE_SIZE;
1388 return PCI_CFG_SPACE_EXP_SIZE;
1391 int pci_cfg_space_size(struct pci_dev *dev)
1397 class = dev->class >> 8;
1398 if (class == PCI_CLASS_BRIDGE_HOST)
1399 return pci_cfg_space_size_ext(dev);
1401 if (pci_is_pcie(dev))
1402 return pci_cfg_space_size_ext(dev);
1404 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1406 return PCI_CFG_SPACE_SIZE;
1408 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1409 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1410 return pci_cfg_space_size_ext(dev);
1412 return PCI_CFG_SPACE_SIZE;
1415 static u32 pci_class(struct pci_dev *dev)
1419 #ifdef CONFIG_PCI_IOV
1421 return dev->physfn->sriov->class;
1423 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1427 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1429 #ifdef CONFIG_PCI_IOV
1430 if (dev->is_virtfn) {
1431 *vendor = dev->physfn->sriov->subsystem_vendor;
1432 *device = dev->physfn->sriov->subsystem_device;
1436 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1437 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1440 static u8 pci_hdr_type(struct pci_dev *dev)
1444 #ifdef CONFIG_PCI_IOV
1446 return dev->physfn->sriov->hdr_type;
1448 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1452 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1454 static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1457 * Disable the MSI hardware to avoid screaming interrupts
1458 * during boot. This is the power on reset default so
1459 * usually this should be a noop.
1461 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1463 pci_msi_set_enable(dev, 0);
1465 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1467 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1471 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1474 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1475 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1477 static int pci_intx_mask_broken(struct pci_dev *dev)
1479 u16 orig, toggle, new;
1481 pci_read_config_word(dev, PCI_COMMAND, &orig);
1482 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1483 pci_write_config_word(dev, PCI_COMMAND, toggle);
1484 pci_read_config_word(dev, PCI_COMMAND, &new);
1486 pci_write_config_word(dev, PCI_COMMAND, orig);
1489 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1490 * r2.3, so strictly speaking, a device is not *broken* if it's not
1491 * writable. But we'll live with the misnomer for now.
1499 * pci_setup_device - Fill in class and map information of a device
1500 * @dev: the device structure to fill
1502 * Initialize the device structure with information about the device's
1503 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1504 * Called at initialisation of the PCI subsystem and by CardBus services.
1505 * Returns 0 on success and negative if unknown type of device (not normal,
1506 * bridge or CardBus).
1508 int pci_setup_device(struct pci_dev *dev)
1514 struct pci_bus_region region;
1515 struct resource *res;
1517 hdr_type = pci_hdr_type(dev);
1519 dev->sysdata = dev->bus->sysdata;
1520 dev->dev.parent = dev->bus->bridge;
1521 dev->dev.bus = &pci_bus_type;
1522 dev->hdr_type = hdr_type & 0x7f;
1523 dev->multifunction = !!(hdr_type & 0x80);
1524 dev->error_state = pci_channel_io_normal;
1525 set_pcie_port_type(dev);
1527 pci_dev_assign_slot(dev);
1530 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1531 * set this higher, assuming the system even supports it.
1533 dev->dma_mask = 0xffffffff;
1535 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1536 dev->bus->number, PCI_SLOT(dev->devfn),
1537 PCI_FUNC(dev->devfn));
1539 class = pci_class(dev);
1541 dev->revision = class & 0xff;
1542 dev->class = class >> 8; /* upper 3 bytes */
1544 pci_printk(KERN_DEBUG, dev, "[%04x:%04x] type %02x class %#08x\n",
1545 dev->vendor, dev->device, dev->hdr_type, dev->class);
1547 /* Need to have dev->class ready */
1548 dev->cfg_size = pci_cfg_space_size(dev);
1550 /* Need to have dev->cfg_size ready */
1551 set_pcie_thunderbolt(dev);
1553 /* "Unknown power state" */
1554 dev->current_state = PCI_UNKNOWN;
1556 /* Early fixups, before probing the BARs */
1557 pci_fixup_device(pci_fixup_early, dev);
1559 /* Device class may be changed after fixup */
1560 class = dev->class >> 8;
1562 if (dev->non_compliant_bars) {
1563 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1564 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1565 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1566 cmd &= ~PCI_COMMAND_IO;
1567 cmd &= ~PCI_COMMAND_MEMORY;
1568 pci_write_config_word(dev, PCI_COMMAND, cmd);
1572 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1574 switch (dev->hdr_type) { /* header type */
1575 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1576 if (class == PCI_CLASS_BRIDGE_PCI)
1579 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1581 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1584 * Do the ugly legacy mode stuff here rather than broken chip
1585 * quirk code. Legacy mode ATA controllers have fixed
1586 * addresses. These are not always echoed in BAR0-3, and
1587 * BAR0-3 in a few cases contain junk!
1589 if (class == PCI_CLASS_STORAGE_IDE) {
1591 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1592 if ((progif & 1) == 0) {
1593 region.start = 0x1F0;
1595 res = &dev->resource[0];
1596 res->flags = LEGACY_IO_RESOURCE;
1597 pcibios_bus_to_resource(dev->bus, res, ®ion);
1598 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1600 region.start = 0x3F6;
1602 res = &dev->resource[1];
1603 res->flags = LEGACY_IO_RESOURCE;
1604 pcibios_bus_to_resource(dev->bus, res, ®ion);
1605 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1608 if ((progif & 4) == 0) {
1609 region.start = 0x170;
1611 res = &dev->resource[2];
1612 res->flags = LEGACY_IO_RESOURCE;
1613 pcibios_bus_to_resource(dev->bus, res, ®ion);
1614 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1616 region.start = 0x376;
1618 res = &dev->resource[3];
1619 res->flags = LEGACY_IO_RESOURCE;
1620 pcibios_bus_to_resource(dev->bus, res, ®ion);
1621 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1627 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1628 if (class != PCI_CLASS_BRIDGE_PCI)
1632 * The PCI-to-PCI bridge spec requires that subtractive
1633 * decoding (i.e. transparent) bridge must have programming
1634 * interface code of 0x01.
1637 dev->transparent = ((dev->class & 0xff) == 1);
1638 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1639 set_pcie_hotplug_bridge(dev);
1640 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1642 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1643 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1647 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1648 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1651 pci_read_bases(dev, 1, 0);
1652 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1653 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1656 default: /* unknown header */
1657 pci_err(dev, "unknown header type %02x, ignoring device\n",
1662 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1663 dev->class, dev->hdr_type);
1664 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1667 /* We found a fine healthy device, go go go... */
1671 static void pci_configure_mps(struct pci_dev *dev)
1673 struct pci_dev *bridge = pci_upstream_bridge(dev);
1676 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1679 mps = pcie_get_mps(dev);
1680 p_mps = pcie_get_mps(bridge);
1685 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1686 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1687 mps, pci_name(bridge), p_mps);
1692 * Fancier MPS configuration is done later by
1693 * pcie_bus_configure_settings()
1695 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1698 rc = pcie_set_mps(dev, p_mps);
1700 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1705 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
1706 p_mps, mps, 128 << dev->pcie_mpss);
1709 static struct hpp_type0 pci_default_type0 = {
1711 .cache_line_size = 8,
1712 .latency_timer = 0x40,
1717 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1719 u16 pci_cmd, pci_bctl;
1722 hpp = &pci_default_type0;
1724 if (hpp->revision > 1) {
1725 pci_warn(dev, "PCI settings rev %d not supported; using defaults\n",
1727 hpp = &pci_default_type0;
1730 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1731 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1732 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1733 if (hpp->enable_serr)
1734 pci_cmd |= PCI_COMMAND_SERR;
1735 if (hpp->enable_perr)
1736 pci_cmd |= PCI_COMMAND_PARITY;
1737 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1739 /* Program bridge control value */
1740 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1741 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1742 hpp->latency_timer);
1743 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1744 if (hpp->enable_serr)
1745 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1746 if (hpp->enable_perr)
1747 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1748 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1752 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1759 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1763 pci_warn(dev, "PCI-X settings not supported\n");
1766 static bool pcie_root_rcb_set(struct pci_dev *dev)
1768 struct pci_dev *rp = pcie_find_root_port(dev);
1774 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1775 if (lnkctl & PCI_EXP_LNKCTL_RCB)
1781 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1789 if (!pci_is_pcie(dev))
1792 if (hpp->revision > 1) {
1793 pci_warn(dev, "PCIe settings rev %d not supported\n",
1799 * Don't allow _HPX to change MPS or MRRS settings. We manage
1800 * those to make sure they're consistent with the rest of the
1803 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1804 PCI_EXP_DEVCTL_READRQ;
1805 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1806 PCI_EXP_DEVCTL_READRQ);
1808 /* Initialize Device Control Register */
1809 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1810 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1812 /* Initialize Link Control Register */
1813 if (pcie_cap_has_lnkctl(dev)) {
1816 * If the Root Port supports Read Completion Boundary of
1817 * 128, set RCB to 128. Otherwise, clear it.
1819 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
1820 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
1821 if (pcie_root_rcb_set(dev))
1822 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
1824 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1825 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1828 /* Find Advanced Error Reporting Enhanced Capability */
1829 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1833 /* Initialize Uncorrectable Error Mask Register */
1834 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1835 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1836 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1838 /* Initialize Uncorrectable Error Severity Register */
1839 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1840 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1841 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1843 /* Initialize Correctable Error Mask Register */
1844 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1845 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1846 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1848 /* Initialize Advanced Error Capabilities and Control Register */
1849 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1850 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1852 /* Don't enable ECRC generation or checking if unsupported */
1853 if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
1854 reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
1855 if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC))
1856 reg32 &= ~PCI_ERR_CAP_ECRC_CHKE;
1857 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1860 * FIXME: The following two registers are not supported yet.
1862 * o Secondary Uncorrectable Error Severity Register
1863 * o Secondary Uncorrectable Error Mask Register
1867 int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
1869 struct pci_host_bridge *host;
1874 if (!pci_is_pcie(dev))
1877 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
1881 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
1884 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
1888 host = pci_find_host_bridge(dev->bus);
1893 * If some device in the hierarchy doesn't handle Extended Tags
1894 * correctly, make sure they're disabled.
1896 if (host->no_ext_tags) {
1897 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
1898 pci_info(dev, "disabling Extended Tags\n");
1899 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
1900 PCI_EXP_DEVCTL_EXT_TAG);
1905 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
1906 pci_info(dev, "enabling Extended Tags\n");
1907 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
1908 PCI_EXP_DEVCTL_EXT_TAG);
1914 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
1915 * @dev: PCI device to query
1917 * Returns true if the device has enabled relaxed ordering attribute.
1919 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
1923 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
1925 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
1927 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
1929 static void pci_configure_relaxed_ordering(struct pci_dev *dev)
1931 struct pci_dev *root;
1933 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
1937 if (!pcie_relaxed_ordering_enabled(dev))
1941 * For now, we only deal with Relaxed Ordering issues with Root
1942 * Ports. Peer-to-Peer DMA is another can of worms.
1944 root = pci_find_pcie_root_port(dev);
1948 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
1949 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
1950 PCI_EXP_DEVCTL_RELAX_EN);
1951 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
1955 static void pci_configure_ltr(struct pci_dev *dev)
1957 #ifdef CONFIG_PCIEASPM
1958 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
1960 struct pci_dev *bridge;
1962 if (!host->native_ltr)
1965 if (!pci_is_pcie(dev))
1968 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
1969 if (!(cap & PCI_EXP_DEVCAP2_LTR))
1973 * Software must not enable LTR in an Endpoint unless the Root
1974 * Complex and all intermediate Switches indicate support for LTR.
1975 * PCIe r3.1, sec 6.18.
1977 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
1980 bridge = pci_upstream_bridge(dev);
1981 if (bridge && bridge->ltr_path)
1986 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
1987 PCI_EXP_DEVCTL2_LTR_EN);
1991 static void pci_configure_device(struct pci_dev *dev)
1993 struct hotplug_params hpp;
1996 pci_configure_mps(dev);
1997 pci_configure_extended_tags(dev, NULL);
1998 pci_configure_relaxed_ordering(dev);
1999 pci_configure_ltr(dev);
2001 memset(&hpp, 0, sizeof(hpp));
2002 ret = pci_get_hp_params(dev, &hpp);
2006 program_hpp_type2(dev, hpp.t2);
2007 program_hpp_type1(dev, hpp.t1);
2008 program_hpp_type0(dev, hpp.t0);
2011 static void pci_release_capabilities(struct pci_dev *dev)
2013 pci_vpd_release(dev);
2014 pci_iov_release(dev);
2015 pci_free_cap_save_buffers(dev);
2019 * pci_release_dev - Free a PCI device structure when all users of it are
2021 * @dev: device that's been disconnected
2023 * Will be called only by the device core when all users of this PCI device are
2026 static void pci_release_dev(struct device *dev)
2028 struct pci_dev *pci_dev;
2030 pci_dev = to_pci_dev(dev);
2031 pci_release_capabilities(pci_dev);
2032 pci_release_of_node(pci_dev);
2033 pcibios_release_device(pci_dev);
2034 pci_bus_put(pci_dev->bus);
2035 kfree(pci_dev->driver_override);
2036 kfree(pci_dev->dma_alias_mask);
2040 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2042 struct pci_dev *dev;
2044 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2048 INIT_LIST_HEAD(&dev->bus_list);
2049 dev->dev.type = &pci_dev_type;
2050 dev->bus = pci_bus_get(bus);
2054 EXPORT_SYMBOL(pci_alloc_dev);
2056 static bool pci_bus_crs_vendor_id(u32 l)
2058 return (l & 0xffff) == 0x0001;
2061 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2066 if (!pci_bus_crs_vendor_id(*l))
2067 return true; /* not a CRS completion */
2070 return false; /* CRS, but caller doesn't want to wait */
2073 * We got the reserved Vendor ID that indicates a completion with
2074 * Configuration Request Retry Status (CRS). Retry until we get a
2075 * valid Vendor ID or we time out.
2077 while (pci_bus_crs_vendor_id(*l)) {
2078 if (delay > timeout) {
2079 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2080 pci_domain_nr(bus), bus->number,
2081 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2086 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2087 pci_domain_nr(bus), bus->number,
2088 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2093 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2098 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2099 pci_domain_nr(bus), bus->number,
2100 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2105 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2108 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2111 /* Some broken boards return 0 or ~0 if a slot is empty: */
2112 if (*l == 0xffffffff || *l == 0x00000000 ||
2113 *l == 0x0000ffff || *l == 0xffff0000)
2116 if (pci_bus_crs_vendor_id(*l))
2117 return pci_bus_wait_crs(bus, devfn, l, timeout);
2121 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2124 * Read the config data for a PCI device, sanity-check it,
2125 * and fill in the dev structure.
2127 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2129 struct pci_dev *dev;
2132 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2135 dev = pci_alloc_dev(bus);
2140 dev->vendor = l & 0xffff;
2141 dev->device = (l >> 16) & 0xffff;
2143 pci_set_of_node(dev);
2145 if (pci_setup_device(dev)) {
2146 pci_bus_put(dev->bus);
2154 static void pci_init_capabilities(struct pci_dev *dev)
2156 /* Enhanced Allocation */
2159 /* Setup MSI caps & disable MSI/MSI-X interrupts */
2160 pci_msi_setup_pci_dev(dev);
2162 /* Buffers for saving PCIe and PCI-X capabilities */
2163 pci_allocate_cap_save_buffers(dev);
2165 /* Power Management */
2168 /* Vital Product Data */
2171 /* Alternative Routing-ID Forwarding */
2172 pci_configure_ari(dev);
2174 /* Single Root I/O Virtualization */
2177 /* Address Translation Services */
2180 /* Enable ACS P2P upstream forwarding */
2181 pci_enable_acs(dev);
2183 /* Precision Time Measurement */
2186 /* Advanced Error Reporting */
2189 if (pci_probe_reset_function(dev) == 0)
2194 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2195 * devices. Firmware interfaces that can select the MSI domain on a
2196 * per-device basis should be called from here.
2198 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2200 struct irq_domain *d;
2203 * If a domain has been set through the pcibios_add_device()
2204 * callback, then this is the one (platform code knows best).
2206 d = dev_get_msi_domain(&dev->dev);
2211 * Let's see if we have a firmware interface able to provide
2214 d = pci_msi_get_device_domain(dev);
2221 static void pci_set_msi_domain(struct pci_dev *dev)
2223 struct irq_domain *d;
2226 * If the platform or firmware interfaces cannot supply a
2227 * device-specific MSI domain, then inherit the default domain
2228 * from the host bridge itself.
2230 d = pci_dev_msi_domain(dev);
2232 d = dev_get_msi_domain(&dev->bus->dev);
2234 dev_set_msi_domain(&dev->dev, d);
2237 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2241 pci_configure_device(dev);
2243 device_initialize(&dev->dev);
2244 dev->dev.release = pci_release_dev;
2246 set_dev_node(&dev->dev, pcibus_to_node(bus));
2247 dev->dev.dma_mask = &dev->dma_mask;
2248 dev->dev.dma_parms = &dev->dma_parms;
2249 dev->dev.coherent_dma_mask = 0xffffffffull;
2251 pci_set_dma_max_seg_size(dev, 65536);
2252 pci_set_dma_seg_boundary(dev, 0xffffffff);
2254 /* Fix up broken headers */
2255 pci_fixup_device(pci_fixup_header, dev);
2257 /* Moved out from quirk header fixup code */
2258 pci_reassigndev_resource_alignment(dev);
2260 /* Clear the state_saved flag */
2261 dev->state_saved = false;
2263 /* Initialize various capabilities */
2264 pci_init_capabilities(dev);
2267 * Add the device to our list of discovered devices
2268 * and the bus list for fixup functions, etc.
2270 down_write(&pci_bus_sem);
2271 list_add_tail(&dev->bus_list, &bus->devices);
2272 up_write(&pci_bus_sem);
2274 ret = pcibios_add_device(dev);
2277 /* Set up MSI IRQ domain */
2278 pci_set_msi_domain(dev);
2280 /* Notifier could use PCI capabilities */
2281 dev->match_driver = false;
2282 ret = device_add(&dev->dev);
2286 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2288 struct pci_dev *dev;
2290 dev = pci_get_slot(bus, devfn);
2296 dev = pci_scan_device(bus, devfn);
2300 pci_device_add(dev, bus);
2304 EXPORT_SYMBOL(pci_scan_single_device);
2306 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
2312 if (pci_ari_enabled(bus)) {
2315 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2319 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2320 next_fn = PCI_ARI_CAP_NFN(cap);
2322 return 0; /* protect against malformed list */
2327 /* dev may be NULL for non-contiguous multifunction devices */
2328 if (!dev || dev->multifunction)
2329 return (fn + 1) % 8;
2334 static int only_one_child(struct pci_bus *bus)
2336 struct pci_dev *bridge = bus->self;
2339 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2340 * we scan for all possible devices, not just Device 0.
2342 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2346 * A PCIe Downstream Port normally leads to a Link with only Device
2347 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2348 * only for Device 0 in that situation.
2350 * Checking has_secondary_link is a hack to identify Downstream
2351 * Ports because sometimes Switches are configured such that the
2352 * PCIe Port Type labels are backwards.
2354 if (bridge && pci_is_pcie(bridge) && bridge->has_secondary_link)
2361 * pci_scan_slot - Scan a PCI slot on a bus for devices
2362 * @bus: PCI bus to scan
2363 * @devfn: slot number to scan (must have zero function)
2365 * Scan a PCI slot on the specified PCI bus for devices, adding
2366 * discovered devices to the @bus->devices list. New devices
2367 * will not have is_added set.
2369 * Returns the number of new devices found.
2371 int pci_scan_slot(struct pci_bus *bus, int devfn)
2373 unsigned fn, nr = 0;
2374 struct pci_dev *dev;
2376 if (only_one_child(bus) && (devfn > 0))
2377 return 0; /* Already scanned the entire slot */
2379 dev = pci_scan_single_device(bus, devfn);
2385 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2386 dev = pci_scan_single_device(bus, devfn + fn);
2390 dev->multifunction = 1;
2394 /* Only one slot has PCIe device */
2395 if (bus->self && nr)
2396 pcie_aspm_init_link_state(bus->self);
2400 EXPORT_SYMBOL(pci_scan_slot);
2402 static int pcie_find_smpss(struct pci_dev *dev, void *data)
2406 if (!pci_is_pcie(dev))
2410 * We don't have a way to change MPS settings on devices that have
2411 * drivers attached. A hot-added device might support only the minimum
2412 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2413 * where devices may be hot-added, we limit the fabric MPS to 128 so
2414 * hot-added devices will work correctly.
2416 * However, if we hot-add a device to a slot directly below a Root
2417 * Port, it's impossible for there to be other existing devices below
2418 * the port. We don't limit the MPS in this case because we can
2419 * reconfigure MPS on both the Root Port and the hot-added device,
2420 * and there are no other devices involved.
2422 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2424 if (dev->is_hotplug_bridge &&
2425 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2428 if (*smpss > dev->pcie_mpss)
2429 *smpss = dev->pcie_mpss;
2434 static void pcie_write_mps(struct pci_dev *dev, int mps)
2438 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2439 mps = 128 << dev->pcie_mpss;
2441 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2445 * For "Performance", the assumption is made that
2446 * downstream communication will never be larger than
2447 * the MRRS. So, the MPS only needs to be configured
2448 * for the upstream communication. This being the case,
2449 * walk from the top down and set the MPS of the child
2450 * to that of the parent bus.
2452 * Configure the device MPS with the smaller of the
2453 * device MPSS or the bridge MPS (which is assumed to be
2454 * properly configured at this point to the largest
2455 * allowable MPS based on its parent bus).
2457 mps = min(mps, pcie_get_mps(dev->bus->self));
2460 rc = pcie_set_mps(dev, mps);
2462 pci_err(dev, "Failed attempting to set the MPS\n");
2465 static void pcie_write_mrrs(struct pci_dev *dev)
2470 * In the "safe" case, do not configure the MRRS. There appear to be
2471 * issues with setting MRRS to 0 on a number of devices.
2473 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2477 * For max performance, the MRRS must be set to the largest supported
2478 * value. However, it cannot be configured larger than the MPS the
2479 * device or the bus can support. This should already be properly
2480 * configured by a prior call to pcie_write_mps().
2482 mrrs = pcie_get_mps(dev);
2485 * MRRS is a R/W register. Invalid values can be written, but a
2486 * subsequent read will verify if the value is acceptable or not.
2487 * If the MRRS value provided is not acceptable (e.g., too large),
2488 * shrink the value until it is acceptable to the HW.
2490 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2491 rc = pcie_set_readrq(dev, mrrs);
2495 pci_warn(dev, "Failed attempting to set the MRRS\n");
2500 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2503 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2507 if (!pci_is_pcie(dev))
2510 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2511 pcie_bus_config == PCIE_BUS_DEFAULT)
2514 mps = 128 << *(u8 *)data;
2515 orig_mps = pcie_get_mps(dev);
2517 pcie_write_mps(dev, mps);
2518 pcie_write_mrrs(dev);
2520 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2521 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2522 orig_mps, pcie_get_readrq(dev));
2528 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2529 * parents then children fashion. If this changes, then this code will not
2532 void pcie_bus_configure_settings(struct pci_bus *bus)
2539 if (!pci_is_pcie(bus->self))
2543 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2544 * to be aware of the MPS of the destination. To work around this,
2545 * simply force the MPS of the entire system to the smallest possible.
2547 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2550 if (pcie_bus_config == PCIE_BUS_SAFE) {
2551 smpss = bus->self->pcie_mpss;
2553 pcie_find_smpss(bus->self, &smpss);
2554 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2557 pcie_bus_configure_set(bus->self, &smpss);
2558 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2560 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2563 * Called after each bus is probed, but before its children are examined. This
2564 * is marked as __weak because multiple architectures define it.
2566 void __weak pcibios_fixup_bus(struct pci_bus *bus)
2568 /* nothing to do, expected to be removed in the future */
2572 * pci_scan_child_bus_extend() - Scan devices below a bus
2573 * @bus: Bus to scan for devices
2574 * @available_buses: Total number of buses available (%0 does not try to
2575 * extend beyond the minimal)
2577 * Scans devices below @bus including subordinate buses. Returns new
2578 * subordinate number including all the found devices. Passing
2579 * @available_buses causes the remaining bus space to be distributed
2580 * equally between hotplug-capable bridges to allow future extension of the
2583 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2584 unsigned int available_buses)
2586 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2587 unsigned int start = bus->busn_res.start;
2588 unsigned int devfn, fn, cmax, max = start;
2589 struct pci_dev *dev;
2592 dev_dbg(&bus->dev, "scanning bus\n");
2594 /* Go find them, Rover! */
2595 for (devfn = 0; devfn < 256; devfn += 8) {
2596 nr_devs = pci_scan_slot(bus, devfn);
2599 * The Jailhouse hypervisor may pass individual functions of a
2600 * multi-function device to a guest without passing function 0.
2601 * Look for them as well.
2603 if (jailhouse_paravirt() && nr_devs == 0) {
2604 for (fn = 1; fn < 8; fn++) {
2605 dev = pci_scan_single_device(bus, devfn + fn);
2607 dev->multifunction = 1;
2612 /* Reserve buses for SR-IOV capability */
2613 used_buses = pci_iov_bus_range(bus);
2617 * After performing arch-dependent fixup of the bus, look behind
2618 * all PCI-to-PCI bridges on this bus.
2620 if (!bus->is_added) {
2621 dev_dbg(&bus->dev, "fixups for bus\n");
2622 pcibios_fixup_bus(bus);
2627 * Calculate how many hotplug bridges and normal bridges there
2628 * are on this bus. We will distribute the additional available
2629 * buses between hotplug bridges.
2631 for_each_pci_bridge(dev, bus) {
2632 if (dev->is_hotplug_bridge)
2639 * Scan bridges that are already configured. We don't touch them
2640 * unless they are misconfigured (which will be done in the second
2643 for_each_pci_bridge(dev, bus) {
2645 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2646 used_buses += cmax - max;
2649 /* Scan bridges that need to be reconfigured */
2650 for_each_pci_bridge(dev, bus) {
2651 unsigned int buses = 0;
2653 if (!hotplug_bridges && normal_bridges == 1) {
2656 * There is only one bridge on the bus (upstream
2657 * port) so it gets all available buses which it
2658 * can then distribute to the possible hotplug
2661 buses = available_buses;
2662 } else if (dev->is_hotplug_bridge) {
2665 * Distribute the extra buses between hotplug
2668 buses = available_buses / hotplug_bridges;
2669 buses = min(buses, available_buses - used_buses);
2673 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2674 used_buses += max - cmax;
2678 * Make sure a hotplug bridge has at least the minimum requested
2679 * number of buses but allow it to grow up to the maximum available
2680 * bus number of there is room.
2682 if (bus->self && bus->self->is_hotplug_bridge) {
2683 used_buses = max_t(unsigned int, available_buses,
2684 pci_hotplug_bus_size - 1);
2685 if (max - start < used_buses) {
2686 max = start + used_buses;
2688 /* Do not allocate more buses than we have room left */
2689 if (max > bus->busn_res.end)
2690 max = bus->busn_res.end;
2692 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2693 &bus->busn_res, max - start);
2698 * We've scanned the bus and so we know all about what's on
2699 * the other side of any bridges that may be on this bus plus
2702 * Return how far we've got finding sub-buses.
2704 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2709 * pci_scan_child_bus() - Scan devices below a bus
2710 * @bus: Bus to scan for devices
2712 * Scans devices below @bus including subordinate buses. Returns new
2713 * subordinate number including all the found devices.
2715 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2717 return pci_scan_child_bus_extend(bus, 0);
2719 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2722 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
2723 * @bridge: Host bridge to set up
2725 * Default empty implementation. Replace with an architecture-specific setup
2726 * routine, if necessary.
2728 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2733 void __weak pcibios_add_bus(struct pci_bus *bus)
2737 void __weak pcibios_remove_bus(struct pci_bus *bus)
2741 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2742 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2745 struct pci_host_bridge *bridge;
2747 bridge = pci_alloc_host_bridge(0);
2751 bridge->dev.parent = parent;
2753 list_splice_init(resources, &bridge->windows);
2754 bridge->sysdata = sysdata;
2755 bridge->busnr = bus;
2758 error = pci_register_host_bridge(bridge);
2768 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2770 int pci_host_probe(struct pci_host_bridge *bridge)
2772 struct pci_bus *bus, *child;
2775 ret = pci_scan_root_bus_bridge(bridge);
2777 dev_err(bridge->dev.parent, "Scanning root bridge failed");
2784 * We insert PCI resources into the iomem_resource and
2785 * ioport_resource trees in either pci_bus_claim_resources()
2786 * or pci_bus_assign_resources().
2788 if (pci_has_flag(PCI_PROBE_ONLY)) {
2789 pci_bus_claim_resources(bus);
2791 pci_bus_size_bridges(bus);
2792 pci_bus_assign_resources(bus);
2794 list_for_each_entry(child, &bus->children, node)
2795 pcie_bus_configure_settings(child);
2798 pci_bus_add_devices(bus);
2801 EXPORT_SYMBOL_GPL(pci_host_probe);
2803 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2805 struct resource *res = &b->busn_res;
2806 struct resource *parent_res, *conflict;
2810 res->flags = IORESOURCE_BUS;
2812 if (!pci_is_root_bus(b))
2813 parent_res = &b->parent->busn_res;
2815 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2816 res->flags |= IORESOURCE_PCI_FIXED;
2819 conflict = request_resource_conflict(parent_res, res);
2822 dev_printk(KERN_DEBUG, &b->dev,
2823 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2824 res, pci_is_root_bus(b) ? "domain " : "",
2825 parent_res, conflict->name, conflict);
2827 return conflict == NULL;
2830 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2832 struct resource *res = &b->busn_res;
2833 struct resource old_res = *res;
2834 resource_size_t size;
2837 if (res->start > bus_max)
2840 size = bus_max - res->start + 1;
2841 ret = adjust_resource(res, res->start, size);
2842 dev_printk(KERN_DEBUG, &b->dev,
2843 "busn_res: %pR end %s updated to %02x\n",
2844 &old_res, ret ? "can not be" : "is", bus_max);
2846 if (!ret && !res->parent)
2847 pci_bus_insert_busn_res(b, res->start, res->end);
2852 void pci_bus_release_busn_res(struct pci_bus *b)
2854 struct resource *res = &b->busn_res;
2857 if (!res->flags || !res->parent)
2860 ret = release_resource(res);
2861 dev_printk(KERN_DEBUG, &b->dev,
2862 "busn_res: %pR %s released\n",
2863 res, ret ? "can not be" : "is");
2866 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
2868 struct resource_entry *window;
2876 resource_list_for_each_entry(window, &bridge->windows)
2877 if (window->res->flags & IORESOURCE_BUS) {
2882 ret = pci_register_host_bridge(bridge);
2887 bus = bridge->busnr;
2891 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2893 pci_bus_insert_busn_res(b, bus, 255);
2896 max = pci_scan_child_bus(b);
2899 pci_bus_update_busn_res_end(b, max);
2903 EXPORT_SYMBOL(pci_scan_root_bus_bridge);
2905 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2906 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2908 struct resource_entry *window;
2913 resource_list_for_each_entry(window, resources)
2914 if (window->res->flags & IORESOURCE_BUS) {
2919 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2925 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2927 pci_bus_insert_busn_res(b, bus, 255);
2930 max = pci_scan_child_bus(b);
2933 pci_bus_update_busn_res_end(b, max);
2937 EXPORT_SYMBOL(pci_scan_root_bus);
2939 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2942 LIST_HEAD(resources);
2945 pci_add_resource(&resources, &ioport_resource);
2946 pci_add_resource(&resources, &iomem_resource);
2947 pci_add_resource(&resources, &busn_resource);
2948 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2950 pci_scan_child_bus(b);
2952 pci_free_resource_list(&resources);
2956 EXPORT_SYMBOL(pci_scan_bus);
2959 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
2960 * @bridge: PCI bridge for the bus to scan
2962 * Scan a PCI bus and child buses for new devices, add them,
2963 * and enable them, resizing bridge mmio/io resource if necessary
2964 * and possible. The caller must ensure the child devices are already
2965 * removed for resizing to occur.
2967 * Returns the max number of subordinate bus discovered.
2969 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2972 struct pci_bus *bus = bridge->subordinate;
2974 max = pci_scan_child_bus(bus);
2976 pci_assign_unassigned_bridge_resources(bridge);
2978 pci_bus_add_devices(bus);
2984 * pci_rescan_bus - Scan a PCI bus for devices
2985 * @bus: PCI bus to scan
2987 * Scan a PCI bus and child buses for new devices, add them,
2990 * Returns the max number of subordinate bus discovered.
2992 unsigned int pci_rescan_bus(struct pci_bus *bus)
2996 max = pci_scan_child_bus(bus);
2997 pci_assign_unassigned_bus_resources(bus);
2998 pci_bus_add_devices(bus);
3002 EXPORT_SYMBOL_GPL(pci_rescan_bus);
3005 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3006 * routines should always be executed under this mutex.
3008 static DEFINE_MUTEX(pci_rescan_remove_lock);
3010 void pci_lock_rescan_remove(void)
3012 mutex_lock(&pci_rescan_remove_lock);
3014 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3016 void pci_unlock_rescan_remove(void)
3018 mutex_unlock(&pci_rescan_remove_lock);
3020 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3022 static int __init pci_sort_bf_cmp(const struct device *d_a,
3023 const struct device *d_b)
3025 const struct pci_dev *a = to_pci_dev(d_a);
3026 const struct pci_dev *b = to_pci_dev(d_b);
3028 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3029 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3031 if (a->bus->number < b->bus->number) return -1;
3032 else if (a->bus->number > b->bus->number) return 1;
3034 if (a->devfn < b->devfn) return -1;
3035 else if (a->devfn > b->devfn) return 1;
3040 void __init pci_sort_breadthfirst(void)
3042 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3045 int pci_hp_add_bridge(struct pci_dev *dev)
3047 struct pci_bus *parent = dev->bus;
3048 int busnr, start = parent->busn_res.start;
3049 unsigned int available_buses = 0;
3050 int end = parent->busn_res.end;
3052 for (busnr = start; busnr <= end; busnr++) {
3053 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3056 if (busnr-- > end) {
3057 pci_err(dev, "No bus number available for hot-added bridge\n");
3061 /* Scan bridges that are already configured */
3062 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3065 * Distribute the available bus numbers between hotplug-capable
3066 * bridges to make extending the chain later possible.
3068 available_buses = end - busnr;
3070 /* Scan bridges that need to be reconfigured */
3071 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3073 if (!dev->subordinate)
3078 EXPORT_SYMBOL_GPL(pci_hp_add_bridge);