1 // SPDX-License-Identifier: GPL-2.0
3 * Support routines for initializing a PCI subsystem
5 * Extruded from code written by
6 * Dave Rusling (david.rusling@reo.mts.dec.com)
7 * David Mosberger (davidm@cs.arizona.edu)
8 * David Miller (davem@redhat.com)
10 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
11 * PCI-PCI bridges cleanup, sorted resource allocation.
12 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13 * Converted to allocation in 3 passes, which gives
14 * tighter packing. Prefetchable range support.
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/errno.h>
22 #include <linux/ioport.h>
23 #include <linux/cache.h>
24 #include <linux/slab.h>
25 #include <linux/acpi.h>
28 unsigned int pci_flags;
30 struct pci_dev_resource {
31 struct list_head list;
34 resource_size_t start;
36 resource_size_t add_size;
37 resource_size_t min_align;
41 static void free_list(struct list_head *head)
43 struct pci_dev_resource *dev_res, *tmp;
45 list_for_each_entry_safe(dev_res, tmp, head, list) {
46 list_del(&dev_res->list);
52 * add_to_list() - Add a new resource tracker to the list
53 * @head: Head of the list
54 * @dev: Device to which the resource belongs
55 * @res: Resource to be tracked
56 * @add_size: Additional size to be optionally added to the resource
58 static int add_to_list(struct list_head *head, struct pci_dev *dev,
59 struct resource *res, resource_size_t add_size,
60 resource_size_t min_align)
62 struct pci_dev_resource *tmp;
64 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
70 tmp->start = res->start;
72 tmp->flags = res->flags;
73 tmp->add_size = add_size;
74 tmp->min_align = min_align;
76 list_add(&tmp->list, head);
81 static void remove_from_list(struct list_head *head, struct resource *res)
83 struct pci_dev_resource *dev_res, *tmp;
85 list_for_each_entry_safe(dev_res, tmp, head, list) {
86 if (dev_res->res == res) {
87 list_del(&dev_res->list);
94 static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
97 struct pci_dev_resource *dev_res;
99 list_for_each_entry(dev_res, head, list) {
100 if (dev_res->res == res)
107 static resource_size_t get_res_add_size(struct list_head *head,
108 struct resource *res)
110 struct pci_dev_resource *dev_res;
112 dev_res = res_to_dev_res(head, res);
113 return dev_res ? dev_res->add_size : 0;
116 static resource_size_t get_res_add_align(struct list_head *head,
117 struct resource *res)
119 struct pci_dev_resource *dev_res;
121 dev_res = res_to_dev_res(head, res);
122 return dev_res ? dev_res->min_align : 0;
126 /* Sort resources by alignment */
127 static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
131 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
133 struct pci_dev_resource *dev_res, *tmp;
134 resource_size_t r_align;
137 r = &dev->resource[i];
139 if (r->flags & IORESOURCE_PCI_FIXED)
142 if (!(r->flags) || r->parent)
145 r_align = pci_resource_alignment(dev, r);
147 pci_warn(dev, "BAR %d: %pR has bogus alignment\n",
152 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
154 panic("pdev_sort_resources(): kmalloc() failed!\n");
158 /* Fallback is smallest one or list is empty */
160 list_for_each_entry(dev_res, head, list) {
161 resource_size_t align;
163 align = pci_resource_alignment(dev_res->dev,
166 if (r_align > align) {
171 /* Insert it just before n */
172 list_add_tail(&tmp->list, n);
176 static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head)
178 u16 class = dev->class >> 8;
180 /* Don't touch classless devices or host bridges or IOAPICs */
181 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
184 /* Don't touch IOAPIC devices already enabled by firmware */
185 if (class == PCI_CLASS_SYSTEM_PIC) {
187 pci_read_config_word(dev, PCI_COMMAND, &command);
188 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
192 pdev_sort_resources(dev, head);
195 static inline void reset_resource(struct resource *res)
203 * reassign_resources_sorted() - Satisfy any additional resource requests
205 * @realloc_head: Head of the list tracking requests requiring
206 * additional resources
207 * @head: Head of the list tracking requests with allocated
210 * Walk through each element of the realloc_head and try to procure additional
211 * resources for the element, provided the element is in the head list.
213 static void reassign_resources_sorted(struct list_head *realloc_head,
214 struct list_head *head)
216 struct resource *res;
217 struct pci_dev_resource *add_res, *tmp;
218 struct pci_dev_resource *dev_res;
219 resource_size_t add_size, align;
222 list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
223 bool found_match = false;
226 /* Skip resource that has been reset */
230 /* Skip this resource if not found in head list */
231 list_for_each_entry(dev_res, head, list) {
232 if (dev_res->res == res) {
237 if (!found_match) /* Just skip */
240 idx = res - &add_res->dev->resource[0];
241 add_size = add_res->add_size;
242 align = add_res->min_align;
243 if (!resource_size(res)) {
245 res->end = res->start + add_size - 1;
246 if (pci_assign_resource(add_res->dev, idx))
249 res->flags |= add_res->flags &
250 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
251 if (pci_reassign_resource(add_res->dev, idx,
253 pci_info(add_res->dev, "failed to add %llx res[%d]=%pR\n",
254 (unsigned long long) add_size, idx,
258 list_del(&add_res->list);
264 * assign_requested_resources_sorted() - Satisfy resource requests
266 * @head: Head of the list tracking requests for resources
267 * @fail_head: Head of the list tracking requests that could not be
270 * Satisfy resource requests of each element in the list. Add requests that
271 * could not be satisfied to the failed_list.
273 static void assign_requested_resources_sorted(struct list_head *head,
274 struct list_head *fail_head)
276 struct resource *res;
277 struct pci_dev_resource *dev_res;
280 list_for_each_entry(dev_res, head, list) {
282 idx = res - &dev_res->dev->resource[0];
283 if (resource_size(res) &&
284 pci_assign_resource(dev_res->dev, idx)) {
287 * If the failed resource is a ROM BAR and
288 * it will be enabled later, don't add it
291 if (!((idx == PCI_ROM_RESOURCE) &&
292 (!(res->flags & IORESOURCE_ROM_ENABLE))))
293 add_to_list(fail_head,
303 static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
305 struct pci_dev_resource *fail_res;
306 unsigned long mask = 0;
308 /* Check failed type */
309 list_for_each_entry(fail_res, fail_head, list)
310 mask |= fail_res->flags;
313 * One pref failed resource will set IORESOURCE_MEM, as we can
314 * allocate pref in non-pref range. Will release all assigned
315 * non-pref sibling resources according to that bit.
317 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
320 static bool pci_need_to_release(unsigned long mask, struct resource *res)
322 if (res->flags & IORESOURCE_IO)
323 return !!(mask & IORESOURCE_IO);
325 /* Check pref at first */
326 if (res->flags & IORESOURCE_PREFETCH) {
327 if (mask & IORESOURCE_PREFETCH)
329 /* Count pref if its parent is non-pref */
330 else if ((mask & IORESOURCE_MEM) &&
331 !(res->parent->flags & IORESOURCE_PREFETCH))
337 if (res->flags & IORESOURCE_MEM)
338 return !!(mask & IORESOURCE_MEM);
340 return false; /* Should not get here */
343 static void __assign_resources_sorted(struct list_head *head,
344 struct list_head *realloc_head,
345 struct list_head *fail_head)
348 * Should not assign requested resources at first. They could be
349 * adjacent, so later reassign can not reallocate them one by one in
350 * parent resource window.
352 * Try to assign requested + add_size at beginning. If could do that,
353 * could get out early. If could not do that, we still try to assign
354 * requested at first, then try to reassign add_size for some resources.
356 * Separate three resource type checking if we need to release
357 * assigned resource after requested + add_size try.
359 * 1. If IO port assignment fails, will release assigned IO
361 * 2. If pref MMIO assignment fails, release assigned pref
362 * MMIO. If assigned pref MMIO's parent is non-pref MMIO
363 * and non-pref MMIO assignment fails, will release that
364 * assigned pref MMIO.
365 * 3. If non-pref MMIO assignment fails or pref MMIO
366 * assignment fails, will release assigned non-pref MMIO.
368 LIST_HEAD(save_head);
369 LIST_HEAD(local_fail_head);
370 struct pci_dev_resource *save_res;
371 struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
372 unsigned long fail_type;
373 resource_size_t add_align, align;
375 /* Check if optional add_size is there */
376 if (!realloc_head || list_empty(realloc_head))
377 goto requested_and_reassign;
379 /* Save original start, end, flags etc at first */
380 list_for_each_entry(dev_res, head, list) {
381 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
382 free_list(&save_head);
383 goto requested_and_reassign;
387 /* Update res in head list with add_size in realloc_head list */
388 list_for_each_entry_safe(dev_res, tmp_res, head, list) {
389 dev_res->res->end += get_res_add_size(realloc_head,
393 * There are two kinds of additional resources in the list:
394 * 1. bridge resource -- IORESOURCE_STARTALIGN
395 * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN
396 * Here just fix the additional alignment for bridge
398 if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
401 add_align = get_res_add_align(realloc_head, dev_res->res);
404 * The "head" list is sorted by alignment so resources with
405 * bigger alignment will be assigned first. After we
406 * change the alignment of a dev_res in "head" list, we
407 * need to reorder the list by alignment to make it
410 if (add_align > dev_res->res->start) {
411 resource_size_t r_size = resource_size(dev_res->res);
413 dev_res->res->start = add_align;
414 dev_res->res->end = add_align + r_size - 1;
416 list_for_each_entry(dev_res2, head, list) {
417 align = pci_resource_alignment(dev_res2->dev,
419 if (add_align > align) {
420 list_move_tail(&dev_res->list,
429 /* Try updated head list with add_size added */
430 assign_requested_resources_sorted(head, &local_fail_head);
432 /* All assigned with add_size? */
433 if (list_empty(&local_fail_head)) {
434 /* Remove head list from realloc_head list */
435 list_for_each_entry(dev_res, head, list)
436 remove_from_list(realloc_head, dev_res->res);
437 free_list(&save_head);
442 /* Check failed type */
443 fail_type = pci_fail_res_type_mask(&local_fail_head);
444 /* Remove not need to be released assigned res from head list etc */
445 list_for_each_entry_safe(dev_res, tmp_res, head, list)
446 if (dev_res->res->parent &&
447 !pci_need_to_release(fail_type, dev_res->res)) {
448 /* Remove it from realloc_head list */
449 remove_from_list(realloc_head, dev_res->res);
450 remove_from_list(&save_head, dev_res->res);
451 list_del(&dev_res->list);
455 free_list(&local_fail_head);
456 /* Release assigned resource */
457 list_for_each_entry(dev_res, head, list)
458 if (dev_res->res->parent)
459 release_resource(dev_res->res);
460 /* Restore start/end/flags from saved list */
461 list_for_each_entry(save_res, &save_head, list) {
462 struct resource *res = save_res->res;
464 res->start = save_res->start;
465 res->end = save_res->end;
466 res->flags = save_res->flags;
468 free_list(&save_head);
470 requested_and_reassign:
471 /* Satisfy the must-have resource requests */
472 assign_requested_resources_sorted(head, fail_head);
474 /* Try to satisfy any additional optional resource requests */
476 reassign_resources_sorted(realloc_head, head);
480 static void pdev_assign_resources_sorted(struct pci_dev *dev,
481 struct list_head *add_head,
482 struct list_head *fail_head)
486 __dev_sort_resources(dev, &head);
487 __assign_resources_sorted(&head, add_head, fail_head);
491 static void pbus_assign_resources_sorted(const struct pci_bus *bus,
492 struct list_head *realloc_head,
493 struct list_head *fail_head)
498 list_for_each_entry(dev, &bus->devices, bus_list)
499 __dev_sort_resources(dev, &head);
501 __assign_resources_sorted(&head, realloc_head, fail_head);
504 void pci_setup_cardbus(struct pci_bus *bus)
506 struct pci_dev *bridge = bus->self;
507 struct resource *res;
508 struct pci_bus_region region;
510 pci_info(bridge, "CardBus bridge to %pR\n",
513 res = bus->resource[0];
514 pcibios_resource_to_bus(bridge->bus, ®ion, res);
515 if (res->flags & IORESOURCE_IO) {
517 * The IO resource is allocated a range twice as large as it
518 * would normally need. This allows us to set both IO regs.
520 pci_info(bridge, " bridge window %pR\n", res);
521 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
523 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
527 res = bus->resource[1];
528 pcibios_resource_to_bus(bridge->bus, ®ion, res);
529 if (res->flags & IORESOURCE_IO) {
530 pci_info(bridge, " bridge window %pR\n", res);
531 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
533 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
537 res = bus->resource[2];
538 pcibios_resource_to_bus(bridge->bus, ®ion, res);
539 if (res->flags & IORESOURCE_MEM) {
540 pci_info(bridge, " bridge window %pR\n", res);
541 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
543 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
547 res = bus->resource[3];
548 pcibios_resource_to_bus(bridge->bus, ®ion, res);
549 if (res->flags & IORESOURCE_MEM) {
550 pci_info(bridge, " bridge window %pR\n", res);
551 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
553 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
557 EXPORT_SYMBOL(pci_setup_cardbus);
560 * Initialize bridges with base/limit values we have collected. PCI-to-PCI
561 * Bridge Architecture Specification rev. 1.1 (1998) requires that if there
562 * are no I/O ports or memory behind the bridge, the corresponding range
563 * must be turned off by writing base value greater than limit to the
564 * bridge's base/limit registers.
566 * Note: care must be taken when updating I/O base/limit registers of
567 * bridges which support 32-bit I/O. This update requires two config space
568 * writes, so it's quite possible that an I/O window of the bridge will
569 * have some undesirable address (e.g. 0) after the first write. Ditto
570 * 64-bit prefetchable MMIO.
572 static void pci_setup_bridge_io(struct pci_dev *bridge)
574 struct resource *res;
575 struct pci_bus_region region;
576 unsigned long io_mask;
577 u8 io_base_lo, io_limit_lo;
581 io_mask = PCI_IO_RANGE_MASK;
582 if (bridge->io_window_1k)
583 io_mask = PCI_IO_1K_RANGE_MASK;
585 /* Set up the top and bottom of the PCI I/O segment for this bus */
586 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
587 pcibios_resource_to_bus(bridge->bus, ®ion, res);
588 if (res->flags & IORESOURCE_IO) {
589 pci_read_config_word(bridge, PCI_IO_BASE, &l);
590 io_base_lo = (region.start >> 8) & io_mask;
591 io_limit_lo = (region.end >> 8) & io_mask;
592 l = ((u16) io_limit_lo << 8) | io_base_lo;
593 /* Set up upper 16 bits of I/O base/limit */
594 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
595 pci_info(bridge, " bridge window %pR\n", res);
597 /* Clear upper 16 bits of I/O base/limit */
601 /* Temporarily disable the I/O range before updating PCI_IO_BASE */
602 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
603 /* Update lower 16 bits of I/O base/limit */
604 pci_write_config_word(bridge, PCI_IO_BASE, l);
605 /* Update upper 16 bits of I/O base/limit */
606 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
609 static void pci_setup_bridge_mmio(struct pci_dev *bridge)
611 struct resource *res;
612 struct pci_bus_region region;
615 /* Set up the top and bottom of the PCI Memory segment for this bus */
616 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
617 pcibios_resource_to_bus(bridge->bus, ®ion, res);
618 if (res->flags & IORESOURCE_MEM) {
619 l = (region.start >> 16) & 0xfff0;
620 l |= region.end & 0xfff00000;
621 pci_info(bridge, " bridge window %pR\n", res);
625 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
628 static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
630 struct resource *res;
631 struct pci_bus_region region;
635 * Clear out the upper 32 bits of PREF limit. If
636 * PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables
637 * PREF range, which is ok.
639 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
641 /* Set up PREF base/limit */
643 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
644 pcibios_resource_to_bus(bridge->bus, ®ion, res);
645 if (res->flags & IORESOURCE_PREFETCH) {
646 l = (region.start >> 16) & 0xfff0;
647 l |= region.end & 0xfff00000;
648 if (res->flags & IORESOURCE_MEM_64) {
649 bu = upper_32_bits(region.start);
650 lu = upper_32_bits(region.end);
652 pci_info(bridge, " bridge window %pR\n", res);
656 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
658 /* Set the upper 32 bits of PREF base & limit */
659 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
660 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
663 static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
665 struct pci_dev *bridge = bus->self;
667 pci_info(bridge, "PCI bridge to %pR\n",
670 if (type & IORESOURCE_IO)
671 pci_setup_bridge_io(bridge);
673 if (type & IORESOURCE_MEM)
674 pci_setup_bridge_mmio(bridge);
676 if (type & IORESOURCE_PREFETCH)
677 pci_setup_bridge_mmio_pref(bridge);
679 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
682 void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
686 void pci_setup_bridge(struct pci_bus *bus)
688 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
691 pcibios_setup_bridge(bus, type);
692 __pci_setup_bridge(bus, type);
696 int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
698 if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
701 if (pci_claim_resource(bridge, i) == 0)
702 return 0; /* Claimed the window */
704 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
707 if (!pci_bus_clip_resource(bridge, i))
708 return -EINVAL; /* Clipping didn't change anything */
710 switch (i - PCI_BRIDGE_RESOURCES) {
712 pci_setup_bridge_io(bridge);
715 pci_setup_bridge_mmio(bridge);
718 pci_setup_bridge_mmio_pref(bridge);
724 if (pci_claim_resource(bridge, i) == 0)
725 return 0; /* Claimed a smaller window */
731 * Check whether the bridge supports optional I/O and prefetchable memory
732 * ranges. If not, the respective base/limit registers must be read-only
735 static void pci_bridge_check_ranges(struct pci_bus *bus)
737 struct pci_dev *bridge = bus->self;
738 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
740 b_res[1].flags |= IORESOURCE_MEM;
742 if (bridge->io_window)
743 b_res[0].flags |= IORESOURCE_IO;
745 if (bridge->pref_window) {
746 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
747 if (bridge->pref_64_window) {
748 b_res[2].flags |= IORESOURCE_MEM_64;
749 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
755 * Helper function for sizing routines. Assigned resources have non-NULL
758 * Return first unassigned resource of the correct type. If there is none,
759 * return first assigned resource of the correct type. If none of the
760 * above, return NULL.
762 * Returning an assigned resource of the correct type allows the caller to
763 * distinguish between already assigned and no resource of the correct type.
765 static struct resource *find_bus_resource_of_type(struct pci_bus *bus,
766 unsigned long type_mask,
769 struct resource *r, *r_assigned = NULL;
772 pci_bus_for_each_resource(bus, r, i) {
773 if (r == &ioport_resource || r == &iomem_resource)
775 if (r && (r->flags & type_mask) == type && !r->parent)
777 if (r && (r->flags & type_mask) == type && !r_assigned)
783 static resource_size_t calculate_iosize(resource_size_t size,
784 resource_size_t min_size,
785 resource_size_t size1,
786 resource_size_t add_size,
787 resource_size_t children_add_size,
788 resource_size_t old_size,
789 resource_size_t align)
796 * To be fixed in 2.5: we should have sort of HAVE_ISA flag in the
799 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
800 size = (size & 0xff) + ((size & ~0xffUL) << 2);
806 size = ALIGN(max(size, add_size) + children_add_size, align);
810 static resource_size_t calculate_memsize(resource_size_t size,
811 resource_size_t min_size,
812 resource_size_t add_size,
813 resource_size_t children_add_size,
814 resource_size_t old_size,
815 resource_size_t align)
824 size = ALIGN(max(size, add_size) + children_add_size, align);
828 resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
834 #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
835 #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
836 #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
838 static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type)
840 resource_size_t align = 1, arch_align;
842 if (type & IORESOURCE_MEM)
843 align = PCI_P2P_DEFAULT_MEM_ALIGN;
844 else if (type & IORESOURCE_IO) {
846 * Per spec, I/O windows are 4K-aligned, but some bridges have
847 * an extension to support 1K alignment.
849 if (bus->self->io_window_1k)
850 align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
852 align = PCI_P2P_DEFAULT_IO_ALIGN;
855 arch_align = pcibios_window_alignment(bus, type);
856 return max(align, arch_align);
860 * pbus_size_io() - Size the I/O window of a given bus
863 * @min_size: The minimum I/O window that must be allocated
864 * @add_size: Additional optional I/O window
865 * @realloc_head: Track the additional I/O window on this list
867 * Sizing the I/O windows of the PCI-PCI bridge is trivial, since these
868 * windows have 1K or 4K granularity and the I/O ranges of non-bridge PCI
869 * devices are limited to 256 bytes. We must be careful with the ISA
872 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
873 resource_size_t add_size,
874 struct list_head *realloc_head)
877 struct resource *b_res = find_bus_resource_of_type(bus, IORESOURCE_IO,
879 resource_size_t size = 0, size0 = 0, size1 = 0;
880 resource_size_t children_add_size = 0;
881 resource_size_t min_align, align;
886 /* If resource is already assigned, nothing more to do */
890 min_align = window_alignment(bus, IORESOURCE_IO);
891 list_for_each_entry(dev, &bus->devices, bus_list) {
894 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
895 struct resource *r = &dev->resource[i];
896 unsigned long r_size;
898 if (r->parent || !(r->flags & IORESOURCE_IO))
900 r_size = resource_size(r);
903 /* Might be re-aligned for ISA */
908 align = pci_resource_alignment(dev, r);
909 if (align > min_align)
913 children_add_size += get_res_add_size(realloc_head, r);
917 size0 = calculate_iosize(size, min_size, size1, 0, 0,
918 resource_size(b_res), min_align);
919 size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
920 calculate_iosize(size, min_size, size1, add_size, children_add_size,
921 resource_size(b_res), min_align);
922 if (!size0 && !size1) {
923 if (b_res->start || b_res->end)
924 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
925 b_res, &bus->busn_res);
930 b_res->start = min_align;
931 b_res->end = b_res->start + size0 - 1;
932 b_res->flags |= IORESOURCE_STARTALIGN;
933 if (size1 > size0 && realloc_head) {
934 add_to_list(realloc_head, bus->self, b_res, size1-size0,
936 pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n",
937 b_res, &bus->busn_res,
938 (unsigned long long) size1 - size0);
942 static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
945 resource_size_t align = 0;
946 resource_size_t min_align = 0;
949 for (order = 0; order <= max_order; order++) {
950 resource_size_t align1 = 1;
952 align1 <<= (order + 20);
956 else if (ALIGN(align + min_align, min_align) < align1)
957 min_align = align1 >> 1;
958 align += aligns[order];
965 * pbus_size_mem() - Size the memory window of a given bus
968 * @mask: Mask the resource flag, then compare it with type
969 * @type: The type of free resource from bridge
970 * @type2: Second match type
971 * @type3: Third match type
972 * @min_size: The minimum memory window that must be allocated
973 * @add_size: Additional optional memory window
974 * @realloc_head: Track the additional memory window on this list
976 * Calculate the size of the bus and minimal alignment which guarantees
977 * that all child resources fit in this size.
979 * Return -ENOSPC if there's no available bus resource of the desired
980 * type. Otherwise, set the bus resource start/end to indicate the
981 * required size, add things to realloc_head (if supplied), and return 0.
983 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
984 unsigned long type, unsigned long type2,
985 unsigned long type3, resource_size_t min_size,
986 resource_size_t add_size,
987 struct list_head *realloc_head)
990 resource_size_t min_align, align, size, size0, size1;
991 resource_size_t aligns[18]; /* Alignments from 1MB to 128GB */
992 int order, max_order;
993 struct resource *b_res = find_bus_resource_of_type(bus,
994 mask | IORESOURCE_PREFETCH, type);
995 resource_size_t children_add_size = 0;
996 resource_size_t children_add_align = 0;
997 resource_size_t add_align = 0;
1002 /* If resource is already assigned, nothing more to do */
1006 memset(aligns, 0, sizeof(aligns));
1010 list_for_each_entry(dev, &bus->devices, bus_list) {
1013 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1014 struct resource *r = &dev->resource[i];
1015 resource_size_t r_size;
1017 if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
1018 ((r->flags & mask) != type &&
1019 (r->flags & mask) != type2 &&
1020 (r->flags & mask) != type3))
1022 r_size = resource_size(r);
1023 #ifdef CONFIG_PCI_IOV
1024 /* Put SRIOV requested res to the optional list */
1025 if (realloc_head && i >= PCI_IOV_RESOURCES &&
1026 i <= PCI_IOV_RESOURCE_END) {
1027 add_align = max(pci_resource_alignment(dev, r), add_align);
1028 r->end = r->start - 1;
1029 add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */);
1030 children_add_size += r_size;
1035 * aligns[0] is for 1MB (since bridge memory
1036 * windows are always at least 1MB aligned), so
1037 * keep "order" from being negative for smaller
1040 align = pci_resource_alignment(dev, r);
1041 order = __ffs(align) - 20;
1044 if (order >= ARRAY_SIZE(aligns)) {
1045 pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
1046 i, r, (unsigned long long) align);
1050 size += max(r_size, align);
1052 * Exclude ranges with size > align from calculation of
1055 if (r_size <= align)
1056 aligns[order] += align;
1057 if (order > max_order)
1061 children_add_size += get_res_add_size(realloc_head, r);
1062 children_add_align = get_res_add_align(realloc_head, r);
1063 add_align = max(add_align, children_add_align);
1068 min_align = calculate_mem_align(aligns, max_order);
1069 min_align = max(min_align, window_alignment(bus, b_res->flags));
1070 size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), min_align);
1071 add_align = max(min_align, add_align);
1072 size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
1073 calculate_memsize(size, min_size, add_size, children_add_size,
1074 resource_size(b_res), add_align);
1075 if (!size0 && !size1) {
1076 if (b_res->start || b_res->end)
1077 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
1078 b_res, &bus->busn_res);
1082 b_res->start = min_align;
1083 b_res->end = size0 + min_align - 1;
1084 b_res->flags |= IORESOURCE_STARTALIGN;
1085 if (size1 > size0 && realloc_head) {
1086 add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
1087 pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
1088 b_res, &bus->busn_res,
1089 (unsigned long long) (size1 - size0),
1090 (unsigned long long) add_align);
1095 unsigned long pci_cardbus_resource_alignment(struct resource *res)
1097 if (res->flags & IORESOURCE_IO)
1098 return pci_cardbus_io_size;
1099 if (res->flags & IORESOURCE_MEM)
1100 return pci_cardbus_mem_size;
1104 static void pci_bus_size_cardbus(struct pci_bus *bus,
1105 struct list_head *realloc_head)
1107 struct pci_dev *bridge = bus->self;
1108 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
1109 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1112 if (b_res[0].parent)
1113 goto handle_b_res_1;
1115 * Reserve some resources for CardBus. We reserve a fixed amount
1116 * of bus space for CardBus bridges.
1118 b_res[0].start = pci_cardbus_io_size;
1119 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
1120 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1122 b_res[0].end -= pci_cardbus_io_size;
1123 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1124 pci_cardbus_io_size);
1128 if (b_res[1].parent)
1129 goto handle_b_res_2;
1130 b_res[1].start = pci_cardbus_io_size;
1131 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
1132 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1134 b_res[1].end -= pci_cardbus_io_size;
1135 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
1136 pci_cardbus_io_size);
1140 /* MEM1 must not be pref MMIO */
1141 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1142 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1143 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1144 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1145 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1148 /* Check whether prefetchable memory is supported by this bridge. */
1149 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1150 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1151 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1152 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1153 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1156 if (b_res[2].parent)
1157 goto handle_b_res_3;
1159 * If we have prefetchable memory support, allocate two regions.
1160 * Otherwise, allocate one region of twice the size.
1162 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1163 b_res[2].start = pci_cardbus_mem_size;
1164 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
1165 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1166 IORESOURCE_STARTALIGN;
1168 b_res[2].end -= pci_cardbus_mem_size;
1169 add_to_list(realloc_head, bridge, b_res+2,
1170 pci_cardbus_mem_size, pci_cardbus_mem_size);
1173 /* Reduce that to half */
1174 b_res_3_size = pci_cardbus_mem_size;
1178 if (b_res[3].parent)
1180 b_res[3].start = pci_cardbus_mem_size;
1181 b_res[3].end = b_res[3].start + b_res_3_size - 1;
1182 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1184 b_res[3].end -= b_res_3_size;
1185 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
1186 pci_cardbus_mem_size);
1193 void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1195 struct pci_dev *dev;
1196 unsigned long mask, prefmask, type2 = 0, type3 = 0;
1197 resource_size_t additional_io_size = 0, additional_mmio_size = 0,
1198 additional_mmio_pref_size = 0;
1199 struct resource *b_res;
1202 list_for_each_entry(dev, &bus->devices, bus_list) {
1203 struct pci_bus *b = dev->subordinate;
1207 switch (dev->hdr_type) {
1208 case PCI_HEADER_TYPE_CARDBUS:
1209 pci_bus_size_cardbus(b, realloc_head);
1212 case PCI_HEADER_TYPE_BRIDGE:
1214 __pci_bus_size_bridges(b, realloc_head);
1220 if (pci_is_root_bus(bus))
1223 switch (bus->self->hdr_type) {
1224 case PCI_HEADER_TYPE_CARDBUS:
1225 /* Don't size CardBuses yet */
1228 case PCI_HEADER_TYPE_BRIDGE:
1229 pci_bridge_check_ranges(bus);
1230 if (bus->self->is_hotplug_bridge) {
1231 additional_io_size = pci_hotplug_io_size;
1232 additional_mmio_size = pci_hotplug_mmio_size;
1233 additional_mmio_pref_size = pci_hotplug_mmio_pref_size;
1237 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1238 additional_io_size, realloc_head);
1241 * If there's a 64-bit prefetchable MMIO window, compute
1242 * the size required to put all 64-bit prefetchable
1245 b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES];
1246 mask = IORESOURCE_MEM;
1247 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1248 if (b_res[2].flags & IORESOURCE_MEM_64) {
1249 prefmask |= IORESOURCE_MEM_64;
1250 ret = pbus_size_mem(bus, prefmask, prefmask,
1252 realloc_head ? 0 : additional_mmio_pref_size,
1253 additional_mmio_pref_size, realloc_head);
1256 * If successful, all non-prefetchable resources
1257 * and any 32-bit prefetchable resources will go in
1258 * the non-prefetchable window.
1262 type2 = prefmask & ~IORESOURCE_MEM_64;
1263 type3 = prefmask & ~IORESOURCE_PREFETCH;
1268 * If there is no 64-bit prefetchable window, compute the
1269 * size required to put all prefetchable resources in the
1270 * 32-bit prefetchable window (if there is one).
1273 prefmask &= ~IORESOURCE_MEM_64;
1274 ret = pbus_size_mem(bus, prefmask, prefmask,
1276 realloc_head ? 0 : additional_mmio_pref_size,
1277 additional_mmio_pref_size, realloc_head);
1280 * If successful, only non-prefetchable resources
1281 * will go in the non-prefetchable window.
1286 additional_mmio_size += additional_mmio_pref_size;
1288 type2 = type3 = IORESOURCE_MEM;
1292 * Compute the size required to put everything else in the
1293 * non-prefetchable window. This includes:
1295 * - all non-prefetchable resources
1296 * - 32-bit prefetchable resources if there's a 64-bit
1297 * prefetchable window or no prefetchable window at all
1298 * - 64-bit prefetchable resources if there's no prefetchable
1301 * Note that the strategy in __pci_assign_resource() must match
1302 * that used here. Specifically, we cannot put a 32-bit
1303 * prefetchable resource in a 64-bit prefetchable window.
1305 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1306 realloc_head ? 0 : additional_mmio_size,
1307 additional_mmio_size, realloc_head);
1312 void pci_bus_size_bridges(struct pci_bus *bus)
1314 __pci_bus_size_bridges(bus, NULL);
1316 EXPORT_SYMBOL(pci_bus_size_bridges);
1318 static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
1321 struct resource *parent_r;
1322 unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM |
1323 IORESOURCE_PREFETCH;
1325 pci_bus_for_each_resource(b, parent_r, i) {
1329 if ((r->flags & mask) == (parent_r->flags & mask) &&
1330 resource_contains(parent_r, r))
1331 request_resource(parent_r, r);
1336 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they are
1337 * skipped by pbus_assign_resources_sorted().
1339 static void pdev_assign_fixed_resources(struct pci_dev *dev)
1343 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1345 struct resource *r = &dev->resource[i];
1347 if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) ||
1348 !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
1352 while (b && !r->parent) {
1353 assign_fixed_resource_on_bus(b, r);
1359 void __pci_bus_assign_resources(const struct pci_bus *bus,
1360 struct list_head *realloc_head,
1361 struct list_head *fail_head)
1364 struct pci_dev *dev;
1366 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1368 list_for_each_entry(dev, &bus->devices, bus_list) {
1369 pdev_assign_fixed_resources(dev);
1371 b = dev->subordinate;
1375 __pci_bus_assign_resources(b, realloc_head, fail_head);
1377 switch (dev->hdr_type) {
1378 case PCI_HEADER_TYPE_BRIDGE:
1379 if (!pci_is_enabled(dev))
1380 pci_setup_bridge(b);
1383 case PCI_HEADER_TYPE_CARDBUS:
1384 pci_setup_cardbus(b);
1388 pci_info(dev, "not setting up bridge for bus %04x:%02x\n",
1389 pci_domain_nr(b), b->number);
1395 void pci_bus_assign_resources(const struct pci_bus *bus)
1397 __pci_bus_assign_resources(bus, NULL, NULL);
1399 EXPORT_SYMBOL(pci_bus_assign_resources);
1401 static void pci_claim_device_resources(struct pci_dev *dev)
1405 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
1406 struct resource *r = &dev->resource[i];
1408 if (!r->flags || r->parent)
1411 pci_claim_resource(dev, i);
1415 static void pci_claim_bridge_resources(struct pci_dev *dev)
1419 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
1420 struct resource *r = &dev->resource[i];
1422 if (!r->flags || r->parent)
1425 pci_claim_bridge_resource(dev, i);
1429 static void pci_bus_allocate_dev_resources(struct pci_bus *b)
1431 struct pci_dev *dev;
1432 struct pci_bus *child;
1434 list_for_each_entry(dev, &b->devices, bus_list) {
1435 pci_claim_device_resources(dev);
1437 child = dev->subordinate;
1439 pci_bus_allocate_dev_resources(child);
1443 static void pci_bus_allocate_resources(struct pci_bus *b)
1445 struct pci_bus *child;
1448 * Carry out a depth-first search on the PCI bus tree to allocate
1449 * bridge apertures. Read the programmed bridge bases and
1450 * recursively claim the respective bridge resources.
1453 pci_read_bridge_bases(b);
1454 pci_claim_bridge_resources(b->self);
1457 list_for_each_entry(child, &b->children, node)
1458 pci_bus_allocate_resources(child);
1461 void pci_bus_claim_resources(struct pci_bus *b)
1463 pci_bus_allocate_resources(b);
1464 pci_bus_allocate_dev_resources(b);
1466 EXPORT_SYMBOL(pci_bus_claim_resources);
1468 static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1469 struct list_head *add_head,
1470 struct list_head *fail_head)
1474 pdev_assign_resources_sorted((struct pci_dev *)bridge,
1475 add_head, fail_head);
1477 b = bridge->subordinate;
1481 __pci_bus_assign_resources(b, add_head, fail_head);
1483 switch (bridge->class >> 8) {
1484 case PCI_CLASS_BRIDGE_PCI:
1485 pci_setup_bridge(b);
1488 case PCI_CLASS_BRIDGE_CARDBUS:
1489 pci_setup_cardbus(b);
1493 pci_info(bridge, "not setting up bridge for bus %04x:%02x\n",
1494 pci_domain_nr(b), b->number);
1499 #define PCI_RES_TYPE_MASK \
1500 (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\
1503 static void pci_bridge_release_resources(struct pci_bus *bus,
1506 struct pci_dev *dev = bus->self;
1508 unsigned old_flags = 0;
1509 struct resource *b_res;
1512 b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1515 * 1. If IO port assignment fails, release bridge IO port.
1516 * 2. If non pref MMIO assignment fails, release bridge nonpref MMIO.
1517 * 3. If 64bit pref MMIO assignment fails, and bridge pref is 64bit,
1518 * release bridge pref MMIO.
1519 * 4. If pref MMIO assignment fails, and bridge pref is 32bit,
1520 * release bridge pref MMIO.
1521 * 5. If pref MMIO assignment fails, and bridge pref is not
1522 * assigned, release bridge nonpref MMIO.
1524 if (type & IORESOURCE_IO)
1526 else if (!(type & IORESOURCE_PREFETCH))
1528 else if ((type & IORESOURCE_MEM_64) &&
1529 (b_res[2].flags & IORESOURCE_MEM_64))
1531 else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
1532 (b_res[2].flags & IORESOURCE_PREFETCH))
1542 /* If there are children, release them all */
1543 release_child_resources(r);
1544 if (!release_resource(r)) {
1545 type = old_flags = r->flags & PCI_RES_TYPE_MASK;
1546 pci_info(dev, "resource %d %pR released\n",
1547 PCI_BRIDGE_RESOURCES + idx, r);
1548 /* Keep the old size */
1549 r->end = resource_size(r) - 1;
1553 /* Avoiding touch the one without PREF */
1554 if (type & IORESOURCE_PREFETCH)
1555 type = IORESOURCE_PREFETCH;
1556 __pci_setup_bridge(bus, type);
1557 /* For next child res under same bridge */
1558 r->flags = old_flags;
1568 * Try to release PCI bridge resources from leaf bridge, so we can allocate
1569 * a larger window later.
1571 static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1573 enum release_type rel_type)
1575 struct pci_dev *dev;
1576 bool is_leaf_bridge = true;
1578 list_for_each_entry(dev, &bus->devices, bus_list) {
1579 struct pci_bus *b = dev->subordinate;
1583 is_leaf_bridge = false;
1585 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1588 if (rel_type == whole_subtree)
1589 pci_bus_release_bridge_resources(b, type,
1593 if (pci_is_root_bus(bus))
1596 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1599 if ((rel_type == whole_subtree) || is_leaf_bridge)
1600 pci_bridge_release_resources(bus, type);
1603 static void pci_bus_dump_res(struct pci_bus *bus)
1605 struct resource *res;
1608 pci_bus_for_each_resource(bus, res, i) {
1609 if (!res || !res->end || !res->flags)
1612 dev_info(&bus->dev, "resource %d %pR\n", i, res);
1616 static void pci_bus_dump_resources(struct pci_bus *bus)
1619 struct pci_dev *dev;
1622 pci_bus_dump_res(bus);
1624 list_for_each_entry(dev, &bus->devices, bus_list) {
1625 b = dev->subordinate;
1629 pci_bus_dump_resources(b);
1633 static int pci_bus_get_depth(struct pci_bus *bus)
1636 struct pci_bus *child_bus;
1638 list_for_each_entry(child_bus, &bus->children, node) {
1641 ret = pci_bus_get_depth(child_bus);
1642 if (ret + 1 > depth)
1650 * -1: undefined, will auto detect later
1651 * 0: disabled by user
1652 * 1: disabled by auto detect
1653 * 2: enabled by user
1654 * 3: enabled by auto detect
1664 static enum enable_type pci_realloc_enable = undefined;
1665 void __init pci_realloc_get_opt(char *str)
1667 if (!strncmp(str, "off", 3))
1668 pci_realloc_enable = user_disabled;
1669 else if (!strncmp(str, "on", 2))
1670 pci_realloc_enable = user_enabled;
1672 static bool pci_realloc_enabled(enum enable_type enable)
1674 return enable >= user_enabled;
1677 #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1678 static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1681 bool *unassigned = data;
1683 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1684 struct resource *r = &dev->resource[i + PCI_IOV_RESOURCES];
1685 struct pci_bus_region region;
1687 /* Not assigned or rejected by kernel? */
1691 pcibios_resource_to_bus(dev->bus, ®ion, r);
1692 if (!region.start) {
1694 return 1; /* Return early from pci_walk_bus() */
1701 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1702 enum enable_type enable_local)
1704 bool unassigned = false;
1705 struct pci_host_bridge *host;
1707 if (enable_local != undefined)
1708 return enable_local;
1710 host = pci_find_host_bridge(bus);
1711 if (host->preserve_config)
1712 return auto_disabled;
1714 pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1716 return auto_enabled;
1718 return enable_local;
1721 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1722 enum enable_type enable_local)
1724 return enable_local;
1729 * First try will not touch PCI bridge res.
1730 * Second and later try will clear small leaf bridge res.
1731 * Will stop till to the max depth if can not find good one.
1733 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1735 LIST_HEAD(realloc_head);
1736 /* List of resources that want additional resources */
1737 struct list_head *add_list = NULL;
1738 int tried_times = 0;
1739 enum release_type rel_type = leaf_only;
1740 LIST_HEAD(fail_head);
1741 struct pci_dev_resource *fail_res;
1742 int pci_try_num = 1;
1743 enum enable_type enable_local;
1745 /* Don't realloc if asked to do so */
1746 enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1747 if (pci_realloc_enabled(enable_local)) {
1748 int max_depth = pci_bus_get_depth(bus);
1750 pci_try_num = max_depth + 1;
1751 dev_info(&bus->dev, "max bus depth: %d pci_try_num: %d\n",
1752 max_depth, pci_try_num);
1757 * Last try will use add_list, otherwise will try good to have as must
1758 * have, so can realloc parent bridge resource
1760 if (tried_times + 1 == pci_try_num)
1761 add_list = &realloc_head;
1763 * Depth first, calculate sizes and alignments of all subordinate buses.
1765 __pci_bus_size_bridges(bus, add_list);
1767 /* Depth last, allocate resources and update the hardware. */
1768 __pci_bus_assign_resources(bus, add_list, &fail_head);
1770 BUG_ON(!list_empty(add_list));
1773 /* Any device complain? */
1774 if (list_empty(&fail_head))
1777 if (tried_times >= pci_try_num) {
1778 if (enable_local == undefined)
1779 dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1780 else if (enable_local == auto_enabled)
1781 dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1783 free_list(&fail_head);
1787 dev_info(&bus->dev, "No. %d try to assign unassigned res\n",
1790 /* Third times and later will not check if it is leaf */
1791 if ((tried_times + 1) > 2)
1792 rel_type = whole_subtree;
1795 * Try to release leaf bridge's resources that doesn't fit resource of
1796 * child device under that bridge.
1798 list_for_each_entry(fail_res, &fail_head, list)
1799 pci_bus_release_bridge_resources(fail_res->dev->bus,
1800 fail_res->flags & PCI_RES_TYPE_MASK,
1803 /* Restore size and flags */
1804 list_for_each_entry(fail_res, &fail_head, list) {
1805 struct resource *res = fail_res->res;
1807 res->start = fail_res->start;
1808 res->end = fail_res->end;
1809 res->flags = fail_res->flags;
1810 if (fail_res->dev->subordinate)
1813 free_list(&fail_head);
1818 /* Dump the resource on buses */
1819 pci_bus_dump_resources(bus);
1822 void __init pci_assign_unassigned_resources(void)
1824 struct pci_bus *root_bus;
1826 list_for_each_entry(root_bus, &pci_root_buses, node) {
1827 pci_assign_unassigned_root_bus_resources(root_bus);
1829 /* Make sure the root bridge has a companion ACPI device */
1830 if (ACPI_HANDLE(root_bus->bridge))
1831 acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge));
1835 static void extend_bridge_window(struct pci_dev *bridge, struct resource *res,
1836 struct list_head *add_list,
1837 resource_size_t available)
1839 struct pci_dev_resource *dev_res;
1844 if (resource_size(res) >= available)
1847 dev_res = res_to_dev_res(add_list, res);
1851 /* Is there room to extend the window? */
1852 if (available - resource_size(res) <= dev_res->add_size)
1855 dev_res->add_size = available - resource_size(res);
1856 pci_dbg(bridge, "bridge window %pR extended by %pa\n", res,
1857 &dev_res->add_size);
1860 static void pci_bus_distribute_available_resources(struct pci_bus *bus,
1861 struct list_head *add_list,
1862 resource_size_t available_io,
1863 resource_size_t available_mmio,
1864 resource_size_t available_mmio_pref)
1866 resource_size_t remaining_io, remaining_mmio, remaining_mmio_pref;
1867 unsigned int normal_bridges = 0, hotplug_bridges = 0;
1868 struct resource *io_res, *mmio_res, *mmio_pref_res;
1869 struct pci_dev *dev, *bridge = bus->self;
1871 io_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
1872 mmio_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
1873 mmio_pref_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
1876 * Update additional resource list (add_list) to fill all the
1877 * extra resource space available for this port except the space
1878 * calculated in __pci_bus_size_bridges() which covers all the
1879 * devices currently connected to the port and below.
1881 extend_bridge_window(bridge, io_res, add_list, available_io);
1882 extend_bridge_window(bridge, mmio_res, add_list, available_mmio);
1883 extend_bridge_window(bridge, mmio_pref_res, add_list,
1884 available_mmio_pref);
1887 * Calculate how many hotplug bridges and normal bridges there
1888 * are on this bus. We will distribute the additional available
1889 * resources between hotplug bridges.
1891 for_each_pci_bridge(dev, bus) {
1892 if (dev->is_hotplug_bridge)
1899 * There is only one bridge on the bus so it gets all available
1900 * resources which it can then distribute to the possible hotplug
1903 if (hotplug_bridges + normal_bridges == 1) {
1904 dev = list_first_entry(&bus->devices, struct pci_dev, bus_list);
1905 if (dev->subordinate) {
1906 pci_bus_distribute_available_resources(dev->subordinate,
1907 add_list, available_io, available_mmio,
1908 available_mmio_pref);
1913 if (hotplug_bridges == 0)
1917 * Calculate the total amount of extra resource space we can
1918 * pass to bridges below this one. This is basically the
1919 * extra space reduced by the minimal required space for the
1920 * non-hotplug bridges.
1922 remaining_io = available_io;
1923 remaining_mmio = available_mmio;
1924 remaining_mmio_pref = available_mmio_pref;
1926 for_each_pci_bridge(dev, bus) {
1927 const struct resource *res;
1929 if (dev->is_hotplug_bridge)
1933 * Reduce the available resource space by what the
1934 * bridge and devices below it occupy.
1936 res = &dev->resource[PCI_BRIDGE_RESOURCES + 0];
1937 if (!res->parent && available_io > resource_size(res))
1938 remaining_io -= resource_size(res);
1940 res = &dev->resource[PCI_BRIDGE_RESOURCES + 1];
1941 if (!res->parent && available_mmio > resource_size(res))
1942 remaining_mmio -= resource_size(res);
1944 res = &dev->resource[PCI_BRIDGE_RESOURCES + 2];
1945 if (!res->parent && available_mmio_pref > resource_size(res))
1946 remaining_mmio_pref -= resource_size(res);
1950 * Go over devices on this bus and distribute the remaining
1951 * resource space between hotplug bridges.
1953 for_each_pci_bridge(dev, bus) {
1954 resource_size_t align, io, mmio, mmio_pref;
1957 b = dev->subordinate;
1958 if (!b || !dev->is_hotplug_bridge)
1962 * Distribute available extra resources equally between
1963 * hotplug-capable downstream ports taking alignment into
1966 align = pci_resource_alignment(bridge, io_res);
1967 io = div64_ul(available_io, hotplug_bridges);
1968 io = min(ALIGN(io, align), remaining_io);
1971 align = pci_resource_alignment(bridge, mmio_res);
1972 mmio = div64_ul(available_mmio, hotplug_bridges);
1973 mmio = min(ALIGN(mmio, align), remaining_mmio);
1974 remaining_mmio -= mmio;
1976 align = pci_resource_alignment(bridge, mmio_pref_res);
1977 mmio_pref = div64_ul(available_mmio_pref, hotplug_bridges);
1978 mmio_pref = min(ALIGN(mmio_pref, align), remaining_mmio_pref);
1979 remaining_mmio_pref -= mmio_pref;
1981 pci_bus_distribute_available_resources(b, add_list, io, mmio,
1986 static void pci_bridge_distribute_available_resources(struct pci_dev *bridge,
1987 struct list_head *add_list)
1989 resource_size_t available_io, available_mmio, available_mmio_pref;
1990 const struct resource *res;
1992 if (!bridge->is_hotplug_bridge)
1995 /* Take the initial extra resources from the hotplug port */
1996 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
1997 available_io = resource_size(res);
1998 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
1999 available_mmio = resource_size(res);
2000 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
2001 available_mmio_pref = resource_size(res);
2003 pci_bus_distribute_available_resources(bridge->subordinate,
2004 add_list, available_io,
2006 available_mmio_pref);
2009 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
2011 struct pci_bus *parent = bridge->subordinate;
2012 /* List of resources that want additional resources */
2013 LIST_HEAD(add_list);
2015 int tried_times = 0;
2016 LIST_HEAD(fail_head);
2017 struct pci_dev_resource *fail_res;
2021 __pci_bus_size_bridges(parent, &add_list);
2024 * Distribute remaining resources (if any) equally between hotplug
2025 * bridges below. This makes it possible to extend the hierarchy
2026 * later without running out of resources.
2028 pci_bridge_distribute_available_resources(bridge, &add_list);
2030 __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
2031 BUG_ON(!list_empty(&add_list));
2034 if (list_empty(&fail_head))
2037 if (tried_times >= 2) {
2038 /* Still fail, don't need to try more */
2039 free_list(&fail_head);
2043 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
2047 * Try to release leaf bridge's resources that aren't big enough
2048 * to contain child device resources.
2050 list_for_each_entry(fail_res, &fail_head, list)
2051 pci_bus_release_bridge_resources(fail_res->dev->bus,
2052 fail_res->flags & PCI_RES_TYPE_MASK,
2055 /* Restore size and flags */
2056 list_for_each_entry(fail_res, &fail_head, list) {
2057 struct resource *res = fail_res->res;
2059 res->start = fail_res->start;
2060 res->end = fail_res->end;
2061 res->flags = fail_res->flags;
2062 if (fail_res->dev->subordinate)
2065 free_list(&fail_head);
2070 retval = pci_reenable_device(bridge);
2072 pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
2073 pci_set_master(bridge);
2075 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
2077 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
2079 struct pci_dev_resource *dev_res;
2080 struct pci_dev *next;
2087 down_read(&pci_bus_sem);
2089 /* Walk to the root hub, releasing bridge BARs when possible */
2093 for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
2095 struct resource *res = &bridge->resource[i];
2097 if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
2100 /* Ignore BARs which are still in use */
2104 ret = add_to_list(&saved, bridge, res, 0, 0);
2108 pci_info(bridge, "BAR %d: releasing %pR\n",
2112 release_resource(res);
2117 if (i == PCI_BRIDGE_RESOURCE_END)
2120 next = bridge->bus ? bridge->bus->self : NULL;
2123 if (list_empty(&saved)) {
2124 up_read(&pci_bus_sem);
2128 __pci_bus_size_bridges(bridge->subordinate, &added);
2129 __pci_bridge_assign_resources(bridge, &added, &failed);
2130 BUG_ON(!list_empty(&added));
2132 if (!list_empty(&failed)) {
2137 list_for_each_entry(dev_res, &saved, list) {
2138 /* Skip the bridge we just assigned resources for */
2139 if (bridge == dev_res->dev)
2142 bridge = dev_res->dev;
2143 pci_setup_bridge(bridge->subordinate);
2147 up_read(&pci_bus_sem);
2151 /* Restore size and flags */
2152 list_for_each_entry(dev_res, &failed, list) {
2153 struct resource *res = dev_res->res;
2155 res->start = dev_res->start;
2156 res->end = dev_res->end;
2157 res->flags = dev_res->flags;
2161 /* Revert to the old configuration */
2162 list_for_each_entry(dev_res, &saved, list) {
2163 struct resource *res = dev_res->res;
2165 bridge = dev_res->dev;
2166 i = res - bridge->resource;
2168 res->start = dev_res->start;
2169 res->end = dev_res->end;
2170 res->flags = dev_res->flags;
2172 pci_claim_resource(bridge, i);
2173 pci_setup_bridge(bridge->subordinate);
2176 up_read(&pci_bus_sem);
2181 void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
2183 struct pci_dev *dev;
2184 /* List of resources that want additional resources */
2185 LIST_HEAD(add_list);
2187 down_read(&pci_bus_sem);
2188 for_each_pci_bridge(dev, bus)
2189 if (pci_has_subordinate(dev))
2190 __pci_bus_size_bridges(dev->subordinate, &add_list);
2191 up_read(&pci_bus_sem);
2192 __pci_bus_assign_resources(bus, &add_list, NULL);
2193 BUG_ON(!list_empty(&add_list));
2195 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);