1 // SPDX-License-Identifier: GPL-2.0
3 * Support routines for initializing a PCI subsystem
5 * Extruded from code written by
6 * Dave Rusling (david.rusling@reo.mts.dec.com)
7 * David Mosberger (davidm@cs.arizona.edu)
8 * David Miller (davem@redhat.com)
10 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
11 * PCI-PCI bridges cleanup, sorted resource allocation.
12 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13 * Converted to allocation in 3 passes, which gives
14 * tighter packing. Prefetchable range support.
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/errno.h>
22 #include <linux/ioport.h>
23 #include <linux/cache.h>
24 #include <linux/slab.h>
25 #include <linux/acpi.h>
28 unsigned int pci_flags;
30 struct pci_dev_resource {
31 struct list_head list;
34 resource_size_t start;
36 resource_size_t add_size;
37 resource_size_t min_align;
41 static void free_list(struct list_head *head)
43 struct pci_dev_resource *dev_res, *tmp;
45 list_for_each_entry_safe(dev_res, tmp, head, list) {
46 list_del(&dev_res->list);
52 * add_to_list() - Add a new resource tracker to the list
53 * @head: Head of the list
54 * @dev: Device to which the resource belongs
55 * @res: Resource to be tracked
56 * @add_size: Additional size to be optionally added to the resource
58 static int add_to_list(struct list_head *head, struct pci_dev *dev,
59 struct resource *res, resource_size_t add_size,
60 resource_size_t min_align)
62 struct pci_dev_resource *tmp;
64 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
70 tmp->start = res->start;
72 tmp->flags = res->flags;
73 tmp->add_size = add_size;
74 tmp->min_align = min_align;
76 list_add(&tmp->list, head);
81 static void remove_from_list(struct list_head *head, struct resource *res)
83 struct pci_dev_resource *dev_res, *tmp;
85 list_for_each_entry_safe(dev_res, tmp, head, list) {
86 if (dev_res->res == res) {
87 list_del(&dev_res->list);
94 static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
97 struct pci_dev_resource *dev_res;
99 list_for_each_entry(dev_res, head, list) {
100 if (dev_res->res == res)
107 static resource_size_t get_res_add_size(struct list_head *head,
108 struct resource *res)
110 struct pci_dev_resource *dev_res;
112 dev_res = res_to_dev_res(head, res);
113 return dev_res ? dev_res->add_size : 0;
116 static resource_size_t get_res_add_align(struct list_head *head,
117 struct resource *res)
119 struct pci_dev_resource *dev_res;
121 dev_res = res_to_dev_res(head, res);
122 return dev_res ? dev_res->min_align : 0;
126 /* Sort resources by alignment */
127 static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
131 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
133 struct pci_dev_resource *dev_res, *tmp;
134 resource_size_t r_align;
137 r = &dev->resource[i];
139 if (r->flags & IORESOURCE_PCI_FIXED)
142 if (!(r->flags) || r->parent)
145 r_align = pci_resource_alignment(dev, r);
147 pci_warn(dev, "BAR %d: %pR has bogus alignment\n",
152 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
154 panic("pdev_sort_resources(): kmalloc() failed!\n");
158 /* Fallback is smallest one or list is empty */
160 list_for_each_entry(dev_res, head, list) {
161 resource_size_t align;
163 align = pci_resource_alignment(dev_res->dev,
166 if (r_align > align) {
171 /* Insert it just before n */
172 list_add_tail(&tmp->list, n);
176 static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head)
178 u16 class = dev->class >> 8;
180 /* Don't touch classless devices or host bridges or IOAPICs */
181 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
184 /* Don't touch IOAPIC devices already enabled by firmware */
185 if (class == PCI_CLASS_SYSTEM_PIC) {
187 pci_read_config_word(dev, PCI_COMMAND, &command);
188 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
192 pdev_sort_resources(dev, head);
195 static inline void reset_resource(struct resource *res)
203 * reassign_resources_sorted() - Satisfy any additional resource requests
205 * @realloc_head: Head of the list tracking requests requiring
206 * additional resources
207 * @head: Head of the list tracking requests with allocated
210 * Walk through each element of the realloc_head and try to procure additional
211 * resources for the element, provided the element is in the head list.
213 static void reassign_resources_sorted(struct list_head *realloc_head,
214 struct list_head *head)
216 struct resource *res;
217 struct pci_dev_resource *add_res, *tmp;
218 struct pci_dev_resource *dev_res;
219 resource_size_t add_size, align;
222 list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
223 bool found_match = false;
226 /* Skip resource that has been reset */
230 /* Skip this resource if not found in head list */
231 list_for_each_entry(dev_res, head, list) {
232 if (dev_res->res == res) {
237 if (!found_match) /* Just skip */
240 idx = res - &add_res->dev->resource[0];
241 add_size = add_res->add_size;
242 align = add_res->min_align;
243 if (!resource_size(res)) {
245 res->end = res->start + add_size - 1;
246 if (pci_assign_resource(add_res->dev, idx))
249 res->flags |= add_res->flags &
250 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
251 if (pci_reassign_resource(add_res->dev, idx,
253 pci_info(add_res->dev, "failed to add %llx res[%d]=%pR\n",
254 (unsigned long long) add_size, idx,
258 list_del(&add_res->list);
264 * assign_requested_resources_sorted() - Satisfy resource requests
266 * @head: Head of the list tracking requests for resources
267 * @fail_head: Head of the list tracking requests that could not be
270 * Satisfy resource requests of each element in the list. Add requests that
271 * could not be satisfied to the failed_list.
273 static void assign_requested_resources_sorted(struct list_head *head,
274 struct list_head *fail_head)
276 struct resource *res;
277 struct pci_dev_resource *dev_res;
280 list_for_each_entry(dev_res, head, list) {
282 idx = res - &dev_res->dev->resource[0];
283 if (resource_size(res) &&
284 pci_assign_resource(dev_res->dev, idx)) {
287 * If the failed resource is a ROM BAR and
288 * it will be enabled later, don't add it
291 if (!((idx == PCI_ROM_RESOURCE) &&
292 (!(res->flags & IORESOURCE_ROM_ENABLE))))
293 add_to_list(fail_head,
303 static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
305 struct pci_dev_resource *fail_res;
306 unsigned long mask = 0;
308 /* Check failed type */
309 list_for_each_entry(fail_res, fail_head, list)
310 mask |= fail_res->flags;
313 * One pref failed resource will set IORESOURCE_MEM, as we can
314 * allocate pref in non-pref range. Will release all assigned
315 * non-pref sibling resources according to that bit.
317 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
320 static bool pci_need_to_release(unsigned long mask, struct resource *res)
322 if (res->flags & IORESOURCE_IO)
323 return !!(mask & IORESOURCE_IO);
325 /* Check pref at first */
326 if (res->flags & IORESOURCE_PREFETCH) {
327 if (mask & IORESOURCE_PREFETCH)
329 /* Count pref if its parent is non-pref */
330 else if ((mask & IORESOURCE_MEM) &&
331 !(res->parent->flags & IORESOURCE_PREFETCH))
337 if (res->flags & IORESOURCE_MEM)
338 return !!(mask & IORESOURCE_MEM);
340 return false; /* Should not get here */
343 static void __assign_resources_sorted(struct list_head *head,
344 struct list_head *realloc_head,
345 struct list_head *fail_head)
348 * Should not assign requested resources at first. They could be
349 * adjacent, so later reassign can not reallocate them one by one in
350 * parent resource window.
352 * Try to assign requested + add_size at beginning. If could do that,
353 * could get out early. If could not do that, we still try to assign
354 * requested at first, then try to reassign add_size for some resources.
356 * Separate three resource type checking if we need to release
357 * assigned resource after requested + add_size try.
359 * 1. If IO port assignment fails, will release assigned IO
361 * 2. If pref MMIO assignment fails, release assigned pref
362 * MMIO. If assigned pref MMIO's parent is non-pref MMIO
363 * and non-pref MMIO assignment fails, will release that
364 * assigned pref MMIO.
365 * 3. If non-pref MMIO assignment fails or pref MMIO
366 * assignment fails, will release assigned non-pref MMIO.
368 LIST_HEAD(save_head);
369 LIST_HEAD(local_fail_head);
370 struct pci_dev_resource *save_res;
371 struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
372 unsigned long fail_type;
373 resource_size_t add_align, align;
375 /* Check if optional add_size is there */
376 if (!realloc_head || list_empty(realloc_head))
377 goto requested_and_reassign;
379 /* Save original start, end, flags etc at first */
380 list_for_each_entry(dev_res, head, list) {
381 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
382 free_list(&save_head);
383 goto requested_and_reassign;
387 /* Update res in head list with add_size in realloc_head list */
388 list_for_each_entry_safe(dev_res, tmp_res, head, list) {
389 dev_res->res->end += get_res_add_size(realloc_head,
393 * There are two kinds of additional resources in the list:
394 * 1. bridge resource -- IORESOURCE_STARTALIGN
395 * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN
396 * Here just fix the additional alignment for bridge
398 if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
401 add_align = get_res_add_align(realloc_head, dev_res->res);
404 * The "head" list is sorted by alignment so resources with
405 * bigger alignment will be assigned first. After we
406 * change the alignment of a dev_res in "head" list, we
407 * need to reorder the list by alignment to make it
410 if (add_align > dev_res->res->start) {
411 resource_size_t r_size = resource_size(dev_res->res);
413 dev_res->res->start = add_align;
414 dev_res->res->end = add_align + r_size - 1;
416 list_for_each_entry(dev_res2, head, list) {
417 align = pci_resource_alignment(dev_res2->dev,
419 if (add_align > align) {
420 list_move_tail(&dev_res->list,
429 /* Try updated head list with add_size added */
430 assign_requested_resources_sorted(head, &local_fail_head);
432 /* All assigned with add_size? */
433 if (list_empty(&local_fail_head)) {
434 /* Remove head list from realloc_head list */
435 list_for_each_entry(dev_res, head, list)
436 remove_from_list(realloc_head, dev_res->res);
437 free_list(&save_head);
442 /* Check failed type */
443 fail_type = pci_fail_res_type_mask(&local_fail_head);
444 /* Remove not need to be released assigned res from head list etc */
445 list_for_each_entry_safe(dev_res, tmp_res, head, list)
446 if (dev_res->res->parent &&
447 !pci_need_to_release(fail_type, dev_res->res)) {
448 /* Remove it from realloc_head list */
449 remove_from_list(realloc_head, dev_res->res);
450 remove_from_list(&save_head, dev_res->res);
451 list_del(&dev_res->list);
455 free_list(&local_fail_head);
456 /* Release assigned resource */
457 list_for_each_entry(dev_res, head, list)
458 if (dev_res->res->parent)
459 release_resource(dev_res->res);
460 /* Restore start/end/flags from saved list */
461 list_for_each_entry(save_res, &save_head, list) {
462 struct resource *res = save_res->res;
464 res->start = save_res->start;
465 res->end = save_res->end;
466 res->flags = save_res->flags;
468 free_list(&save_head);
470 requested_and_reassign:
471 /* Satisfy the must-have resource requests */
472 assign_requested_resources_sorted(head, fail_head);
474 /* Try to satisfy any additional optional resource requests */
476 reassign_resources_sorted(realloc_head, head);
480 static void pdev_assign_resources_sorted(struct pci_dev *dev,
481 struct list_head *add_head,
482 struct list_head *fail_head)
486 __dev_sort_resources(dev, &head);
487 __assign_resources_sorted(&head, add_head, fail_head);
491 static void pbus_assign_resources_sorted(const struct pci_bus *bus,
492 struct list_head *realloc_head,
493 struct list_head *fail_head)
498 list_for_each_entry(dev, &bus->devices, bus_list)
499 __dev_sort_resources(dev, &head);
501 __assign_resources_sorted(&head, realloc_head, fail_head);
504 void pci_setup_cardbus(struct pci_bus *bus)
506 struct pci_dev *bridge = bus->self;
507 struct resource *res;
508 struct pci_bus_region region;
510 pci_info(bridge, "CardBus bridge to %pR\n",
513 res = bus->resource[0];
514 pcibios_resource_to_bus(bridge->bus, ®ion, res);
515 if (res->flags & IORESOURCE_IO) {
517 * The IO resource is allocated a range twice as large as it
518 * would normally need. This allows us to set both IO regs.
520 pci_info(bridge, " bridge window %pR\n", res);
521 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
523 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
527 res = bus->resource[1];
528 pcibios_resource_to_bus(bridge->bus, ®ion, res);
529 if (res->flags & IORESOURCE_IO) {
530 pci_info(bridge, " bridge window %pR\n", res);
531 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
533 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
537 res = bus->resource[2];
538 pcibios_resource_to_bus(bridge->bus, ®ion, res);
539 if (res->flags & IORESOURCE_MEM) {
540 pci_info(bridge, " bridge window %pR\n", res);
541 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
543 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
547 res = bus->resource[3];
548 pcibios_resource_to_bus(bridge->bus, ®ion, res);
549 if (res->flags & IORESOURCE_MEM) {
550 pci_info(bridge, " bridge window %pR\n", res);
551 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
553 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
557 EXPORT_SYMBOL(pci_setup_cardbus);
560 * Initialize bridges with base/limit values we have collected. PCI-to-PCI
561 * Bridge Architecture Specification rev. 1.1 (1998) requires that if there
562 * are no I/O ports or memory behind the bridge, the corresponding range
563 * must be turned off by writing base value greater than limit to the
564 * bridge's base/limit registers.
566 * Note: care must be taken when updating I/O base/limit registers of
567 * bridges which support 32-bit I/O. This update requires two config space
568 * writes, so it's quite possible that an I/O window of the bridge will
569 * have some undesirable address (e.g. 0) after the first write. Ditto
570 * 64-bit prefetchable MMIO.
572 static void pci_setup_bridge_io(struct pci_dev *bridge)
574 struct resource *res;
575 struct pci_bus_region region;
576 unsigned long io_mask;
577 u8 io_base_lo, io_limit_lo;
581 io_mask = PCI_IO_RANGE_MASK;
582 if (bridge->io_window_1k)
583 io_mask = PCI_IO_1K_RANGE_MASK;
585 /* Set up the top and bottom of the PCI I/O segment for this bus */
586 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
587 pcibios_resource_to_bus(bridge->bus, ®ion, res);
588 if (res->flags & IORESOURCE_IO) {
589 pci_read_config_word(bridge, PCI_IO_BASE, &l);
590 io_base_lo = (region.start >> 8) & io_mask;
591 io_limit_lo = (region.end >> 8) & io_mask;
592 l = ((u16) io_limit_lo << 8) | io_base_lo;
593 /* Set up upper 16 bits of I/O base/limit */
594 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
595 pci_info(bridge, " bridge window %pR\n", res);
597 /* Clear upper 16 bits of I/O base/limit */
601 /* Temporarily disable the I/O range before updating PCI_IO_BASE */
602 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
603 /* Update lower 16 bits of I/O base/limit */
604 pci_write_config_word(bridge, PCI_IO_BASE, l);
605 /* Update upper 16 bits of I/O base/limit */
606 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
609 static void pci_setup_bridge_mmio(struct pci_dev *bridge)
611 struct resource *res;
612 struct pci_bus_region region;
615 /* Set up the top and bottom of the PCI Memory segment for this bus */
616 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
617 pcibios_resource_to_bus(bridge->bus, ®ion, res);
618 if (res->flags & IORESOURCE_MEM) {
619 l = (region.start >> 16) & 0xfff0;
620 l |= region.end & 0xfff00000;
621 pci_info(bridge, " bridge window %pR\n", res);
625 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
628 static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
630 struct resource *res;
631 struct pci_bus_region region;
635 * Clear out the upper 32 bits of PREF limit. If
636 * PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables
637 * PREF range, which is ok.
639 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
641 /* Set up PREF base/limit */
643 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
644 pcibios_resource_to_bus(bridge->bus, ®ion, res);
645 if (res->flags & IORESOURCE_PREFETCH) {
646 l = (region.start >> 16) & 0xfff0;
647 l |= region.end & 0xfff00000;
648 if (res->flags & IORESOURCE_MEM_64) {
649 bu = upper_32_bits(region.start);
650 lu = upper_32_bits(region.end);
652 pci_info(bridge, " bridge window %pR\n", res);
656 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
658 /* Set the upper 32 bits of PREF base & limit */
659 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
660 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
663 static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
665 struct pci_dev *bridge = bus->self;
667 pci_info(bridge, "PCI bridge to %pR\n",
670 if (type & IORESOURCE_IO)
671 pci_setup_bridge_io(bridge);
673 if (type & IORESOURCE_MEM)
674 pci_setup_bridge_mmio(bridge);
676 if (type & IORESOURCE_PREFETCH)
677 pci_setup_bridge_mmio_pref(bridge);
679 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
682 void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
686 void pci_setup_bridge(struct pci_bus *bus)
688 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
691 pcibios_setup_bridge(bus, type);
692 __pci_setup_bridge(bus, type);
696 int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
698 if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
701 if (pci_claim_resource(bridge, i) == 0)
702 return 0; /* Claimed the window */
704 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
707 if (!pci_bus_clip_resource(bridge, i))
708 return -EINVAL; /* Clipping didn't change anything */
710 switch (i - PCI_BRIDGE_RESOURCES) {
712 pci_setup_bridge_io(bridge);
715 pci_setup_bridge_mmio(bridge);
718 pci_setup_bridge_mmio_pref(bridge);
724 if (pci_claim_resource(bridge, i) == 0)
725 return 0; /* Claimed a smaller window */
731 * Check whether the bridge supports optional I/O and prefetchable memory
732 * ranges. If not, the respective base/limit registers must be read-only
735 static void pci_bridge_check_ranges(struct pci_bus *bus)
737 struct pci_dev *bridge = bus->self;
738 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
740 b_res[1].flags |= IORESOURCE_MEM;
742 if (bridge->io_window)
743 b_res[0].flags |= IORESOURCE_IO;
745 if (bridge->pref_window) {
746 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
747 if (bridge->pref_64_window) {
748 b_res[2].flags |= IORESOURCE_MEM_64;
749 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
755 * Helper function for sizing routines: find first available bus resource
756 * of a given type. Note: we intentionally skip the bus resources which
757 * have already been assigned (that is, have non-NULL parent resource).
759 static struct resource *find_free_bus_resource(struct pci_bus *bus,
760 unsigned long type_mask,
766 pci_bus_for_each_resource(bus, r, i) {
767 if (r == &ioport_resource || r == &iomem_resource)
769 if (r && (r->flags & type_mask) == type && !r->parent)
775 static resource_size_t calculate_iosize(resource_size_t size,
776 resource_size_t min_size,
777 resource_size_t size1,
778 resource_size_t add_size,
779 resource_size_t children_add_size,
780 resource_size_t old_size,
781 resource_size_t align)
788 * To be fixed in 2.5: we should have sort of HAVE_ISA flag in the
791 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
792 size = (size & 0xff) + ((size & ~0xffUL) << 2);
798 size = ALIGN(max(size, add_size) + children_add_size, align);
802 static resource_size_t calculate_memsize(resource_size_t size,
803 resource_size_t min_size,
804 resource_size_t add_size,
805 resource_size_t children_add_size,
806 resource_size_t old_size,
807 resource_size_t align)
816 size = ALIGN(max(size, add_size) + children_add_size, align);
820 resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
826 #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
827 #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
828 #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
830 static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type)
832 resource_size_t align = 1, arch_align;
834 if (type & IORESOURCE_MEM)
835 align = PCI_P2P_DEFAULT_MEM_ALIGN;
836 else if (type & IORESOURCE_IO) {
838 * Per spec, I/O windows are 4K-aligned, but some bridges have
839 * an extension to support 1K alignment.
841 if (bus->self->io_window_1k)
842 align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
844 align = PCI_P2P_DEFAULT_IO_ALIGN;
847 arch_align = pcibios_window_alignment(bus, type);
848 return max(align, arch_align);
852 * pbus_size_io() - Size the I/O window of a given bus
855 * @min_size: The minimum I/O window that must be allocated
856 * @add_size: Additional optional I/O window
857 * @realloc_head: Track the additional I/O window on this list
859 * Sizing the I/O windows of the PCI-PCI bridge is trivial, since these
860 * windows have 1K or 4K granularity and the I/O ranges of non-bridge PCI
861 * devices are limited to 256 bytes. We must be careful with the ISA
864 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
865 resource_size_t add_size,
866 struct list_head *realloc_head)
869 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO,
871 resource_size_t size = 0, size0 = 0, size1 = 0;
872 resource_size_t children_add_size = 0;
873 resource_size_t min_align, align;
878 min_align = window_alignment(bus, IORESOURCE_IO);
879 list_for_each_entry(dev, &bus->devices, bus_list) {
882 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
883 struct resource *r = &dev->resource[i];
884 unsigned long r_size;
886 if (r->parent || !(r->flags & IORESOURCE_IO))
888 r_size = resource_size(r);
891 /* Might be re-aligned for ISA */
896 align = pci_resource_alignment(dev, r);
897 if (align > min_align)
901 children_add_size += get_res_add_size(realloc_head, r);
905 size0 = calculate_iosize(size, min_size, size1, 0, 0,
906 resource_size(b_res), min_align);
907 size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
908 calculate_iosize(size, min_size, size1, add_size, children_add_size,
909 resource_size(b_res), min_align);
910 if (!size0 && !size1) {
911 if (b_res->start || b_res->end)
912 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
913 b_res, &bus->busn_res);
918 b_res->start = min_align;
919 b_res->end = b_res->start + size0 - 1;
920 b_res->flags |= IORESOURCE_STARTALIGN;
921 if (size1 > size0 && realloc_head) {
922 add_to_list(realloc_head, bus->self, b_res, size1-size0,
924 pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n",
925 b_res, &bus->busn_res,
926 (unsigned long long) size1 - size0);
930 static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
933 resource_size_t align = 0;
934 resource_size_t min_align = 0;
937 for (order = 0; order <= max_order; order++) {
938 resource_size_t align1 = 1;
940 align1 <<= (order + 20);
944 else if (ALIGN(align + min_align, min_align) < align1)
945 min_align = align1 >> 1;
946 align += aligns[order];
953 * pbus_size_mem() - Size the memory window of a given bus
956 * @mask: Mask the resource flag, then compare it with type
957 * @type: The type of free resource from bridge
958 * @type2: Second match type
959 * @type3: Third match type
960 * @min_size: The minimum memory window that must be allocated
961 * @add_size: Additional optional memory window
962 * @realloc_head: Track the additional memory window on this list
964 * Calculate the size of the bus and minimal alignment which guarantees
965 * that all child resources fit in this size.
967 * Return -ENOSPC if there's no available bus resource of the desired
968 * type. Otherwise, set the bus resource start/end to indicate the
969 * required size, add things to realloc_head (if supplied), and return 0.
971 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
972 unsigned long type, unsigned long type2,
973 unsigned long type3, resource_size_t min_size,
974 resource_size_t add_size,
975 struct list_head *realloc_head)
978 resource_size_t min_align, align, size, size0, size1;
979 resource_size_t aligns[18]; /* Alignments from 1MB to 128GB */
980 int order, max_order;
981 struct resource *b_res = find_free_bus_resource(bus,
982 mask | IORESOURCE_PREFETCH, type);
983 resource_size_t children_add_size = 0;
984 resource_size_t children_add_align = 0;
985 resource_size_t add_align = 0;
990 memset(aligns, 0, sizeof(aligns));
994 list_for_each_entry(dev, &bus->devices, bus_list) {
997 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
998 struct resource *r = &dev->resource[i];
999 resource_size_t r_size;
1001 if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
1002 ((r->flags & mask) != type &&
1003 (r->flags & mask) != type2 &&
1004 (r->flags & mask) != type3))
1006 r_size = resource_size(r);
1007 #ifdef CONFIG_PCI_IOV
1008 /* Put SRIOV requested res to the optional list */
1009 if (realloc_head && i >= PCI_IOV_RESOURCES &&
1010 i <= PCI_IOV_RESOURCE_END) {
1011 add_align = max(pci_resource_alignment(dev, r), add_align);
1012 r->end = r->start - 1;
1013 add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */);
1014 children_add_size += r_size;
1019 * aligns[0] is for 1MB (since bridge memory
1020 * windows are always at least 1MB aligned), so
1021 * keep "order" from being negative for smaller
1024 align = pci_resource_alignment(dev, r);
1025 order = __ffs(align) - 20;
1028 if (order >= ARRAY_SIZE(aligns)) {
1029 pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
1030 i, r, (unsigned long long) align);
1034 size += max(r_size, align);
1036 * Exclude ranges with size > align from calculation of
1039 if (r_size <= align)
1040 aligns[order] += align;
1041 if (order > max_order)
1045 children_add_size += get_res_add_size(realloc_head, r);
1046 children_add_align = get_res_add_align(realloc_head, r);
1047 add_align = max(add_align, children_add_align);
1052 min_align = calculate_mem_align(aligns, max_order);
1053 min_align = max(min_align, window_alignment(bus, b_res->flags));
1054 size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), min_align);
1055 add_align = max(min_align, add_align);
1056 size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
1057 calculate_memsize(size, min_size, add_size, children_add_size,
1058 resource_size(b_res), add_align);
1059 if (!size0 && !size1) {
1060 if (b_res->start || b_res->end)
1061 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
1062 b_res, &bus->busn_res);
1066 b_res->start = min_align;
1067 b_res->end = size0 + min_align - 1;
1068 b_res->flags |= IORESOURCE_STARTALIGN;
1069 if (size1 > size0 && realloc_head) {
1070 add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
1071 pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
1072 b_res, &bus->busn_res,
1073 (unsigned long long) (size1 - size0),
1074 (unsigned long long) add_align);
1079 unsigned long pci_cardbus_resource_alignment(struct resource *res)
1081 if (res->flags & IORESOURCE_IO)
1082 return pci_cardbus_io_size;
1083 if (res->flags & IORESOURCE_MEM)
1084 return pci_cardbus_mem_size;
1088 static void pci_bus_size_cardbus(struct pci_bus *bus,
1089 struct list_head *realloc_head)
1091 struct pci_dev *bridge = bus->self;
1092 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
1093 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1096 if (b_res[0].parent)
1097 goto handle_b_res_1;
1099 * Reserve some resources for CardBus. We reserve a fixed amount
1100 * of bus space for CardBus bridges.
1102 b_res[0].start = pci_cardbus_io_size;
1103 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
1104 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1106 b_res[0].end -= pci_cardbus_io_size;
1107 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1108 pci_cardbus_io_size);
1112 if (b_res[1].parent)
1113 goto handle_b_res_2;
1114 b_res[1].start = pci_cardbus_io_size;
1115 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
1116 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1118 b_res[1].end -= pci_cardbus_io_size;
1119 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
1120 pci_cardbus_io_size);
1124 /* MEM1 must not be pref MMIO */
1125 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1126 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1127 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1128 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1129 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1132 /* Check whether prefetchable memory is supported by this bridge. */
1133 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1134 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1135 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1136 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1137 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1140 if (b_res[2].parent)
1141 goto handle_b_res_3;
1143 * If we have prefetchable memory support, allocate two regions.
1144 * Otherwise, allocate one region of twice the size.
1146 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1147 b_res[2].start = pci_cardbus_mem_size;
1148 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
1149 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1150 IORESOURCE_STARTALIGN;
1152 b_res[2].end -= pci_cardbus_mem_size;
1153 add_to_list(realloc_head, bridge, b_res+2,
1154 pci_cardbus_mem_size, pci_cardbus_mem_size);
1157 /* Reduce that to half */
1158 b_res_3_size = pci_cardbus_mem_size;
1162 if (b_res[3].parent)
1164 b_res[3].start = pci_cardbus_mem_size;
1165 b_res[3].end = b_res[3].start + b_res_3_size - 1;
1166 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1168 b_res[3].end -= b_res_3_size;
1169 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
1170 pci_cardbus_mem_size);
1177 void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1179 struct pci_dev *dev;
1180 unsigned long mask, prefmask, type2 = 0, type3 = 0;
1181 resource_size_t additional_mem_size = 0, additional_io_size = 0;
1182 struct resource *b_res;
1185 list_for_each_entry(dev, &bus->devices, bus_list) {
1186 struct pci_bus *b = dev->subordinate;
1190 switch (dev->hdr_type) {
1191 case PCI_HEADER_TYPE_CARDBUS:
1192 pci_bus_size_cardbus(b, realloc_head);
1195 case PCI_HEADER_TYPE_BRIDGE:
1197 __pci_bus_size_bridges(b, realloc_head);
1203 if (pci_is_root_bus(bus))
1206 switch (bus->self->hdr_type) {
1207 case PCI_HEADER_TYPE_CARDBUS:
1208 /* Don't size CardBuses yet */
1211 case PCI_HEADER_TYPE_BRIDGE:
1212 pci_bridge_check_ranges(bus);
1213 if (bus->self->is_hotplug_bridge) {
1214 additional_io_size = pci_hotplug_io_size;
1215 additional_mem_size = pci_hotplug_mem_size;
1219 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1220 additional_io_size, realloc_head);
1223 * If there's a 64-bit prefetchable MMIO window, compute
1224 * the size required to put all 64-bit prefetchable
1227 b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES];
1228 mask = IORESOURCE_MEM;
1229 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1230 if (b_res[2].flags & IORESOURCE_MEM_64) {
1231 prefmask |= IORESOURCE_MEM_64;
1232 ret = pbus_size_mem(bus, prefmask, prefmask,
1234 realloc_head ? 0 : additional_mem_size,
1235 additional_mem_size, realloc_head);
1238 * If successful, all non-prefetchable resources
1239 * and any 32-bit prefetchable resources will go in
1240 * the non-prefetchable window.
1244 type2 = prefmask & ~IORESOURCE_MEM_64;
1245 type3 = prefmask & ~IORESOURCE_PREFETCH;
1250 * If there is no 64-bit prefetchable window, compute the
1251 * size required to put all prefetchable resources in the
1252 * 32-bit prefetchable window (if there is one).
1255 prefmask &= ~IORESOURCE_MEM_64;
1256 ret = pbus_size_mem(bus, prefmask, prefmask,
1258 realloc_head ? 0 : additional_mem_size,
1259 additional_mem_size, realloc_head);
1262 * If successful, only non-prefetchable resources
1263 * will go in the non-prefetchable window.
1268 additional_mem_size += additional_mem_size;
1270 type2 = type3 = IORESOURCE_MEM;
1274 * Compute the size required to put everything else in the
1275 * non-prefetchable window. This includes:
1277 * - all non-prefetchable resources
1278 * - 32-bit prefetchable resources if there's a 64-bit
1279 * prefetchable window or no prefetchable window at all
1280 * - 64-bit prefetchable resources if there's no prefetchable
1283 * Note that the strategy in __pci_assign_resource() must match
1284 * that used here. Specifically, we cannot put a 32-bit
1285 * prefetchable resource in a 64-bit prefetchable window.
1287 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1288 realloc_head ? 0 : additional_mem_size,
1289 additional_mem_size, realloc_head);
1294 void pci_bus_size_bridges(struct pci_bus *bus)
1296 __pci_bus_size_bridges(bus, NULL);
1298 EXPORT_SYMBOL(pci_bus_size_bridges);
1300 static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
1303 struct resource *parent_r;
1304 unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM |
1305 IORESOURCE_PREFETCH;
1307 pci_bus_for_each_resource(b, parent_r, i) {
1311 if ((r->flags & mask) == (parent_r->flags & mask) &&
1312 resource_contains(parent_r, r))
1313 request_resource(parent_r, r);
1318 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they are
1319 * skipped by pbus_assign_resources_sorted().
1321 static void pdev_assign_fixed_resources(struct pci_dev *dev)
1325 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1327 struct resource *r = &dev->resource[i];
1329 if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) ||
1330 !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
1334 while (b && !r->parent) {
1335 assign_fixed_resource_on_bus(b, r);
1341 void __pci_bus_assign_resources(const struct pci_bus *bus,
1342 struct list_head *realloc_head,
1343 struct list_head *fail_head)
1346 struct pci_dev *dev;
1348 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1350 list_for_each_entry(dev, &bus->devices, bus_list) {
1351 pdev_assign_fixed_resources(dev);
1353 b = dev->subordinate;
1357 __pci_bus_assign_resources(b, realloc_head, fail_head);
1359 switch (dev->hdr_type) {
1360 case PCI_HEADER_TYPE_BRIDGE:
1361 if (!pci_is_enabled(dev))
1362 pci_setup_bridge(b);
1365 case PCI_HEADER_TYPE_CARDBUS:
1366 pci_setup_cardbus(b);
1370 pci_info(dev, "not setting up bridge for bus %04x:%02x\n",
1371 pci_domain_nr(b), b->number);
1377 void pci_bus_assign_resources(const struct pci_bus *bus)
1379 __pci_bus_assign_resources(bus, NULL, NULL);
1381 EXPORT_SYMBOL(pci_bus_assign_resources);
1383 static void pci_claim_device_resources(struct pci_dev *dev)
1387 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
1388 struct resource *r = &dev->resource[i];
1390 if (!r->flags || r->parent)
1393 pci_claim_resource(dev, i);
1397 static void pci_claim_bridge_resources(struct pci_dev *dev)
1401 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
1402 struct resource *r = &dev->resource[i];
1404 if (!r->flags || r->parent)
1407 pci_claim_bridge_resource(dev, i);
1411 static void pci_bus_allocate_dev_resources(struct pci_bus *b)
1413 struct pci_dev *dev;
1414 struct pci_bus *child;
1416 list_for_each_entry(dev, &b->devices, bus_list) {
1417 pci_claim_device_resources(dev);
1419 child = dev->subordinate;
1421 pci_bus_allocate_dev_resources(child);
1425 static void pci_bus_allocate_resources(struct pci_bus *b)
1427 struct pci_bus *child;
1430 * Carry out a depth-first search on the PCI bus tree to allocate
1431 * bridge apertures. Read the programmed bridge bases and
1432 * recursively claim the respective bridge resources.
1435 pci_read_bridge_bases(b);
1436 pci_claim_bridge_resources(b->self);
1439 list_for_each_entry(child, &b->children, node)
1440 pci_bus_allocate_resources(child);
1443 void pci_bus_claim_resources(struct pci_bus *b)
1445 pci_bus_allocate_resources(b);
1446 pci_bus_allocate_dev_resources(b);
1448 EXPORT_SYMBOL(pci_bus_claim_resources);
1450 static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1451 struct list_head *add_head,
1452 struct list_head *fail_head)
1456 pdev_assign_resources_sorted((struct pci_dev *)bridge,
1457 add_head, fail_head);
1459 b = bridge->subordinate;
1463 __pci_bus_assign_resources(b, add_head, fail_head);
1465 switch (bridge->class >> 8) {
1466 case PCI_CLASS_BRIDGE_PCI:
1467 pci_setup_bridge(b);
1470 case PCI_CLASS_BRIDGE_CARDBUS:
1471 pci_setup_cardbus(b);
1475 pci_info(bridge, "not setting up bridge for bus %04x:%02x\n",
1476 pci_domain_nr(b), b->number);
1481 #define PCI_RES_TYPE_MASK \
1482 (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\
1485 static void pci_bridge_release_resources(struct pci_bus *bus,
1488 struct pci_dev *dev = bus->self;
1490 unsigned old_flags = 0;
1491 struct resource *b_res;
1494 b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1497 * 1. If IO port assignment fails, release bridge IO port.
1498 * 2. If non pref MMIO assignment fails, release bridge nonpref MMIO.
1499 * 3. If 64bit pref MMIO assignment fails, and bridge pref is 64bit,
1500 * release bridge pref MMIO.
1501 * 4. If pref MMIO assignment fails, and bridge pref is 32bit,
1502 * release bridge pref MMIO.
1503 * 5. If pref MMIO assignment fails, and bridge pref is not
1504 * assigned, release bridge nonpref MMIO.
1506 if (type & IORESOURCE_IO)
1508 else if (!(type & IORESOURCE_PREFETCH))
1510 else if ((type & IORESOURCE_MEM_64) &&
1511 (b_res[2].flags & IORESOURCE_MEM_64))
1513 else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
1514 (b_res[2].flags & IORESOURCE_PREFETCH))
1524 /* If there are children, release them all */
1525 release_child_resources(r);
1526 if (!release_resource(r)) {
1527 type = old_flags = r->flags & PCI_RES_TYPE_MASK;
1528 pci_info(dev, "resource %d %pR released\n",
1529 PCI_BRIDGE_RESOURCES + idx, r);
1530 /* Keep the old size */
1531 r->end = resource_size(r) - 1;
1535 /* Avoiding touch the one without PREF */
1536 if (type & IORESOURCE_PREFETCH)
1537 type = IORESOURCE_PREFETCH;
1538 __pci_setup_bridge(bus, type);
1539 /* For next child res under same bridge */
1540 r->flags = old_flags;
1550 * Try to release PCI bridge resources from leaf bridge, so we can allocate
1551 * a larger window later.
1553 static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1555 enum release_type rel_type)
1557 struct pci_dev *dev;
1558 bool is_leaf_bridge = true;
1560 list_for_each_entry(dev, &bus->devices, bus_list) {
1561 struct pci_bus *b = dev->subordinate;
1565 is_leaf_bridge = false;
1567 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1570 if (rel_type == whole_subtree)
1571 pci_bus_release_bridge_resources(b, type,
1575 if (pci_is_root_bus(bus))
1578 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1581 if ((rel_type == whole_subtree) || is_leaf_bridge)
1582 pci_bridge_release_resources(bus, type);
1585 static void pci_bus_dump_res(struct pci_bus *bus)
1587 struct resource *res;
1590 pci_bus_for_each_resource(bus, res, i) {
1591 if (!res || !res->end || !res->flags)
1594 dev_info(&bus->dev, "resource %d %pR\n", i, res);
1598 static void pci_bus_dump_resources(struct pci_bus *bus)
1601 struct pci_dev *dev;
1604 pci_bus_dump_res(bus);
1606 list_for_each_entry(dev, &bus->devices, bus_list) {
1607 b = dev->subordinate;
1611 pci_bus_dump_resources(b);
1615 static int pci_bus_get_depth(struct pci_bus *bus)
1618 struct pci_bus *child_bus;
1620 list_for_each_entry(child_bus, &bus->children, node) {
1623 ret = pci_bus_get_depth(child_bus);
1624 if (ret + 1 > depth)
1632 * -1: undefined, will auto detect later
1633 * 0: disabled by user
1634 * 1: disabled by auto detect
1635 * 2: enabled by user
1636 * 3: enabled by auto detect
1646 static enum enable_type pci_realloc_enable = undefined;
1647 void __init pci_realloc_get_opt(char *str)
1649 if (!strncmp(str, "off", 3))
1650 pci_realloc_enable = user_disabled;
1651 else if (!strncmp(str, "on", 2))
1652 pci_realloc_enable = user_enabled;
1654 static bool pci_realloc_enabled(enum enable_type enable)
1656 return enable >= user_enabled;
1659 #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1660 static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1663 bool *unassigned = data;
1665 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1666 struct resource *r = &dev->resource[i + PCI_IOV_RESOURCES];
1667 struct pci_bus_region region;
1669 /* Not assigned or rejected by kernel? */
1673 pcibios_resource_to_bus(dev->bus, ®ion, r);
1674 if (!region.start) {
1676 return 1; /* Return early from pci_walk_bus() */
1683 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1684 enum enable_type enable_local)
1686 bool unassigned = false;
1687 struct pci_host_bridge *host;
1689 if (enable_local != undefined)
1690 return enable_local;
1692 host = pci_find_host_bridge(bus);
1693 if (host->preserve_config)
1694 return auto_disabled;
1696 pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1698 return auto_enabled;
1700 return enable_local;
1703 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1704 enum enable_type enable_local)
1706 return enable_local;
1711 * First try will not touch PCI bridge res.
1712 * Second and later try will clear small leaf bridge res.
1713 * Will stop till to the max depth if can not find good one.
1715 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1717 LIST_HEAD(realloc_head);
1718 /* List of resources that want additional resources */
1719 struct list_head *add_list = NULL;
1720 int tried_times = 0;
1721 enum release_type rel_type = leaf_only;
1722 LIST_HEAD(fail_head);
1723 struct pci_dev_resource *fail_res;
1724 int pci_try_num = 1;
1725 enum enable_type enable_local;
1727 /* Don't realloc if asked to do so */
1728 enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1729 if (pci_realloc_enabled(enable_local)) {
1730 int max_depth = pci_bus_get_depth(bus);
1732 pci_try_num = max_depth + 1;
1733 dev_info(&bus->dev, "max bus depth: %d pci_try_num: %d\n",
1734 max_depth, pci_try_num);
1739 * Last try will use add_list, otherwise will try good to have as must
1740 * have, so can realloc parent bridge resource
1742 if (tried_times + 1 == pci_try_num)
1743 add_list = &realloc_head;
1745 * Depth first, calculate sizes and alignments of all subordinate buses.
1747 __pci_bus_size_bridges(bus, add_list);
1749 /* Depth last, allocate resources and update the hardware. */
1750 __pci_bus_assign_resources(bus, add_list, &fail_head);
1752 BUG_ON(!list_empty(add_list));
1755 /* Any device complain? */
1756 if (list_empty(&fail_head))
1759 if (tried_times >= pci_try_num) {
1760 if (enable_local == undefined)
1761 dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1762 else if (enable_local == auto_enabled)
1763 dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1765 free_list(&fail_head);
1769 dev_info(&bus->dev, "No. %d try to assign unassigned res\n",
1772 /* Third times and later will not check if it is leaf */
1773 if ((tried_times + 1) > 2)
1774 rel_type = whole_subtree;
1777 * Try to release leaf bridge's resources that doesn't fit resource of
1778 * child device under that bridge.
1780 list_for_each_entry(fail_res, &fail_head, list)
1781 pci_bus_release_bridge_resources(fail_res->dev->bus,
1782 fail_res->flags & PCI_RES_TYPE_MASK,
1785 /* Restore size and flags */
1786 list_for_each_entry(fail_res, &fail_head, list) {
1787 struct resource *res = fail_res->res;
1789 res->start = fail_res->start;
1790 res->end = fail_res->end;
1791 res->flags = fail_res->flags;
1792 if (fail_res->dev->subordinate)
1795 free_list(&fail_head);
1800 /* Dump the resource on buses */
1801 pci_bus_dump_resources(bus);
1804 void __init pci_assign_unassigned_resources(void)
1806 struct pci_bus *root_bus;
1808 list_for_each_entry(root_bus, &pci_root_buses, node) {
1809 pci_assign_unassigned_root_bus_resources(root_bus);
1811 /* Make sure the root bridge has a companion ACPI device */
1812 if (ACPI_HANDLE(root_bus->bridge))
1813 acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge));
1817 static void extend_bridge_window(struct pci_dev *bridge, struct resource *res,
1818 struct list_head *add_list,
1819 resource_size_t available)
1821 struct pci_dev_resource *dev_res;
1826 if (resource_size(res) >= available)
1829 dev_res = res_to_dev_res(add_list, res);
1833 /* Is there room to extend the window? */
1834 if (available - resource_size(res) <= dev_res->add_size)
1837 dev_res->add_size = available - resource_size(res);
1838 pci_dbg(bridge, "bridge window %pR extended by %pa\n", res,
1839 &dev_res->add_size);
1842 static void pci_bus_distribute_available_resources(struct pci_bus *bus,
1843 struct list_head *add_list,
1844 resource_size_t available_io,
1845 resource_size_t available_mmio,
1846 resource_size_t available_mmio_pref)
1848 resource_size_t remaining_io, remaining_mmio, remaining_mmio_pref;
1849 unsigned int normal_bridges = 0, hotplug_bridges = 0;
1850 struct resource *io_res, *mmio_res, *mmio_pref_res;
1851 struct pci_dev *dev, *bridge = bus->self;
1853 io_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
1854 mmio_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
1855 mmio_pref_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
1858 * Update additional resource list (add_list) to fill all the
1859 * extra resource space available for this port except the space
1860 * calculated in __pci_bus_size_bridges() which covers all the
1861 * devices currently connected to the port and below.
1863 extend_bridge_window(bridge, io_res, add_list, available_io);
1864 extend_bridge_window(bridge, mmio_res, add_list, available_mmio);
1865 extend_bridge_window(bridge, mmio_pref_res, add_list,
1866 available_mmio_pref);
1869 * Calculate how many hotplug bridges and normal bridges there
1870 * are on this bus. We will distribute the additional available
1871 * resources between hotplug bridges.
1873 for_each_pci_bridge(dev, bus) {
1874 if (dev->is_hotplug_bridge)
1881 * There is only one bridge on the bus so it gets all available
1882 * resources which it can then distribute to the possible hotplug
1885 if (hotplug_bridges + normal_bridges == 1) {
1886 dev = list_first_entry(&bus->devices, struct pci_dev, bus_list);
1887 if (dev->subordinate) {
1888 pci_bus_distribute_available_resources(dev->subordinate,
1889 add_list, available_io, available_mmio,
1890 available_mmio_pref);
1895 if (hotplug_bridges == 0)
1899 * Calculate the total amount of extra resource space we can
1900 * pass to bridges below this one. This is basically the
1901 * extra space reduced by the minimal required space for the
1902 * non-hotplug bridges.
1904 remaining_io = available_io;
1905 remaining_mmio = available_mmio;
1906 remaining_mmio_pref = available_mmio_pref;
1908 for_each_pci_bridge(dev, bus) {
1909 const struct resource *res;
1911 if (dev->is_hotplug_bridge)
1915 * Reduce the available resource space by what the
1916 * bridge and devices below it occupy.
1918 res = &dev->resource[PCI_BRIDGE_RESOURCES + 0];
1919 if (!res->parent && available_io > resource_size(res))
1920 remaining_io -= resource_size(res);
1922 res = &dev->resource[PCI_BRIDGE_RESOURCES + 1];
1923 if (!res->parent && available_mmio > resource_size(res))
1924 remaining_mmio -= resource_size(res);
1926 res = &dev->resource[PCI_BRIDGE_RESOURCES + 2];
1927 if (!res->parent && available_mmio_pref > resource_size(res))
1928 remaining_mmio_pref -= resource_size(res);
1932 * Go over devices on this bus and distribute the remaining
1933 * resource space between hotplug bridges.
1935 for_each_pci_bridge(dev, bus) {
1936 resource_size_t align, io, mmio, mmio_pref;
1939 b = dev->subordinate;
1940 if (!b || !dev->is_hotplug_bridge)
1944 * Distribute available extra resources equally between
1945 * hotplug-capable downstream ports taking alignment into
1948 align = pci_resource_alignment(bridge, io_res);
1949 io = div64_ul(available_io, hotplug_bridges);
1950 io = min(ALIGN(io, align), remaining_io);
1953 align = pci_resource_alignment(bridge, mmio_res);
1954 mmio = div64_ul(available_mmio, hotplug_bridges);
1955 mmio = min(ALIGN(mmio, align), remaining_mmio);
1956 remaining_mmio -= mmio;
1958 align = pci_resource_alignment(bridge, mmio_pref_res);
1959 mmio_pref = div64_ul(available_mmio_pref, hotplug_bridges);
1960 mmio_pref = min(ALIGN(mmio_pref, align), remaining_mmio_pref);
1961 remaining_mmio_pref -= mmio_pref;
1963 pci_bus_distribute_available_resources(b, add_list, io, mmio,
1968 static void pci_bridge_distribute_available_resources(struct pci_dev *bridge,
1969 struct list_head *add_list)
1971 resource_size_t available_io, available_mmio, available_mmio_pref;
1972 const struct resource *res;
1974 if (!bridge->is_hotplug_bridge)
1977 /* Take the initial extra resources from the hotplug port */
1978 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
1979 available_io = resource_size(res);
1980 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
1981 available_mmio = resource_size(res);
1982 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
1983 available_mmio_pref = resource_size(res);
1985 pci_bus_distribute_available_resources(bridge->subordinate,
1986 add_list, available_io,
1988 available_mmio_pref);
1991 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1993 struct pci_bus *parent = bridge->subordinate;
1994 /* List of resources that want additional resources */
1995 LIST_HEAD(add_list);
1997 int tried_times = 0;
1998 LIST_HEAD(fail_head);
1999 struct pci_dev_resource *fail_res;
2003 __pci_bus_size_bridges(parent, &add_list);
2006 * Distribute remaining resources (if any) equally between hotplug
2007 * bridges below. This makes it possible to extend the hierarchy
2008 * later without running out of resources.
2010 pci_bridge_distribute_available_resources(bridge, &add_list);
2012 __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
2013 BUG_ON(!list_empty(&add_list));
2016 if (list_empty(&fail_head))
2019 if (tried_times >= 2) {
2020 /* Still fail, don't need to try more */
2021 free_list(&fail_head);
2025 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
2029 * Try to release leaf bridge's resources that aren't big enough
2030 * to contain child device resources.
2032 list_for_each_entry(fail_res, &fail_head, list)
2033 pci_bus_release_bridge_resources(fail_res->dev->bus,
2034 fail_res->flags & PCI_RES_TYPE_MASK,
2037 /* Restore size and flags */
2038 list_for_each_entry(fail_res, &fail_head, list) {
2039 struct resource *res = fail_res->res;
2041 res->start = fail_res->start;
2042 res->end = fail_res->end;
2043 res->flags = fail_res->flags;
2044 if (fail_res->dev->subordinate)
2047 free_list(&fail_head);
2052 retval = pci_reenable_device(bridge);
2054 pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
2055 pci_set_master(bridge);
2057 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
2059 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
2061 struct pci_dev_resource *dev_res;
2062 struct pci_dev *next;
2069 /* Walk to the root hub, releasing bridge BARs when possible */
2073 for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
2075 struct resource *res = &bridge->resource[i];
2077 if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
2080 /* Ignore BARs which are still in use */
2084 ret = add_to_list(&saved, bridge, res, 0, 0);
2088 pci_info(bridge, "BAR %d: releasing %pR\n",
2092 release_resource(res);
2097 if (i == PCI_BRIDGE_RESOURCE_END)
2100 next = bridge->bus ? bridge->bus->self : NULL;
2103 if (list_empty(&saved))
2106 __pci_bus_size_bridges(bridge->subordinate, &added);
2107 __pci_bridge_assign_resources(bridge, &added, &failed);
2108 BUG_ON(!list_empty(&added));
2110 if (!list_empty(&failed)) {
2115 list_for_each_entry(dev_res, &saved, list) {
2116 /* Skip the bridge we just assigned resources for */
2117 if (bridge == dev_res->dev)
2120 bridge = dev_res->dev;
2121 pci_setup_bridge(bridge->subordinate);
2128 /* Restore size and flags */
2129 list_for_each_entry(dev_res, &failed, list) {
2130 struct resource *res = dev_res->res;
2132 res->start = dev_res->start;
2133 res->end = dev_res->end;
2134 res->flags = dev_res->flags;
2138 /* Revert to the old configuration */
2139 list_for_each_entry(dev_res, &saved, list) {
2140 struct resource *res = dev_res->res;
2142 bridge = dev_res->dev;
2143 i = res - bridge->resource;
2145 res->start = dev_res->start;
2146 res->end = dev_res->end;
2147 res->flags = dev_res->flags;
2149 pci_claim_resource(bridge, i);
2150 pci_setup_bridge(bridge->subordinate);
2157 void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
2159 struct pci_dev *dev;
2160 /* List of resources that want additional resources */
2161 LIST_HEAD(add_list);
2163 down_read(&pci_bus_sem);
2164 for_each_pci_bridge(dev, bus)
2165 if (pci_has_subordinate(dev))
2166 __pci_bus_size_bridges(dev->subordinate, &add_list);
2167 up_read(&pci_bus_sem);
2168 __pci_bus_assign_resources(bus, &add_list, NULL);
2169 BUG_ON(!list_empty(&add_list));
2171 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);