drivers/phy/qualcomm/phy-qcom-qmp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_address.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/reset.h>
  21 #include <linux/slab.h>
  22
  23 #include <dt-bindings/phy/phy.h>
  24
  25 #include "phy-qcom-qmp.h"
  26
  27 /* QPHY_SW_RESET bit */
  28 #define SW_RESET                                BIT(0)
  29 /* QPHY_POWER_DOWN_CONTROL */
  30 #define SW_PWRDN                                BIT(0)
  31 #define REFCLK_DRV_DSBL                         BIT(1)
  32 /* QPHY_START_CONTROL bits */
  33 #define SERDES_START                            BIT(0)
  34 #define PCS_START                               BIT(1)
  35 #define PLL_READY_GATE_EN                       BIT(3)
  36 /* QPHY_PCS_STATUS bit */
  37 #define PHYSTATUS                               BIT(6)
  38 /* QPHY_COM_PCS_READY_STATUS bit */
  39 #define PCS_READY                               BIT(0)
  40
  41 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  42 /* DP PHY soft reset */
  43 #define SW_DPPHY_RESET                          BIT(0)
  44 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  45 #define SW_DPPHY_RESET_MUX                      BIT(1)
  46 /* USB3 PHY soft reset */
  47 #define SW_USB3PHY_RESET                        BIT(2)
  48 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  49 #define SW_USB3PHY_RESET_MUX                    BIT(3)
  50
  51 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  52 #define USB3_MODE                               BIT(0) /* enables USB3 mode */
  53 #define DP_MODE                                 BIT(1) /* enables DP mode */
  54
  55 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
  56 #define ARCVR_DTCT_EN                           BIT(0)
  57 #define ALFPS_DTCT_EN                           BIT(1)
  58 #define ARCVR_DTCT_EVENT_SEL                    BIT(4)
  59
  60 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
  61 #define IRQ_CLEAR                               BIT(0)
  62
  63 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
  64 #define RCVR_DETECT                             BIT(0)
  65
  66 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
  67 #define CLAMP_EN                                BIT(0) /* enables i/o clamp_n */
  68
  69 #define PHY_INIT_COMPLETE_TIMEOUT               1000
  70 #define POWER_DOWN_DELAY_US_MIN                 10
  71 #define POWER_DOWN_DELAY_US_MAX                 11
  72
  73 #define MAX_PROP_NAME                           32
  74
  75 /* Define the assumed distance between lanes for underspecified device trees. */
  76 #define QMP_PHY_LEGACY_LANE_STRIDE              0x400
  77
  78 struct qmp_phy_init_tbl {
  79         unsigned int offset;
  80         unsigned int val;
  81         /*
  82          * register part of layout ?
  83          * if yes, then offset gives index in the reg-layout
  84          */
  85         int in_layout;
  86 };
  87
  88 #define QMP_PHY_INIT_CFG(o, v)          \
  89         {                               \
  90                 .offset = o,            \
  91                 .val = v,               \
  92         }
  93
  94 #define QMP_PHY_INIT_CFG_L(o, v)        \
  95         {                               \
  96                 .offset = o,            \
  97                 .val = v,               \
  98                 .in_layout = 1,         \
  99         }
 100
 101 /* set of registers with offsets different per-PHY */
 102 enum qphy_reg_layout {
 103         /* Common block control registers */
 104         QPHY_COM_SW_RESET,
 105         QPHY_COM_POWER_DOWN_CONTROL,
 106         QPHY_COM_START_CONTROL,
 107         QPHY_COM_PCS_READY_STATUS,
 108         /* PCS registers */
 109         QPHY_PLL_LOCK_CHK_DLY_TIME,
 110         QPHY_FLL_CNTRL1,
 111         QPHY_FLL_CNTRL2,
 112         QPHY_FLL_CNT_VAL_L,
 113         QPHY_FLL_CNT_VAL_H_TOL,
 114         QPHY_FLL_MAN_CODE,
 115         QPHY_SW_RESET,
 116         QPHY_START_CTRL,
 117         QPHY_PCS_READY_STATUS,
 118         QPHY_PCS_AUTONOMOUS_MODE_CTRL,
 119         QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
 120         QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
 121 };
 122
 123 static const unsigned int pciephy_regs_layout[] = {
 124         [QPHY_COM_SW_RESET]             = 0x400,
 125         [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
 126         [QPHY_COM_START_CONTROL]        = 0x408,
 127         [QPHY_COM_PCS_READY_STATUS]     = 0x448,
 128         [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
 129         [QPHY_FLL_CNTRL1]               = 0xc4,
 130         [QPHY_FLL_CNTRL2]               = 0xc8,
 131         [QPHY_FLL_CNT_VAL_L]            = 0xcc,
 132         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
 133         [QPHY_FLL_MAN_CODE]             = 0xd4,
 134         [QPHY_SW_RESET]                 = 0x00,
 135         [QPHY_START_CTRL]               = 0x08,
 136         [QPHY_PCS_READY_STATUS]         = 0x174,
 137 };
 138
 139 static const unsigned int usb3phy_regs_layout[] = {
 140         [QPHY_FLL_CNTRL1]               = 0xc0,
 141         [QPHY_FLL_CNTRL2]               = 0xc4,
 142         [QPHY_FLL_CNT_VAL_L]            = 0xc8,
 143         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
 144         [QPHY_FLL_MAN_CODE]             = 0xd0,
 145         [QPHY_SW_RESET]                 = 0x00,
 146         [QPHY_START_CTRL]               = 0x08,
 147         [QPHY_PCS_READY_STATUS]         = 0x17c,
 148         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
 149         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
 150         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
 151 };
 152
 153 static const unsigned int qmp_v3_usb3phy_regs_layout[] = {
 154         [QPHY_SW_RESET]                 = 0x00,
 155         [QPHY_START_CTRL]               = 0x08,
 156         [QPHY_PCS_READY_STATUS]         = 0x174,
 157         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
 158         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
 159         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
 160 };
 161
 162 static const unsigned int sdm845_ufsphy_regs_layout[] = {
 163         [QPHY_START_CTRL]               = 0x00,
 164         [QPHY_PCS_READY_STATUS]         = 0x160,
 165 };
 166
 167 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
 168         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
 169         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 170         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 171         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 172         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
 173         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 174         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 175         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 176         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
 177         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 178         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 179         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 180         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
 181         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 182         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 183         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 184         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 185         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 186         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
 187         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
 188         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 189         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
 190         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 191         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
 192         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 193         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 194         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 195         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 196         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 197         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 198         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 199         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 200         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
 201         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 202         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 203         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 204         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
 205         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 206         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 207         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 208         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 209         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 210         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
 211 };
 212
 213 static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
 214         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 215         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 216 };
 217
 218 static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
 219         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 220         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
 221         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
 222         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 223         QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
 224         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 225         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
 226         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 227         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 228         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
 229 };
 230
 231 static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
 232         QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
 233         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
 234         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 235
 236         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
 237
 238         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
 239         QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
 240         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
 241         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
 242         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
 243 };
 244
 245 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
 246         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 247         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 248         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
 249         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 250         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 251         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 252         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 253         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 254         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 255         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 256         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 257         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 258         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 259         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 260         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 261         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 262         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 263         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
 264         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
 265         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
 266         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 267         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 268         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 269         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 270         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
 271         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 272         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
 273         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 274         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 275         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 276         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
 277         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 278         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 279         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 280         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 281         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 282         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 283         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 284         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 285         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 286         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 287         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 288 };
 289
 290 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
 291         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 292         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 293         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 294         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 295 };
 296
 297 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
 298         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 299         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
 300         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 301         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
 302         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 303         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 304         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 305         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 306         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 307         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
 308         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 309         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 310         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 311         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 312 };
 313
 314 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
 315         QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 316         QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 317         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 318         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 319         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 320         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 321         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 322         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 323         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
 324         QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 325 };
 326
 327 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
 328         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 329         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 330         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 331         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 332         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 333         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 334         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 335         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 336         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
 337         /* PLL and Loop filter settings */
 338         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 339         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 340         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 341         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 342         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 343         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 344         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 345         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 346         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 347         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 348         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 349         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 350         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 351         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 352         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 353         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 354         /* SSC settings */
 355         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 356         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 357         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 358         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 359         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 360         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 361         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 362 };
 363
 364 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
 365         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 366         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 367         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 368 };
 369
 370 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
 371         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 372         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 373         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 374         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 375         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
 376         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 377         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 378         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 379         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
 380         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 381 };
 382
 383 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
 384         /* FLL settings */
 385         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
 386         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
 387         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
 388         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
 389         QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
 390
 391         /* Lock Det settings */
 392         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
 393         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
 394         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
 395         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
 396 };
 397
 398 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
 399         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
 400         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 401         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
 402         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
 403         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
 404         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),
 405         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
 406         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
 407         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
 408         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
 409         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
 410         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
 411         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
 412         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 413         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
 414         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
 415         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 416         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
 417         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 418         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 419         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
 420         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
 421         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
 422         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 423         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
 424         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 425         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
 426         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 427         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 428         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
 429         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 430         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
 431         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),
 432         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
 433         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 434         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
 435         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
 436         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
 437         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 438         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 439         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 440         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),
 441 };
 442
 443 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
 444         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 445         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
 446         QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
 447         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 448 };
 449
 450 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
 451         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 452         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 453         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
 454         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
 455         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 456         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 457         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
 458         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
 459 };
 460
 461 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
 462         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
 463         QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
 464         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
 465         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
 466         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
 467         QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
 468         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
 469         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
 470         QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
 471         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
 472         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
 473         QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
 474         QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
 475 };
 476
 477 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
 478         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 479         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 480         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 481         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 482         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 483         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 484         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
 485         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 486         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 487         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 488         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 489         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 490         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 491         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 492         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 493         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 494         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 495         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 496         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 497         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 498         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 499         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 500         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 501         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 502         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 503         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 504         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 505         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 506         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 507         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 508         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 509         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 510         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 511         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 512         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 513         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 514 };
 515
 516 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
 517         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 518         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 519         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 520         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 521         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 522 };
 523
 524 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
 525         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 526         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 527         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 528         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 529         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 530         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 531         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 532         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 533         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 534 };
 535
 536 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
 537         /* FLL settings */
 538         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 539         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 540         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 541         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 542         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 543
 544         /* Lock Det settings */
 545         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 546         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 547         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 548         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 549
 550         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 551         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 552         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 553         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 554         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 555         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 556         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 557         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 558         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 559         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 560         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 561         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 562         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 563         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 564         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 565         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 566         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 567         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 568         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 569
 570         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 571         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 572         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 573         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 574         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 575         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 576         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 577         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 578         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 579         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 580         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 581 };
 582
 583 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
 584         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 585         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 586         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 587         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 588         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 589         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 590         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 591         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 592         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 593         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 594         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 595         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 596         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 597         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 598         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 599         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 600         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 601         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 602         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 603         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 604         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 605         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 606         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 607         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 608         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 609         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 610         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 611         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 612         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 613         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 614         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 615         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 616         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 617         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 618         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 619         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 620 };
 621
 622 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
 623         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 624         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 625         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
 626         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
 627         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 628 };
 629
 630 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
 631         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
 632         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
 633         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 634         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
 635         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 636         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 637         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 638         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 639         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 640         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
 641         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 642 };
 643
 644 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
 645         /* FLL settings */
 646         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 647         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 648         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 649         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 650         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 651
 652         /* Lock Det settings */
 653         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 654         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 655         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 656         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 657
 658         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 659         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 660         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 661         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
 662         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
 663         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
 664         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
 665         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 666         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 667         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 668         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 669         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 670         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 671         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 672         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 673         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 674         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 675         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 676         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 677
 678         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 679         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 680         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 681         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 682         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 683         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 684         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 685         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 686         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 687         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 688         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 689
 690         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
 691         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
 692 };
 693
 694 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
 695         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 696         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 697         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
 698         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 699         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 700         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
 701         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 702         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 703         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 704         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 705         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
 706         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 707         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
 708         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
 709         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
 710         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
 711         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 712         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 713         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 714         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 715         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 716         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 717         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
 718         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 719         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
 720         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
 721         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
 722         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
 723         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
 724         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
 725         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
 726         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 727         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
 728         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
 729         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
 730         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
 731
 732         /* Rate B */
 733         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
 734 };
 735
 736 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
 737         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 738         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
 739         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
 740 };
 741
 742 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
 743         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
 744         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
 745         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 746         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 747         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 748         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
 749         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 750         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 751         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
 752         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
 753         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
 754         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
 755         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 756         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
 757         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 758         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
 759 };
 760
 761 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
 762         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
 763         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
 764         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
 765         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
 766         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
 767         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
 768         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
 769         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
 770 };
 771
 772 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
 773         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 774         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 775         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 776         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
 777         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 778         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 779         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 780         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 781         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 782         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 783         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 784         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 785         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 786         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 787         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 788         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 789         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 790         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 791         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 792         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 793         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 794         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 795         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 796         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 797         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 798         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 799         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 800         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
 801         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 802         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
 803         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
 804         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 805         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 806         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 807         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 808         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 809         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 810         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 811 };
 812
 813 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
 814         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 815         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 816         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 817         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
 818 };
 819
 820 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
 821         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 822         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 823         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 824         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 825         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
 826         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 827         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
 828         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
 829         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 830         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
 831         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
 832         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
 833         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
 834         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
 835         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
 836         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
 837         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
 838 };
 839
 840 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
 841         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 842         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 843         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 844         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 845         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 846         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 847         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 848         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 849         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 850         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 851         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 852         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 853         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 854         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 855         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 856         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 857         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 858         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
 859         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 860         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 861         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 862         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 863         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
 864         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 865         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 866         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 867         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 868         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 869         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 870         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 871         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 872         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 873         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 874         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 875         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
 876         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 877         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 878         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 879 };
 880
 881
 882 /* struct qmp_phy_cfg - per-PHY initialization config */
 883 struct qmp_phy_cfg {
 884         /* phy-type - PCIE/UFS/USB */
 885         unsigned int type;
 886         /* number of lanes provided by phy */
 887         int nlanes;
 888
 889         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
 890         const struct qmp_phy_init_tbl *serdes_tbl;
 891         int serdes_tbl_num;
 892         const struct qmp_phy_init_tbl *tx_tbl;
 893         int tx_tbl_num;
 894         const struct qmp_phy_init_tbl *rx_tbl;
 895         int rx_tbl_num;
 896         const struct qmp_phy_init_tbl *pcs_tbl;
 897         int pcs_tbl_num;
 898
 899         /* clock ids to be requested */
 900         const char * const *clk_list;
 901         int num_clks;
 902         /* resets to be requested */
 903         const char * const *reset_list;
 904         int num_resets;
 905         /* regulators to be requested */
 906         const char * const *vreg_list;
 907         int num_vregs;
 908
 909         /* array of registers with different offsets */
 910         const unsigned int *regs;
 911
 912         unsigned int start_ctrl;
 913         unsigned int pwrdn_ctrl;
 914         unsigned int mask_pcs_ready;
 915         unsigned int mask_com_pcs_ready;
 916
 917         /* true, if PHY has a separate PHY_COM control block */
 918         bool has_phy_com_ctrl;
 919         /* true, if PHY has a reset for individual lanes */
 920         bool has_lane_rst;
 921         /* true, if PHY needs delay after POWER_DOWN */
 922         bool has_pwrdn_delay;
 923         /* power_down delay in usec */
 924         int pwrdn_delay_min;
 925         int pwrdn_delay_max;
 926
 927         /* true, if PHY has a separate DP_COM control block */
 928         bool has_phy_dp_com_ctrl;
 929         /* true, if PHY has secondary tx/rx lanes to be configured */
 930         bool is_dual_lane_phy;
 931
 932         /* true, if PCS block has no separate SW_RESET register */
 933         bool no_pcs_sw_reset;
 934 };
 935
 936 /**
 937  * struct qmp_phy - per-lane phy descriptor
 938  *
 939  * @phy: generic phy
 940  * @tx: iomapped memory space for lane's tx
 941  * @rx: iomapped memory space for lane's rx
 942  * @pcs: iomapped memory space for lane's pcs
 943  * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
 944  * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
 945  * @pcs_misc: iomapped memory space for lane's pcs_misc
 946  * @pipe_clk: pipe lock
 947  * @index: lane index
 948  * @qmp: QMP phy to which this lane belongs
 949  * @lane_rst: lane's reset controller
 950  */
 951 struct qmp_phy {
 952         struct phy *phy;
 953         void __iomem *tx;
 954         void __iomem *rx;
 955         void __iomem *pcs;
 956         void __iomem *tx2;
 957         void __iomem *rx2;
 958         void __iomem *pcs_misc;
 959         struct clk *pipe_clk;
 960         unsigned int index;
 961         struct qcom_qmp *qmp;
 962         struct reset_control *lane_rst;
 963 };
 964
 965 /**
 966  * struct qcom_qmp - structure holding QMP phy block attributes
 967  *
 968  * @dev: device
 969  * @serdes: iomapped memory space for phy's serdes
 970  * @dp_com: iomapped memory space for phy's dp_com control block
 971  *
 972  * @clks: array of clocks required by phy
 973  * @resets: array of resets required by phy
 974  * @vregs: regulator supplies bulk data
 975  *
 976  * @cfg: phy specific configuration
 977  * @phys: array of per-lane phy descriptors
 978  * @phy_mutex: mutex lock for PHY common block initialization
 979  * @init_count: phy common block initialization count
 980  * @phy_initialized: indicate if PHY has been initialized
 981  * @mode: current PHY mode
 982  * @ufs_reset: optional UFS PHY reset handle
 983  */
 984 struct qcom_qmp {
 985         struct device *dev;
 986         void __iomem *serdes;
 987         void __iomem *dp_com;
 988
 989         struct clk_bulk_data *clks;
 990         struct reset_control **resets;
 991         struct regulator_bulk_data *vregs;
 992
 993         const struct qmp_phy_cfg *cfg;
 994         struct qmp_phy **phys;
 995
 996         struct mutex phy_mutex;
 997         int init_count;
 998         bool phy_initialized;
 999         enum phy_mode mode;
1000
1001         struct reset_control *ufs_reset;
1002 };
1003
1004 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1005 {
1006         u32 reg;
1007
1008         reg = readl(base + offset);
1009         reg |= val;
1010         writel(reg, base + offset);
1011
1012         /* ensure that above write is through */
1013         readl(base + offset);
1014 }
1015
1016 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1017 {
1018         u32 reg;
1019
1020         reg = readl(base + offset);
1021         reg &= ~val;
1022         writel(reg, base + offset);
1023
1024         /* ensure that above write is through */
1025         readl(base + offset);
1026 }
1027
1028 /* list of clocks required by phy */
1029 static const char * const msm8996_phy_clk_l[] = {
1030         "aux", "cfg_ahb", "ref",
1031 };
1032
1033 static const char * const qmp_v3_phy_clk_l[] = {
1034         "aux", "cfg_ahb", "ref", "com_aux",
1035 };
1036
1037 static const char * const sdm845_ufs_phy_clk_l[] = {
1038         "ref", "ref_aux",
1039 };
1040
1041 /* list of resets */
1042 static const char * const msm8996_pciephy_reset_l[] = {
1043         "phy", "common", "cfg",
1044 };
1045
1046 static const char * const msm8996_usb3phy_reset_l[] = {
1047         "phy", "common",
1048 };
1049
1050 /* list of regulators */
1051 static const char * const qmp_phy_vreg_l[] = {
1052         "vdda-phy", "vdda-pll",
1053 };
1054
1055 static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
1056         .type                   = PHY_TYPE_PCIE,
1057         .nlanes                 = 3,
1058
1059         .serdes_tbl             = msm8996_pcie_serdes_tbl,
1060         .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
1061         .tx_tbl                 = msm8996_pcie_tx_tbl,
1062         .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
1063         .rx_tbl                 = msm8996_pcie_rx_tbl,
1064         .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
1065         .pcs_tbl                = msm8996_pcie_pcs_tbl,
1066         .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
1067         .clk_list               = msm8996_phy_clk_l,
1068         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1069         .reset_list             = msm8996_pciephy_reset_l,
1070         .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
1071         .vreg_list              = qmp_phy_vreg_l,
1072         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1073         .regs                   = pciephy_regs_layout,
1074
1075         .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
1076         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
1077         .mask_pcs_ready         = PHYSTATUS,
1078         .mask_com_pcs_ready     = PCS_READY,
1079
1080         .has_phy_com_ctrl       = true,
1081         .has_lane_rst           = true,
1082         .has_pwrdn_delay        = true,
1083         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1084         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1085 };
1086
1087 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
1088         .type                   = PHY_TYPE_USB3,
1089         .nlanes                 = 1,
1090
1091         .serdes_tbl             = msm8996_usb3_serdes_tbl,
1092         .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1093         .tx_tbl                 = msm8996_usb3_tx_tbl,
1094         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1095         .rx_tbl                 = msm8996_usb3_rx_tbl,
1096         .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1097         .pcs_tbl                = msm8996_usb3_pcs_tbl,
1098         .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1099         .clk_list               = msm8996_phy_clk_l,
1100         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1101         .reset_list             = msm8996_usb3phy_reset_l,
1102         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1103         .vreg_list              = qmp_phy_vreg_l,
1104         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1105         .regs                   = usb3phy_regs_layout,
1106
1107         .start_ctrl             = SERDES_START | PCS_START,
1108         .pwrdn_ctrl             = SW_PWRDN,
1109         .mask_pcs_ready         = PHYSTATUS,
1110 };
1111
1112 /* list of resets */
1113 static const char * const ipq8074_pciephy_reset_l[] = {
1114         "phy", "common",
1115 };
1116
1117 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
1118         .type                   = PHY_TYPE_PCIE,
1119         .nlanes                 = 1,
1120
1121         .serdes_tbl             = ipq8074_pcie_serdes_tbl,
1122         .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
1123         .tx_tbl                 = ipq8074_pcie_tx_tbl,
1124         .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
1125         .rx_tbl                 = ipq8074_pcie_rx_tbl,
1126         .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
1127         .pcs_tbl                = ipq8074_pcie_pcs_tbl,
1128         .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
1129         .clk_list               = NULL,
1130         .num_clks               = 0,
1131         .reset_list             = ipq8074_pciephy_reset_l,
1132         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1133         .vreg_list              = NULL,
1134         .num_vregs              = 0,
1135         .regs                   = pciephy_regs_layout,
1136
1137         .start_ctrl             = SERDES_START | PCS_START,
1138         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
1139         .mask_pcs_ready         = PHYSTATUS,
1140
1141         .has_phy_com_ctrl       = false,
1142         .has_lane_rst           = false,
1143         .has_pwrdn_delay        = true,
1144         .pwrdn_delay_min        = 995,          /* us */
1145         .pwrdn_delay_max        = 1005,         /* us */
1146 };
1147
1148 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
1149         .type                   = PHY_TYPE_USB3,
1150         .nlanes                 = 1,
1151
1152         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
1153         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1154         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
1155         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1156         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
1157         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1158         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
1159         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1160         .clk_list               = qmp_v3_phy_clk_l,
1161         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
1162         .reset_list             = msm8996_usb3phy_reset_l,
1163         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1164         .vreg_list              = qmp_phy_vreg_l,
1165         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1166         .regs                   = qmp_v3_usb3phy_regs_layout,
1167
1168         .start_ctrl             = SERDES_START | PCS_START,
1169         .pwrdn_ctrl             = SW_PWRDN,
1170         .mask_pcs_ready         = PHYSTATUS,
1171
1172         .has_pwrdn_delay        = true,
1173         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1174         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1175
1176         .has_phy_dp_com_ctrl    = true,
1177         .is_dual_lane_phy       = true,
1178 };
1179
1180 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
1181         .type                   = PHY_TYPE_USB3,
1182         .nlanes                 = 1,
1183
1184         .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
1185         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1186         .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
1187         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1188         .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
1189         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1190         .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
1191         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1192         .clk_list               = qmp_v3_phy_clk_l,
1193         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
1194         .reset_list             = msm8996_usb3phy_reset_l,
1195         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1196         .vreg_list              = qmp_phy_vreg_l,
1197         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1198         .regs                   = qmp_v3_usb3phy_regs_layout,
1199
1200         .start_ctrl             = SERDES_START | PCS_START,
1201         .pwrdn_ctrl             = SW_PWRDN,
1202         .mask_pcs_ready         = PHYSTATUS,
1203
1204         .has_pwrdn_delay        = true,
1205         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1206         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1207 };
1208
1209 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
1210         .type                   = PHY_TYPE_UFS,
1211         .nlanes                 = 2,
1212
1213         .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
1214         .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
1215         .tx_tbl                 = sdm845_ufsphy_tx_tbl,
1216         .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
1217         .rx_tbl                 = sdm845_ufsphy_rx_tbl,
1218         .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
1219         .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
1220         .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
1221         .clk_list               = sdm845_ufs_phy_clk_l,
1222         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1223         .vreg_list              = qmp_phy_vreg_l,
1224         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1225         .regs                   = sdm845_ufsphy_regs_layout,
1226
1227         .start_ctrl             = SERDES_START,
1228         .pwrdn_ctrl             = SW_PWRDN,
1229         .mask_pcs_ready         = PCS_READY,
1230
1231         .is_dual_lane_phy       = true,
1232         .no_pcs_sw_reset        = true,
1233 };
1234
1235 static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
1236         .type                   = PHY_TYPE_PCIE,
1237         .nlanes                 = 1,
1238
1239         .serdes_tbl             = msm8998_pcie_serdes_tbl,
1240         .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
1241         .tx_tbl                 = msm8998_pcie_tx_tbl,
1242         .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
1243         .rx_tbl                 = msm8998_pcie_rx_tbl,
1244         .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
1245         .pcs_tbl                = msm8998_pcie_pcs_tbl,
1246         .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
1247         .clk_list               = msm8996_phy_clk_l,
1248         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1249         .reset_list             = ipq8074_pciephy_reset_l,
1250         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1251         .vreg_list              = qmp_phy_vreg_l,
1252         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1253         .regs                   = pciephy_regs_layout,
1254
1255         .start_ctrl             = SERDES_START | PCS_START,
1256         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
1257         .mask_pcs_ready         = PHYSTATUS,
1258 };
1259
1260 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
1261         .type                   = PHY_TYPE_USB3,
1262         .nlanes                 = 1,
1263
1264         .serdes_tbl             = msm8998_usb3_serdes_tbl,
1265         .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
1266         .tx_tbl                 = msm8998_usb3_tx_tbl,
1267         .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
1268         .rx_tbl                 = msm8998_usb3_rx_tbl,
1269         .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
1270         .pcs_tbl                = msm8998_usb3_pcs_tbl,
1271         .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
1272         .clk_list               = msm8996_phy_clk_l,
1273         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1274         .reset_list             = msm8996_usb3phy_reset_l,
1275         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1276         .vreg_list              = qmp_phy_vreg_l,
1277         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1278         .regs                   = qmp_v3_usb3phy_regs_layout,
1279
1280         .start_ctrl             = SERDES_START | PCS_START,
1281         .pwrdn_ctrl             = SW_PWRDN,
1282         .mask_pcs_ready         = PHYSTATUS,
1283
1284         .is_dual_lane_phy       = true,
1285 };
1286
1287 static void qcom_qmp_phy_configure(void __iomem *base,
1288                                    const unsigned int *regs,
1289                                    const struct qmp_phy_init_tbl tbl[],
1290                                    int num)
1291 {
1292         int i;
1293         const struct qmp_phy_init_tbl *t = tbl;
1294
1295         if (!t)
1296                 return;
1297
1298         for (i = 0; i < num; i++, t++) {
1299                 if (t->in_layout)
1300                         writel(t->val, base + regs[t->offset]);
1301                 else
1302                         writel(t->val, base + t->offset);
1303         }
1304 }
1305
1306 static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
1307 {
1308         struct qcom_qmp *qmp = qphy->qmp;
1309         const struct qmp_phy_cfg *cfg = qmp->cfg;
1310         void __iomem *serdes = qmp->serdes;
1311         void __iomem *pcs = qphy->pcs;
1312         void __iomem *dp_com = qmp->dp_com;
1313         int ret, i;
1314
1315         mutex_lock(&qmp->phy_mutex);
1316         if (qmp->init_count++) {
1317                 mutex_unlock(&qmp->phy_mutex);
1318                 return 0;
1319         }
1320
1321         /* turn on regulator supplies */
1322         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1323         if (ret) {
1324                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1325                 goto err_reg_enable;
1326         }
1327
1328         for (i = 0; i < cfg->num_resets; i++) {
1329                 ret = reset_control_assert(qmp->resets[i]);
1330                 if (ret) {
1331                         dev_err(qmp->dev, "%s reset assert failed\n",
1332                                 cfg->reset_list[i]);
1333                         goto err_rst_assert;
1334                 }
1335         }
1336
1337         for (i = cfg->num_resets - 1; i >= 0; i--) {
1338                 ret = reset_control_deassert(qmp->resets[i]);
1339                 if (ret) {
1340                         dev_err(qmp->dev, "%s reset deassert failed\n",
1341                                 qmp->cfg->reset_list[i]);
1342                         goto err_rst;
1343                 }
1344         }
1345
1346         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1347         if (ret) {
1348                 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
1349                 goto err_rst;
1350         }
1351
1352         if (cfg->has_phy_dp_com_ctrl) {
1353                 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
1354                              SW_PWRDN);
1355                 /* override hardware control for reset of qmp phy */
1356                 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
1357                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
1358                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
1359
1360                 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
1361                              USB3_MODE | DP_MODE);
1362
1363                 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
1364                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
1365                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
1366                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
1367         }
1368
1369         if (cfg->has_phy_com_ctrl)
1370                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
1371                              SW_PWRDN);
1372         else
1373                 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1374
1375         /* Serdes configuration */
1376         qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
1377                                cfg->serdes_tbl_num);
1378
1379         if (cfg->has_phy_com_ctrl) {
1380                 void __iomem *status;
1381                 unsigned int mask, val;
1382
1383                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
1384                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
1385                              SERDES_START | PCS_START);
1386
1387                 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
1388                 mask = cfg->mask_com_pcs_ready;
1389
1390                 ret = readl_poll_timeout(status, val, (val & mask), 10,
1391                                          PHY_INIT_COMPLETE_TIMEOUT);
1392                 if (ret) {
1393                         dev_err(qmp->dev,
1394                                 "phy common block init timed-out\n");
1395                         goto err_com_init;
1396                 }
1397         }
1398
1399         mutex_unlock(&qmp->phy_mutex);
1400
1401         return 0;
1402
1403 err_com_init:
1404         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1405 err_rst:
1406         while (++i < cfg->num_resets)
1407                 reset_control_assert(qmp->resets[i]);
1408 err_rst_assert:
1409         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1410 err_reg_enable:
1411         mutex_unlock(&qmp->phy_mutex);
1412
1413         return ret;
1414 }
1415
1416 static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
1417 {
1418         const struct qmp_phy_cfg *cfg = qmp->cfg;
1419         void __iomem *serdes = qmp->serdes;
1420         int i = cfg->num_resets;
1421
1422         mutex_lock(&qmp->phy_mutex);
1423         if (--qmp->init_count) {
1424                 mutex_unlock(&qmp->phy_mutex);
1425                 return 0;
1426         }
1427
1428         reset_control_assert(qmp->ufs_reset);
1429         if (cfg->has_phy_com_ctrl) {
1430                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
1431                              SERDES_START | PCS_START);
1432                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
1433                              SW_RESET);
1434                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
1435                              SW_PWRDN);
1436         }
1437
1438         while (--i >= 0)
1439                 reset_control_assert(qmp->resets[i]);
1440
1441         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1442
1443         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1444
1445         mutex_unlock(&qmp->phy_mutex);
1446
1447         return 0;
1448 }
1449
1450 static int qcom_qmp_phy_enable(struct phy *phy)
1451 {
1452         struct qmp_phy *qphy = phy_get_drvdata(phy);
1453         struct qcom_qmp *qmp = qphy->qmp;
1454         const struct qmp_phy_cfg *cfg = qmp->cfg;
1455         void __iomem *tx = qphy->tx;
1456         void __iomem *rx = qphy->rx;
1457         void __iomem *pcs = qphy->pcs;
1458         void __iomem *dp_com = qmp->dp_com;
1459         void __iomem *status;
1460         unsigned int mask, val;
1461         int ret;
1462
1463         dev_vdbg(qmp->dev, "Initializing QMP phy\n");
1464
1465         if (cfg->no_pcs_sw_reset) {
1466                 /*
1467                  * Get UFS reset, which is delayed until now to avoid a
1468                  * circular dependency where UFS needs its PHY, but the PHY
1469                  * needs this UFS reset.
1470                  */
1471                 if (!qmp->ufs_reset) {
1472                         qmp->ufs_reset =
1473                                 devm_reset_control_get_exclusive(qmp->dev,
1474                                                                  "ufsphy");
1475
1476                         if (IS_ERR(qmp->ufs_reset)) {
1477                                 ret = PTR_ERR(qmp->ufs_reset);
1478                                 dev_err(qmp->dev,
1479                                         "failed to get UFS reset: %d\n",
1480                                         ret);
1481
1482                                 qmp->ufs_reset = NULL;
1483                                 return ret;
1484                         }
1485                 }
1486
1487                 ret = reset_control_assert(qmp->ufs_reset);
1488                 if (ret)
1489                         goto err_lane_rst;
1490         }
1491
1492         ret = qcom_qmp_phy_com_init(qphy);
1493         if (ret)
1494                 return ret;
1495
1496         if (cfg->has_lane_rst) {
1497                 ret = reset_control_deassert(qphy->lane_rst);
1498                 if (ret) {
1499                         dev_err(qmp->dev, "lane%d reset deassert failed\n",
1500                                 qphy->index);
1501                         goto err_lane_rst;
1502                 }
1503         }
1504
1505         ret = clk_prepare_enable(qphy->pipe_clk);
1506         if (ret) {
1507                 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
1508                 goto err_clk_enable;
1509         }
1510
1511         /* Tx, Rx, and PCS configurations */
1512         qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num);
1513         /* Configuration for other LANE for USB-DP combo PHY */
1514         if (cfg->is_dual_lane_phy)
1515                 qcom_qmp_phy_configure(qphy->tx2, cfg->regs,
1516                                        cfg->tx_tbl, cfg->tx_tbl_num);
1517
1518         qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num);
1519         if (cfg->is_dual_lane_phy)
1520                 qcom_qmp_phy_configure(qphy->rx2, cfg->regs,
1521                                        cfg->rx_tbl, cfg->rx_tbl_num);
1522
1523         qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
1524         ret = reset_control_deassert(qmp->ufs_reset);
1525         if (ret)
1526                 goto err_lane_rst;
1527
1528         /*
1529          * Pull out PHY from POWER DOWN state.
1530          * This is active low enable signal to power-down PHY.
1531          */
1532         if(cfg->type == PHY_TYPE_PCIE)
1533                 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1534
1535         if (cfg->has_pwrdn_delay)
1536                 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
1537
1538         /* Pull PHY out of reset state */
1539         if (!cfg->no_pcs_sw_reset)
1540                 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1541
1542         if (cfg->has_phy_dp_com_ctrl)
1543                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
1544
1545         /* start SerDes and Phy-Coding-Sublayer */
1546         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1547
1548         status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
1549         mask = cfg->mask_pcs_ready;
1550
1551         ret = readl_poll_timeout(status, val, val & mask, 10,
1552                                  PHY_INIT_COMPLETE_TIMEOUT);
1553         if (ret) {
1554                 dev_err(qmp->dev, "phy initialization timed-out\n");
1555                 goto err_pcs_ready;
1556         }
1557         qmp->phy_initialized = true;
1558         return 0;
1559
1560 err_pcs_ready:
1561         reset_control_assert(qmp->ufs_reset);
1562         clk_disable_unprepare(qphy->pipe_clk);
1563 err_clk_enable:
1564         if (cfg->has_lane_rst)
1565                 reset_control_assert(qphy->lane_rst);
1566 err_lane_rst:
1567         qcom_qmp_phy_com_exit(qmp);
1568
1569         return ret;
1570 }
1571
1572 static int qcom_qmp_phy_disable(struct phy *phy)
1573 {
1574         struct qmp_phy *qphy = phy_get_drvdata(phy);
1575         struct qcom_qmp *qmp = qphy->qmp;
1576         const struct qmp_phy_cfg *cfg = qmp->cfg;
1577
1578         clk_disable_unprepare(qphy->pipe_clk);
1579
1580         /* PHY reset */
1581         if (!cfg->no_pcs_sw_reset)
1582                 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1583
1584         /* stop SerDes and Phy-Coding-Sublayer */
1585         qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1586
1587         /* Put PHY into POWER DOWN state: active low */
1588         qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1589
1590         if (cfg->has_lane_rst)
1591                 reset_control_assert(qphy->lane_rst);
1592
1593         qcom_qmp_phy_com_exit(qmp);
1594
1595         qmp->phy_initialized = false;
1596
1597         return 0;
1598 }
1599
1600 static int qcom_qmp_phy_set_mode(struct phy *phy,
1601                                  enum phy_mode mode, int submode)
1602 {
1603         struct qmp_phy *qphy = phy_get_drvdata(phy);
1604         struct qcom_qmp *qmp = qphy->qmp;
1605
1606         qmp->mode = mode;
1607
1608         return 0;
1609 }
1610
1611 static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
1612 {
1613         struct qcom_qmp *qmp = qphy->qmp;
1614         const struct qmp_phy_cfg *cfg = qmp->cfg;
1615         void __iomem *pcs = qphy->pcs;
1616         void __iomem *pcs_misc = qphy->pcs_misc;
1617         u32 intr_mask;
1618
1619         if (qmp->mode == PHY_MODE_USB_HOST_SS ||
1620             qmp->mode == PHY_MODE_USB_DEVICE_SS)
1621                 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
1622         else
1623                 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
1624
1625         /* Clear any pending interrupts status */
1626         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1627         /* Writing 1 followed by 0 clears the interrupt */
1628         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1629
1630         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1631                      ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
1632
1633         /* Enable required PHY autonomous mode interrupts */
1634         qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
1635
1636         /* Enable i/o clamp_n for autonomous mode */
1637         if (pcs_misc)
1638                 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1639 }
1640
1641 static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
1642 {
1643         struct qcom_qmp *qmp = qphy->qmp;
1644         const struct qmp_phy_cfg *cfg = qmp->cfg;
1645         void __iomem *pcs = qphy->pcs;
1646         void __iomem *pcs_misc = qphy->pcs_misc;
1647
1648         /* Disable i/o clamp_n on resume for normal mode */
1649         if (pcs_misc)
1650                 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1651
1652         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1653                      ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
1654
1655         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1656         /* Writing 1 followed by 0 clears the interrupt */
1657         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1658 }
1659
1660 static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
1661 {
1662         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1663         struct qmp_phy *qphy = qmp->phys[0];
1664         const struct qmp_phy_cfg *cfg = qmp->cfg;
1665
1666         dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
1667
1668         /* Supported only for USB3 PHY */
1669         if (cfg->type != PHY_TYPE_USB3)
1670                 return 0;
1671
1672         if (!qmp->phy_initialized) {
1673                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1674                 return 0;
1675         }
1676
1677         qcom_qmp_phy_enable_autonomous_mode(qphy);
1678
1679         clk_disable_unprepare(qphy->pipe_clk);
1680         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1681
1682         return 0;
1683 }
1684
1685 static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
1686 {
1687         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1688         struct qmp_phy *qphy = qmp->phys[0];
1689         const struct qmp_phy_cfg *cfg = qmp->cfg;
1690         int ret = 0;
1691
1692         dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
1693
1694         /* Supported only for USB3 PHY */
1695         if (cfg->type != PHY_TYPE_USB3)
1696                 return 0;
1697
1698         if (!qmp->phy_initialized) {
1699                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1700                 return 0;
1701         }
1702
1703         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1704         if (ret) {
1705                 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
1706                 return ret;
1707         }
1708
1709         ret = clk_prepare_enable(qphy->pipe_clk);
1710         if (ret) {
1711                 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
1712                 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1713                 return ret;
1714         }
1715
1716         qcom_qmp_phy_disable_autonomous_mode(qphy);
1717
1718         return 0;
1719 }
1720
1721 static int qcom_qmp_phy_vreg_init(struct device *dev)
1722 {
1723         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1724         int num = qmp->cfg->num_vregs;
1725         int i;
1726
1727         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
1728         if (!qmp->vregs)
1729                 return -ENOMEM;
1730
1731         for (i = 0; i < num; i++)
1732                 qmp->vregs[i].supply = qmp->cfg->vreg_list[i];
1733
1734         return devm_regulator_bulk_get(dev, num, qmp->vregs);
1735 }
1736
1737 static int qcom_qmp_phy_reset_init(struct device *dev)
1738 {
1739         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1740         int i;
1741
1742         qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets,
1743                                    sizeof(*qmp->resets), GFP_KERNEL);
1744         if (!qmp->resets)
1745                 return -ENOMEM;
1746
1747         for (i = 0; i < qmp->cfg->num_resets; i++) {
1748                 struct reset_control *rst;
1749                 const char *name = qmp->cfg->reset_list[i];
1750
1751                 rst = devm_reset_control_get(dev, name);
1752                 if (IS_ERR(rst)) {
1753                         dev_err(dev, "failed to get %s reset\n", name);
1754                         return PTR_ERR(rst);
1755                 }
1756                 qmp->resets[i] = rst;
1757         }
1758
1759         return 0;
1760 }
1761
1762 static int qcom_qmp_phy_clk_init(struct device *dev)
1763 {
1764         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1765         int num = qmp->cfg->num_clks;
1766         int i;
1767
1768         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
1769         if (!qmp->clks)
1770                 return -ENOMEM;
1771
1772         for (i = 0; i < num; i++)
1773                 qmp->clks[i].id = qmp->cfg->clk_list[i];
1774
1775         return devm_clk_bulk_get(dev, num, qmp->clks);
1776 }
1777
1778 static void phy_pipe_clk_release_provider(void *res)
1779 {
1780         of_clk_del_provider(res);
1781 }
1782
1783 /*
1784  * Register a fixed rate pipe clock.
1785  *
1786  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
1787  * controls it. The <s>_pipe_clk coming out of the GCC is requested
1788  * by the PHY driver for its operations.
1789  * We register the <s>_pipe_clksrc here. The gcc driver takes care
1790  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
1791  * Below picture shows this relationship.
1792  *
1793  *         +---------------+
1794  *         |   PHY block   |<<---------------------------------------+
1795  *         |               |                                         |
1796  *         |   +-------+   |                   +-----+               |
1797  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
1798  *    clk  |   +-------+   |                   +-----+
1799  *         +---------------+
1800  */
1801 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
1802 {
1803         struct clk_fixed_rate *fixed;
1804         struct clk_init_data init = { };
1805         int ret;
1806
1807         if ((qmp->cfg->type != PHY_TYPE_USB3) &&
1808             (qmp->cfg->type != PHY_TYPE_PCIE)) {
1809                 /* not all phys register pipe clocks, so return success */
1810                 return 0;
1811         }
1812
1813         ret = of_property_read_string(np, "clock-output-names", &init.name);
1814         if (ret) {
1815                 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
1816                 return ret;
1817         }
1818
1819         fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
1820         if (!fixed)
1821                 return -ENOMEM;
1822
1823         init.ops = &clk_fixed_rate_ops;
1824
1825         /* controllers using QMP phys use 125MHz pipe clock interface */
1826         fixed->fixed_rate = 125000000;
1827         fixed->hw.init = &init;
1828
1829         ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
1830         if (ret)
1831                 return ret;
1832
1833         ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
1834         if (ret)
1835                 return ret;
1836
1837         /*
1838          * Roll a devm action because the clock provider is the child node, but
1839          * the child node is not actually a device.
1840          */
1841         ret = devm_add_action(qmp->dev, phy_pipe_clk_release_provider, np);
1842         if (ret)
1843                 phy_pipe_clk_release_provider(np);
1844
1845         return ret;
1846 }
1847
1848 static const struct phy_ops qcom_qmp_phy_gen_ops = {
1849         .init           = qcom_qmp_phy_enable,
1850         .exit           = qcom_qmp_phy_disable,
1851         .set_mode       = qcom_qmp_phy_set_mode,
1852         .owner          = THIS_MODULE,
1853 };
1854
1855 static const struct phy_ops qcom_qmp_ufs_ops = {
1856         .power_on       = qcom_qmp_phy_enable,
1857         .power_off      = qcom_qmp_phy_disable,
1858         .set_mode       = qcom_qmp_phy_set_mode,
1859         .owner          = THIS_MODULE,
1860 };
1861
1862 static
1863 int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
1864 {
1865         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1866         struct phy *generic_phy;
1867         struct qmp_phy *qphy;
1868         const struct phy_ops *ops = &qcom_qmp_phy_gen_ops;
1869         char prop_name[MAX_PROP_NAME];
1870         int ret;
1871
1872         qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
1873         if (!qphy)
1874                 return -ENOMEM;
1875
1876         /*
1877          * Get memory resources for each phy lane:
1878          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
1879          * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
1880          * For single lane PHYs: pcs_misc (optional) -> 3.
1881          */
1882         qphy->tx = of_iomap(np, 0);
1883         if (!qphy->tx)
1884                 return -ENOMEM;
1885
1886         qphy->rx = of_iomap(np, 1);
1887         if (!qphy->rx)
1888                 return -ENOMEM;
1889
1890         qphy->pcs = of_iomap(np, 2);
1891         if (!qphy->pcs)
1892                 return -ENOMEM;
1893
1894         /*
1895          * If this is a dual-lane PHY, then there should be registers for the
1896          * second lane. Some old device trees did not specify this, so fall
1897          * back to old legacy behavior of assuming they can be reached at an
1898          * offset from the first lane.
1899          */
1900         if (qmp->cfg->is_dual_lane_phy) {
1901                 qphy->tx2 = of_iomap(np, 3);
1902                 qphy->rx2 = of_iomap(np, 4);
1903                 if (!qphy->tx2 || !qphy->rx2) {
1904                         dev_warn(dev,
1905                                  "Underspecified device tree, falling back to legacy register regions\n");
1906
1907                         /* In the old version, pcs_misc is at index 3. */
1908                         qphy->pcs_misc = qphy->tx2;
1909                         qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
1910                         qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
1911
1912                 } else {
1913                         qphy->pcs_misc = of_iomap(np, 5);
1914                 }
1915
1916         } else {
1917                 qphy->pcs_misc = of_iomap(np, 3);
1918         }
1919
1920         if (!qphy->pcs_misc)
1921                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
1922
1923         /*
1924          * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
1925          * based phys, so they essentially have pipe clock. So,
1926          * we return error in case phy is USB3 or PIPE type.
1927          * Otherwise, we initialize pipe clock to NULL for
1928          * all phys that don't need this.
1929          */
1930         snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
1931         qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
1932         if (IS_ERR(qphy->pipe_clk)) {
1933                 if (qmp->cfg->type == PHY_TYPE_PCIE ||
1934                     qmp->cfg->type == PHY_TYPE_USB3) {
1935                         ret = PTR_ERR(qphy->pipe_clk);
1936                         if (ret != -EPROBE_DEFER)
1937                                 dev_err(dev,
1938                                         "failed to get lane%d pipe_clk, %d\n",
1939                                         id, ret);
1940                         return ret;
1941                 }
1942                 qphy->pipe_clk = NULL;
1943         }
1944
1945         /* Get lane reset, if any */
1946         if (qmp->cfg->has_lane_rst) {
1947                 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
1948                 qphy->lane_rst = of_reset_control_get(np, prop_name);
1949                 if (IS_ERR(qphy->lane_rst)) {
1950                         dev_err(dev, "failed to get lane%d reset\n", id);
1951                         return PTR_ERR(qphy->lane_rst);
1952                 }
1953         }
1954
1955         if (qmp->cfg->type == PHY_TYPE_UFS)
1956                 ops = &qcom_qmp_ufs_ops;
1957
1958         generic_phy = devm_phy_create(dev, np, ops);
1959         if (IS_ERR(generic_phy)) {
1960                 ret = PTR_ERR(generic_phy);
1961                 dev_err(dev, "failed to create qphy %d\n", ret);
1962                 return ret;
1963         }
1964
1965         qphy->phy = generic_phy;
1966         qphy->index = id;
1967         qphy->qmp = qmp;
1968         qmp->phys[id] = qphy;
1969         phy_set_drvdata(generic_phy, qphy);
1970
1971         return 0;
1972 }
1973
1974 static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
1975         {
1976                 .compatible = "qcom,msm8996-qmp-pcie-phy",
1977                 .data = &msm8996_pciephy_cfg,
1978         }, {
1979                 .compatible = "qcom,msm8996-qmp-usb3-phy",
1980                 .data = &msm8996_usb3phy_cfg,
1981         }, {
1982                 .compatible = "qcom,msm8998-qmp-pcie-phy",
1983                 .data = &msm8998_pciephy_cfg,
1984         }, {
1985                 .compatible = "qcom,msm8998-qmp-ufs-phy",
1986                 .data = &sdm845_ufsphy_cfg,
1987         }, {
1988                 .compatible = "qcom,ipq8074-qmp-pcie-phy",
1989                 .data = &ipq8074_pciephy_cfg,
1990         }, {
1991                 .compatible = "qcom,sdm845-qmp-usb3-phy",
1992                 .data = &qmp_v3_usb3phy_cfg,
1993         }, {
1994                 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
1995                 .data = &qmp_v3_usb3_uniphy_cfg,
1996         }, {
1997                 .compatible = "qcom,sdm845-qmp-ufs-phy",
1998                 .data = &sdm845_ufsphy_cfg,
1999         }, {
2000                 .compatible = "qcom,msm8998-qmp-usb3-phy",
2001                 .data = &msm8998_usb3phy_cfg,
2002         },
2003         { },
2004 };
2005 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
2006
2007 static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
2008         SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
2009                            qcom_qmp_phy_runtime_resume, NULL)
2010 };
2011
2012 static int qcom_qmp_phy_probe(struct platform_device *pdev)
2013 {
2014         struct qcom_qmp *qmp;
2015         struct device *dev = &pdev->dev;
2016         struct resource *res;
2017         struct device_node *child;
2018         struct phy_provider *phy_provider;
2019         void __iomem *base;
2020         int num, id;
2021         int ret;
2022
2023         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2024         if (!qmp)
2025                 return -ENOMEM;
2026
2027         qmp->dev = dev;
2028         dev_set_drvdata(dev, qmp);
2029
2030         /* Get the specific init parameters of QMP phy */
2031         qmp->cfg = of_device_get_match_data(dev);
2032         if (!qmp->cfg)
2033                 return -EINVAL;
2034
2035         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2036         base = devm_ioremap_resource(dev, res);
2037         if (IS_ERR(base))
2038                 return PTR_ERR(base);
2039
2040         /* per PHY serdes; usually located at base address */
2041         qmp->serdes = base;
2042
2043         /* per PHY dp_com; if PHY has dp_com control block */
2044         if (qmp->cfg->has_phy_dp_com_ctrl) {
2045                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2046                                                    "dp_com");
2047                 base = devm_ioremap_resource(dev, res);
2048                 if (IS_ERR(base))
2049                         return PTR_ERR(base);
2050
2051                 qmp->dp_com = base;
2052         }
2053
2054         mutex_init(&qmp->phy_mutex);
2055
2056         ret = qcom_qmp_phy_clk_init(dev);
2057         if (ret)
2058                 return ret;
2059
2060         ret = qcom_qmp_phy_reset_init(dev);
2061         if (ret)
2062                 return ret;
2063
2064         ret = qcom_qmp_phy_vreg_init(dev);
2065         if (ret) {
2066                 if (ret != -EPROBE_DEFER)
2067                         dev_err(dev, "failed to get regulator supplies: %d\n",
2068                                 ret);
2069                 return ret;
2070         }
2071
2072         num = of_get_available_child_count(dev->of_node);
2073         /* do we have a rogue child node ? */
2074         if (num > qmp->cfg->nlanes)
2075                 return -EINVAL;
2076
2077         qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
2078         if (!qmp->phys)
2079                 return -ENOMEM;
2080
2081         id = 0;
2082         pm_runtime_set_active(dev);
2083         pm_runtime_enable(dev);
2084         /*
2085          * Prevent runtime pm from being ON by default. Users can enable
2086          * it using power/control in sysfs.
2087          */
2088         pm_runtime_forbid(dev);
2089
2090         for_each_available_child_of_node(dev->of_node, child) {
2091                 /* Create per-lane phy */
2092                 ret = qcom_qmp_phy_create(dev, child, id);
2093                 if (ret) {
2094                         dev_err(dev, "failed to create lane%d phy, %d\n",
2095                                 id, ret);
2096                         pm_runtime_disable(dev);
2097                         return ret;
2098                 }
2099
2100                 /*
2101                  * Register the pipe clock provided by phy.
2102                  * See function description to see details of this pipe clock.
2103                  */
2104                 ret = phy_pipe_clk_register(qmp, child);
2105                 if (ret) {
2106                         dev_err(qmp->dev,
2107                                 "failed to register pipe clock source\n");
2108                         pm_runtime_disable(dev);
2109                         return ret;
2110                 }
2111                 id++;
2112         }
2113
2114         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2115         if (!IS_ERR(phy_provider))
2116                 dev_info(dev, "Registered Qcom-QMP phy\n");
2117         else
2118                 pm_runtime_disable(dev);
2119
2120         return PTR_ERR_OR_ZERO(phy_provider);
2121 }
2122
2123 static struct platform_driver qcom_qmp_phy_driver = {
2124         .probe          = qcom_qmp_phy_probe,
2125         .driver = {
2126                 .name   = "qcom-qmp-phy",
2127                 .pm     = &qcom_qmp_phy_pm_ops,
2128                 .of_match_table = qcom_qmp_phy_of_match_table,
2129         },
2130 };
2131
2132 module_platform_driver(qcom_qmp_phy_driver);
2133
2134 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
2135 MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
2136 MODULE_LICENSE("GPL v2");