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Merge tag 'apparmor-pr-2019-12-03' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux.git] / drivers / phy / qualcomm / phy-qcom-ufs-qmp-14nm.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
4  */
5
6 #include "phy-qcom-ufs-qmp-14nm.h"
7
8 #define UFS_PHY_NAME "ufs_phy_qmp_14nm"
9 #define UFS_PHY_VDDA_PHY_UV     (925000)
10
11 static
12 int ufs_qcom_phy_qmp_14nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
13                                         bool is_rate_B)
14 {
15         int tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);
16         int tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
17         int err;
18
19         err = ufs_qcom_phy_calibrate(ufs_qcom_phy, phy_cal_table_rate_A,
20                 tbl_size_A, phy_cal_table_rate_B, tbl_size_B, is_rate_B);
21
22         if (err)
23                 dev_err(ufs_qcom_phy->dev,
24                         "%s: ufs_qcom_phy_calibrate() failed %d\n",
25                         __func__, err);
26         return err;
27 }
28
29 static
30 void ufs_qcom_phy_qmp_14nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
31 {
32         phy_common->quirks =
33                 UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
34 }
35
36 static
37 int ufs_qcom_phy_qmp_14nm_set_mode(struct phy *generic_phy,
38                                    enum phy_mode mode, int submode)
39 {
40         struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
41
42         phy_common->mode = PHY_MODE_INVALID;
43
44         if (mode > 0)
45                 phy_common->mode = mode;
46
47         return 0;
48 }
49
50 static
51 void ufs_qcom_phy_qmp_14nm_power_control(struct ufs_qcom_phy *phy, bool val)
52 {
53         writel_relaxed(val ? 0x1 : 0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
54         /*
55          * Before any transactions involving PHY, ensure PHY knows
56          * that it's analog rail is powered ON (or OFF).
57          */
58         mb();
59 }
60
61 static inline
62 void ufs_qcom_phy_qmp_14nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
63 {
64         /*
65          * 14nm PHY does not have TX_LANE_ENABLE register.
66          * Implement this function so as not to propagate error to caller.
67          */
68 }
69
70 static inline void ufs_qcom_phy_qmp_14nm_start_serdes(struct ufs_qcom_phy *phy)
71 {
72         u32 tmp;
73
74         tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
75         tmp &= ~MASK_SERDES_START;
76         tmp |= (1 << OFFSET_SERDES_START);
77         writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
78         /* Ensure register value is committed */
79         mb();
80 }
81
82 static int ufs_qcom_phy_qmp_14nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
83 {
84         int err = 0;
85         u32 val;
86
87         err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
88                 val, (val & MASK_PCS_READY), 10, 1000000);
89         if (err)
90                 dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
91                         __func__, err);
92         return err;
93 }
94
95 static const struct phy_ops ufs_qcom_phy_qmp_14nm_phy_ops = {
96         .power_on       = ufs_qcom_phy_power_on,
97         .power_off      = ufs_qcom_phy_power_off,
98         .set_mode       = ufs_qcom_phy_qmp_14nm_set_mode,
99         .owner          = THIS_MODULE,
100 };
101
102 static struct ufs_qcom_phy_specific_ops phy_14nm_ops = {
103         .calibrate              = ufs_qcom_phy_qmp_14nm_phy_calibrate,
104         .start_serdes           = ufs_qcom_phy_qmp_14nm_start_serdes,
105         .is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_14nm_is_pcs_ready,
106         .set_tx_lane_enable     = ufs_qcom_phy_qmp_14nm_set_tx_lane_enable,
107         .power_control          = ufs_qcom_phy_qmp_14nm_power_control,
108 };
109
110 static int ufs_qcom_phy_qmp_14nm_probe(struct platform_device *pdev)
111 {
112         struct device *dev = &pdev->dev;
113         struct phy *generic_phy;
114         struct ufs_qcom_phy_qmp_14nm *phy;
115         struct ufs_qcom_phy *phy_common;
116         int err = 0;
117
118         phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
119         if (!phy) {
120                 err = -ENOMEM;
121                 goto out;
122         }
123         phy_common = &phy->common_cfg;
124
125         generic_phy = ufs_qcom_phy_generic_probe(pdev, phy_common,
126                                 &ufs_qcom_phy_qmp_14nm_phy_ops, &phy_14nm_ops);
127
128         if (!generic_phy) {
129                 err = -EIO;
130                 goto out;
131         }
132
133         err = ufs_qcom_phy_init_clks(phy_common);
134         if (err)
135                 goto out;
136
137         err = ufs_qcom_phy_init_vregulators(phy_common);
138         if (err)
139                 goto out;
140
141         phy_common->vdda_phy.max_uV = UFS_PHY_VDDA_PHY_UV;
142         phy_common->vdda_phy.min_uV = UFS_PHY_VDDA_PHY_UV;
143
144         ufs_qcom_phy_qmp_14nm_advertise_quirks(phy_common);
145
146         phy_set_drvdata(generic_phy, phy);
147
148         strlcpy(phy_common->name, UFS_PHY_NAME, sizeof(phy_common->name));
149
150 out:
151         return err;
152 }
153
154 static const struct of_device_id ufs_qcom_phy_qmp_14nm_of_match[] = {
155         {.compatible = "qcom,ufs-phy-qmp-14nm"},
156         {.compatible = "qcom,msm8996-ufs-phy-qmp-14nm"},
157         {},
158 };
159 MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_14nm_of_match);
160
161 static struct platform_driver ufs_qcom_phy_qmp_14nm_driver = {
162         .probe = ufs_qcom_phy_qmp_14nm_probe,
163         .driver = {
164                 .of_match_table = ufs_qcom_phy_qmp_14nm_of_match,
165                 .name = "ufs_qcom_phy_qmp_14nm",
166         },
167 };
168
169 module_platform_driver(ufs_qcom_phy_qmp_14nm_driver);
170
171 MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 14nm");
172 MODULE_LICENSE("GPL v2");