1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
6 #include "phy-qcom-ufs-i.h"
8 #define MAX_PROP_NAME 32
9 #define VDDA_PHY_MIN_UV 1000000
10 #define VDDA_PHY_MAX_UV 1000000
11 #define VDDA_PLL_MIN_UV 1800000
12 #define VDDA_PLL_MAX_UV 1800000
13 #define VDDP_REF_CLK_MIN_UV 1200000
14 #define VDDP_REF_CLK_MAX_UV 1200000
16 int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
17 struct ufs_qcom_phy_calibration *tbl_A,
19 struct ufs_qcom_phy_calibration *tbl_B,
20 int tbl_size_B, bool is_rate_B)
26 dev_err(ufs_qcom_phy->dev, "%s: tbl_A is NULL", __func__);
31 for (i = 0; i < tbl_size_A; i++)
32 writel_relaxed(tbl_A[i].cfg_value,
33 ufs_qcom_phy->mmio + tbl_A[i].reg_offset);
36 * In case we would like to work in rate B, we need
37 * to override a registers that were configured in rate A table
38 * with registers of rate B table.
43 dev_err(ufs_qcom_phy->dev, "%s: tbl_B is NULL",
49 for (i = 0; i < tbl_size_B; i++)
50 writel_relaxed(tbl_B[i].cfg_value,
51 ufs_qcom_phy->mmio + tbl_B[i].reg_offset);
54 /* flush buffered writes */
60 EXPORT_SYMBOL_GPL(ufs_qcom_phy_calibrate);
63 * This assumes the embedded phy structure inside generic_phy is of type
64 * struct ufs_qcom_phy. In order to function properly it's crucial
65 * to keep the embedded struct "struct ufs_qcom_phy common_cfg"
66 * as the first inside generic_phy.
68 struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy)
70 return (struct ufs_qcom_phy *)phy_get_drvdata(generic_phy);
72 EXPORT_SYMBOL_GPL(get_ufs_qcom_phy);
75 int ufs_qcom_phy_base_init(struct platform_device *pdev,
76 struct ufs_qcom_phy *phy_common)
78 struct device *dev = &pdev->dev;
82 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_mem");
83 phy_common->mmio = devm_ioremap_resource(dev, res);
84 if (IS_ERR((void const *)phy_common->mmio)) {
85 err = PTR_ERR((void const *)phy_common->mmio);
86 phy_common->mmio = NULL;
87 dev_err(dev, "%s: ioremap for phy_mem resource failed %d\n",
92 /* "dev_ref_clk_ctrl_mem" is optional resource */
93 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
94 "dev_ref_clk_ctrl_mem");
95 phy_common->dev_ref_clk_ctrl_mmio = devm_ioremap_resource(dev, res);
96 if (IS_ERR((void const *)phy_common->dev_ref_clk_ctrl_mmio))
97 phy_common->dev_ref_clk_ctrl_mmio = NULL;
102 struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
103 struct ufs_qcom_phy *common_cfg,
104 const struct phy_ops *ufs_qcom_phy_gen_ops,
105 struct ufs_qcom_phy_specific_ops *phy_spec_ops)
108 struct device *dev = &pdev->dev;
109 struct phy *generic_phy = NULL;
110 struct phy_provider *phy_provider;
112 err = ufs_qcom_phy_base_init(pdev, common_cfg);
114 dev_err(dev, "%s: phy base init failed %d\n", __func__, err);
118 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
119 if (IS_ERR(phy_provider)) {
120 err = PTR_ERR(phy_provider);
121 dev_err(dev, "%s: failed to register phy %d\n", __func__, err);
125 generic_phy = devm_phy_create(dev, NULL, ufs_qcom_phy_gen_ops);
126 if (IS_ERR(generic_phy)) {
127 err = PTR_ERR(generic_phy);
128 dev_err(dev, "%s: failed to create phy %d\n", __func__, err);
133 common_cfg->phy_spec_ops = phy_spec_ops;
134 common_cfg->dev = dev;
139 EXPORT_SYMBOL_GPL(ufs_qcom_phy_generic_probe);
141 static int ufs_qcom_phy_get_reset(struct ufs_qcom_phy *phy_common)
143 struct reset_control *reset;
145 if (phy_common->ufs_reset)
148 reset = devm_reset_control_get_exclusive_by_index(phy_common->dev, 0);
150 return PTR_ERR(reset);
152 phy_common->ufs_reset = reset;
156 static int __ufs_qcom_phy_clk_get(struct device *dev,
157 const char *name, struct clk **clk_out, bool err_print)
162 clk = devm_clk_get(dev, name);
166 dev_err(dev, "failed to get %s err %d", name, err);
174 static int ufs_qcom_phy_clk_get(struct device *dev,
175 const char *name, struct clk **clk_out)
177 return __ufs_qcom_phy_clk_get(dev, name, clk_out, true);
180 int ufs_qcom_phy_init_clks(struct ufs_qcom_phy *phy_common)
184 if (of_device_is_compatible(phy_common->dev->of_node,
185 "qcom,msm8996-ufs-phy-qmp-14nm"))
188 err = ufs_qcom_phy_clk_get(phy_common->dev, "tx_iface_clk",
189 &phy_common->tx_iface_clk);
193 err = ufs_qcom_phy_clk_get(phy_common->dev, "rx_iface_clk",
194 &phy_common->rx_iface_clk);
199 err = ufs_qcom_phy_clk_get(phy_common->dev, "ref_clk_src",
200 &phy_common->ref_clk_src);
205 * "ref_clk_parent" is optional hence don't abort init if it's not
208 __ufs_qcom_phy_clk_get(phy_common->dev, "ref_clk_parent",
209 &phy_common->ref_clk_parent, false);
211 err = ufs_qcom_phy_clk_get(phy_common->dev, "ref_clk",
212 &phy_common->ref_clk);
217 EXPORT_SYMBOL_GPL(ufs_qcom_phy_init_clks);
219 static int ufs_qcom_phy_init_vreg(struct device *dev,
220 struct ufs_qcom_phy_vreg *vreg,
225 char prop_name[MAX_PROP_NAME];
228 vreg->reg = devm_regulator_get(dev, name);
229 if (IS_ERR(vreg->reg)) {
230 err = PTR_ERR(vreg->reg);
231 dev_err(dev, "failed to get %s, %d\n", name, err);
236 snprintf(prop_name, MAX_PROP_NAME, "%s-max-microamp", name);
237 err = of_property_read_u32(dev->of_node,
238 prop_name, &vreg->max_uA);
239 if (err && err != -EINVAL) {
240 dev_err(dev, "%s: failed to read %s\n",
241 __func__, prop_name);
243 } else if (err == -EINVAL || !vreg->max_uA) {
244 if (regulator_count_voltages(vreg->reg) > 0) {
245 dev_err(dev, "%s: %s is mandatory\n",
246 __func__, prop_name);
253 if (!strcmp(name, "vdda-pll")) {
254 vreg->max_uV = VDDA_PLL_MAX_UV;
255 vreg->min_uV = VDDA_PLL_MIN_UV;
256 } else if (!strcmp(name, "vdda-phy")) {
257 vreg->max_uV = VDDA_PHY_MAX_UV;
258 vreg->min_uV = VDDA_PHY_MIN_UV;
259 } else if (!strcmp(name, "vddp-ref-clk")) {
260 vreg->max_uV = VDDP_REF_CLK_MAX_UV;
261 vreg->min_uV = VDDP_REF_CLK_MIN_UV;
268 int ufs_qcom_phy_init_vregulators(struct ufs_qcom_phy *phy_common)
272 err = ufs_qcom_phy_init_vreg(phy_common->dev, &phy_common->vdda_pll,
277 err = ufs_qcom_phy_init_vreg(phy_common->dev, &phy_common->vdda_phy,
283 err = ufs_qcom_phy_init_vreg(phy_common->dev, &phy_common->vddp_ref_clk,
289 EXPORT_SYMBOL_GPL(ufs_qcom_phy_init_vregulators);
291 static int ufs_qcom_phy_cfg_vreg(struct device *dev,
292 struct ufs_qcom_phy_vreg *vreg, bool on)
295 struct regulator *reg = vreg->reg;
296 const char *name = vreg->name;
300 if (regulator_count_voltages(reg) > 0) {
301 min_uV = on ? vreg->min_uV : 0;
302 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
304 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
305 __func__, name, ret);
308 uA_load = on ? vreg->max_uA : 0;
309 ret = regulator_set_load(reg, uA_load);
312 * regulator_set_load() returns new regulator
317 dev_err(dev, "%s: %s set optimum mode(uA_load=%d) failed, err=%d\n",
318 __func__, name, uA_load, ret);
326 static int ufs_qcom_phy_enable_vreg(struct device *dev,
327 struct ufs_qcom_phy_vreg *vreg)
331 if (!vreg || vreg->enabled)
334 ret = ufs_qcom_phy_cfg_vreg(dev, vreg, true);
336 dev_err(dev, "%s: ufs_qcom_phy_cfg_vreg() failed, err=%d\n",
341 ret = regulator_enable(vreg->reg);
343 dev_err(dev, "%s: enable failed, err=%d\n",
348 vreg->enabled = true;
353 static int ufs_qcom_phy_enable_ref_clk(struct ufs_qcom_phy *phy)
357 if (phy->is_ref_clk_enabled)
361 * reference clock is propagated in a daisy-chained manner from
362 * source to phy, so ungate them at each stage.
364 ret = clk_prepare_enable(phy->ref_clk_src);
366 dev_err(phy->dev, "%s: ref_clk_src enable failed %d\n",
372 * "ref_clk_parent" is optional clock hence make sure that clk reference
373 * is available before trying to enable the clock.
375 if (phy->ref_clk_parent) {
376 ret = clk_prepare_enable(phy->ref_clk_parent);
378 dev_err(phy->dev, "%s: ref_clk_parent enable failed %d\n",
380 goto out_disable_src;
384 ret = clk_prepare_enable(phy->ref_clk);
386 dev_err(phy->dev, "%s: ref_clk enable failed %d\n",
388 goto out_disable_parent;
391 phy->is_ref_clk_enabled = true;
395 if (phy->ref_clk_parent)
396 clk_disable_unprepare(phy->ref_clk_parent);
398 clk_disable_unprepare(phy->ref_clk_src);
403 static int ufs_qcom_phy_disable_vreg(struct device *dev,
404 struct ufs_qcom_phy_vreg *vreg)
408 if (!vreg || !vreg->enabled)
411 ret = regulator_disable(vreg->reg);
414 /* ignore errors on applying disable config */
415 ufs_qcom_phy_cfg_vreg(dev, vreg, false);
416 vreg->enabled = false;
418 dev_err(dev, "%s: %s disable failed, err=%d\n",
419 __func__, vreg->name, ret);
425 static void ufs_qcom_phy_disable_ref_clk(struct ufs_qcom_phy *phy)
427 if (phy->is_ref_clk_enabled) {
428 clk_disable_unprepare(phy->ref_clk);
430 * "ref_clk_parent" is optional clock hence make sure that clk
431 * reference is available before trying to disable the clock.
433 if (phy->ref_clk_parent)
434 clk_disable_unprepare(phy->ref_clk_parent);
435 clk_disable_unprepare(phy->ref_clk_src);
436 phy->is_ref_clk_enabled = false;
440 /* Turn ON M-PHY RMMI interface clocks */
441 static int ufs_qcom_phy_enable_iface_clk(struct ufs_qcom_phy *phy)
445 if (phy->is_iface_clk_enabled)
448 ret = clk_prepare_enable(phy->tx_iface_clk);
450 dev_err(phy->dev, "%s: tx_iface_clk enable failed %d\n",
454 ret = clk_prepare_enable(phy->rx_iface_clk);
456 clk_disable_unprepare(phy->tx_iface_clk);
457 dev_err(phy->dev, "%s: rx_iface_clk enable failed %d. disabling also tx_iface_clk\n",
461 phy->is_iface_clk_enabled = true;
467 /* Turn OFF M-PHY RMMI interface clocks */
468 static void ufs_qcom_phy_disable_iface_clk(struct ufs_qcom_phy *phy)
470 if (phy->is_iface_clk_enabled) {
471 clk_disable_unprepare(phy->tx_iface_clk);
472 clk_disable_unprepare(phy->rx_iface_clk);
473 phy->is_iface_clk_enabled = false;
477 static int ufs_qcom_phy_start_serdes(struct ufs_qcom_phy *ufs_qcom_phy)
481 if (!ufs_qcom_phy->phy_spec_ops->start_serdes) {
482 dev_err(ufs_qcom_phy->dev, "%s: start_serdes() callback is not supported\n",
486 ufs_qcom_phy->phy_spec_ops->start_serdes(ufs_qcom_phy);
492 int ufs_qcom_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes)
494 struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
497 if (!ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable) {
498 dev_err(ufs_qcom_phy->dev, "%s: set_tx_lane_enable() callback is not supported\n",
502 ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable(ufs_qcom_phy,
508 EXPORT_SYMBOL_GPL(ufs_qcom_phy_set_tx_lane_enable);
510 void ufs_qcom_phy_save_controller_version(struct phy *generic_phy,
511 u8 major, u16 minor, u16 step)
513 struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
515 ufs_qcom_phy->host_ctrl_rev_major = major;
516 ufs_qcom_phy->host_ctrl_rev_minor = minor;
517 ufs_qcom_phy->host_ctrl_rev_step = step;
519 EXPORT_SYMBOL_GPL(ufs_qcom_phy_save_controller_version);
521 static int ufs_qcom_phy_is_pcs_ready(struct ufs_qcom_phy *ufs_qcom_phy)
523 if (!ufs_qcom_phy->phy_spec_ops->is_physical_coding_sublayer_ready) {
524 dev_err(ufs_qcom_phy->dev, "%s: is_physical_coding_sublayer_ready() callback is not supported\n",
529 return ufs_qcom_phy->phy_spec_ops->
530 is_physical_coding_sublayer_ready(ufs_qcom_phy);
533 int ufs_qcom_phy_power_on(struct phy *generic_phy)
535 struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
536 struct device *dev = phy_common->dev;
537 bool is_rate_B = false;
540 err = ufs_qcom_phy_get_reset(phy_common);
544 err = reset_control_assert(phy_common->ufs_reset);
548 if (phy_common->mode == PHY_MODE_UFS_HS_B)
551 err = phy_common->phy_spec_ops->calibrate(phy_common, is_rate_B);
555 err = reset_control_deassert(phy_common->ufs_reset);
557 dev_err(dev, "Failed to assert UFS PHY reset");
561 err = ufs_qcom_phy_start_serdes(phy_common);
565 err = ufs_qcom_phy_is_pcs_ready(phy_common);
569 err = ufs_qcom_phy_enable_vreg(dev, &phy_common->vdda_phy);
571 dev_err(dev, "%s enable vdda_phy failed, err=%d\n",
576 phy_common->phy_spec_ops->power_control(phy_common, true);
578 /* vdda_pll also enables ref clock LDOs so enable it first */
579 err = ufs_qcom_phy_enable_vreg(dev, &phy_common->vdda_pll);
581 dev_err(dev, "%s enable vdda_pll failed, err=%d\n",
583 goto out_disable_phy;
586 err = ufs_qcom_phy_enable_iface_clk(phy_common);
588 dev_err(dev, "%s enable phy iface clock failed, err=%d\n",
590 goto out_disable_pll;
593 err = ufs_qcom_phy_enable_ref_clk(phy_common);
595 dev_err(dev, "%s enable phy ref clock failed, err=%d\n",
597 goto out_disable_iface_clk;
600 /* enable device PHY ref_clk pad rail */
601 if (phy_common->vddp_ref_clk.reg) {
602 err = ufs_qcom_phy_enable_vreg(dev,
603 &phy_common->vddp_ref_clk);
605 dev_err(dev, "%s enable vddp_ref_clk failed, err=%d\n",
607 goto out_disable_ref_clk;
614 ufs_qcom_phy_disable_ref_clk(phy_common);
615 out_disable_iface_clk:
616 ufs_qcom_phy_disable_iface_clk(phy_common);
618 ufs_qcom_phy_disable_vreg(dev, &phy_common->vdda_pll);
620 ufs_qcom_phy_disable_vreg(dev, &phy_common->vdda_phy);
624 EXPORT_SYMBOL_GPL(ufs_qcom_phy_power_on);
626 int ufs_qcom_phy_power_off(struct phy *generic_phy)
628 struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
630 phy_common->phy_spec_ops->power_control(phy_common, false);
632 if (phy_common->vddp_ref_clk.reg)
633 ufs_qcom_phy_disable_vreg(phy_common->dev,
634 &phy_common->vddp_ref_clk);
635 ufs_qcom_phy_disable_ref_clk(phy_common);
636 ufs_qcom_phy_disable_iface_clk(phy_common);
638 ufs_qcom_phy_disable_vreg(phy_common->dev, &phy_common->vdda_pll);
639 ufs_qcom_phy_disable_vreg(phy_common->dev, &phy_common->vdda_phy);
640 reset_control_assert(phy_common->ufs_reset);
643 EXPORT_SYMBOL_GPL(ufs_qcom_phy_power_off);
645 MODULE_AUTHOR("Yaniv Gardi <ygardi@codeaurora.org>");
646 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
647 MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY");
648 MODULE_LICENSE("GPL v2");