drivers/phy/ti/phy-ti-pipe3.c

   1 /*
   2  * phy-ti-pipe3 - PIPE3 PHY driver.
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * Author: Kishon Vijay Abraham I <kishon@ti.com>
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22 #include <linux/phy/phy.h>
  23 #include <linux/of.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/io.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/delay.h>
  29 #include <linux/phy/omap_control_phy.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/mfd/syscon.h>
  32 #include <linux/regmap.h>
  33
  34 #define PLL_STATUS              0x00000004
  35 #define PLL_GO                  0x00000008
  36 #define PLL_CONFIGURATION1      0x0000000C
  37 #define PLL_CONFIGURATION2      0x00000010
  38 #define PLL_CONFIGURATION3      0x00000014
  39 #define PLL_CONFIGURATION4      0x00000020
  40
  41 #define PLL_REGM_MASK           0x001FFE00
  42 #define PLL_REGM_SHIFT          0x9
  43 #define PLL_REGM_F_MASK         0x0003FFFF
  44 #define PLL_REGM_F_SHIFT        0x0
  45 #define PLL_REGN_MASK           0x000001FE
  46 #define PLL_REGN_SHIFT          0x1
  47 #define PLL_SELFREQDCO_MASK     0x0000000E
  48 #define PLL_SELFREQDCO_SHIFT    0x1
  49 #define PLL_SD_MASK             0x0003FC00
  50 #define PLL_SD_SHIFT            10
  51 #define SET_PLL_GO              0x1
  52 #define PLL_LDOPWDN             BIT(15)
  53 #define PLL_TICOPWDN            BIT(16)
  54 #define PLL_LOCK                0x2
  55 #define PLL_IDLE                0x1
  56
  57 #define SATA_PLL_SOFT_RESET     BIT(18)
  58
  59 #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK   0x003FC000
  60 #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT  14
  61
  62 #define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK  0xFFC00000
  63 #define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22
  64
  65 #define PIPE3_PHY_TX_RX_POWERON         0x3
  66 #define PIPE3_PHY_TX_RX_POWEROFF        0x0
  67
  68 #define PCIE_PCS_MASK                   0xFF0000
  69 #define PCIE_PCS_DELAY_COUNT_SHIFT      0x10
  70
  71 #define PIPE3_PHY_RX_ANA_PROGRAMMABILITY        0x0000000C
  72 #define INTERFACE_MASK                  GENMASK(31, 27)
  73 #define INTERFACE_SHIFT                 27
  74 #define INTERFACE_MODE_USBSS            BIT(4)
  75 #define INTERFACE_MODE_SATA_1P5         BIT(3)
  76 #define INTERFACE_MODE_SATA_3P0         BIT(2)
  77 #define INTERFACE_MODE_PCIE             BIT(0)
  78
  79 #define LOSD_MASK                       GENMASK(17, 14)
  80 #define LOSD_SHIFT                      14
  81 #define MEM_PLLDIV                      GENMASK(6, 5)
  82
  83 #define PIPE3_PHY_RX_TRIM               0x0000001C
  84 #define MEM_DLL_TRIM_SEL_MASK           GENMASK(31, 30)
  85 #define MEM_DLL_TRIM_SHIFT              30
  86
  87 #define PIPE3_PHY_RX_DLL                0x00000024
  88 #define MEM_DLL_PHINT_RATE_MASK         GENMASK(31, 30)
  89 #define MEM_DLL_PHINT_RATE_SHIFT        30
  90
  91 #define PIPE3_PHY_RX_DIGITAL_MODES              0x00000028
  92 #define MEM_HS_RATE_MASK                GENMASK(28, 27)
  93 #define MEM_HS_RATE_SHIFT               27
  94 #define MEM_OVRD_HS_RATE                BIT(26)
  95 #define MEM_OVRD_HS_RATE_SHIFT          26
  96 #define MEM_CDR_FASTLOCK                BIT(23)
  97 #define MEM_CDR_FASTLOCK_SHIFT          23
  98 #define MEM_CDR_LBW_MASK                GENMASK(22, 21)
  99 #define MEM_CDR_LBW_SHIFT               21
 100 #define MEM_CDR_STEPCNT_MASK            GENMASK(20, 19)
 101 #define MEM_CDR_STEPCNT_SHIFT           19
 102 #define MEM_CDR_STL_MASK                GENMASK(18, 16)
 103 #define MEM_CDR_STL_SHIFT               16
 104 #define MEM_CDR_THR_MASK                GENMASK(15, 13)
 105 #define MEM_CDR_THR_SHIFT               13
 106 #define MEM_CDR_THR_MODE                BIT(12)
 107 #define MEM_CDR_THR_MODE_SHIFT          12
 108 #define MEM_CDR_2NDO_SDM_MODE           BIT(11)
 109 #define MEM_CDR_2NDO_SDM_MODE_SHIFT     11
 110
 111 #define PIPE3_PHY_RX_EQUALIZER          0x00000038
 112 #define MEM_EQLEV_MASK                  GENMASK(31, 16)
 113 #define MEM_EQLEV_SHIFT                 16
 114 #define MEM_EQFTC_MASK                  GENMASK(15, 11)
 115 #define MEM_EQFTC_SHIFT                 11
 116 #define MEM_EQCTL_MASK                  GENMASK(10, 7)
 117 #define MEM_EQCTL_SHIFT                 7
 118 #define MEM_OVRD_EQLEV                  BIT(2)
 119 #define MEM_OVRD_EQLEV_SHIFT            2
 120 #define MEM_OVRD_EQFTC                  BIT(1)
 121 #define MEM_OVRD_EQFTC_SHIFT            1
 122
 123 #define SATA_PHY_RX_IO_AND_A2D_OVERRIDES        0x44
 124 #define MEM_CDR_LOS_SOURCE_MASK         GENMASK(10, 9)
 125 #define MEM_CDR_LOS_SOURCE_SHIFT        9
 126
 127 /*
 128  * This is an Empirical value that works, need to confirm the actual
 129  * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
 130  * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
 131  */
 132 #define PLL_IDLE_TIME   100     /* in milliseconds */
 133 #define PLL_LOCK_TIME   100     /* in milliseconds */
 134
 135 enum pipe3_mode { PIPE3_MODE_PCIE = 1,
 136                   PIPE3_MODE_SATA,
 137                   PIPE3_MODE_USBSS };
 138
 139 struct pipe3_dpll_params {
 140         u16     m;
 141         u8      n;
 142         u8      freq:3;
 143         u8      sd;
 144         u32     mf;
 145 };
 146
 147 struct pipe3_dpll_map {
 148         unsigned long rate;
 149         struct pipe3_dpll_params params;
 150 };
 151
 152 struct pipe3_settings {
 153         u8 ana_interface;
 154         u8 ana_losd;
 155         u8 dig_fastlock;
 156         u8 dig_lbw;
 157         u8 dig_stepcnt;
 158         u8 dig_stl;
 159         u8 dig_thr;
 160         u8 dig_thr_mode;
 161         u8 dig_2ndo_sdm_mode;
 162         u8 dig_hs_rate;
 163         u8 dig_ovrd_hs_rate;
 164         u8 dll_trim_sel;
 165         u8 dll_phint_rate;
 166         u8 eq_lev;
 167         u8 eq_ftc;
 168         u8 eq_ctl;
 169         u8 eq_ovrd_lev;
 170         u8 eq_ovrd_ftc;
 171 };
 172
 173 struct ti_pipe3 {
 174         void __iomem            *pll_ctrl_base;
 175         void __iomem            *phy_rx;
 176         void __iomem            *phy_tx;
 177         struct device           *dev;
 178         struct device           *control_dev;
 179         struct clk              *wkupclk;
 180         struct clk              *sys_clk;
 181         struct clk              *refclk;
 182         struct clk              *div_clk;
 183         struct pipe3_dpll_map   *dpll_map;
 184         struct regmap           *phy_power_syscon; /* ctrl. reg. acces */
 185         struct regmap           *pcs_syscon; /* ctrl. reg. acces */
 186         struct regmap           *dpll_reset_syscon; /* ctrl. reg. acces */
 187         unsigned int            dpll_reset_reg; /* reg. index within syscon */
 188         unsigned int            power_reg; /* power reg. index within syscon */
 189         unsigned int            pcie_pcs_reg; /* pcs reg. index in syscon */
 190         bool                    sata_refclk_enabled;
 191         enum pipe3_mode         mode;
 192         struct pipe3_settings   settings;
 193 };
 194
 195 static struct pipe3_dpll_map dpll_map_usb[] = {
 196         {12000000, {1250, 5, 4, 20, 0} },       /* 12 MHz */
 197         {16800000, {3125, 20, 4, 20, 0} },      /* 16.8 MHz */
 198         {19200000, {1172, 8, 4, 20, 65537} },   /* 19.2 MHz */
 199         {20000000, {1000, 7, 4, 10, 0} },       /* 20 MHz */
 200         {26000000, {1250, 12, 4, 20, 0} },      /* 26 MHz */
 201         {38400000, {3125, 47, 4, 20, 92843} },  /* 38.4 MHz */
 202         { },                                    /* Terminator */
 203 };
 204
 205 static struct pipe3_dpll_map dpll_map_sata[] = {
 206         {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
 207         {16800000, {625, 6, 4, 7, 0} },         /* 16.8 MHz */
 208         {19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
 209         {20000000, {750, 9, 4, 6, 0} },         /* 20 MHz */
 210         {26000000, {750, 12, 4, 6, 0} },        /* 26 MHz */
 211         {38400000, {625, 15, 4, 6, 0} },        /* 38.4 MHz */
 212         { },                                    /* Terminator */
 213 };
 214
 215 struct pipe3_data {
 216         enum pipe3_mode mode;
 217         struct pipe3_dpll_map *dpll_map;
 218         struct pipe3_settings settings;
 219 };
 220
 221 static struct pipe3_data data_usb = {
 222         .mode = PIPE3_MODE_USBSS,
 223         .dpll_map = dpll_map_usb,
 224         .settings = {
 225         /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
 226                 .ana_interface = INTERFACE_MODE_USBSS,
 227                 .ana_losd = 0xa,
 228                 .dig_fastlock = 1,
 229                 .dig_lbw = 3,
 230                 .dig_stepcnt = 0,
 231                 .dig_stl = 0x3,
 232                 .dig_thr = 1,
 233                 .dig_thr_mode = 1,
 234                 .dig_2ndo_sdm_mode = 0,
 235                 .dig_hs_rate = 0,
 236                 .dig_ovrd_hs_rate = 1,
 237                 .dll_trim_sel = 0x2,
 238                 .dll_phint_rate = 0x3,
 239                 .eq_lev = 0,
 240                 .eq_ftc = 0,
 241                 .eq_ctl = 0x9,
 242                 .eq_ovrd_lev = 0,
 243                 .eq_ovrd_ftc = 0,
 244         },
 245 };
 246
 247 static struct pipe3_data data_sata = {
 248         .mode = PIPE3_MODE_SATA,
 249         .dpll_map = dpll_map_sata,
 250         .settings = {
 251         /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
 252                 .ana_interface = INTERFACE_MODE_SATA_3P0,
 253                 .ana_losd = 0x5,
 254                 .dig_fastlock = 1,
 255                 .dig_lbw = 3,
 256                 .dig_stepcnt = 0,
 257                 .dig_stl = 0x3,
 258                 .dig_thr = 1,
 259                 .dig_thr_mode = 1,
 260                 .dig_2ndo_sdm_mode = 0,
 261                 .dig_hs_rate = 0,       /* Not in TRM preferred settings */
 262                 .dig_ovrd_hs_rate = 0,  /* Not in TRM preferred settings */
 263                 .dll_trim_sel = 0x1,
 264                 .dll_phint_rate = 0x2,  /* for 1.5 GHz DPLL clock */
 265                 .eq_lev = 0,
 266                 .eq_ftc = 0x1f,
 267                 .eq_ctl = 0,
 268                 .eq_ovrd_lev = 1,
 269                 .eq_ovrd_ftc = 1,
 270         },
 271 };
 272
 273 static struct pipe3_data data_pcie = {
 274         .mode = PIPE3_MODE_PCIE,
 275         .settings = {
 276         /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
 277                 .ana_interface = INTERFACE_MODE_PCIE,
 278                 .ana_losd = 0xa,
 279                 .dig_fastlock = 1,
 280                 .dig_lbw = 3,
 281                 .dig_stepcnt = 0,
 282                 .dig_stl = 0x3,
 283                 .dig_thr = 1,
 284                 .dig_thr_mode = 1,
 285                 .dig_2ndo_sdm_mode = 0,
 286                 .dig_hs_rate = 0,
 287                 .dig_ovrd_hs_rate = 0,
 288                 .dll_trim_sel = 0x2,
 289                 .dll_phint_rate = 0x3,
 290                 .eq_lev = 0,
 291                 .eq_ftc = 0x1f,
 292                 .eq_ctl = 1,
 293                 .eq_ovrd_lev = 0,
 294                 .eq_ovrd_ftc = 0,
 295         },
 296 };
 297
 298 static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
 299 {
 300         return __raw_readl(addr + offset);
 301 }
 302
 303 static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
 304         u32 data)
 305 {
 306         __raw_writel(data, addr + offset);
 307 }
 308
 309 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
 310 {
 311         unsigned long rate;
 312         struct pipe3_dpll_map *dpll_map = phy->dpll_map;
 313
 314         rate = clk_get_rate(phy->sys_clk);
 315
 316         for (; dpll_map->rate; dpll_map++) {
 317                 if (rate == dpll_map->rate)
 318                         return &dpll_map->params;
 319         }
 320
 321         dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
 322
 323         return NULL;
 324 }
 325
 326 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy);
 327 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
 328
 329 static int ti_pipe3_power_off(struct phy *x)
 330 {
 331         u32 val;
 332         int ret;
 333         struct ti_pipe3 *phy = phy_get_drvdata(x);
 334
 335         if (!phy->phy_power_syscon) {
 336                 omap_control_phy_power(phy->control_dev, 0);
 337                 return 0;
 338         }
 339
 340         val = PIPE3_PHY_TX_RX_POWEROFF << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
 341
 342         ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
 343                                  PIPE3_PHY_PWRCTL_CLK_CMD_MASK, val);
 344         return ret;
 345 }
 346
 347 static int ti_pipe3_power_on(struct phy *x)
 348 {
 349         u32 val;
 350         u32 mask;
 351         int ret;
 352         unsigned long rate;
 353         struct ti_pipe3 *phy = phy_get_drvdata(x);
 354
 355         if (!phy->phy_power_syscon) {
 356                 omap_control_phy_power(phy->control_dev, 1);
 357                 return 0;
 358         }
 359
 360         rate = clk_get_rate(phy->sys_clk);
 361         if (!rate) {
 362                 dev_err(phy->dev, "Invalid clock rate\n");
 363                 return -EINVAL;
 364         }
 365         rate = rate / 1000000;
 366         mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
 367                   OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK;
 368         val = PIPE3_PHY_TX_RX_POWERON << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
 369         val |= rate << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
 370
 371         ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
 372                                  mask, val);
 373         return ret;
 374 }
 375
 376 static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
 377 {
 378         u32             val;
 379         unsigned long   timeout;
 380
 381         timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
 382         do {
 383                 cpu_relax();
 384                 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 385                 if (val & PLL_LOCK)
 386                         return 0;
 387         } while (!time_after(jiffies, timeout));
 388
 389         dev_err(phy->dev, "DPLL failed to lock\n");
 390         return -EBUSY;
 391 }
 392
 393 static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
 394 {
 395         u32                     val;
 396         struct pipe3_dpll_params *dpll_params;
 397
 398         dpll_params = ti_pipe3_get_dpll_params(phy);
 399         if (!dpll_params)
 400                 return -EINVAL;
 401
 402         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 403         val &= ~PLL_REGN_MASK;
 404         val |= dpll_params->n << PLL_REGN_SHIFT;
 405         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 406
 407         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 408         val &= ~PLL_SELFREQDCO_MASK;
 409         val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
 410         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 411
 412         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 413         val &= ~PLL_REGM_MASK;
 414         val |= dpll_params->m << PLL_REGM_SHIFT;
 415         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 416
 417         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
 418         val &= ~PLL_REGM_F_MASK;
 419         val |= dpll_params->mf << PLL_REGM_F_SHIFT;
 420         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
 421
 422         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
 423         val &= ~PLL_SD_MASK;
 424         val |= dpll_params->sd << PLL_SD_SHIFT;
 425         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
 426
 427         ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
 428
 429         return ti_pipe3_dpll_wait_lock(phy);
 430 }
 431
 432 static void ti_pipe3_calibrate(struct ti_pipe3 *phy)
 433 {
 434         u32 val;
 435         struct pipe3_settings *s = &phy->settings;
 436
 437         val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
 438         val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
 439         val |= (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT);
 440         ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
 441
 442         val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
 443         val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK |
 444                  MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK |
 445                  MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE);
 446         val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT |
 447                 s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT |
 448                 s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT |
 449                 s->dig_lbw << MEM_CDR_LBW_SHIFT |
 450                 s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT |
 451                 s->dig_stl << MEM_CDR_STL_SHIFT |
 452                 s->dig_thr << MEM_CDR_THR_SHIFT |
 453                 s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT |
 454                 s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT;
 455         ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
 456
 457         val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
 458         val &= ~MEM_DLL_TRIM_SEL_MASK;
 459         val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT;
 460         ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
 461
 462         val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
 463         val &= ~MEM_DLL_PHINT_RATE_MASK;
 464         val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT;
 465         ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
 466
 467         val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
 468         val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK |
 469                  MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
 470         val |= s->eq_lev << MEM_EQLEV_SHIFT |
 471                 s->eq_ftc << MEM_EQFTC_SHIFT |
 472                 s->eq_ctl << MEM_EQCTL_SHIFT |
 473                 s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT |
 474                 s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT;
 475         ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
 476
 477         if (phy->mode == PIPE3_MODE_SATA) {
 478                 val = ti_pipe3_readl(phy->phy_rx,
 479                                      SATA_PHY_RX_IO_AND_A2D_OVERRIDES);
 480                 val &= ~MEM_CDR_LOS_SOURCE_MASK;
 481                 ti_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
 482                                 val);
 483         }
 484 }
 485
 486 static int ti_pipe3_init(struct phy *x)
 487 {
 488         struct ti_pipe3 *phy = phy_get_drvdata(x);
 489         u32 val;
 490         int ret = 0;
 491
 492         ti_pipe3_enable_clocks(phy);
 493         /*
 494          * Set pcie_pcs register to 0x96 for proper functioning of phy
 495          * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
 496          * 18-1804.
 497          */
 498         if (phy->mode == PIPE3_MODE_PCIE) {
 499                 if (!phy->pcs_syscon) {
 500                         omap_control_pcie_pcs(phy->control_dev, 0x96);
 501                         return 0;
 502                 }
 503
 504                 val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT;
 505                 ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg,
 506                                          PCIE_PCS_MASK, val);
 507                 if (ret)
 508                         return ret;
 509
 510                 ti_pipe3_calibrate(phy);
 511
 512                 return 0;
 513         }
 514
 515         /* Bring it out of IDLE if it is IDLE */
 516         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 517         if (val & PLL_IDLE) {
 518                 val &= ~PLL_IDLE;
 519                 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 520                 ret = ti_pipe3_dpll_wait_lock(phy);
 521         }
 522
 523         /* SATA has issues if re-programmed when locked */
 524         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 525         if ((val & PLL_LOCK) && phy->mode == PIPE3_MODE_SATA)
 526                 return ret;
 527
 528         /* Program the DPLL */
 529         ret = ti_pipe3_dpll_program(phy);
 530         if (ret) {
 531                 ti_pipe3_disable_clocks(phy);
 532                 return -EINVAL;
 533         }
 534
 535         ti_pipe3_calibrate(phy);
 536
 537         return ret;
 538 }
 539
 540 static int ti_pipe3_exit(struct phy *x)
 541 {
 542         struct ti_pipe3 *phy = phy_get_drvdata(x);
 543         u32 val;
 544         unsigned long timeout;
 545
 546         /* If dpll_reset_syscon is not present we wont power down SATA DPLL
 547          * due to Errata i783
 548          */
 549         if (phy->mode == PIPE3_MODE_SATA && !phy->dpll_reset_syscon)
 550                 return 0;
 551
 552         /* PCIe doesn't have internal DPLL */
 553         if (phy->mode != PIPE3_MODE_PCIE) {
 554                 /* Put DPLL in IDLE mode */
 555                 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 556                 val |= PLL_IDLE;
 557                 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 558
 559                 /* wait for LDO and Oscillator to power down */
 560                 timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
 561                 do {
 562                         cpu_relax();
 563                         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 564                         if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
 565                                 break;
 566                 } while (!time_after(jiffies, timeout));
 567
 568                 if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
 569                         dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
 570                                 val);
 571                         return -EBUSY;
 572                 }
 573         }
 574
 575         /* i783: SATA needs control bit toggle after PLL unlock */
 576         if (phy->mode == PIPE3_MODE_SATA) {
 577                 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
 578                                    SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET);
 579                 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
 580                                    SATA_PLL_SOFT_RESET, 0);
 581         }
 582
 583         ti_pipe3_disable_clocks(phy);
 584
 585         return 0;
 586 }
 587 static const struct phy_ops ops = {
 588         .init           = ti_pipe3_init,
 589         .exit           = ti_pipe3_exit,
 590         .power_on       = ti_pipe3_power_on,
 591         .power_off      = ti_pipe3_power_off,
 592         .owner          = THIS_MODULE,
 593 };
 594
 595 static const struct of_device_id ti_pipe3_id_table[];
 596
 597 static int ti_pipe3_get_clk(struct ti_pipe3 *phy)
 598 {
 599         struct clk *clk;
 600         struct device *dev = phy->dev;
 601
 602         phy->refclk = devm_clk_get(dev, "refclk");
 603         if (IS_ERR(phy->refclk)) {
 604                 dev_err(dev, "unable to get refclk\n");
 605                 /* older DTBs have missing refclk in SATA PHY
 606                  * so don't bail out in case of SATA PHY.
 607                  */
 608                 if (phy->mode != PIPE3_MODE_SATA)
 609                         return PTR_ERR(phy->refclk);
 610         }
 611
 612         if (phy->mode != PIPE3_MODE_SATA) {
 613                 phy->wkupclk = devm_clk_get(dev, "wkupclk");
 614                 if (IS_ERR(phy->wkupclk)) {
 615                         dev_err(dev, "unable to get wkupclk\n");
 616                         return PTR_ERR(phy->wkupclk);
 617                 }
 618         } else {
 619                 phy->wkupclk = ERR_PTR(-ENODEV);
 620         }
 621
 622         if (phy->mode != PIPE3_MODE_PCIE || phy->phy_power_syscon) {
 623                 phy->sys_clk = devm_clk_get(dev, "sysclk");
 624                 if (IS_ERR(phy->sys_clk)) {
 625                         dev_err(dev, "unable to get sysclk\n");
 626                         return -EINVAL;
 627                 }
 628         }
 629
 630         if (phy->mode == PIPE3_MODE_PCIE) {
 631                 clk = devm_clk_get(dev, "dpll_ref");
 632                 if (IS_ERR(clk)) {
 633                         dev_err(dev, "unable to get dpll ref clk\n");
 634                         return PTR_ERR(clk);
 635                 }
 636                 clk_set_rate(clk, 1500000000);
 637
 638                 clk = devm_clk_get(dev, "dpll_ref_m2");
 639                 if (IS_ERR(clk)) {
 640                         dev_err(dev, "unable to get dpll ref m2 clk\n");
 641                         return PTR_ERR(clk);
 642                 }
 643                 clk_set_rate(clk, 100000000);
 644
 645                 clk = devm_clk_get(dev, "phy-div");
 646                 if (IS_ERR(clk)) {
 647                         dev_err(dev, "unable to get phy-div clk\n");
 648                         return PTR_ERR(clk);
 649                 }
 650                 clk_set_rate(clk, 100000000);
 651
 652                 phy->div_clk = devm_clk_get(dev, "div-clk");
 653                 if (IS_ERR(phy->div_clk)) {
 654                         dev_err(dev, "unable to get div-clk\n");
 655                         return PTR_ERR(phy->div_clk);
 656                 }
 657         } else {
 658                 phy->div_clk = ERR_PTR(-ENODEV);
 659         }
 660
 661         return 0;
 662 }
 663
 664 static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy)
 665 {
 666         struct device *dev = phy->dev;
 667         struct device_node *node = dev->of_node;
 668         struct device_node *control_node;
 669         struct platform_device *control_pdev;
 670
 671         phy->phy_power_syscon = syscon_regmap_lookup_by_phandle(node,
 672                                                         "syscon-phy-power");
 673         if (IS_ERR(phy->phy_power_syscon)) {
 674                 dev_dbg(dev,
 675                         "can't get syscon-phy-power, using control device\n");
 676                 phy->phy_power_syscon = NULL;
 677         } else {
 678                 if (of_property_read_u32_index(node,
 679                                                "syscon-phy-power", 1,
 680                                                &phy->power_reg)) {
 681                         dev_err(dev, "couldn't get power reg. offset\n");
 682                         return -EINVAL;
 683                 }
 684         }
 685
 686         if (!phy->phy_power_syscon) {
 687                 control_node = of_parse_phandle(node, "ctrl-module", 0);
 688                 if (!control_node) {
 689                         dev_err(dev, "Failed to get control device phandle\n");
 690                         return -EINVAL;
 691                 }
 692
 693                 control_pdev = of_find_device_by_node(control_node);
 694                 if (!control_pdev) {
 695                         dev_err(dev, "Failed to get control device\n");
 696                         return -EINVAL;
 697                 }
 698
 699                 phy->control_dev = &control_pdev->dev;
 700         }
 701
 702         if (phy->mode == PIPE3_MODE_PCIE) {
 703                 phy->pcs_syscon = syscon_regmap_lookup_by_phandle(node,
 704                                                                   "syscon-pcs");
 705                 if (IS_ERR(phy->pcs_syscon)) {
 706                         dev_dbg(dev,
 707                                 "can't get syscon-pcs, using omap control\n");
 708                         phy->pcs_syscon = NULL;
 709                 } else {
 710                         if (of_property_read_u32_index(node,
 711                                                        "syscon-pcs", 1,
 712                                                        &phy->pcie_pcs_reg)) {
 713                                 dev_err(dev,
 714                                         "couldn't get pcie pcs reg. offset\n");
 715                                 return -EINVAL;
 716                         }
 717                 }
 718         }
 719
 720         if (phy->mode == PIPE3_MODE_SATA) {
 721                 phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node,
 722                                                         "syscon-pllreset");
 723                 if (IS_ERR(phy->dpll_reset_syscon)) {
 724                         dev_info(dev,
 725                                  "can't get syscon-pllreset, sata dpll won't idle\n");
 726                         phy->dpll_reset_syscon = NULL;
 727                 } else {
 728                         if (of_property_read_u32_index(node,
 729                                                        "syscon-pllreset", 1,
 730                                                        &phy->dpll_reset_reg)) {
 731                                 dev_err(dev,
 732                                         "couldn't get pllreset reg. offset\n");
 733                                 return -EINVAL;
 734                         }
 735                 }
 736         }
 737
 738         return 0;
 739 }
 740
 741 static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy)
 742 {
 743         struct resource *res;
 744         struct device *dev = phy->dev;
 745         struct platform_device *pdev = to_platform_device(dev);
 746
 747         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 748                                            "phy_rx");
 749         phy->phy_rx = devm_ioremap_resource(dev, res);
 750         if (IS_ERR(phy->phy_rx))
 751                 return PTR_ERR(phy->phy_rx);
 752
 753         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 754                                            "phy_tx");
 755         phy->phy_tx = devm_ioremap_resource(dev, res);
 756
 757         return PTR_ERR_OR_ZERO(phy->phy_tx);
 758 }
 759
 760 static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy)
 761 {
 762         struct resource *res;
 763         struct device *dev = phy->dev;
 764         struct platform_device *pdev = to_platform_device(dev);
 765
 766         if (phy->mode == PIPE3_MODE_PCIE)
 767                 return 0;
 768
 769         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 770                                            "pll_ctrl");
 771         phy->pll_ctrl_base = devm_ioremap_resource(dev, res);
 772         return PTR_ERR_OR_ZERO(phy->pll_ctrl_base);
 773 }
 774
 775 static int ti_pipe3_probe(struct platform_device *pdev)
 776 {
 777         struct ti_pipe3 *phy;
 778         struct phy *generic_phy;
 779         struct phy_provider *phy_provider;
 780         struct device *dev = &pdev->dev;
 781         int ret;
 782         const struct of_device_id *match;
 783         struct pipe3_data *data;
 784
 785         phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
 786         if (!phy)
 787                 return -ENOMEM;
 788
 789         match = of_match_device(ti_pipe3_id_table, dev);
 790         if (!match)
 791                 return -EINVAL;
 792
 793         data = (struct pipe3_data *)match->data;
 794         if (!data) {
 795                 dev_err(dev, "no driver data\n");
 796                 return -EINVAL;
 797         }
 798
 799         phy->dev = dev;
 800         phy->mode = data->mode;
 801         phy->dpll_map = data->dpll_map;
 802         phy->settings = data->settings;
 803
 804         ret = ti_pipe3_get_pll_base(phy);
 805         if (ret)
 806                 return ret;
 807
 808         ret = ti_pipe3_get_tx_rx_base(phy);
 809         if (ret)
 810                 return ret;
 811
 812         ret = ti_pipe3_get_sysctrl(phy);
 813         if (ret)
 814                 return ret;
 815
 816         ret = ti_pipe3_get_clk(phy);
 817         if (ret)
 818                 return ret;
 819
 820         platform_set_drvdata(pdev, phy);
 821         pm_runtime_enable(dev);
 822
 823         /*
 824          * Prevent auto-disable of refclk for SATA PHY due to Errata i783
 825          */
 826         if (phy->mode == PIPE3_MODE_SATA) {
 827                 if (!IS_ERR(phy->refclk)) {
 828                         clk_prepare_enable(phy->refclk);
 829                         phy->sata_refclk_enabled = true;
 830                 }
 831         }
 832
 833         generic_phy = devm_phy_create(dev, NULL, &ops);
 834         if (IS_ERR(generic_phy))
 835                 return PTR_ERR(generic_phy);
 836
 837         phy_set_drvdata(generic_phy, phy);
 838
 839         ti_pipe3_power_off(generic_phy);
 840
 841         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 842         return PTR_ERR_OR_ZERO(phy_provider);
 843 }
 844
 845 static int ti_pipe3_remove(struct platform_device *pdev)
 846 {
 847         pm_runtime_disable(&pdev->dev);
 848
 849         return 0;
 850 }
 851
 852 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
 853 {
 854         int ret = 0;
 855
 856         if (!IS_ERR(phy->refclk)) {
 857                 ret = clk_prepare_enable(phy->refclk);
 858                 if (ret) {
 859                         dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
 860                         return ret;
 861                 }
 862         }
 863
 864         if (!IS_ERR(phy->wkupclk)) {
 865                 ret = clk_prepare_enable(phy->wkupclk);
 866                 if (ret) {
 867                         dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
 868                         goto disable_refclk;
 869                 }
 870         }
 871
 872         if (!IS_ERR(phy->div_clk)) {
 873                 ret = clk_prepare_enable(phy->div_clk);
 874                 if (ret) {
 875                         dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
 876                         goto disable_wkupclk;
 877                 }
 878         }
 879
 880         return 0;
 881
 882 disable_wkupclk:
 883         if (!IS_ERR(phy->wkupclk))
 884                 clk_disable_unprepare(phy->wkupclk);
 885
 886 disable_refclk:
 887         if (!IS_ERR(phy->refclk))
 888                 clk_disable_unprepare(phy->refclk);
 889
 890         return ret;
 891 }
 892
 893 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
 894 {
 895         if (!IS_ERR(phy->wkupclk))
 896                 clk_disable_unprepare(phy->wkupclk);
 897         if (!IS_ERR(phy->refclk)) {
 898                 clk_disable_unprepare(phy->refclk);
 899                 /*
 900                  * SATA refclk needs an additional disable as we left it
 901                  * on in probe to avoid Errata i783
 902                  */
 903                 if (phy->sata_refclk_enabled) {
 904                         clk_disable_unprepare(phy->refclk);
 905                         phy->sata_refclk_enabled = false;
 906                 }
 907         }
 908
 909         if (!IS_ERR(phy->div_clk))
 910                 clk_disable_unprepare(phy->div_clk);
 911 }
 912
 913 static const struct of_device_id ti_pipe3_id_table[] = {
 914         {
 915                 .compatible = "ti,phy-usb3",
 916                 .data = &data_usb,
 917         },
 918         {
 919                 .compatible = "ti,omap-usb3",
 920                 .data = &data_usb,
 921         },
 922         {
 923                 .compatible = "ti,phy-pipe3-sata",
 924                 .data = &data_sata,
 925         },
 926         {
 927                 .compatible = "ti,phy-pipe3-pcie",
 928                 .data = &data_pcie,
 929         },
 930         {}
 931 };
 932 MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
 933
 934 static struct platform_driver ti_pipe3_driver = {
 935         .probe          = ti_pipe3_probe,
 936         .remove         = ti_pipe3_remove,
 937         .driver         = {
 938                 .name   = "ti-pipe3",
 939                 .of_match_table = ti_pipe3_id_table,
 940         },
 941 };
 942
 943 module_platform_driver(ti_pipe3_driver);
 944
 945 MODULE_ALIAS("platform:ti_pipe3");
 946 MODULE_AUTHOR("Texas Instruments Inc.");
 947 MODULE_DESCRIPTION("TI PIPE3 phy driver");
 948 MODULE_LICENSE("GPL v2");