1 // SPDX-License-Identifier: GPL-2.0+
3 * OWL SoC's Pinctrl driver
5 * Copyright (c) 2014 Actions Semi Inc.
6 * Author: David Liu <liuwei@actions-semi.com>
8 * Copyright (c) 2018 Linaro Ltd.
9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12 #include <linux/clk.h>
13 #include <linux/err.h>
14 #include <linux/gpio/driver.h>
16 #include <linux/irq.h>
17 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/pinctrl/machine.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
29 #include "../pinctrl-utils.h"
30 #include "pinctrl-owl.h"
33 * struct owl_pinctrl - pinctrl state of the device
35 * @pctrldev: pinctrl handle
37 * @lock: spinlock to protect registers
38 * @soc: reference to soc_data
39 * @base: pinctrl register base address
43 struct pinctrl_dev *pctrldev;
44 struct gpio_chip chip;
47 const struct owl_pinctrl_soc_data *soc;
49 struct irq_chip irq_chip;
54 static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
58 reg_val = readl_relaxed(base);
60 reg_val = (reg_val & ~mask) | (val & mask);
62 writel_relaxed(reg_val, base);
65 static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg,
70 tmp = readl_relaxed(pctrl->base + reg);
71 mask = (1 << width) - 1;
73 return (tmp >> bit) & mask;
76 static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg,
81 mask = (1 << width) - 1;
84 owl_update_bits(pctrl->base + reg, mask, (arg << bit));
87 static int owl_get_groups_count(struct pinctrl_dev *pctrldev)
89 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
91 return pctrl->soc->ngroups;
94 static const char *owl_get_group_name(struct pinctrl_dev *pctrldev,
97 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
99 return pctrl->soc->groups[group].name;
102 static int owl_get_group_pins(struct pinctrl_dev *pctrldev,
104 const unsigned int **pins,
105 unsigned int *num_pins)
107 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
109 *pins = pctrl->soc->groups[group].pads;
110 *num_pins = pctrl->soc->groups[group].npads;
115 static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev,
119 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
121 seq_printf(s, "%s", dev_name(pctrl->dev));
124 static struct pinctrl_ops owl_pinctrl_ops = {
125 .get_groups_count = owl_get_groups_count,
126 .get_group_name = owl_get_group_name,
127 .get_group_pins = owl_get_group_pins,
128 .pin_dbg_show = owl_pin_dbg_show,
129 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
130 .dt_free_map = pinctrl_utils_free_map,
133 static int owl_get_funcs_count(struct pinctrl_dev *pctrldev)
135 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
137 return pctrl->soc->nfunctions;
140 static const char *owl_get_func_name(struct pinctrl_dev *pctrldev,
141 unsigned int function)
143 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
145 return pctrl->soc->functions[function].name;
148 static int owl_get_func_groups(struct pinctrl_dev *pctrldev,
149 unsigned int function,
150 const char * const **groups,
151 unsigned int * const num_groups)
153 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
155 *groups = pctrl->soc->functions[function].groups;
156 *num_groups = pctrl->soc->functions[function].ngroups;
161 static inline int get_group_mfp_mask_val(const struct owl_pingroup *g,
170 for (id = 0; id < g->nfuncs; id++) {
171 if (g->funcs[id] == function)
174 if (WARN_ON(id == g->nfuncs))
177 option_num = (1 << g->mfpctl_width);
181 option_mask = option_num - 1;
182 *mask = (option_mask << g->mfpctl_shift);
183 *val = (id << g->mfpctl_shift);
188 static int owl_set_mux(struct pinctrl_dev *pctrldev,
189 unsigned int function,
192 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
193 const struct owl_pingroup *g;
197 g = &pctrl->soc->groups[group];
199 if (get_group_mfp_mask_val(g, function, &mask, &val))
202 raw_spin_lock_irqsave(&pctrl->lock, flags);
204 owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val);
206 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
211 static struct pinmux_ops owl_pinmux_ops = {
212 .get_functions_count = owl_get_funcs_count,
213 .get_function_name = owl_get_func_name,
214 .get_function_groups = owl_get_func_groups,
215 .set_mux = owl_set_mux,
218 static int owl_pad_pinconf_reg(const struct owl_padinfo *info,
225 case PIN_CONFIG_BIAS_BUS_HOLD:
226 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
227 case PIN_CONFIG_BIAS_PULL_DOWN:
228 case PIN_CONFIG_BIAS_PULL_UP:
231 *reg = info->pullctl->reg;
232 *bit = info->pullctl->shift;
233 *width = info->pullctl->width;
235 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
238 *reg = info->st->reg;
239 *bit = info->st->shift;
240 *width = info->st->width;
249 static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
251 unsigned long *config)
254 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
255 const struct owl_padinfo *info;
256 unsigned int param = pinconf_to_config_param(*config);
257 u32 reg, bit, width, arg;
259 info = &pctrl->soc->padinfo[pin];
261 ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width);
265 arg = owl_read_field(pctrl, reg, bit, width);
267 if (!pctrl->soc->padctl_val2arg)
270 ret = pctrl->soc->padctl_val2arg(info, param, &arg);
274 *config = pinconf_to_config_packed(param, arg);
279 static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
281 unsigned long *configs,
282 unsigned int num_configs)
284 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
285 const struct owl_padinfo *info;
288 u32 reg, bit, width, arg;
291 info = &pctrl->soc->padinfo[pin];
293 for (i = 0; i < num_configs; i++) {
294 param = pinconf_to_config_param(configs[i]);
295 arg = pinconf_to_config_argument(configs[i]);
297 ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width);
301 if (!pctrl->soc->padctl_arg2val)
304 ret = pctrl->soc->padctl_arg2val(info, param, &arg);
308 raw_spin_lock_irqsave(&pctrl->lock, flags);
310 owl_write_field(pctrl, reg, arg, bit, width);
312 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
318 static int owl_group_pinconf_reg(const struct owl_pingroup *g,
325 case PIN_CONFIG_DRIVE_STRENGTH:
330 *width = g->drv_width;
332 case PIN_CONFIG_SLEW_RATE:
337 *width = g->sr_width;
346 static int owl_group_pinconf_arg2val(const struct owl_pingroup *g,
351 case PIN_CONFIG_DRIVE_STRENGTH:
354 *arg = OWL_PINCONF_DRV_2MA;
357 *arg = OWL_PINCONF_DRV_4MA;
360 *arg = OWL_PINCONF_DRV_8MA;
363 *arg = OWL_PINCONF_DRV_12MA;
369 case PIN_CONFIG_SLEW_RATE:
371 *arg = OWL_PINCONF_SLEW_FAST;
373 *arg = OWL_PINCONF_SLEW_SLOW;
382 static int owl_group_pinconf_val2arg(const struct owl_pingroup *g,
387 case PIN_CONFIG_DRIVE_STRENGTH:
389 case OWL_PINCONF_DRV_2MA:
392 case OWL_PINCONF_DRV_4MA:
395 case OWL_PINCONF_DRV_8MA:
398 case OWL_PINCONF_DRV_12MA:
405 case PIN_CONFIG_SLEW_RATE:
418 static int owl_group_config_get(struct pinctrl_dev *pctrldev,
420 unsigned long *config)
422 const struct owl_pingroup *g;
423 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
424 unsigned int param = pinconf_to_config_param(*config);
425 u32 reg, bit, width, arg;
428 g = &pctrl->soc->groups[group];
430 ret = owl_group_pinconf_reg(g, param, ®, &bit, &width);
434 arg = owl_read_field(pctrl, reg, bit, width);
436 ret = owl_group_pinconf_val2arg(g, param, &arg);
440 *config = pinconf_to_config_packed(param, arg);
446 static int owl_group_config_set(struct pinctrl_dev *pctrldev,
448 unsigned long *configs,
449 unsigned int num_configs)
451 const struct owl_pingroup *g;
452 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
455 u32 reg, bit, width, arg;
458 g = &pctrl->soc->groups[group];
460 for (i = 0; i < num_configs; i++) {
461 param = pinconf_to_config_param(configs[i]);
462 arg = pinconf_to_config_argument(configs[i]);
464 ret = owl_group_pinconf_reg(g, param, ®, &bit, &width);
468 ret = owl_group_pinconf_arg2val(g, param, &arg);
472 /* Update register */
473 raw_spin_lock_irqsave(&pctrl->lock, flags);
475 owl_write_field(pctrl, reg, arg, bit, width);
477 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
483 static const struct pinconf_ops owl_pinconf_ops = {
485 .pin_config_get = owl_pin_config_get,
486 .pin_config_set = owl_pin_config_set,
487 .pin_config_group_get = owl_group_config_get,
488 .pin_config_group_set = owl_group_config_set,
491 static struct pinctrl_desc owl_pinctrl_desc = {
492 .pctlops = &owl_pinctrl_ops,
493 .pmxops = &owl_pinmux_ops,
494 .confops = &owl_pinconf_ops,
495 .owner = THIS_MODULE,
498 static const struct owl_gpio_port *
499 owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin)
501 unsigned int start = 0, i;
503 for (i = 0; i < pctrl->soc->nports; i++) {
504 const struct owl_gpio_port *port = &pctrl->soc->ports[i];
506 if (*pin >= start && *pin < start + port->pins) {
517 static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag)
521 val = readl_relaxed(base);
528 writel_relaxed(val, base);
531 static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset)
533 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
534 const struct owl_gpio_port *port;
535 void __iomem *gpio_base;
538 port = owl_gpio_get_port(pctrl, &offset);
539 if (WARN_ON(port == NULL))
542 gpio_base = pctrl->base + port->offset;
545 * GPIOs have higher priority over other modules, so either setting
546 * them as OUT or IN is sufficient
548 raw_spin_lock_irqsave(&pctrl->lock, flags);
549 owl_gpio_update_reg(gpio_base + port->outen, offset, true);
550 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
555 static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset)
557 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
558 const struct owl_gpio_port *port;
559 void __iomem *gpio_base;
562 port = owl_gpio_get_port(pctrl, &offset);
563 if (WARN_ON(port == NULL))
566 gpio_base = pctrl->base + port->offset;
568 raw_spin_lock_irqsave(&pctrl->lock, flags);
569 /* disable gpio output */
570 owl_gpio_update_reg(gpio_base + port->outen, offset, false);
572 /* disable gpio input */
573 owl_gpio_update_reg(gpio_base + port->inen, offset, false);
574 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
577 static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset)
579 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
580 const struct owl_gpio_port *port;
581 void __iomem *gpio_base;
585 port = owl_gpio_get_port(pctrl, &offset);
586 if (WARN_ON(port == NULL))
589 gpio_base = pctrl->base + port->offset;
591 raw_spin_lock_irqsave(&pctrl->lock, flags);
592 val = readl_relaxed(gpio_base + port->dat);
593 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
595 return !!(val & BIT(offset));
598 static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
600 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
601 const struct owl_gpio_port *port;
602 void __iomem *gpio_base;
605 port = owl_gpio_get_port(pctrl, &offset);
606 if (WARN_ON(port == NULL))
609 gpio_base = pctrl->base + port->offset;
611 raw_spin_lock_irqsave(&pctrl->lock, flags);
612 owl_gpio_update_reg(gpio_base + port->dat, offset, value);
613 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
616 static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
618 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
619 const struct owl_gpio_port *port;
620 void __iomem *gpio_base;
623 port = owl_gpio_get_port(pctrl, &offset);
624 if (WARN_ON(port == NULL))
627 gpio_base = pctrl->base + port->offset;
629 raw_spin_lock_irqsave(&pctrl->lock, flags);
630 owl_gpio_update_reg(gpio_base + port->outen, offset, false);
631 owl_gpio_update_reg(gpio_base + port->inen, offset, true);
632 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
637 static int owl_gpio_direction_output(struct gpio_chip *chip,
638 unsigned int offset, int value)
640 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
641 const struct owl_gpio_port *port;
642 void __iomem *gpio_base;
645 port = owl_gpio_get_port(pctrl, &offset);
646 if (WARN_ON(port == NULL))
649 gpio_base = pctrl->base + port->offset;
651 raw_spin_lock_irqsave(&pctrl->lock, flags);
652 owl_gpio_update_reg(gpio_base + port->inen, offset, false);
653 owl_gpio_update_reg(gpio_base + port->outen, offset, true);
654 owl_gpio_update_reg(gpio_base + port->dat, offset, value);
655 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
660 static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type)
662 const struct owl_gpio_port *port;
663 void __iomem *gpio_base;
665 unsigned int offset, value, irq_type = 0;
668 case IRQ_TYPE_EDGE_BOTH:
670 * Since the hardware doesn't support interrupts on both edges,
671 * emulate it in the software by setting the single edge
672 * interrupt and switching to the opposite edge while ACKing
675 if (owl_gpio_get(&pctrl->chip, gpio))
676 irq_type = OWL_GPIO_INT_EDGE_FALLING;
678 irq_type = OWL_GPIO_INT_EDGE_RISING;
681 case IRQ_TYPE_EDGE_RISING:
682 irq_type = OWL_GPIO_INT_EDGE_RISING;
685 case IRQ_TYPE_EDGE_FALLING:
686 irq_type = OWL_GPIO_INT_EDGE_FALLING;
689 case IRQ_TYPE_LEVEL_HIGH:
690 irq_type = OWL_GPIO_INT_LEVEL_HIGH;
693 case IRQ_TYPE_LEVEL_LOW:
694 irq_type = OWL_GPIO_INT_LEVEL_LOW;
701 port = owl_gpio_get_port(pctrl, &gpio);
702 if (WARN_ON(port == NULL))
705 gpio_base = pctrl->base + port->offset;
707 raw_spin_lock_irqsave(&pctrl->lock, flags);
709 offset = (gpio < 16) ? 4 : 0;
710 value = readl_relaxed(gpio_base + port->intc_type + offset);
711 value &= ~(OWL_GPIO_INT_MASK << ((gpio % 16) * 2));
712 value |= irq_type << ((gpio % 16) * 2);
713 writel_relaxed(value, gpio_base + port->intc_type + offset);
715 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
718 static void owl_gpio_irq_mask(struct irq_data *data)
720 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
721 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
722 const struct owl_gpio_port *port;
723 void __iomem *gpio_base;
725 unsigned int gpio = data->hwirq;
728 port = owl_gpio_get_port(pctrl, &gpio);
729 if (WARN_ON(port == NULL))
732 gpio_base = pctrl->base + port->offset;
734 raw_spin_lock_irqsave(&pctrl->lock, flags);
736 owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, false);
738 /* disable port interrupt if no interrupt pending bit is active */
739 val = readl_relaxed(gpio_base + port->intc_msk);
741 owl_gpio_update_reg(gpio_base + port->intc_ctl,
742 OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false);
744 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
747 static void owl_gpio_irq_unmask(struct irq_data *data)
749 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
750 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
751 const struct owl_gpio_port *port;
752 void __iomem *gpio_base;
754 unsigned int gpio = data->hwirq;
757 port = owl_gpio_get_port(pctrl, &gpio);
758 if (WARN_ON(port == NULL))
761 gpio_base = pctrl->base + port->offset;
762 raw_spin_lock_irqsave(&pctrl->lock, flags);
764 /* enable port interrupt */
765 value = readl_relaxed(gpio_base + port->intc_ctl);
766 value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M))
767 << port->shared_ctl_offset * 5);
768 writel_relaxed(value, gpio_base + port->intc_ctl);
770 /* enable GPIO interrupt */
771 owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, true);
773 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
776 static void owl_gpio_irq_ack(struct irq_data *data)
778 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
779 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
780 const struct owl_gpio_port *port;
781 void __iomem *gpio_base;
783 unsigned int gpio = data->hwirq;
786 * Switch the interrupt edge to the opposite edge of the interrupt
787 * which got triggered for the case of emulating both edges
789 if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) {
790 if (owl_gpio_get(gc, gpio))
791 irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_FALLING);
793 irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_RISING);
796 port = owl_gpio_get_port(pctrl, &gpio);
797 if (WARN_ON(port == NULL))
800 gpio_base = pctrl->base + port->offset;
802 raw_spin_lock_irqsave(&pctrl->lock, flags);
804 owl_gpio_update_reg(gpio_base + port->intc_ctl,
805 OWL_GPIO_CTLR_PENDING + port->shared_ctl_offset * 5, true);
807 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
810 static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type)
812 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
813 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
815 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
816 irq_set_handler_locked(data, handle_level_irq);
818 irq_set_handler_locked(data, handle_edge_irq);
820 irq_set_type(pctrl, data->hwirq, type);
825 static void owl_gpio_irq_handler(struct irq_desc *desc)
827 struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc);
828 struct irq_chip *chip = irq_desc_get_chip(desc);
829 struct irq_domain *domain = pctrl->chip.irq.domain;
830 unsigned int parent = irq_desc_get_irq(desc);
831 const struct owl_gpio_port *port;
833 unsigned int pin, irq, offset = 0, i;
834 unsigned long pending_irq;
836 chained_irq_enter(chip, desc);
838 for (i = 0; i < pctrl->soc->nports; i++) {
839 port = &pctrl->soc->ports[i];
840 base = pctrl->base + port->offset;
842 /* skip ports that are not associated with this irq */
843 if (parent != pctrl->irq[i])
846 pending_irq = readl_relaxed(base + port->intc_pd);
848 for_each_set_bit(pin, &pending_irq, port->pins) {
849 irq = irq_find_mapping(domain, offset + pin);
850 generic_handle_irq(irq);
852 /* clear pending interrupt */
853 owl_gpio_update_reg(base + port->intc_pd, pin, true);
857 offset += port->pins;
860 chained_irq_exit(chip, desc);
863 static int owl_gpio_init(struct owl_pinctrl *pctrl)
865 struct gpio_chip *chip;
866 struct gpio_irq_chip *gpio_irq;
867 int ret, i, j, offset;
871 chip->ngpio = pctrl->soc->ngpios;
872 chip->label = dev_name(pctrl->dev);
873 chip->parent = pctrl->dev;
874 chip->owner = THIS_MODULE;
875 chip->of_node = pctrl->dev->of_node;
877 pctrl->irq_chip.name = chip->of_node->name;
878 pctrl->irq_chip.irq_ack = owl_gpio_irq_ack;
879 pctrl->irq_chip.irq_mask = owl_gpio_irq_mask;
880 pctrl->irq_chip.irq_unmask = owl_gpio_irq_unmask;
881 pctrl->irq_chip.irq_set_type = owl_gpio_irq_set_type;
883 gpio_irq = &chip->irq;
884 gpio_irq->chip = &pctrl->irq_chip;
885 gpio_irq->handler = handle_simple_irq;
886 gpio_irq->default_type = IRQ_TYPE_NONE;
887 gpio_irq->parent_handler = owl_gpio_irq_handler;
888 gpio_irq->parent_handler_data = pctrl;
889 gpio_irq->num_parents = pctrl->num_irq;
890 gpio_irq->parents = pctrl->irq;
892 gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio,
893 sizeof(*gpio_irq->map), GFP_KERNEL);
897 for (i = 0, offset = 0; i < pctrl->soc->nports; i++) {
898 const struct owl_gpio_port *port = &pctrl->soc->ports[i];
900 for (j = 0; j < port->pins; j++)
901 gpio_irq->map[offset + j] = gpio_irq->parents[i];
903 offset += port->pins;
906 ret = gpiochip_add_data(&pctrl->chip, pctrl);
908 dev_err(pctrl->dev, "failed to register gpiochip\n");
915 int owl_pinctrl_probe(struct platform_device *pdev,
916 struct owl_pinctrl_soc_data *soc_data)
918 struct resource *res;
919 struct owl_pinctrl *pctrl;
922 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
926 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
927 pctrl->base = devm_ioremap_resource(&pdev->dev, res);
928 if (IS_ERR(pctrl->base))
929 return PTR_ERR(pctrl->base);
931 /* enable GPIO/MFP clock */
932 pctrl->clk = devm_clk_get(&pdev->dev, NULL);
933 if (IS_ERR(pctrl->clk)) {
934 dev_err(&pdev->dev, "no clock defined\n");
935 return PTR_ERR(pctrl->clk);
938 ret = clk_prepare_enable(pctrl->clk);
940 dev_err(&pdev->dev, "clk enable failed\n");
944 raw_spin_lock_init(&pctrl->lock);
946 owl_pinctrl_desc.name = dev_name(&pdev->dev);
947 owl_pinctrl_desc.pins = soc_data->pins;
948 owl_pinctrl_desc.npins = soc_data->npins;
950 pctrl->chip.direction_input = owl_gpio_direction_input;
951 pctrl->chip.direction_output = owl_gpio_direction_output;
952 pctrl->chip.get = owl_gpio_get;
953 pctrl->chip.set = owl_gpio_set;
954 pctrl->chip.request = owl_gpio_request;
955 pctrl->chip.free = owl_gpio_free;
957 pctrl->soc = soc_data;
958 pctrl->dev = &pdev->dev;
960 pctrl->pctrldev = devm_pinctrl_register(&pdev->dev,
961 &owl_pinctrl_desc, pctrl);
962 if (IS_ERR(pctrl->pctrldev)) {
963 dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n");
964 ret = PTR_ERR(pctrl->pctrldev);
968 ret = platform_irq_count(pdev);
972 pctrl->num_irq = ret;
974 pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq,
975 sizeof(*pctrl->irq), GFP_KERNEL);
981 for (i = 0; i < pctrl->num_irq ; i++) {
982 ret = platform_get_irq(pdev, i);
988 ret = owl_gpio_init(pctrl);
992 platform_set_drvdata(pdev, pctrl);
997 clk_disable_unprepare(pctrl->clk);