1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2016 IBM Corp.
9 #include <linux/pinctrl/pinctrl.h>
10 #include <linux/pinctrl/pinmux.h>
11 #include <linux/pinctrl/pinconf.h>
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <linux/regmap.h>
16 * The ASPEED SoCs provide typically more than 200 pins for GPIO and other
17 * functions. The SoC function enabled on a pin is determined on a priority
18 * basis where a given pin can provide a number of different signal types.
20 * The signal active on a pin is described by both a priority level and
21 * compound logical expressions involving multiple operators, registers and
22 * bits. Some difficulty arises as the pin's function bit masks for each
23 * priority level are frequently not the same (i.e. cannot just flip a bit to
24 * change from a high to low priority signal), or even in the same register.
25 * Further, not all signals can be unmuxed, as some expressions depend on
26 * values in the hardware strapping register (which is treated as read-only).
28 * SoC Multi-function Pin Expression Examples
29 * ------------------------------------------
31 * Here are some sample mux configurations from the AST2400 and AST2500
32 * datasheets to illustrate the corner cases, roughly in order of least to most
33 * corner. The signal priorities are in decending order from P0 (highest).
35 * D6 is a pin with a single function (beside GPIO); a high priority signal
36 * that participates in one function:
38 * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
39 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
40 * D6 GPIOA0 MAC1LINK SCU80[0]=1 GPIOA0
41 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
43 * C5 is a multi-signal pin (high and low priority signals). Here we touch
44 * different registers for the different functions that enable each signal:
46 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
47 * C5 GPIOA4 SCL9 SCU90[22]=1 TIMER5 SCU80[4]=1 GPIOA4
48 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
50 * E19 is a single-signal pin with two functions that influence the active
51 * signal. In this case both bits have the same meaning - enable a dedicated
52 * LPC reset pin. However it's not always the case that the bits in the
53 * OR-relationship have the same meaning.
55 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
56 * E19 GPIOB4 LPCRST# SCU80[12]=1 | Strap[14]=1 GPIOB4
57 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
59 * For example, pin B19 has a low-priority signal that's enabled by two
60 * distinct SoC functions: A specific SIOPBI bit in register SCUA4, and an ACPI
61 * bit in the STRAP register. The ACPI bit configures signals on pins in
62 * addition to B19. Both of the low priority functions as well as the high
63 * priority function must be disabled for GPIOF1 to be used.
65 * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
66 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
67 * B19 GPIOF1 NDCD4 SCU80[25]=1 SIOPBI# SCUA4[12]=1 | Strap[19]=0 GPIOF1
68 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
70 * For pin E18, the SoC ANDs the expected state of three bits to determine the
71 * pin's active signal:
73 * * SCU3C[3]: Enable external SOC reset function
74 * * SCU80[15]: Enable SPICS1# or EXTRST# function pin
75 * * SCU90[31]: Select SPI interface CS# output
77 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
78 * E18 GPIOB7 EXTRST# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=0 SPICS1# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=1 GPIOB7
79 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
81 * (Bits SCU3C[3] and SCU80[15] appear to only be used in the expressions for
82 * selecting the signals on pin E18)
84 * Pin T5 is a multi-signal pin with a more complex configuration:
86 * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
87 * -----+---------+-----------+------------------------------+-----------+---------------+----------
88 * T5 GPIOL1 VPIDE SCU90[5:4]!=0 & SCU84[17]=1 NDCD1 SCU84[17]=1 GPIOL1
89 * -----+---------+-----------+------------------------------+-----------+---------------+----------
91 * The high priority signal configuration is best thought of in terms of its
92 * exploded form, with reference to the SCU90[5:4] bits:
94 * * SCU90[5:4]=00: disable
95 * * SCU90[5:4]=01: 18 bits (R6/G6/B6) video mode.
96 * * SCU90[5:4]=10: 24 bits (R8/G8/B8) video mode.
97 * * SCU90[5:4]=11: 30 bits (R10/G10/B10) video mode.
101 * -----+---------+-----------+------------------------------+-----------+---------------+----------
102 * T5 GPIOL1 VPIDE (SCU90[5:4]=1 & SCU84[17]=1) NDCD1 SCU84[17]=1 GPIOL1
103 * | (SCU90[5:4]=2 & SCU84[17]=1)
104 * | (SCU90[5:4]=3 & SCU84[17]=1)
105 * -----+---------+-----------+------------------------------+-----------+---------------+----------
107 * For reference the SCU84[17] bit configure the "UART1 NDCD1 or Video VPIDE
108 * function pin", where the signal itself is determined by whether SCU94[5:4]
109 * is disabled or in one of the 18, 24 or 30bit video modes.
111 * Other video-input-related pins require an explicit state in SCU90[5:4], e.g.
114 * -----+---------+-----------+------------------------------+-----------+---------------+----------
115 * W1 GPIOL6 VPIB0 SCU90[5:4]=3 & SCU84[22]=1 TXD1 SCU84[22]=1 GPIOL6
116 * U5 GPIOL7 VPIB1 SCU90[5:4]=3 & SCU84[23]=1 RXD1 SCU84[23]=1 GPIOL7
117 * -----+---------+-----------+------------------------------+-----------+---------------+----------
119 * The examples of T5 and W1 are particularly fertile, as they also demonstrate
120 * that despite operating as part of the video input bus each signal needs to
121 * be enabled individually via it's own SCU84 (in the cases of T5 and W1)
122 * register bit. This is a little crazy if the bus doesn't have optional
123 * signals, but is used to decent effect with some of the UARTs where not all
124 * signals are required. However, this isn't done consistently - UART1 is
125 * enabled on a per-pin basis, and by contrast, all signals for UART6 are
126 * enabled by a single bit.
128 * Further, the high and low priority signals listed in the table above share
129 * a configuration bit. The VPI signals should operate in concert in a single
130 * function, but the UART signals should retain the ability to be configured
131 * independently. This pushes the implementation down the path of tagging a
132 * signal's expressions with the function they participate in, rather than
133 * defining masks affecting multiple signals per function. The latter approach
134 * fails in this instance where applying the configuration for the UART pin of
135 * interest will stomp on the state of other UART signals when disabling the
136 * VPI functions on the current pin.
138 * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
139 * -----+------------+-----------+---------------------------+-----------+---------------+------------
140 * A12 RGMII1TXCK GPIOT0 SCUA0[0]=1 RMII1TXEN Strap[6]=0 RGMII1TXCK
141 * B12 RGMII1TXCTL GPIOT1 SCUA0[1]=1 – Strap[6]=0 RGMII1TXCTL
142 * -----+------------+-----------+---------------------------+-----------+---------------+------------
144 * A12 demonstrates that the "Other" signal isn't always GPIO - in this case
145 * GPIOT0 is a high-priority signal and RGMII1TXCK is Other. Thus, GPIO
146 * should be treated like any other signal type with full function expression
147 * requirements, and not assumed to be the default case. Separately, GPIOT0 and
148 * GPIOT1's signal descriptor bits are distinct, therefore we must iterate all
149 * pins in the function's group to disable the higher-priority signals such
150 * that the signal for the function of interest is correctly enabled.
152 * Finally, three priority levels aren't always enough; the AST2500 brings with
153 * it 18 pins of five priority levels, however the 18 pins only use three of
154 * the five priority levels.
156 * Ultimately the requirement to control pins in the examples above drive the
159 * * Pins provide signals according to functions activated in the mux
162 * * Pins provide up to five signal types in a priority order
164 * * For priorities levels defined on a pin, each priority provides one signal
166 * * Enabling lower priority signals requires higher priority signals be
169 * * A function represents a set of signals; functions are distinct if their
170 * sets of signals are not equal
172 * * Signals participate in one or more functions
174 * * A function is described by an expression of one or more signal
175 * descriptors, which compare bit values in a register
177 * * A signal expression is the smallest set of signal descriptors whose
178 * comparisons must evaluate 'true' for a signal to be enabled on a pin.
180 * * A function's signal is active on a pin if evaluating all signal
181 * descriptors in the pin's signal expression for the function yields a 'true'
184 * * A signal at a given priority on a given pin is active if any of the
185 * functions in which the signal participates are active, and no higher
186 * priority signal on the pin is active
188 * * GPIO is configured per-pin
192 * * To disable a signal, any function(s) activating the signal must be
195 * * Each pin must know the signal expressions of functions in which it
196 * participates, for the purpose of enabling the Other function. This is done
197 * by deactivating all functions that activate higher priority signals on the
200 * As a concrete example:
202 * * T5 provides three signals types: VPIDE, NDCD1 and GPIO
204 * * The VPIDE signal participates in 3 functions: VPI18, VPI24 and VPI30
206 * * The NDCD1 signal participates in just its own NDCD1 function
208 * * VPIDE is high priority, NDCD1 is low priority, and GPIOL1 is the least
211 * * The prerequisit for activating the NDCD1 signal is that the VPI18, VPI24
212 * and VPI30 functions all be disabled
214 * * Similarly, all of VPI18, VPI24, VPI30 and NDCD1 functions must be disabled
220 * If pinctrl allows us to allocate a pin we can configure a function without
221 * concern for the function of already allocated pins, if pin groups are
222 * created with respect to the SoC functions in which they participate. This is
223 * intuitive, but it did not feel obvious from the bit/pin relationships.
225 * Conversely, failing to allocate all pins in a group indicates some bits (as
226 * well as pins) required for the group's configuration will already be in use,
227 * likely in a way that's inconsistent with the requirements of the failed
231 #define ASPEED_IP_SCU 0
232 #define ASPEED_IP_GFX 1
233 #define ASPEED_IP_LPC 2
234 #define ASPEED_NR_PINMUX_IPS 3
237 * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
238 * references registers by the device/offset mnemonic. The register macros
239 * below are named the same way to ease transcription and verification (as
240 * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
241 * reference registers beyond those dedicated to pinmux, such as the system
242 * reset control and MAC clock configuration registers. The AST2500 goes a step
243 * further and references registers in the graphics IP block, but that isn't
246 #define SCU2C 0x2C /* Misc. Control Register */
247 #define SCU3C 0x3C /* System Reset Control/Status Register */
248 #define SCU48 0x48 /* MAC Interface Clock Delay Setting */
249 #define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
250 #define HW_REVISION_ID 0x7C /* Silicon revision ID register */
251 #define SCU80 0x80 /* Multi-function Pin Control #1 */
252 #define SCU84 0x84 /* Multi-function Pin Control #2 */
253 #define SCU88 0x88 /* Multi-function Pin Control #3 */
254 #define SCU8C 0x8C /* Multi-function Pin Control #4 */
255 #define SCU90 0x90 /* Multi-function Pin Control #5 */
256 #define SCU94 0x94 /* Multi-function Pin Control #6 */
257 #define SCUA0 0xA0 /* Multi-function Pin Control #7 */
258 #define SCUA4 0xA4 /* Multi-function Pin Control #8 */
259 #define SCUA8 0xA8 /* Multi-function Pin Control #9 */
260 #define SCUAC 0xAC /* Multi-function Pin Control #10 */
261 #define HW_STRAP2 0xD0 /* Strapping */
264 * A signal descriptor, which describes the register, bits and the
265 * enable/disable values that should be compared or written.
267 * @ip: The IP block identifier, used as an index into the regmap array in
268 * struct aspeed_pinctrl_data
269 * @reg: The register offset with respect to the base address of the IP block
270 * @mask: The mask to apply to the register. The lowest set bit of the mask is
271 * used to derive the shift value.
272 * @enable: The value that enables the function. Value should be in the LSBs,
273 * not at the position of the mask.
274 * @disable: The value that disables the function. Value should be in the
275 * LSBs, not at the position of the mask.
277 struct aspeed_sig_desc {
286 * Describes a signal expression. The expression is evaluated by ANDing the
287 * evaluation of the descriptors.
289 * @signal: The signal name for the priority level on the pin. If the signal
290 * type is GPIO, then the signal name must begin with the string
291 * "GPIO", e.g. GPIOA0, GPIOT4 etc.
292 * @function: The name of the function the signal participates in for the
293 * associated expression
294 * @ndescs: The number of signal descriptors in the expression
295 * @descs: Pointer to an array of signal descriptors that comprise the
296 * function expression
298 struct aspeed_sig_expr {
300 const char *function;
302 const struct aspeed_sig_desc *descs;
306 * A struct capturing the list of expressions enabling signals at each priority
307 * for a given pin. The signal configuration for a priority level is evaluated
308 * by ORing the evaluation of the signal expressions in the respective
311 * @name: A name for the pin
312 * @prios: A pointer to an array of expression list pointers
315 struct aspeed_pin_desc {
317 const struct aspeed_sig_expr ***prios;
322 #define SIG_DESC_IP_BIT(ip, reg, idx, val) \
323 { ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) }
326 * Short-hand macro for describing an SCU descriptor enabled by the state of
327 * one bit. The disable value is derived.
329 * @reg: The signal's associated register, offset from base
330 * @idx: The signal's bit index in the register
331 * @val: The value (0 or 1) that enables the function
333 #define SIG_DESC_BIT(reg, idx, val) \
334 SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val)
336 #define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1)
339 * A further short-hand macro expanding to an SCU descriptor enabled by a set
342 * @reg: The register, offset from base
343 * @idx: The bit index in the register
345 #define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
347 #define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func
348 #define SIG_DESC_LIST_DECL(sig, func, ...) \
349 static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, func)[] = \
352 #define SIG_EXPR_SYM(sig, func) sig_expr_ ## sig ## _ ## func
353 #define SIG_EXPR_DECL_(sig, func) \
354 static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, func) = \
358 .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, func)), \
359 .descs = &(SIG_DESC_LIST_SYM(sig, func))[0], \
363 * Declare a signal expression.
365 * @sig: A macro symbol name for the signal (is subjected to stringification
367 * @func: The function in which the signal is participating
368 * @...: Signal descriptors that define the signal expression
370 * For example, the following declares the ROMD8 signal for the ROM16 function:
372 * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
374 * And with multiple signal descriptors:
376 * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
377 * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
379 #define SIG_EXPR_DECL(sig, func, ...) \
380 SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
381 SIG_EXPR_DECL_(sig, func)
384 * Declare a pointer to a signal expression
386 * @sig: The macro symbol name for the signal (subjected to token pasting)
387 * @func: The macro symbol name for the function (subjected to token pasting)
389 #define SIG_EXPR_PTR(sig, func) (&SIG_EXPR_SYM(sig, func))
391 #define SIG_EXPR_LIST_SYM(sig) sig_exprs_ ## sig
394 * Declare a signal expression list for reference in a struct aspeed_pin_prio.
396 * @sig: A macro symbol name for the signal (is subjected to token pasting)
397 * @...: Signal expression structure pointers (use SIG_EXPR_PTR())
399 * For example, the 16-bit ROM bus can be enabled by one of two possible signal
402 * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
403 * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
404 * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
405 * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
406 * SIG_EXPR_PTR(ROMD8, ROM16S));
408 #define SIG_EXPR_LIST_DECL(sig, ...) \
409 static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig)[] = \
410 { __VA_ARGS__, NULL }
413 * A short-hand macro for declaring a function expression and an expression
414 * list with a single function.
416 * @func: A macro symbol name for the function (is subjected to token pasting)
417 * @...: Function descriptors that define the function expression
419 * For example, signal NCTS6 participates in its own function with one group:
421 * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
423 #define SIG_EXPR_LIST_DECL_SINGLE(sig, func, ...) \
424 SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
425 SIG_EXPR_DECL_(sig, func); \
426 SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, func))
428 #define SIG_EXPR_LIST_DECL_DUAL(sig, f0, f1) \
429 SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, f0), SIG_EXPR_PTR(sig, f1))
431 #define SIG_EXPR_LIST_PTR(sig) (&SIG_EXPR_LIST_SYM(sig)[0])
433 #define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin
434 #define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0])
435 #define PIN_SYM(pin) pin_ ## pin
437 #define MS_PIN_DECL_(pin, ...) \
438 static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \
439 { __VA_ARGS__, NULL }; \
440 static const struct aspeed_pin_desc PIN_SYM(pin) = \
441 { #pin, PIN_EXPRS_PTR(pin) }
444 * Declare a multi-signal pin
446 * @pin: The pin number
447 * @other: Macro name for "other" functionality (subjected to stringification)
448 * @high: Macro name for the highest priority signal functions
449 * @low: Macro name for the low signal functions
454 * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
455 * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
456 * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
457 * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
458 * SIG_EXPR_PTR(ROMD8, ROM16S));
459 * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
460 * MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6);
462 #define MS_PIN_DECL(pin, other, high, low) \
463 SIG_EXPR_LIST_DECL_SINGLE(other, other); \
465 SIG_EXPR_LIST_PTR(high), \
466 SIG_EXPR_LIST_PTR(low), \
467 SIG_EXPR_LIST_PTR(other))
469 #define PIN_GROUP_SYM(func) pins_ ## func
470 #define FUNC_GROUP_SYM(func) groups_ ## func
471 #define FUNC_GROUP_DECL(func, ...) \
472 static const int PIN_GROUP_SYM(func)[] = { __VA_ARGS__ }; \
473 static const char *FUNC_GROUP_SYM(func)[] = { #func }
476 * Declare a single signal pin
478 * @pin: The pin number
479 * @other: Macro name for "other" functionality (subjected to stringification)
480 * @sig: Macro name for the signal (subjected to stringification)
485 * SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
486 * SS_PIN_DECL(E3, GPIOK0, SCL5);
488 #define SS_PIN_DECL(pin, other, sig) \
489 SIG_EXPR_LIST_DECL_SINGLE(other, other); \
490 MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other))
493 * Single signal, single function pin declaration
495 * @pin: The pin number
496 * @other: Macro name for "other" functionality (subjected to stringification)
497 * @sig: Macro name for the signal (subjected to stringification)
498 * @...: Signal descriptors that define the function expression
502 * SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
504 #define SSSF_PIN_DECL(pin, other, sig, ...) \
505 SIG_EXPR_LIST_DECL_SINGLE(sig, sig, __VA_ARGS__); \
506 SIG_EXPR_LIST_DECL_SINGLE(other, other); \
507 MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)); \
508 FUNC_GROUP_DECL(sig, pin)
510 #define GPIO_PIN_DECL(pin, gpio) \
511 SIG_EXPR_LIST_DECL_SINGLE(gpio, gpio); \
512 MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio))
515 * @param The pinconf parameter type
516 * @pins The pin range this config struct covers, [low, high]
517 * @reg The register housing the configuration bits
518 * @mask The mask to select the bits of interest in @reg
520 struct aspeed_pin_config {
521 enum pin_config_param param;
522 unsigned int pins[2];
528 struct aspeed_pinctrl_data {
529 struct regmap *maps[ASPEED_NR_PINMUX_IPS];
531 const struct pinctrl_pin_desc *pins;
532 const unsigned int npins;
534 const struct aspeed_pin_group *groups;
535 const unsigned int ngroups;
537 const struct aspeed_pin_function *functions;
538 const unsigned int nfunctions;
540 const struct aspeed_pin_config *configs;
541 const unsigned int nconfigs;
544 #define ASPEED_PINCTRL_PIN(name_) \
548 .drv_data = (void *) &(PIN_SYM(name_)) \
551 struct aspeed_pin_group {
553 const unsigned int *pins;
554 const unsigned int npins;
557 #define ASPEED_PINCTRL_GROUP(name_) { \
559 .pins = &(PIN_GROUP_SYM(name_))[0], \
560 .npins = ARRAY_SIZE(PIN_GROUP_SYM(name_)), \
563 struct aspeed_pin_function {
565 const char *const *groups;
566 unsigned int ngroups;
569 #define ASPEED_PINCTRL_FUNC(name_, ...) { \
571 .groups = &FUNC_GROUP_SYM(name_)[0], \
572 .ngroups = ARRAY_SIZE(FUNC_GROUP_SYM(name_)), \
575 int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev);
576 const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
578 int aspeed_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
579 unsigned int group, const unsigned int **pins,
580 unsigned int *npins);
581 void aspeed_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
582 struct seq_file *s, unsigned int offset);
583 int aspeed_pinmux_get_fn_count(struct pinctrl_dev *pctldev);
584 const char *aspeed_pinmux_get_fn_name(struct pinctrl_dev *pctldev,
585 unsigned int function);
586 int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev,
587 unsigned int function, const char * const **groups,
588 unsigned int * const num_groups);
589 int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
591 int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
592 struct pinctrl_gpio_range *range,
593 unsigned int offset);
594 int aspeed_pinctrl_probe(struct platform_device *pdev,
595 struct pinctrl_desc *pdesc,
596 struct aspeed_pinctrl_data *pdata);
597 int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset,
598 unsigned long *config);
599 int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
600 unsigned long *configs, unsigned int num_configs);
601 int aspeed_pin_config_group_get(struct pinctrl_dev *pctldev,
602 unsigned int selector,
603 unsigned long *config);
604 int aspeed_pin_config_group_set(struct pinctrl_dev *pctldev,
605 unsigned int selector,
606 unsigned long *configs,
607 unsigned int num_configs);
609 #endif /* PINCTRL_ASPEED */