1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
5 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
7 * This driver is inspired by:
8 * pinctrl-nomadik.c, please see original file for copyright information
9 * pinctrl-tegra.c, please see original file for copyright information
12 #include <linux/bitmap.h>
13 #include <linux/bug.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
19 #include <linux/irq.h>
20 #include <linux/irqdesc.h>
21 #include <linux/init.h>
22 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/pinctrl/machine.h>
27 #include <linux/pinctrl/pinconf.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_device.h>
32 #include <linux/seq_file.h>
33 #include <linux/slab.h>
34 #include <linux/spinlock.h>
35 #include <linux/types.h>
36 #include <dt-bindings/pinctrl/bcm2835.h>
38 #define MODULE_NAME "pinctrl-bcm2835"
39 #define BCM2835_NUM_GPIOS 54
40 #define BCM2835_NUM_BANKS 2
41 #define BCM2835_NUM_IRQS 3
43 #define BCM2835_PIN_BITMAP_SZ \
44 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
46 /* GPIO register offsets */
47 #define GPFSEL0 0x0 /* Function Select */
48 #define GPSET0 0x1c /* Pin Output Set */
49 #define GPCLR0 0x28 /* Pin Output Clear */
50 #define GPLEV0 0x34 /* Pin Level */
51 #define GPEDS0 0x40 /* Pin Event Detect Status */
52 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
53 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
54 #define GPHEN0 0x64 /* Pin High Detect Enable */
55 #define GPLEN0 0x70 /* Pin Low Detect Enable */
56 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
57 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
58 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
59 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
61 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
62 #define FSEL_SHIFT(p) (((p) % 10) * 3)
63 #define GPIO_REG_OFFSET(p) ((p) / 32)
64 #define GPIO_REG_SHIFT(p) ((p) % 32)
66 /* argument: bcm2835_pinconf_pull */
67 #define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1)
69 struct bcm2835_pinctrl {
72 int irq[BCM2835_NUM_IRQS];
74 /* note: locking assumes each bank will have its own unsigned long */
75 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
76 unsigned int irq_type[BCM2835_NUM_GPIOS];
78 struct pinctrl_dev *pctl_dev;
79 struct gpio_chip gpio_chip;
80 struct pinctrl_gpio_range gpio_range;
82 raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
85 /* pins are just named GPIO0..GPIO53 */
86 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
87 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
100 BCM2835_GPIO_PIN(12),
101 BCM2835_GPIO_PIN(13),
102 BCM2835_GPIO_PIN(14),
103 BCM2835_GPIO_PIN(15),
104 BCM2835_GPIO_PIN(16),
105 BCM2835_GPIO_PIN(17),
106 BCM2835_GPIO_PIN(18),
107 BCM2835_GPIO_PIN(19),
108 BCM2835_GPIO_PIN(20),
109 BCM2835_GPIO_PIN(21),
110 BCM2835_GPIO_PIN(22),
111 BCM2835_GPIO_PIN(23),
112 BCM2835_GPIO_PIN(24),
113 BCM2835_GPIO_PIN(25),
114 BCM2835_GPIO_PIN(26),
115 BCM2835_GPIO_PIN(27),
116 BCM2835_GPIO_PIN(28),
117 BCM2835_GPIO_PIN(29),
118 BCM2835_GPIO_PIN(30),
119 BCM2835_GPIO_PIN(31),
120 BCM2835_GPIO_PIN(32),
121 BCM2835_GPIO_PIN(33),
122 BCM2835_GPIO_PIN(34),
123 BCM2835_GPIO_PIN(35),
124 BCM2835_GPIO_PIN(36),
125 BCM2835_GPIO_PIN(37),
126 BCM2835_GPIO_PIN(38),
127 BCM2835_GPIO_PIN(39),
128 BCM2835_GPIO_PIN(40),
129 BCM2835_GPIO_PIN(41),
130 BCM2835_GPIO_PIN(42),
131 BCM2835_GPIO_PIN(43),
132 BCM2835_GPIO_PIN(44),
133 BCM2835_GPIO_PIN(45),
134 BCM2835_GPIO_PIN(46),
135 BCM2835_GPIO_PIN(47),
136 BCM2835_GPIO_PIN(48),
137 BCM2835_GPIO_PIN(49),
138 BCM2835_GPIO_PIN(50),
139 BCM2835_GPIO_PIN(51),
140 BCM2835_GPIO_PIN(52),
141 BCM2835_GPIO_PIN(53),
144 /* one pin per group */
145 static const char * const bcm2835_gpio_groups[] = {
203 BCM2835_FSEL_COUNT = 8,
204 BCM2835_FSEL_MASK = 0x7,
207 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
208 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
209 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
210 [BCM2835_FSEL_ALT0] = "alt0",
211 [BCM2835_FSEL_ALT1] = "alt1",
212 [BCM2835_FSEL_ALT2] = "alt2",
213 [BCM2835_FSEL_ALT3] = "alt3",
214 [BCM2835_FSEL_ALT4] = "alt4",
215 [BCM2835_FSEL_ALT5] = "alt5",
218 static const char * const irq_type_names[] = {
219 [IRQ_TYPE_NONE] = "none",
220 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
221 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
222 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
223 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
224 [IRQ_TYPE_LEVEL_LOW] = "level-low",
227 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
229 return readl(pc->base + reg);
232 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
235 writel(val, pc->base + reg);
238 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
241 reg += GPIO_REG_OFFSET(bit) * 4;
242 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
245 /* note NOT a read/modify/write cycle */
246 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
247 unsigned reg, unsigned bit)
249 reg += GPIO_REG_OFFSET(bit) * 4;
250 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
253 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
254 struct bcm2835_pinctrl *pc, unsigned pin)
256 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
257 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
259 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
260 bcm2835_functions[status]);
265 static inline void bcm2835_pinctrl_fsel_set(
266 struct bcm2835_pinctrl *pc, unsigned pin,
267 enum bcm2835_fsel fsel)
269 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
270 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
272 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
273 bcm2835_functions[cur]);
278 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
279 /* always transition through GPIO_IN */
280 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
281 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
283 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
284 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
285 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
288 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
289 val |= fsel << FSEL_SHIFT(pin);
291 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
292 bcm2835_functions[fsel]);
293 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
296 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
298 return pinctrl_gpio_direction_input(chip->base + offset);
301 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
303 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
305 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
308 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
310 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
311 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
313 /* Alternative function doesn't clearly provide a direction */
314 if (fsel > BCM2835_FSEL_GPIO_OUT)
317 return (fsel == BCM2835_FSEL_GPIO_IN);
320 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
322 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
324 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
327 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
328 unsigned offset, int value)
330 bcm2835_gpio_set(chip, offset, value);
331 return pinctrl_gpio_direction_output(chip->base + offset);
334 static const struct gpio_chip bcm2835_gpio_chip = {
335 .label = MODULE_NAME,
336 .owner = THIS_MODULE,
337 .request = gpiochip_generic_request,
338 .free = gpiochip_generic_free,
339 .direction_input = bcm2835_gpio_direction_input,
340 .direction_output = bcm2835_gpio_direction_output,
341 .get_direction = bcm2835_gpio_get_direction,
342 .get = bcm2835_gpio_get,
343 .set = bcm2835_gpio_set,
345 .ngpio = BCM2835_NUM_GPIOS,
349 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
350 unsigned int bank, u32 mask)
352 unsigned long events;
356 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
358 events &= pc->enabled_irq_map[bank];
359 for_each_set_bit(offset, &events, 32) {
360 gpio = (32 * bank) + offset;
361 generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,
366 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
368 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
369 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
370 struct irq_chip *host_chip = irq_desc_get_chip(desc);
371 int irq = irq_desc_get_irq(desc);
375 for (i = 0; i < ARRAY_SIZE(pc->irq); i++) {
376 if (pc->irq[i] == irq) {
381 /* This should not happen, every IRQ has a bank */
382 if (i == ARRAY_SIZE(pc->irq))
385 chained_irq_enter(host_chip, desc);
388 case 0: /* IRQ0 covers GPIOs 0-27 */
389 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
391 case 1: /* IRQ1 covers GPIOs 28-45 */
392 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
393 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
395 case 2: /* IRQ2 covers GPIOs 46-53 */
396 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
400 chained_irq_exit(host_chip, desc);
403 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
404 unsigned reg, unsigned offset, bool enable)
407 reg += GPIO_REG_OFFSET(offset) * 4;
408 value = bcm2835_gpio_rd(pc, reg);
410 value |= BIT(GPIO_REG_SHIFT(offset));
412 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
413 bcm2835_gpio_wr(pc, reg, value);
416 /* fast path for IRQ handler */
417 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
418 unsigned offset, bool enable)
420 switch (pc->irq_type[offset]) {
421 case IRQ_TYPE_EDGE_RISING:
422 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
425 case IRQ_TYPE_EDGE_FALLING:
426 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
429 case IRQ_TYPE_EDGE_BOTH:
430 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
431 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
434 case IRQ_TYPE_LEVEL_HIGH:
435 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
438 case IRQ_TYPE_LEVEL_LOW:
439 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
444 static void bcm2835_gpio_irq_enable(struct irq_data *data)
446 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
447 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
448 unsigned gpio = irqd_to_hwirq(data);
449 unsigned offset = GPIO_REG_SHIFT(gpio);
450 unsigned bank = GPIO_REG_OFFSET(gpio);
453 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
454 set_bit(offset, &pc->enabled_irq_map[bank]);
455 bcm2835_gpio_irq_config(pc, gpio, true);
456 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
459 static void bcm2835_gpio_irq_disable(struct irq_data *data)
461 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
462 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
463 unsigned gpio = irqd_to_hwirq(data);
464 unsigned offset = GPIO_REG_SHIFT(gpio);
465 unsigned bank = GPIO_REG_OFFSET(gpio);
468 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
469 bcm2835_gpio_irq_config(pc, gpio, false);
470 /* Clear events that were latched prior to clearing event sources */
471 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
472 clear_bit(offset, &pc->enabled_irq_map[bank]);
473 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
476 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
477 unsigned offset, unsigned int type)
481 case IRQ_TYPE_EDGE_RISING:
482 case IRQ_TYPE_EDGE_FALLING:
483 case IRQ_TYPE_EDGE_BOTH:
484 case IRQ_TYPE_LEVEL_HIGH:
485 case IRQ_TYPE_LEVEL_LOW:
486 pc->irq_type[offset] = type;
495 /* slower path for reconfiguring IRQ type */
496 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
497 unsigned offset, unsigned int type)
501 if (pc->irq_type[offset] != type) {
502 bcm2835_gpio_irq_config(pc, offset, false);
503 pc->irq_type[offset] = type;
507 case IRQ_TYPE_EDGE_RISING:
508 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
509 /* RISING already enabled, disable FALLING */
510 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
511 bcm2835_gpio_irq_config(pc, offset, false);
512 pc->irq_type[offset] = type;
513 } else if (pc->irq_type[offset] != type) {
514 bcm2835_gpio_irq_config(pc, offset, false);
515 pc->irq_type[offset] = type;
516 bcm2835_gpio_irq_config(pc, offset, true);
520 case IRQ_TYPE_EDGE_FALLING:
521 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
522 /* FALLING already enabled, disable RISING */
523 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
524 bcm2835_gpio_irq_config(pc, offset, false);
525 pc->irq_type[offset] = type;
526 } else if (pc->irq_type[offset] != type) {
527 bcm2835_gpio_irq_config(pc, offset, false);
528 pc->irq_type[offset] = type;
529 bcm2835_gpio_irq_config(pc, offset, true);
533 case IRQ_TYPE_EDGE_BOTH:
534 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
535 /* RISING already enabled, enable FALLING too */
536 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
537 bcm2835_gpio_irq_config(pc, offset, true);
538 pc->irq_type[offset] = type;
539 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
540 /* FALLING already enabled, enable RISING too */
541 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
542 bcm2835_gpio_irq_config(pc, offset, true);
543 pc->irq_type[offset] = type;
544 } else if (pc->irq_type[offset] != type) {
545 bcm2835_gpio_irq_config(pc, offset, false);
546 pc->irq_type[offset] = type;
547 bcm2835_gpio_irq_config(pc, offset, true);
551 case IRQ_TYPE_LEVEL_HIGH:
552 case IRQ_TYPE_LEVEL_LOW:
553 if (pc->irq_type[offset] != type) {
554 bcm2835_gpio_irq_config(pc, offset, false);
555 pc->irq_type[offset] = type;
556 bcm2835_gpio_irq_config(pc, offset, true);
566 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
568 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
569 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
570 unsigned gpio = irqd_to_hwirq(data);
571 unsigned offset = GPIO_REG_SHIFT(gpio);
572 unsigned bank = GPIO_REG_OFFSET(gpio);
576 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
578 if (test_bit(offset, &pc->enabled_irq_map[bank]))
579 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
581 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
583 if (type & IRQ_TYPE_EDGE_BOTH)
584 irq_set_handler_locked(data, handle_edge_irq);
586 irq_set_handler_locked(data, handle_level_irq);
588 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
593 static void bcm2835_gpio_irq_ack(struct irq_data *data)
595 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
596 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
597 unsigned gpio = irqd_to_hwirq(data);
599 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
602 static struct irq_chip bcm2835_gpio_irq_chip = {
604 .irq_enable = bcm2835_gpio_irq_enable,
605 .irq_disable = bcm2835_gpio_irq_disable,
606 .irq_set_type = bcm2835_gpio_irq_set_type,
607 .irq_ack = bcm2835_gpio_irq_ack,
608 .irq_mask = bcm2835_gpio_irq_disable,
609 .irq_unmask = bcm2835_gpio_irq_enable,
612 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
614 return ARRAY_SIZE(bcm2835_gpio_groups);
617 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
620 return bcm2835_gpio_groups[selector];
623 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
625 const unsigned **pins,
628 *pins = &bcm2835_gpio_pins[selector].number;
634 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
638 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
639 struct gpio_chip *chip = &pc->gpio_chip;
640 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
641 const char *fname = bcm2835_functions[fsel];
642 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
643 int irq = irq_find_mapping(chip->irq.domain, offset);
645 seq_printf(s, "function %s in %s; irq %d (%s)",
646 fname, value ? "hi" : "lo",
647 irq, irq_type_names[pc->irq_type[offset]]);
650 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
651 struct pinctrl_map *maps, unsigned num_maps)
655 for (i = 0; i < num_maps; i++)
656 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
657 kfree(maps[i].data.configs.configs);
662 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
663 struct device_node *np, u32 pin, u32 fnum,
664 struct pinctrl_map **maps)
666 struct pinctrl_map *map = *maps;
668 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
669 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
673 map->type = PIN_MAP_TYPE_MUX_GROUP;
674 map->data.mux.group = bcm2835_gpio_groups[pin];
675 map->data.mux.function = bcm2835_functions[fnum];
681 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
682 struct device_node *np, u32 pin, u32 pull,
683 struct pinctrl_map **maps)
685 struct pinctrl_map *map = *maps;
686 unsigned long *configs;
689 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
693 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
696 configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
698 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
699 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
700 map->data.configs.configs = configs;
701 map->data.configs.num_configs = 1;
707 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
708 struct device_node *np,
709 struct pinctrl_map **map, unsigned int *num_maps)
711 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
712 struct property *pins, *funcs, *pulls;
713 int num_pins, num_funcs, num_pulls, maps_per_pin;
714 struct pinctrl_map *maps, *cur_map;
718 /* Check for generic binding in this node */
719 err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
720 if (err || *num_maps)
723 /* Generic binding did not find anything continue with legacy parse */
724 pins = of_find_property(np, "brcm,pins", NULL);
726 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
730 funcs = of_find_property(np, "brcm,function", NULL);
731 pulls = of_find_property(np, "brcm,pull", NULL);
733 if (!funcs && !pulls) {
735 "%pOF: neither brcm,function nor brcm,pull specified\n",
740 num_pins = pins->length / 4;
741 num_funcs = funcs ? (funcs->length / 4) : 0;
742 num_pulls = pulls ? (pulls->length / 4) : 0;
744 if (num_funcs > 1 && num_funcs != num_pins) {
746 "%pOF: brcm,function must have 1 or %d entries\n",
751 if (num_pulls > 1 && num_pulls != num_pins) {
753 "%pOF: brcm,pull must have 1 or %d entries\n",
763 cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
768 for (i = 0; i < num_pins; i++) {
769 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
772 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
773 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
780 err = of_property_read_u32_index(np, "brcm,function",
781 (num_funcs > 1) ? i : 0, &func);
784 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
790 err = of_property_read_u32_index(np, "brcm,pull",
791 (num_pulls > 1) ? i : 0, &pull);
794 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
802 *num_maps = num_pins * maps_per_pin;
807 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
811 static const struct pinctrl_ops bcm2835_pctl_ops = {
812 .get_groups_count = bcm2835_pctl_get_groups_count,
813 .get_group_name = bcm2835_pctl_get_group_name,
814 .get_group_pins = bcm2835_pctl_get_group_pins,
815 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
816 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
817 .dt_free_map = bcm2835_pctl_dt_free_map,
820 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
823 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
825 /* disable by setting to GPIO_IN */
826 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
830 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
832 return BCM2835_FSEL_COUNT;
835 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
838 return bcm2835_functions[selector];
841 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
843 const char * const **groups,
844 unsigned * const num_groups)
846 /* every pin can do every function */
847 *groups = bcm2835_gpio_groups;
848 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
853 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
854 unsigned func_selector,
855 unsigned group_selector)
857 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
859 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
864 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
865 struct pinctrl_gpio_range *range,
868 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
870 /* disable by setting to GPIO_IN */
871 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
874 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
875 struct pinctrl_gpio_range *range,
879 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
880 enum bcm2835_fsel fsel = input ?
881 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
883 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
888 static const struct pinmux_ops bcm2835_pmx_ops = {
889 .free = bcm2835_pmx_free,
890 .get_functions_count = bcm2835_pmx_get_functions_count,
891 .get_function_name = bcm2835_pmx_get_function_name,
892 .get_function_groups = bcm2835_pmx_get_function_groups,
893 .set_mux = bcm2835_pmx_set,
894 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
895 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
898 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
899 unsigned pin, unsigned long *config)
901 /* No way to read back config in HW */
905 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
906 unsigned int pin, unsigned int arg)
910 off = GPIO_REG_OFFSET(pin);
911 bit = GPIO_REG_SHIFT(pin);
913 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
915 * BCM2835 datasheet say to wait 150 cycles, but not of what.
916 * But the VideoCore firmware delay for this operation
917 * based nearly on the same amount of VPU cycles and this clock
921 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
923 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
926 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
927 unsigned int pin, unsigned long *configs,
928 unsigned int num_configs)
930 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
934 for (i = 0; i < num_configs; i++) {
935 param = pinconf_to_config_param(configs[i]);
936 arg = pinconf_to_config_argument(configs[i]);
939 /* Set legacy brcm,pull */
940 case BCM2835_PINCONF_PARAM_PULL:
941 bcm2835_pull_config_set(pc, pin, arg);
944 /* Set pull generic bindings */
945 case PIN_CONFIG_BIAS_DISABLE:
946 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
949 case PIN_CONFIG_BIAS_PULL_DOWN:
950 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
953 case PIN_CONFIG_BIAS_PULL_UP:
954 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
957 /* Set output-high or output-low */
958 case PIN_CONFIG_OUTPUT:
959 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
965 } /* switch param type */
966 } /* for each config */
971 static const struct pinconf_ops bcm2835_pinconf_ops = {
973 .pin_config_get = bcm2835_pinconf_get,
974 .pin_config_set = bcm2835_pinconf_set,
977 static struct pinctrl_desc bcm2835_pinctrl_desc = {
979 .pins = bcm2835_gpio_pins,
980 .npins = ARRAY_SIZE(bcm2835_gpio_pins),
981 .pctlops = &bcm2835_pctl_ops,
982 .pmxops = &bcm2835_pmx_ops,
983 .confops = &bcm2835_pinconf_ops,
984 .owner = THIS_MODULE,
987 static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
989 .npins = BCM2835_NUM_GPIOS,
992 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
994 struct device *dev = &pdev->dev;
995 struct device_node *np = dev->of_node;
996 struct bcm2835_pinctrl *pc;
997 struct resource iomem;
999 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
1000 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
1002 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1006 platform_set_drvdata(pdev, pc);
1009 err = of_address_to_resource(np, 0, &iomem);
1011 dev_err(dev, "could not get IO memory\n");
1015 pc->base = devm_ioremap_resource(dev, &iomem);
1016 if (IS_ERR(pc->base))
1017 return PTR_ERR(pc->base);
1019 pc->gpio_chip = bcm2835_gpio_chip;
1020 pc->gpio_chip.parent = dev;
1021 pc->gpio_chip.of_node = np;
1023 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1024 unsigned long events;
1027 /* clear event detection flags */
1028 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1029 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1030 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1031 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1032 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1033 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1035 /* clear all the events */
1036 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1037 for_each_set_bit(offset, &events, 32)
1038 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1040 raw_spin_lock_init(&pc->irq_lock[i]);
1043 err = gpiochip_add_data(&pc->gpio_chip, pc);
1045 dev_err(dev, "could not add GPIO chip\n");
1049 err = gpiochip_irqchip_add(&pc->gpio_chip, &bcm2835_gpio_irq_chip,
1050 0, handle_level_irq, IRQ_TYPE_NONE);
1052 dev_info(dev, "could not add irqchip\n");
1056 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1057 pc->irq[i] = irq_of_parse_and_map(np, i);
1059 if (pc->irq[i] == 0)
1063 * Use the same handler for all groups: this is necessary
1064 * since we use one gpiochip to cover all lines - the
1065 * irq handler then needs to figure out which group and
1066 * bank that was firing the IRQ and look up the per-group
1069 gpiochip_set_chained_irqchip(&pc->gpio_chip,
1070 &bcm2835_gpio_irq_chip,
1072 bcm2835_gpio_irq_handler);
1075 pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
1076 if (IS_ERR(pc->pctl_dev)) {
1077 gpiochip_remove(&pc->gpio_chip);
1078 return PTR_ERR(pc->pctl_dev);
1081 pc->gpio_range = bcm2835_pinctrl_gpio_range;
1082 pc->gpio_range.base = pc->gpio_chip.base;
1083 pc->gpio_range.gc = &pc->gpio_chip;
1084 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1089 static const struct of_device_id bcm2835_pinctrl_match[] = {
1090 { .compatible = "brcm,bcm2835-gpio" },
1094 static struct platform_driver bcm2835_pinctrl_driver = {
1095 .probe = bcm2835_pinctrl_probe,
1097 .name = MODULE_NAME,
1098 .of_match_table = bcm2835_pinctrl_match,
1099 .suppress_bind_attrs = true,
1102 builtin_platform_driver(bcm2835_pinctrl_driver);