2 * Pinctrl GPIO driver for Intel Baytrail
3 * Copyright (c) 2012-2013, Intel Corporation.
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/types.h>
20 #include <linux/bitops.h>
21 #include <linux/interrupt.h>
22 #include <linux/gpio.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/acpi.h>
25 #include <linux/platform_device.h>
26 #include <linux/seq_file.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/pinctrl/pinconf.h>
32 #include <linux/pinctrl/pinconf-generic.h>
34 /* memory mapped register offsets */
35 #define BYT_CONF0_REG 0x000
36 #define BYT_CONF1_REG 0x004
37 #define BYT_VAL_REG 0x008
38 #define BYT_DFT_REG 0x00c
39 #define BYT_INT_STAT_REG 0x800
40 #define BYT_DEBOUNCE_REG 0x9d0
42 /* BYT_CONF0_REG register bits */
43 #define BYT_IODEN BIT(31)
44 #define BYT_DIRECT_IRQ_EN BIT(27)
45 #define BYT_TRIG_NEG BIT(26)
46 #define BYT_TRIG_POS BIT(25)
47 #define BYT_TRIG_LVL BIT(24)
48 #define BYT_DEBOUNCE_EN BIT(20)
49 #define BYT_PULL_STR_SHIFT 9
50 #define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
51 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
52 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
53 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
54 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
55 #define BYT_PULL_ASSIGN_SHIFT 7
56 #define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
57 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
58 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
59 #define BYT_PIN_MUX 0x07
61 /* BYT_VAL_REG register bits */
62 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
63 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
64 #define BYT_LEVEL BIT(0)
66 #define BYT_DIR_MASK (BIT(1) | BIT(2))
67 #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
69 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | \
71 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
73 /* BYT_DEBOUNCE_REG bits */
74 #define BYT_DEBOUNCE_PULSE_MASK 0x7
75 #define BYT_DEBOUNCE_PULSE_375US 1
76 #define BYT_DEBOUNCE_PULSE_750US 2
77 #define BYT_DEBOUNCE_PULSE_1500US 3
78 #define BYT_DEBOUNCE_PULSE_3MS 4
79 #define BYT_DEBOUNCE_PULSE_6MS 5
80 #define BYT_DEBOUNCE_PULSE_12MS 6
81 #define BYT_DEBOUNCE_PULSE_24MS 7
83 #define BYT_NGPIO_SCORE 102
84 #define BYT_NGPIO_NCORE 28
85 #define BYT_NGPIO_SUS 44
87 #define BYT_SCORE_ACPI_UID "1"
88 #define BYT_NCORE_ACPI_UID "2"
89 #define BYT_SUS_ACPI_UID "3"
92 * This is the function value most pins have for GPIO muxing. If the value
93 * differs from the default one, it must be explicitly mentioned. Otherwise, the
94 * pin control implementation will set the muxing value to default GPIO if it
95 * does not find a match for the requested function.
97 #define BYT_DEFAULT_GPIO_MUX 0
99 struct byt_gpio_pin_context {
104 struct byt_simple_func_mux {
109 struct byt_mixed_func_mux {
111 const unsigned short *func_values;
114 struct byt_pingroup {
116 const unsigned int *pins;
118 unsigned short has_simple_funcs;
120 const struct byt_simple_func_mux *simple_funcs;
121 const struct byt_mixed_func_mux *mixed_funcs;
126 struct byt_function {
128 const char * const *groups;
132 struct byt_community {
133 unsigned int pin_base;
135 const unsigned int *pad_map;
136 void __iomem *reg_base;
139 #define SIMPLE_FUNC(n, f) \
144 #define MIXED_FUNC(n, f) \
147 .func_values = (f), \
150 #define PIN_GROUP_SIMPLE(n, p, f) \
154 .npins = ARRAY_SIZE((p)), \
155 .has_simple_funcs = 1, \
157 .simple_funcs = (f), \
159 .nfuncs = ARRAY_SIZE((f)), \
161 #define PIN_GROUP_MIXED(n, p, f) \
165 .npins = ARRAY_SIZE((p)), \
166 .has_simple_funcs = 0, \
168 .mixed_funcs = (f), \
170 .nfuncs = ARRAY_SIZE((f)), \
173 #define FUNCTION(n, g) \
177 .ngroups = ARRAY_SIZE((g)), \
180 #define COMMUNITY(p, n, map) \
187 struct byt_pinctrl_soc_data {
189 const struct pinctrl_pin_desc *pins;
191 const struct byt_pingroup *groups;
193 const struct byt_function *functions;
195 const struct byt_community *communities;
200 struct gpio_chip chip;
201 struct platform_device *pdev;
202 struct pinctrl_dev *pctl_dev;
203 struct pinctrl_desc pctl_desc;
205 const struct byt_pinctrl_soc_data *soc_data;
206 struct byt_community *communities_copy;
207 struct byt_gpio_pin_context *saved_context;
210 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
211 static const struct pinctrl_pin_desc byt_score_pins[] = {
212 PINCTRL_PIN(0, "SATA_GP0"),
213 PINCTRL_PIN(1, "SATA_GP1"),
214 PINCTRL_PIN(2, "SATA_LED#"),
215 PINCTRL_PIN(3, "PCIE_CLKREQ0"),
216 PINCTRL_PIN(4, "PCIE_CLKREQ1"),
217 PINCTRL_PIN(5, "PCIE_CLKREQ2"),
218 PINCTRL_PIN(6, "PCIE_CLKREQ3"),
219 PINCTRL_PIN(7, "SD3_WP"),
220 PINCTRL_PIN(8, "HDA_RST"),
221 PINCTRL_PIN(9, "HDA_SYNC"),
222 PINCTRL_PIN(10, "HDA_CLK"),
223 PINCTRL_PIN(11, "HDA_SDO"),
224 PINCTRL_PIN(12, "HDA_SDI0"),
225 PINCTRL_PIN(13, "HDA_SDI1"),
226 PINCTRL_PIN(14, "GPIO_S0_SC14"),
227 PINCTRL_PIN(15, "GPIO_S0_SC15"),
228 PINCTRL_PIN(16, "MMC1_CLK"),
229 PINCTRL_PIN(17, "MMC1_D0"),
230 PINCTRL_PIN(18, "MMC1_D1"),
231 PINCTRL_PIN(19, "MMC1_D2"),
232 PINCTRL_PIN(20, "MMC1_D3"),
233 PINCTRL_PIN(21, "MMC1_D4"),
234 PINCTRL_PIN(22, "MMC1_D5"),
235 PINCTRL_PIN(23, "MMC1_D6"),
236 PINCTRL_PIN(24, "MMC1_D7"),
237 PINCTRL_PIN(25, "MMC1_CMD"),
238 PINCTRL_PIN(26, "MMC1_RST"),
239 PINCTRL_PIN(27, "SD2_CLK"),
240 PINCTRL_PIN(28, "SD2_D0"),
241 PINCTRL_PIN(29, "SD2_D1"),
242 PINCTRL_PIN(30, "SD2_D2"),
243 PINCTRL_PIN(31, "SD2_D3_CD"),
244 PINCTRL_PIN(32, "SD2_CMD"),
245 PINCTRL_PIN(33, "SD3_CLK"),
246 PINCTRL_PIN(34, "SD3_D0"),
247 PINCTRL_PIN(35, "SD3_D1"),
248 PINCTRL_PIN(36, "SD3_D2"),
249 PINCTRL_PIN(37, "SD3_D3"),
250 PINCTRL_PIN(38, "SD3_CD"),
251 PINCTRL_PIN(39, "SD3_CMD"),
252 PINCTRL_PIN(40, "SD3_1P8EN"),
253 PINCTRL_PIN(41, "SD3_PWREN#"),
254 PINCTRL_PIN(42, "ILB_LPC_AD0"),
255 PINCTRL_PIN(43, "ILB_LPC_AD1"),
256 PINCTRL_PIN(44, "ILB_LPC_AD2"),
257 PINCTRL_PIN(45, "ILB_LPC_AD3"),
258 PINCTRL_PIN(46, "ILB_LPC_FRAME"),
259 PINCTRL_PIN(47, "ILB_LPC_CLK0"),
260 PINCTRL_PIN(48, "ILB_LPC_CLK1"),
261 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
262 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
263 PINCTRL_PIN(51, "PCU_SMB_DATA"),
264 PINCTRL_PIN(52, "PCU_SMB_CLK"),
265 PINCTRL_PIN(53, "PCU_SMB_ALERT"),
266 PINCTRL_PIN(54, "ILB_8254_SPKR"),
267 PINCTRL_PIN(55, "GPIO_S0_SC55"),
268 PINCTRL_PIN(56, "GPIO_S0_SC56"),
269 PINCTRL_PIN(57, "GPIO_S0_SC57"),
270 PINCTRL_PIN(58, "GPIO_S0_SC58"),
271 PINCTRL_PIN(59, "GPIO_S0_SC59"),
272 PINCTRL_PIN(60, "GPIO_S0_SC60"),
273 PINCTRL_PIN(61, "GPIO_S0_SC61"),
274 PINCTRL_PIN(62, "LPE_I2S2_CLK"),
275 PINCTRL_PIN(63, "LPE_I2S2_FRM"),
276 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
277 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
278 PINCTRL_PIN(66, "SIO_SPI_CS"),
279 PINCTRL_PIN(67, "SIO_SPI_MISO"),
280 PINCTRL_PIN(68, "SIO_SPI_MOSI"),
281 PINCTRL_PIN(69, "SIO_SPI_CLK"),
282 PINCTRL_PIN(70, "SIO_UART1_RXD"),
283 PINCTRL_PIN(71, "SIO_UART1_TXD"),
284 PINCTRL_PIN(72, "SIO_UART1_RTS"),
285 PINCTRL_PIN(73, "SIO_UART1_CTS"),
286 PINCTRL_PIN(74, "SIO_UART2_RXD"),
287 PINCTRL_PIN(75, "SIO_UART2_TXD"),
288 PINCTRL_PIN(76, "SIO_UART2_RTS"),
289 PINCTRL_PIN(77, "SIO_UART2_CTS"),
290 PINCTRL_PIN(78, "SIO_I2C0_DATA"),
291 PINCTRL_PIN(79, "SIO_I2C0_CLK"),
292 PINCTRL_PIN(80, "SIO_I2C1_DATA"),
293 PINCTRL_PIN(81, "SIO_I2C1_CLK"),
294 PINCTRL_PIN(82, "SIO_I2C2_DATA"),
295 PINCTRL_PIN(83, "SIO_I2C2_CLK"),
296 PINCTRL_PIN(84, "SIO_I2C3_DATA"),
297 PINCTRL_PIN(85, "SIO_I2C3_CLK"),
298 PINCTRL_PIN(86, "SIO_I2C4_DATA"),
299 PINCTRL_PIN(87, "SIO_I2C4_CLK"),
300 PINCTRL_PIN(88, "SIO_I2C5_DATA"),
301 PINCTRL_PIN(89, "SIO_I2C5_CLK"),
302 PINCTRL_PIN(90, "SIO_I2C6_DATA"),
303 PINCTRL_PIN(91, "SIO_I2C6_CLK"),
304 PINCTRL_PIN(92, "GPIO_S0_SC92"),
305 PINCTRL_PIN(93, "GPIO_S0_SC93"),
306 PINCTRL_PIN(94, "SIO_PWM0"),
307 PINCTRL_PIN(95, "SIO_PWM1"),
308 PINCTRL_PIN(96, "PMC_PLT_CLK0"),
309 PINCTRL_PIN(97, "PMC_PLT_CLK1"),
310 PINCTRL_PIN(98, "PMC_PLT_CLK2"),
311 PINCTRL_PIN(99, "PMC_PLT_CLK3"),
312 PINCTRL_PIN(100, "PMC_PLT_CLK4"),
313 PINCTRL_PIN(101, "PMC_PLT_CLK5"),
316 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
317 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
318 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
319 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
320 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
321 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
322 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
323 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
324 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
325 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
326 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
331 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
332 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
333 static const struct byt_simple_func_mux byt_score_uart_mux[] = {
334 SIMPLE_FUNC("uart", 1),
337 static const unsigned int byt_score_pwm0_pins[] = { 94 };
338 static const unsigned int byt_score_pwm1_pins[] = { 95 };
339 static const struct byt_simple_func_mux byt_score_pwm_mux[] = {
340 SIMPLE_FUNC("pwm", 1),
343 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
344 static const struct byt_simple_func_mux byt_score_spi_mux[] = {
345 SIMPLE_FUNC("spi", 1),
348 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
349 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
350 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
351 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
352 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
353 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
354 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
355 static const struct byt_simple_func_mux byt_score_i2c_mux[] = {
356 SIMPLE_FUNC("i2c", 1),
359 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
360 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
361 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
362 static const struct byt_simple_func_mux byt_score_ssp_mux[] = {
363 SIMPLE_FUNC("ssp", 1),
366 static const unsigned int byt_score_sdcard_pins[] = {
367 7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
369 static const unsigned short byt_score_sdcard_mux_values[] = {
370 2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
372 static const struct byt_mixed_func_mux byt_score_sdcard_mux[] = {
373 MIXED_FUNC("sdcard", byt_score_sdcard_mux_values),
376 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
377 static const struct byt_simple_func_mux byt_score_sdio_mux[] = {
378 SIMPLE_FUNC("sdio", 1),
381 static const unsigned int byt_score_emmc_pins[] = {
382 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
384 static const struct byt_simple_func_mux byt_score_emmc_mux[] = {
385 SIMPLE_FUNC("emmc", 1),
388 static const unsigned int byt_score_ilb_lpc_pins[] = {
389 42, 43, 44, 45, 46, 47, 48, 49, 50,
391 static const struct byt_simple_func_mux byt_score_lpc_mux[] = {
392 SIMPLE_FUNC("lpc", 1),
395 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
396 static const struct byt_simple_func_mux byt_score_sata_mux[] = {
397 SIMPLE_FUNC("sata", 1),
400 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
401 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
402 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
403 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
404 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
405 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
406 static const struct byt_simple_func_mux byt_score_plt_clk_mux[] = {
407 SIMPLE_FUNC("plt_clk", 1),
410 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
411 static const struct byt_simple_func_mux byt_score_smbus_mux[] = {
412 SIMPLE_FUNC("smbus", 1),
415 static const struct byt_pingroup byt_score_groups[] = {
416 PIN_GROUP_SIMPLE("uart1_grp",
417 byt_score_uart1_pins, byt_score_uart_mux),
418 PIN_GROUP_SIMPLE("uart2_grp",
419 byt_score_uart2_pins, byt_score_uart_mux),
420 PIN_GROUP_SIMPLE("pwm0_grp",
421 byt_score_pwm0_pins, byt_score_pwm_mux),
422 PIN_GROUP_SIMPLE("pwm1_grp",
423 byt_score_pwm1_pins, byt_score_pwm_mux),
424 PIN_GROUP_SIMPLE("ssp2_grp",
425 byt_score_ssp2_pins, byt_score_pwm_mux),
426 PIN_GROUP_SIMPLE("sio_spi_grp",
427 byt_score_sio_spi_pins, byt_score_spi_mux),
428 PIN_GROUP_SIMPLE("i2c5_grp",
429 byt_score_i2c5_pins, byt_score_i2c_mux),
430 PIN_GROUP_SIMPLE("i2c6_grp",
431 byt_score_i2c6_pins, byt_score_i2c_mux),
432 PIN_GROUP_SIMPLE("i2c4_grp",
433 byt_score_i2c4_pins, byt_score_i2c_mux),
434 PIN_GROUP_SIMPLE("i2c3_grp",
435 byt_score_i2c3_pins, byt_score_i2c_mux),
436 PIN_GROUP_SIMPLE("i2c2_grp",
437 byt_score_i2c2_pins, byt_score_i2c_mux),
438 PIN_GROUP_SIMPLE("i2c1_grp",
439 byt_score_i2c1_pins, byt_score_i2c_mux),
440 PIN_GROUP_SIMPLE("i2c0_grp",
441 byt_score_i2c0_pins, byt_score_i2c_mux),
442 PIN_GROUP_SIMPLE("ssp0_grp",
443 byt_score_ssp0_pins, byt_score_ssp_mux),
444 PIN_GROUP_SIMPLE("ssp1_grp",
445 byt_score_ssp1_pins, byt_score_ssp_mux),
446 PIN_GROUP_MIXED("sdcard_grp",
447 byt_score_sdcard_pins, byt_score_sdcard_mux),
448 PIN_GROUP_SIMPLE("sdio_grp",
449 byt_score_sdio_pins, byt_score_sdio_mux),
450 PIN_GROUP_SIMPLE("emmc_grp",
451 byt_score_emmc_pins, byt_score_emmc_mux),
452 PIN_GROUP_SIMPLE("lpc_grp",
453 byt_score_ilb_lpc_pins, byt_score_lpc_mux),
454 PIN_GROUP_SIMPLE("sata_grp",
455 byt_score_sata_pins, byt_score_sata_mux),
456 PIN_GROUP_SIMPLE("plt_clk0_grp",
457 byt_score_plt_clk0_pins, byt_score_plt_clk_mux),
458 PIN_GROUP_SIMPLE("plt_clk1_grp",
459 byt_score_plt_clk1_pins, byt_score_plt_clk_mux),
460 PIN_GROUP_SIMPLE("plt_clk2_grp",
461 byt_score_plt_clk2_pins, byt_score_plt_clk_mux),
462 PIN_GROUP_SIMPLE("plt_clk3_grp",
463 byt_score_plt_clk3_pins, byt_score_plt_clk_mux),
464 PIN_GROUP_SIMPLE("plt_clk4_grp",
465 byt_score_plt_clk4_pins, byt_score_plt_clk_mux),
466 PIN_GROUP_SIMPLE("plt_clk5_grp",
467 byt_score_plt_clk5_pins, byt_score_plt_clk_mux),
468 PIN_GROUP_SIMPLE("smbus_grp",
469 byt_score_smbus_pins, byt_score_smbus_mux),
472 static const char * const byt_score_uart_groups[] = {
473 "uart1_grp", "uart2_grp",
475 static const char * const byt_score_pwm_groups[] = {
476 "pwm0_grp", "pwm1_grp",
478 static const char * const byt_score_ssp_groups[] = {
479 "ssp0_grp", "ssp1_grp", "ssp2_grp",
481 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
482 static const char * const byt_score_i2c_groups[] = {
483 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
486 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
487 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
488 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
489 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
490 static const char * const byt_score_sata_groups[] = { "sata_grp" };
491 static const char * const byt_score_plt_clk_groups[] = {
492 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
493 "plt_clk4_grp", "plt_clk5_grp",
495 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
496 static const char * const byt_score_gpio_groups[] = {
497 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
498 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
499 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
500 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
501 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
502 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
506 static const struct byt_function byt_score_functions[] = {
507 FUNCTION("uart", byt_score_uart_groups),
508 FUNCTION("pwm", byt_score_pwm_groups),
509 FUNCTION("ssp", byt_score_ssp_groups),
510 FUNCTION("spi", byt_score_spi_groups),
511 FUNCTION("i2c", byt_score_i2c_groups),
512 FUNCTION("sdcard", byt_score_sdcard_groups),
513 FUNCTION("sdio", byt_score_sdio_groups),
514 FUNCTION("emmc", byt_score_emmc_groups),
515 FUNCTION("lpc", byt_score_lpc_groups),
516 FUNCTION("sata", byt_score_sata_groups),
517 FUNCTION("plt_clk", byt_score_plt_clk_groups),
518 FUNCTION("smbus", byt_score_smbus_groups),
519 FUNCTION("gpio", byt_score_gpio_groups),
522 static const struct byt_community byt_score_communities[] = {
523 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
526 static const struct byt_pinctrl_soc_data byt_score_soc_data = {
527 .uid = BYT_SCORE_ACPI_UID,
528 .pins = byt_score_pins,
529 .npins = ARRAY_SIZE(byt_score_pins),
530 .groups = byt_score_groups,
531 .ngroups = ARRAY_SIZE(byt_score_groups),
532 .functions = byt_score_functions,
533 .nfunctions = ARRAY_SIZE(byt_score_functions),
534 .communities = byt_score_communities,
535 .ncommunities = ARRAY_SIZE(byt_score_communities),
538 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */
539 static const struct pinctrl_pin_desc byt_sus_pins[] = {
540 PINCTRL_PIN(0, "GPIO_S50"),
541 PINCTRL_PIN(1, "GPIO_S51"),
542 PINCTRL_PIN(2, "GPIO_S52"),
543 PINCTRL_PIN(3, "GPIO_S53"),
544 PINCTRL_PIN(4, "GPIO_S54"),
545 PINCTRL_PIN(5, "GPIO_S55"),
546 PINCTRL_PIN(6, "GPIO_S56"),
547 PINCTRL_PIN(7, "GPIO_S57"),
548 PINCTRL_PIN(8, "GPIO_S58"),
549 PINCTRL_PIN(9, "GPIO_S59"),
550 PINCTRL_PIN(10, "GPIO_S510"),
551 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
552 PINCTRL_PIN(12, "PMC_SUSCLK0"),
553 PINCTRL_PIN(13, "GPIO_S513"),
554 PINCTRL_PIN(14, "USB_ULPI_RST"),
555 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
556 PINCTRL_PIN(16, "PMC_PWRBTN"),
557 PINCTRL_PIN(17, "GPIO_S517"),
558 PINCTRL_PIN(18, "PMC_SUS_STAT"),
559 PINCTRL_PIN(19, "USB_OC0"),
560 PINCTRL_PIN(20, "USB_OC1"),
561 PINCTRL_PIN(21, "PCU_SPI_CS1"),
562 PINCTRL_PIN(22, "GPIO_S522"),
563 PINCTRL_PIN(23, "GPIO_S523"),
564 PINCTRL_PIN(24, "GPIO_S524"),
565 PINCTRL_PIN(25, "GPIO_S525"),
566 PINCTRL_PIN(26, "GPIO_S526"),
567 PINCTRL_PIN(27, "GPIO_S527"),
568 PINCTRL_PIN(28, "GPIO_S528"),
569 PINCTRL_PIN(29, "GPIO_S529"),
570 PINCTRL_PIN(30, "GPIO_S530"),
571 PINCTRL_PIN(31, "USB_ULPI_CLK"),
572 PINCTRL_PIN(32, "USB_ULPI_DATA0"),
573 PINCTRL_PIN(33, "USB_ULPI_DATA1"),
574 PINCTRL_PIN(34, "USB_ULPI_DATA2"),
575 PINCTRL_PIN(35, "USB_ULPI_DATA3"),
576 PINCTRL_PIN(36, "USB_ULPI_DATA4"),
577 PINCTRL_PIN(37, "USB_ULPI_DATA5"),
578 PINCTRL_PIN(38, "USB_ULPI_DATA6"),
579 PINCTRL_PIN(39, "USB_ULPI_DATA7"),
580 PINCTRL_PIN(40, "USB_ULPI_DIR"),
581 PINCTRL_PIN(41, "USB_ULPI_NXT"),
582 PINCTRL_PIN(42, "USB_ULPI_STP"),
583 PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
586 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
587 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
588 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
589 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
590 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
594 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
595 static const struct byt_simple_func_mux byt_sus_usb_oc_mux[] = {
596 SIMPLE_FUNC("usb", 0),
597 SIMPLE_FUNC("gpio", 1),
600 static const unsigned int byt_sus_usb_ulpi_pins[] = {
601 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
603 static const unsigned short byt_sus_usb_ulpi_mode_values[] = {
604 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
606 static const unsigned short byt_sus_usb_ulpi_gpio_mode_values[] = {
607 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
609 static const struct byt_mixed_func_mux byt_sus_usb_ulpi_mux[] = {
610 MIXED_FUNC("usb", byt_sus_usb_ulpi_mode_values),
611 MIXED_FUNC("gpio", byt_sus_usb_ulpi_gpio_mode_values),
614 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
615 static const struct byt_simple_func_mux byt_sus_pcu_spi_mux[] = {
616 SIMPLE_FUNC("spi", 0),
617 SIMPLE_FUNC("gpio", 1),
620 static const struct byt_pingroup byt_sus_groups[] = {
621 PIN_GROUP_SIMPLE("usb_oc_grp",
622 byt_sus_usb_over_current_pins, byt_sus_usb_oc_mux),
623 PIN_GROUP_MIXED("usb_ulpi_grp",
624 byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mux),
625 PIN_GROUP_SIMPLE("pcu_spi_grp",
626 byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mux),
629 static const char * const byt_sus_usb_groups[] = {
630 "usb_oc_grp", "usb_ulpi_grp",
632 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
633 static const char * const byt_sus_gpio_groups[] = {
634 "usb_oc_grp", "usb_ulpi_grp", "pcu_spi_grp",
637 static const struct byt_function byt_sus_functions[] = {
638 FUNCTION("usb", byt_sus_usb_groups),
639 FUNCTION("spi", byt_sus_spi_groups),
640 FUNCTION("gpio", byt_sus_gpio_groups),
643 static const struct byt_community byt_sus_communities[] = {
644 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
647 static const struct byt_pinctrl_soc_data byt_sus_soc_data = {
648 .uid = BYT_SUS_ACPI_UID,
649 .pins = byt_sus_pins,
650 .npins = ARRAY_SIZE(byt_sus_pins),
651 .groups = byt_sus_groups,
652 .ngroups = ARRAY_SIZE(byt_sus_groups),
653 .functions = byt_sus_functions,
654 .nfunctions = ARRAY_SIZE(byt_sus_functions),
655 .communities = byt_sus_communities,
656 .ncommunities = ARRAY_SIZE(byt_sus_communities),
659 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
660 PINCTRL_PIN(0, "GPIO_NCORE0"),
661 PINCTRL_PIN(1, "GPIO_NCORE1"),
662 PINCTRL_PIN(2, "GPIO_NCORE2"),
663 PINCTRL_PIN(3, "GPIO_NCORE3"),
664 PINCTRL_PIN(4, "GPIO_NCORE4"),
665 PINCTRL_PIN(5, "GPIO_NCORE5"),
666 PINCTRL_PIN(6, "GPIO_NCORE6"),
667 PINCTRL_PIN(7, "GPIO_NCORE7"),
668 PINCTRL_PIN(8, "GPIO_NCORE8"),
669 PINCTRL_PIN(9, "GPIO_NCORE9"),
670 PINCTRL_PIN(10, "GPIO_NCORE10"),
671 PINCTRL_PIN(11, "GPIO_NCORE11"),
672 PINCTRL_PIN(12, "GPIO_NCORE12"),
673 PINCTRL_PIN(13, "GPIO_NCORE13"),
674 PINCTRL_PIN(14, "GPIO_NCORE14"),
675 PINCTRL_PIN(15, "GPIO_NCORE15"),
676 PINCTRL_PIN(16, "GPIO_NCORE16"),
677 PINCTRL_PIN(17, "GPIO_NCORE17"),
678 PINCTRL_PIN(18, "GPIO_NCORE18"),
679 PINCTRL_PIN(19, "GPIO_NCORE19"),
680 PINCTRL_PIN(20, "GPIO_NCORE20"),
681 PINCTRL_PIN(21, "GPIO_NCORE21"),
682 PINCTRL_PIN(22, "GPIO_NCORE22"),
683 PINCTRL_PIN(23, "GPIO_NCORE23"),
684 PINCTRL_PIN(24, "GPIO_NCORE24"),
685 PINCTRL_PIN(25, "GPIO_NCORE25"),
686 PINCTRL_PIN(26, "GPIO_NCORE26"),
687 PINCTRL_PIN(27, "GPIO_NCORE27"),
690 static unsigned const byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
691 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
692 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
693 3, 6, 10, 13, 2, 5, 9, 7,
696 static const struct byt_community byt_ncore_communities[] = {
697 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
700 static const struct byt_pinctrl_soc_data byt_ncore_soc_data = {
701 .uid = BYT_NCORE_ACPI_UID,
702 .pins = byt_ncore_pins,
703 .npins = ARRAY_SIZE(byt_ncore_pins),
704 .communities = byt_ncore_communities,
705 .ncommunities = ARRAY_SIZE(byt_ncore_communities),
708 static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
715 static struct byt_community *byt_get_community(struct byt_gpio *vg,
718 struct byt_community *comm;
721 for (i = 0; i < vg->soc_data->ncommunities; i++) {
722 comm = vg->communities_copy + i;
723 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
730 static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
733 struct byt_community *comm = byt_get_community(vg, offset);
739 offset -= comm->pin_base;
740 if (reg == BYT_INT_STAT_REG)
741 reg_offset = (offset / 32) * 4;
743 reg_offset = comm->pad_map[offset] * 16;
745 return comm->reg_base + reg_offset + reg;
748 static int byt_get_groups_count(struct pinctrl_dev *pctldev)
750 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
752 return vg->soc_data->ngroups;
755 static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
756 unsigned int selector)
758 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
760 return vg->soc_data->groups[selector].name;
763 static int byt_get_group_pins(struct pinctrl_dev *pctldev,
764 unsigned int selector,
765 const unsigned int **pins,
766 unsigned int *num_pins)
768 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
770 *pins = vg->soc_data->groups[selector].pins;
771 *num_pins = vg->soc_data->groups[selector].npins;
776 static const struct pinctrl_ops byt_pinctrl_ops = {
777 .get_groups_count = byt_get_groups_count,
778 .get_group_name = byt_get_group_name,
779 .get_group_pins = byt_get_group_pins,
782 static int byt_get_functions_count(struct pinctrl_dev *pctldev)
784 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
786 return vg->soc_data->nfunctions;
789 static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
790 unsigned int selector)
792 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
794 return vg->soc_data->functions[selector].name;
797 static int byt_get_function_groups(struct pinctrl_dev *pctldev,
798 unsigned int selector,
799 const char * const **groups,
800 unsigned int *num_groups)
802 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
804 *groups = vg->soc_data->functions[selector].groups;
805 *num_groups = vg->soc_data->functions[selector].ngroups;
810 static int byt_get_group_simple_mux(const struct byt_pingroup group,
811 const char *func_name,
812 unsigned short *func)
816 for (i = 0; i < group.nfuncs; i++) {
817 if (!strcmp(group.simple_funcs[i].name, func_name)) {
818 *func = group.simple_funcs[i].func;
826 static int byt_get_group_mixed_mux(const struct byt_pingroup group,
827 const char *func_name,
828 const unsigned short **func)
832 for (i = 0; i < group.nfuncs; i++) {
833 if (!strcmp(group.mixed_funcs[i].name, func_name)) {
834 *func = group.mixed_funcs[i].func_values;
842 static void byt_set_group_simple_mux(struct byt_gpio *vg,
843 const struct byt_pingroup group,
849 raw_spin_lock_irqsave(&vg->lock, flags);
851 for (i = 0; i < group.npins; i++) {
852 void __iomem *padcfg0;
855 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
857 dev_warn(&vg->pdev->dev,
858 "Group %s, pin %i not muxed (no padcfg0)\n",
863 value = readl(padcfg0);
864 value &= ~BYT_PIN_MUX;
866 writel(value, padcfg0);
869 raw_spin_unlock_irqrestore(&vg->lock, flags);
872 static void byt_set_group_mixed_mux(struct byt_gpio *vg,
873 const struct byt_pingroup group,
874 const unsigned short *func)
879 raw_spin_lock_irqsave(&vg->lock, flags);
881 for (i = 0; i < group.npins; i++) {
882 void __iomem *padcfg0;
885 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
887 dev_warn(&vg->pdev->dev,
888 "Group %s, pin %i not muxed (no padcfg0)\n",
893 value = readl(padcfg0);
894 value &= ~BYT_PIN_MUX;
896 writel(value, padcfg0);
899 raw_spin_unlock_irqrestore(&vg->lock, flags);
902 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
903 unsigned int group_selector)
905 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
906 const struct byt_function func = vg->soc_data->functions[func_selector];
907 const struct byt_pingroup group = vg->soc_data->groups[group_selector];
908 const unsigned short *mixed_func;
909 unsigned short simple_func;
912 if (group.has_simple_funcs)
913 ret = byt_get_group_simple_mux(group, func.name, &simple_func);
915 ret = byt_get_group_mixed_mux(group, func.name, &mixed_func);
918 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
919 else if (group.has_simple_funcs)
920 byt_set_group_simple_mux(vg, group, simple_func);
922 byt_set_group_mixed_mux(vg, group, mixed_func);
927 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
929 /* SCORE pin 92-93 */
930 if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&
931 offset >= 92 && offset <= 93)
935 if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) &&
936 offset >= 11 && offset <= 21)
942 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
944 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
948 raw_spin_lock_irqsave(&vg->lock, flags);
950 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
952 raw_spin_unlock_irqrestore(&vg->lock, flags);
955 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
956 struct pinctrl_gpio_range *range,
959 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
960 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
964 raw_spin_lock_irqsave(&vg->lock, flags);
967 * In most cases, func pin mux 000 means GPIO function.
968 * But, some pins may have func pin mux 001 represents
971 * Because there are devices out there where some pins were not
972 * configured correctly we allow changing the mux value from
973 * request (but print out warning about that).
975 value = readl(reg) & BYT_PIN_MUX;
976 gpio_mux = byt_get_gpio_mux(vg, offset);
977 if (WARN_ON(gpio_mux != value)) {
978 value = readl(reg) & ~BYT_PIN_MUX;
982 dev_warn(&vg->pdev->dev,
983 "pin %u forcibly re-configured as GPIO\n", offset);
986 raw_spin_unlock_irqrestore(&vg->lock, flags);
988 pm_runtime_get(&vg->pdev->dev);
993 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
994 struct pinctrl_gpio_range *range,
997 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
999 byt_gpio_clear_triggering(vg, offset);
1000 pm_runtime_put(&vg->pdev->dev);
1003 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
1004 struct pinctrl_gpio_range *range,
1005 unsigned int offset,
1008 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1009 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1010 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1011 unsigned long flags;
1014 raw_spin_lock_irqsave(&vg->lock, flags);
1016 value = readl(val_reg);
1017 value &= ~BYT_DIR_MASK;
1019 value |= BYT_OUTPUT_EN;
1022 * Before making any direction modifications, do a check if gpio
1023 * is set for direct IRQ. On baytrail, setting GPIO to output
1024 * does not make sense, so let's at least warn the caller before
1025 * they shoot themselves in the foot.
1027 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
1028 "Potential Error: Setting GPIO with direct_irq_en to output");
1029 writel(value, val_reg);
1031 raw_spin_unlock_irqrestore(&vg->lock, flags);
1036 static const struct pinmux_ops byt_pinmux_ops = {
1037 .get_functions_count = byt_get_functions_count,
1038 .get_function_name = byt_get_function_name,
1039 .get_function_groups = byt_get_function_groups,
1040 .set_mux = byt_set_mux,
1041 .gpio_request_enable = byt_gpio_request_enable,
1042 .gpio_disable_free = byt_gpio_disable_free,
1043 .gpio_set_direction = byt_gpio_set_direction,
1046 static void byt_get_pull_strength(u32 reg, u16 *strength)
1048 switch (reg & BYT_PULL_STR_MASK) {
1049 case BYT_PULL_STR_2K:
1052 case BYT_PULL_STR_10K:
1055 case BYT_PULL_STR_20K:
1058 case BYT_PULL_STR_40K:
1064 static int byt_set_pull_strength(u32 *reg, u16 strength)
1066 *reg &= ~BYT_PULL_STR_MASK;
1070 *reg |= BYT_PULL_STR_2K;
1073 *reg |= BYT_PULL_STR_10K;
1076 *reg |= BYT_PULL_STR_20K;
1079 *reg |= BYT_PULL_STR_40K;
1088 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
1089 unsigned long *config)
1091 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1092 enum pin_config_param param = pinconf_to_config_param(*config);
1093 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1094 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1095 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
1096 unsigned long flags;
1097 u32 conf, pull, val, debounce;
1100 raw_spin_lock_irqsave(&vg->lock, flags);
1101 conf = readl(conf_reg);
1102 pull = conf & BYT_PULL_ASSIGN_MASK;
1103 val = readl(val_reg);
1104 raw_spin_unlock_irqrestore(&vg->lock, flags);
1107 case PIN_CONFIG_BIAS_DISABLE:
1111 case PIN_CONFIG_BIAS_PULL_DOWN:
1112 /* Pull assignment is only applicable in input mode */
1113 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
1116 byt_get_pull_strength(conf, &arg);
1119 case PIN_CONFIG_BIAS_PULL_UP:
1120 /* Pull assignment is only applicable in input mode */
1121 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
1124 byt_get_pull_strength(conf, &arg);
1127 case PIN_CONFIG_INPUT_DEBOUNCE:
1128 if (!(conf & BYT_DEBOUNCE_EN))
1131 raw_spin_lock_irqsave(&vg->lock, flags);
1132 debounce = readl(db_reg);
1133 raw_spin_unlock_irqrestore(&vg->lock, flags);
1135 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
1136 case BYT_DEBOUNCE_PULSE_375US:
1139 case BYT_DEBOUNCE_PULSE_750US:
1142 case BYT_DEBOUNCE_PULSE_1500US:
1145 case BYT_DEBOUNCE_PULSE_3MS:
1148 case BYT_DEBOUNCE_PULSE_6MS:
1151 case BYT_DEBOUNCE_PULSE_12MS:
1154 case BYT_DEBOUNCE_PULSE_24MS:
1166 *config = pinconf_to_config_packed(param, arg);
1171 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
1172 unsigned int offset,
1173 unsigned long *configs,
1174 unsigned int num_configs)
1176 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1177 unsigned int param, arg;
1178 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1179 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1180 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
1181 unsigned long flags;
1182 u32 conf, val, debounce;
1185 raw_spin_lock_irqsave(&vg->lock, flags);
1187 conf = readl(conf_reg);
1188 val = readl(val_reg);
1190 for (i = 0; i < num_configs; i++) {
1191 param = pinconf_to_config_param(configs[i]);
1192 arg = pinconf_to_config_argument(configs[i]);
1195 case PIN_CONFIG_BIAS_DISABLE:
1196 conf &= ~BYT_PULL_ASSIGN_MASK;
1198 case PIN_CONFIG_BIAS_PULL_DOWN:
1199 /* Set default strength value in case none is given */
1204 * Pull assignment is only applicable in input mode. If
1205 * chip is not in input mode, set it and warn about it.
1207 if (val & BYT_INPUT_EN) {
1208 val &= ~BYT_INPUT_EN;
1209 writel(val, val_reg);
1210 dev_warn(&vg->pdev->dev,
1211 "pin %u forcibly set to input mode\n",
1215 conf &= ~BYT_PULL_ASSIGN_MASK;
1216 conf |= BYT_PULL_ASSIGN_DOWN;
1217 ret = byt_set_pull_strength(&conf, arg);
1220 case PIN_CONFIG_BIAS_PULL_UP:
1221 /* Set default strength value in case none is given */
1226 * Pull assignment is only applicable in input mode. If
1227 * chip is not in input mode, set it and warn about it.
1229 if (val & BYT_INPUT_EN) {
1230 val &= ~BYT_INPUT_EN;
1231 writel(val, val_reg);
1232 dev_warn(&vg->pdev->dev,
1233 "pin %u forcibly set to input mode\n",
1237 conf &= ~BYT_PULL_ASSIGN_MASK;
1238 conf |= BYT_PULL_ASSIGN_UP;
1239 ret = byt_set_pull_strength(&conf, arg);
1242 case PIN_CONFIG_INPUT_DEBOUNCE:
1243 debounce = readl(db_reg);
1244 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1248 conf &= BYT_DEBOUNCE_EN;
1251 debounce |= BYT_DEBOUNCE_PULSE_375US;
1254 debounce |= BYT_DEBOUNCE_PULSE_750US;
1257 debounce |= BYT_DEBOUNCE_PULSE_1500US;
1260 debounce |= BYT_DEBOUNCE_PULSE_3MS;
1263 debounce |= BYT_DEBOUNCE_PULSE_6MS;
1266 debounce |= BYT_DEBOUNCE_PULSE_12MS;
1269 debounce |= BYT_DEBOUNCE_PULSE_24MS;
1276 writel(debounce, db_reg);
1287 writel(conf, conf_reg);
1289 raw_spin_unlock_irqrestore(&vg->lock, flags);
1294 static const struct pinconf_ops byt_pinconf_ops = {
1296 .pin_config_get = byt_pin_config_get,
1297 .pin_config_set = byt_pin_config_set,
1300 static const struct pinctrl_desc byt_pinctrl_desc = {
1301 .pctlops = &byt_pinctrl_ops,
1302 .pmxops = &byt_pinmux_ops,
1303 .confops = &byt_pinconf_ops,
1304 .owner = THIS_MODULE,
1307 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
1309 struct byt_gpio *vg = gpiochip_get_data(chip);
1310 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1311 unsigned long flags;
1314 raw_spin_lock_irqsave(&vg->lock, flags);
1316 raw_spin_unlock_irqrestore(&vg->lock, flags);
1318 return !!(val & BYT_LEVEL);
1321 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1323 struct byt_gpio *vg = gpiochip_get_data(chip);
1324 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1325 unsigned long flags;
1331 raw_spin_lock_irqsave(&vg->lock, flags);
1332 old_val = readl(reg);
1334 writel(old_val | BYT_LEVEL, reg);
1336 writel(old_val & ~BYT_LEVEL, reg);
1337 raw_spin_unlock_irqrestore(&vg->lock, flags);
1340 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1342 struct byt_gpio *vg = gpiochip_get_data(chip);
1343 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1344 unsigned long flags;
1350 raw_spin_lock_irqsave(&vg->lock, flags);
1352 raw_spin_unlock_irqrestore(&vg->lock, flags);
1354 if (!(value & BYT_OUTPUT_EN))
1355 return GPIOF_DIR_OUT;
1356 if (!(value & BYT_INPUT_EN))
1357 return GPIOF_DIR_IN;
1362 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1364 return pinctrl_gpio_direction_input(chip->base + offset);
1367 static int byt_gpio_direction_output(struct gpio_chip *chip,
1368 unsigned int offset, int value)
1370 int ret = pinctrl_gpio_direction_output(chip->base + offset);
1375 byt_gpio_set(chip, offset, value);
1380 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1382 struct byt_gpio *vg = gpiochip_get_data(chip);
1386 for (i = 0; i < vg->soc_data->npins; i++) {
1387 const struct byt_community *comm;
1388 const char *pull_str = NULL;
1389 const char *pull = NULL;
1391 unsigned long flags;
1395 raw_spin_lock_irqsave(&vg->lock, flags);
1396 pin = vg->soc_data->pins[i].number;
1397 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1400 "Could not retrieve pin %i conf0 reg\n",
1402 raw_spin_unlock_irqrestore(&vg->lock, flags);
1407 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1410 "Could not retrieve pin %i val reg\n", pin);
1411 raw_spin_unlock_irqrestore(&vg->lock, flags);
1415 raw_spin_unlock_irqrestore(&vg->lock, flags);
1417 comm = byt_get_community(vg, pin);
1420 "Could not get community for pin %i\n", pin);
1423 label = gpiochip_is_requested(chip, i);
1425 label = "Unrequested";
1427 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1428 case BYT_PULL_ASSIGN_UP:
1431 case BYT_PULL_ASSIGN_DOWN:
1436 switch (conf0 & BYT_PULL_STR_MASK) {
1437 case BYT_PULL_STR_2K:
1440 case BYT_PULL_STR_10K:
1443 case BYT_PULL_STR_20K:
1446 case BYT_PULL_STR_40K:
1452 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1455 val & BYT_INPUT_EN ? " " : "in",
1456 val & BYT_OUTPUT_EN ? " " : "out",
1457 val & BYT_LEVEL ? "hi" : "lo",
1458 comm->pad_map[i], comm->pad_map[i] * 32,
1460 conf0 & BYT_TRIG_NEG ? " fall" : " ",
1461 conf0 & BYT_TRIG_POS ? " rise" : " ",
1462 conf0 & BYT_TRIG_LVL ? " level" : " ");
1464 if (pull && pull_str)
1465 seq_printf(s, " %-4s %-3s", pull, pull_str);
1469 if (conf0 & BYT_IODEN)
1470 seq_puts(s, " open-drain");
1476 static const struct gpio_chip byt_gpio_chip = {
1477 .owner = THIS_MODULE,
1478 .request = gpiochip_generic_request,
1479 .free = gpiochip_generic_free,
1480 .get_direction = byt_gpio_get_direction,
1481 .direction_input = byt_gpio_direction_input,
1482 .direction_output = byt_gpio_direction_output,
1483 .get = byt_gpio_get,
1484 .set = byt_gpio_set,
1485 .dbg_show = byt_gpio_dbg_show,
1488 static void byt_irq_ack(struct irq_data *d)
1490 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1491 struct byt_gpio *vg = gpiochip_get_data(gc);
1492 unsigned offset = irqd_to_hwirq(d);
1495 reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
1499 raw_spin_lock(&vg->lock);
1500 writel(BIT(offset % 32), reg);
1501 raw_spin_unlock(&vg->lock);
1504 static void byt_irq_mask(struct irq_data *d)
1506 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1507 struct byt_gpio *vg = gpiochip_get_data(gc);
1509 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1512 static void byt_irq_unmask(struct irq_data *d)
1514 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1515 struct byt_gpio *vg = gpiochip_get_data(gc);
1516 unsigned offset = irqd_to_hwirq(d);
1517 unsigned long flags;
1521 reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1525 raw_spin_lock_irqsave(&vg->lock, flags);
1528 switch (irqd_get_trigger_type(d)) {
1529 case IRQ_TYPE_LEVEL_HIGH:
1530 value |= BYT_TRIG_LVL;
1531 case IRQ_TYPE_EDGE_RISING:
1532 value |= BYT_TRIG_POS;
1534 case IRQ_TYPE_LEVEL_LOW:
1535 value |= BYT_TRIG_LVL;
1536 case IRQ_TYPE_EDGE_FALLING:
1537 value |= BYT_TRIG_NEG;
1539 case IRQ_TYPE_EDGE_BOTH:
1540 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1546 raw_spin_unlock_irqrestore(&vg->lock, flags);
1549 static int byt_irq_type(struct irq_data *d, unsigned int type)
1551 struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1552 u32 offset = irqd_to_hwirq(d);
1554 unsigned long flags;
1555 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1557 if (!reg || offset >= vg->chip.ngpio)
1560 raw_spin_lock_irqsave(&vg->lock, flags);
1563 WARN(value & BYT_DIRECT_IRQ_EN,
1564 "Bad pad config for io mode, force direct_irq_en bit clearing");
1566 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1567 * are used to indicate high and low level triggering
1569 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1574 if (type & IRQ_TYPE_EDGE_BOTH)
1575 irq_set_handler_locked(d, handle_edge_irq);
1576 else if (type & IRQ_TYPE_LEVEL_MASK)
1577 irq_set_handler_locked(d, handle_level_irq);
1579 raw_spin_unlock_irqrestore(&vg->lock, flags);
1584 static struct irq_chip byt_irqchip = {
1586 .irq_ack = byt_irq_ack,
1587 .irq_mask = byt_irq_mask,
1588 .irq_unmask = byt_irq_unmask,
1589 .irq_set_type = byt_irq_type,
1590 .flags = IRQCHIP_SKIP_SET_WAKE,
1593 static void byt_gpio_irq_handler(struct irq_desc *desc)
1595 struct irq_data *data = irq_desc_get_irq_data(desc);
1596 struct byt_gpio *vg = gpiochip_get_data(
1597 irq_desc_get_handler_data(desc));
1598 struct irq_chip *chip = irq_data_get_irq_chip(data);
1601 unsigned long pending;
1604 /* check from GPIO controller which pin triggered the interrupt */
1605 for (base = 0; base < vg->chip.ngpio; base += 32) {
1606 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1609 dev_warn(&vg->pdev->dev,
1610 "Pin %i: could not retrieve interrupt status register\n",
1615 pending = readl(reg);
1616 for_each_set_bit(pin, &pending, 32) {
1617 virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
1618 generic_handle_irq(virq);
1621 chip->irq_eoi(data);
1624 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
1626 struct gpio_chip *gc = &vg->chip;
1627 struct device *dev = &vg->pdev->dev;
1633 * Clear interrupt triggers for all pins that are GPIOs and
1634 * do not use direct IRQ mode. This will prevent spurious
1635 * interrupts from misconfigured pins.
1637 for (i = 0; i < vg->soc_data->npins; i++) {
1638 unsigned int pin = vg->soc_data->pins[i].number;
1640 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1642 dev_warn(&vg->pdev->dev,
1643 "Pin %i: could not retrieve conf0 register\n",
1649 if (value & BYT_DIRECT_IRQ_EN) {
1650 clear_bit(i, gc->irq_valid_mask);
1651 dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i);
1652 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1653 byt_gpio_clear_triggering(vg, i);
1654 dev_dbg(dev, "disabling GPIO %d\n", i);
1658 /* clear interrupt status trigger registers */
1659 for (base = 0; base < vg->soc_data->npins; base += 32) {
1660 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1663 dev_warn(&vg->pdev->dev,
1664 "Pin %i: could not retrieve irq status reg\n",
1669 writel(0xffffffff, reg);
1670 /* make sure trigger bits are cleared, if not then a pin
1671 might be misconfigured in bios */
1674 dev_err(&vg->pdev->dev,
1675 "GPIO interrupt error, pins misconfigured\n");
1679 static int byt_gpio_probe(struct byt_gpio *vg)
1681 struct gpio_chip *gc;
1682 struct resource *irq_rc;
1685 /* Set up gpio chip */
1686 vg->chip = byt_gpio_chip;
1688 gc->label = dev_name(&vg->pdev->dev);
1690 gc->can_sleep = false;
1691 gc->parent = &vg->pdev->dev;
1692 gc->ngpio = vg->soc_data->npins;
1693 gc->irq_need_valid_mask = true;
1695 #ifdef CONFIG_PM_SLEEP
1696 vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
1697 sizeof(*vg->saved_context), GFP_KERNEL);
1699 ret = gpiochip_add_data(gc, vg);
1701 dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
1705 ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev),
1706 0, 0, vg->soc_data->npins);
1708 dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n");
1712 /* set up interrupts */
1713 irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0);
1714 if (irq_rc && irq_rc->start) {
1715 byt_gpio_irq_init_hw(vg);
1716 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
1717 handle_bad_irq, IRQ_TYPE_NONE);
1719 dev_err(&vg->pdev->dev, "failed to add irqchip\n");
1723 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
1724 (unsigned)irq_rc->start,
1725 byt_gpio_irq_handler);
1731 gpiochip_remove(&vg->chip);
1736 static int byt_set_soc_data(struct byt_gpio *vg,
1737 const struct byt_pinctrl_soc_data *soc_data)
1741 vg->soc_data = soc_data;
1742 vg->communities_copy = devm_kcalloc(&vg->pdev->dev,
1743 soc_data->ncommunities,
1744 sizeof(*vg->communities_copy),
1746 if (!vg->communities_copy)
1749 for (i = 0; i < soc_data->ncommunities; i++) {
1750 struct byt_community *comm = vg->communities_copy + i;
1751 struct resource *mem_rc;
1753 *comm = vg->soc_data->communities[i];
1755 mem_rc = platform_get_resource(vg->pdev, IORESOURCE_MEM, 0);
1756 comm->reg_base = devm_ioremap_resource(&vg->pdev->dev, mem_rc);
1757 if (IS_ERR(comm->reg_base))
1758 return PTR_ERR(comm->reg_base);
1764 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1765 { "INT33B2", (kernel_ulong_t)byt_soc_data },
1766 { "INT33FC", (kernel_ulong_t)byt_soc_data },
1769 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
1771 static int byt_pinctrl_probe(struct platform_device *pdev)
1773 const struct byt_pinctrl_soc_data *soc_data = NULL;
1774 const struct byt_pinctrl_soc_data **soc_table;
1775 const struct acpi_device_id *acpi_id;
1776 struct acpi_device *acpi_dev;
1777 struct byt_gpio *vg;
1780 acpi_dev = ACPI_COMPANION(&pdev->dev);
1784 acpi_id = acpi_match_device(byt_gpio_acpi_match, &pdev->dev);
1788 soc_table = (const struct byt_pinctrl_soc_data **)acpi_id->driver_data;
1790 for (i = 0; soc_table[i]; i++) {
1791 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
1792 soc_data = soc_table[i];
1800 vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL);
1805 ret = byt_set_soc_data(vg, soc_data);
1807 dev_err(&pdev->dev, "failed to set soc data\n");
1811 vg->pctl_desc = byt_pinctrl_desc;
1812 vg->pctl_desc.name = dev_name(&pdev->dev);
1813 vg->pctl_desc.pins = vg->soc_data->pins;
1814 vg->pctl_desc.npins = vg->soc_data->npins;
1816 vg->pctl_dev = pinctrl_register(&vg->pctl_desc, &pdev->dev, vg);
1817 if (IS_ERR(vg->pctl_dev)) {
1818 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1819 return PTR_ERR(vg->pctl_dev);
1822 raw_spin_lock_init(&vg->lock);
1824 ret = byt_gpio_probe(vg);
1826 pinctrl_unregister(vg->pctl_dev);
1830 platform_set_drvdata(pdev, vg);
1831 pm_runtime_enable(&pdev->dev);
1836 #ifdef CONFIG_PM_SLEEP
1837 static int byt_gpio_suspend(struct device *dev)
1839 struct platform_device *pdev = to_platform_device(dev);
1840 struct byt_gpio *vg = platform_get_drvdata(pdev);
1843 for (i = 0; i < vg->soc_data->npins; i++) {
1846 unsigned int pin = vg->soc_data->pins[i].number;
1848 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1850 dev_warn(&vg->pdev->dev,
1851 "Pin %i: could not retrieve conf0 register\n",
1855 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1856 vg->saved_context[i].conf0 = value;
1858 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1859 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1860 vg->saved_context[i].val = value;
1866 static int byt_gpio_resume(struct device *dev)
1868 struct platform_device *pdev = to_platform_device(dev);
1869 struct byt_gpio *vg = platform_get_drvdata(pdev);
1872 for (i = 0; i < vg->soc_data->npins; i++) {
1875 unsigned int pin = vg->soc_data->pins[i].number;
1877 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1879 dev_warn(&vg->pdev->dev,
1880 "Pin %i: could not retrieve conf0 register\n",
1885 if ((value & BYT_CONF0_RESTORE_MASK) !=
1886 vg->saved_context[i].conf0) {
1887 value &= ~BYT_CONF0_RESTORE_MASK;
1888 value |= vg->saved_context[i].conf0;
1890 dev_info(dev, "restored pin %d conf0 %#08x", i, value);
1893 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1895 if ((value & BYT_VAL_RESTORE_MASK) !=
1896 vg->saved_context[i].val) {
1899 v = value & ~BYT_VAL_RESTORE_MASK;
1900 v |= vg->saved_context[i].val;
1903 dev_dbg(dev, "restored pin %d val %#08x\n",
1914 static int byt_gpio_runtime_suspend(struct device *dev)
1919 static int byt_gpio_runtime_resume(struct device *dev)
1925 static const struct dev_pm_ops byt_gpio_pm_ops = {
1926 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1927 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
1931 static struct platform_driver byt_gpio_driver = {
1932 .probe = byt_pinctrl_probe,
1935 .pm = &byt_gpio_pm_ops,
1936 .suppress_bind_attrs = true,
1938 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
1942 static int __init byt_gpio_init(void)
1944 return platform_driver_register(&byt_gpio_driver);
1946 subsys_initcall(byt_gpio_init);