drivers/pinctrl/intel/pinctrl-cannonlake.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel Cannon Lake PCH pinctrl/GPIO driver
   4  *
   5  * Copyright (C) 2017, Intel Corporation
   6  * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
   7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   8  */
   9
  10 #include <linux/mod_devicetable.h>
  11 #include <linux/module.h>
  12 #include <linux/platform_device.h>
  13
  14 #include <linux/pinctrl/pinctrl.h>
  15
  16 #include "pinctrl-intel.h"
  17
  18 #define CNL_PAD_OWN             0x020
  19 #define CNL_PADCFGLOCK          0x080
  20 #define CNL_LP_HOSTSW_OWN       0x0b0
  21 #define CNL_H_HOSTSW_OWN        0x0c0
  22 #define CNL_GPI_IS              0x100
  23 #define CNL_GPI_IE              0x120
  24
  25 #define CNL_GPP(r, s, e, g)                             \
  26         {                                               \
  27                 .reg_num = (r),                         \
  28                 .base = (s),                            \
  29                 .size = ((e) - (s) + 1),                \
  30                 .gpio_base = (g),                       \
  31         }
  32
  33 #define CNL_NO_GPIO     -1
  34
  35 #define CNL_COMMUNITY(b, s, e, o, g)                    \
  36         {                                               \
  37                 .barno = (b),                           \
  38                 .padown_offset = CNL_PAD_OWN,           \
  39                 .padcfglock_offset = CNL_PADCFGLOCK,    \
  40                 .hostown_offset = (o),                  \
  41                 .is_offset = CNL_GPI_IS,                \
  42                 .ie_offset = CNL_GPI_IE,                \
  43                 .pin_base = (s),                        \
  44                 .npins = ((e) - (s) + 1),               \
  45                 .gpps = (g),                            \
  46                 .ngpps = ARRAY_SIZE(g),                 \
  47         }
  48
  49 #define CNLLP_COMMUNITY(b, s, e, g)                     \
  50         CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g)
  51
  52 #define CNLH_COMMUNITY(b, s, e, g)                      \
  53         CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g)
  54
  55 /* Cannon Lake-H */
  56 static const struct pinctrl_pin_desc cnlh_pins[] = {
  57         /* GPP_A */
  58         PINCTRL_PIN(0, "RCINB"),
  59         PINCTRL_PIN(1, "LAD_0"),
  60         PINCTRL_PIN(2, "LAD_1"),
  61         PINCTRL_PIN(3, "LAD_2"),
  62         PINCTRL_PIN(4, "LAD_3"),
  63         PINCTRL_PIN(5, "LFRAMEB"),
  64         PINCTRL_PIN(6, "SERIRQ"),
  65         PINCTRL_PIN(7, "PIRQAB"),
  66         PINCTRL_PIN(8, "CLKRUNB"),
  67         PINCTRL_PIN(9, "CLKOUT_LPC_0"),
  68         PINCTRL_PIN(10, "CLKOUT_LPC_1"),
  69         PINCTRL_PIN(11, "PMEB"),
  70         PINCTRL_PIN(12, "BM_BUSYB"),
  71         PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
  72         PINCTRL_PIN(14, "SUS_STATB"),
  73         PINCTRL_PIN(15, "SUSACKB"),
  74         PINCTRL_PIN(16, "CLKOUT_48"),
  75         PINCTRL_PIN(17, "SD_VDD1_PWR_EN_B"),
  76         PINCTRL_PIN(18, "ISH_GP_0"),
  77         PINCTRL_PIN(19, "ISH_GP_1"),
  78         PINCTRL_PIN(20, "ISH_GP_2"),
  79         PINCTRL_PIN(21, "ISH_GP_3"),
  80         PINCTRL_PIN(22, "ISH_GP_4"),
  81         PINCTRL_PIN(23, "ISH_GP_5"),
  82         PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
  83         /* GPP_B */
  84         PINCTRL_PIN(25, "GSPI0_CS1B"),
  85         PINCTRL_PIN(26, "GSPI1_CS1B"),
  86         PINCTRL_PIN(27, "VRALERTB"),
  87         PINCTRL_PIN(28, "CPU_GP_2"),
  88         PINCTRL_PIN(29, "CPU_GP_3"),
  89         PINCTRL_PIN(30, "SRCCLKREQB_0"),
  90         PINCTRL_PIN(31, "SRCCLKREQB_1"),
  91         PINCTRL_PIN(32, "SRCCLKREQB_2"),
  92         PINCTRL_PIN(33, "SRCCLKREQB_3"),
  93         PINCTRL_PIN(34, "SRCCLKREQB_4"),
  94         PINCTRL_PIN(35, "SRCCLKREQB_5"),
  95         PINCTRL_PIN(36, "SSP_MCLK"),
  96         PINCTRL_PIN(37, "SLP_S0B"),
  97         PINCTRL_PIN(38, "PLTRSTB"),
  98         PINCTRL_PIN(39, "SPKR"),
  99         PINCTRL_PIN(40, "GSPI0_CS0B"),
 100         PINCTRL_PIN(41, "GSPI0_CLK"),
 101         PINCTRL_PIN(42, "GSPI0_MISO"),
 102         PINCTRL_PIN(43, "GSPI0_MOSI"),
 103         PINCTRL_PIN(44, "GSPI1_CS0B"),
 104         PINCTRL_PIN(45, "GSPI1_CLK"),
 105         PINCTRL_PIN(46, "GSPI1_MISO"),
 106         PINCTRL_PIN(47, "GSPI1_MOSI"),
 107         PINCTRL_PIN(48, "SML1ALERTB"),
 108         PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"),
 109         PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"),
 110         /* GPP_C */
 111         PINCTRL_PIN(51, "SMBCLK"),
 112         PINCTRL_PIN(52, "SMBDATA"),
 113         PINCTRL_PIN(53, "SMBALERTB"),
 114         PINCTRL_PIN(54, "SML0CLK"),
 115         PINCTRL_PIN(55, "SML0DATA"),
 116         PINCTRL_PIN(56, "SML0ALERTB"),
 117         PINCTRL_PIN(57, "SML1CLK"),
 118         PINCTRL_PIN(58, "SML1DATA"),
 119         PINCTRL_PIN(59, "UART0_RXD"),
 120         PINCTRL_PIN(60, "UART0_TXD"),
 121         PINCTRL_PIN(61, "UART0_RTSB"),
 122         PINCTRL_PIN(62, "UART0_CTSB"),
 123         PINCTRL_PIN(63, "UART1_RXD"),
 124         PINCTRL_PIN(64, "UART1_TXD"),
 125         PINCTRL_PIN(65, "UART1_RTSB"),
 126         PINCTRL_PIN(66, "UART1_CTSB"),
 127         PINCTRL_PIN(67, "I2C0_SDA"),
 128         PINCTRL_PIN(68, "I2C0_SCL"),
 129         PINCTRL_PIN(69, "I2C1_SDA"),
 130         PINCTRL_PIN(70, "I2C1_SCL"),
 131         PINCTRL_PIN(71, "UART2_RXD"),
 132         PINCTRL_PIN(72, "UART2_TXD"),
 133         PINCTRL_PIN(73, "UART2_RTSB"),
 134         PINCTRL_PIN(74, "UART2_CTSB"),
 135         /* GPP_D */
 136         PINCTRL_PIN(75, "SPI1_CSB"),
 137         PINCTRL_PIN(76, "SPI1_CLK"),
 138         PINCTRL_PIN(77, "SPI1_MISO_IO_1"),
 139         PINCTRL_PIN(78, "SPI1_MOSI_IO_0"),
 140         PINCTRL_PIN(79, "ISH_I2C2_SDA"),
 141         PINCTRL_PIN(80, "SSP2_SFRM"),
 142         PINCTRL_PIN(81, "SSP2_TXD"),
 143         PINCTRL_PIN(82, "SSP2_RXD"),
 144         PINCTRL_PIN(83, "SSP2_SCLK"),
 145         PINCTRL_PIN(84, "ISH_SPI_CSB"),
 146         PINCTRL_PIN(85, "ISH_SPI_CLK"),
 147         PINCTRL_PIN(86, "ISH_SPI_MISO"),
 148         PINCTRL_PIN(87, "ISH_SPI_MOSI"),
 149         PINCTRL_PIN(88, "ISH_UART0_RXD"),
 150         PINCTRL_PIN(89, "ISH_UART0_TXD"),
 151         PINCTRL_PIN(90, "ISH_UART0_RTSB"),
 152         PINCTRL_PIN(91, "ISH_UART0_CTSB"),
 153         PINCTRL_PIN(92, "DMIC_CLK_1"),
 154         PINCTRL_PIN(93, "DMIC_DATA_1"),
 155         PINCTRL_PIN(94, "DMIC_CLK_0"),
 156         PINCTRL_PIN(95, "DMIC_DATA_0"),
 157         PINCTRL_PIN(96, "SPI1_IO_2"),
 158         PINCTRL_PIN(97, "SPI1_IO_3"),
 159         PINCTRL_PIN(98, "ISH_I2C2_SCL"),
 160         /* GPP_G */
 161         PINCTRL_PIN(99, "SD3_CMD"),
 162         PINCTRL_PIN(100, "SD3_D0"),
 163         PINCTRL_PIN(101, "SD3_D1"),
 164         PINCTRL_PIN(102, "SD3_D2"),
 165         PINCTRL_PIN(103, "SD3_D3"),
 166         PINCTRL_PIN(104, "SD3_CDB"),
 167         PINCTRL_PIN(105, "SD3_CLK"),
 168         PINCTRL_PIN(106, "SD3_WP"),
 169         /* AZA */
 170         PINCTRL_PIN(107, "HDA_BCLK"),
 171         PINCTRL_PIN(108, "HDA_RSTB"),
 172         PINCTRL_PIN(109, "HDA_SYNC"),
 173         PINCTRL_PIN(110, "HDA_SDO"),
 174         PINCTRL_PIN(111, "HDA_SDI_0"),
 175         PINCTRL_PIN(112, "HDA_SDI_1"),
 176         PINCTRL_PIN(113, "SSP1_SFRM"),
 177         PINCTRL_PIN(114, "SSP1_TXD"),
 178         /* vGPIO */
 179         PINCTRL_PIN(115, "CNV_BTEN"),
 180         PINCTRL_PIN(116, "CNV_GNEN"),
 181         PINCTRL_PIN(117, "CNV_WFEN"),
 182         PINCTRL_PIN(118, "CNV_WCEN"),
 183         PINCTRL_PIN(119, "CNV_BT_HOST_WAKEB"),
 184         PINCTRL_PIN(120, "vCNV_GNSS_HOST_WAKEB"),
 185         PINCTRL_PIN(121, "vSD3_CD_B"),
 186         PINCTRL_PIN(122, "CNV_BT_IF_SELECT"),
 187         PINCTRL_PIN(123, "vCNV_BT_UART_TXD"),
 188         PINCTRL_PIN(124, "vCNV_BT_UART_RXD"),
 189         PINCTRL_PIN(125, "vCNV_BT_UART_CTS_B"),
 190         PINCTRL_PIN(126, "vCNV_BT_UART_RTS_B"),
 191         PINCTRL_PIN(127, "vCNV_MFUART1_TXD"),
 192         PINCTRL_PIN(128, "vCNV_MFUART1_RXD"),
 193         PINCTRL_PIN(129, "vCNV_MFUART1_CTS_B"),
 194         PINCTRL_PIN(130, "vCNV_MFUART1_RTS_B"),
 195         PINCTRL_PIN(131, "vCNV_GNSS_UART_TXD"),
 196         PINCTRL_PIN(132, "vCNV_GNSS_UART_RXD"),
 197         PINCTRL_PIN(133, "vCNV_GNSS_UART_CTS_B"),
 198         PINCTRL_PIN(134, "vCNV_GNSS_UART_RTS_B"),
 199         PINCTRL_PIN(135, "vUART0_TXD"),
 200         PINCTRL_PIN(136, "vUART0_RXD"),
 201         PINCTRL_PIN(137, "vUART0_CTS_B"),
 202         PINCTRL_PIN(138, "vUART0_RTSB"),
 203         PINCTRL_PIN(139, "vISH_UART0_TXD"),
 204         PINCTRL_PIN(140, "vISH_UART0_RXD"),
 205         PINCTRL_PIN(141, "vISH_UART0_CTS_B"),
 206         PINCTRL_PIN(142, "vISH_UART0_RTSB"),
 207         PINCTRL_PIN(143, "vISH_UART1_TXD"),
 208         PINCTRL_PIN(144, "vISH_UART1_RXD"),
 209         PINCTRL_PIN(145, "vISH_UART1_CTS_B"),
 210         PINCTRL_PIN(146, "vISH_UART1_RTS_B"),
 211         PINCTRL_PIN(147, "vCNV_BT_I2S_BCLK"),
 212         PINCTRL_PIN(148, "vCNV_BT_I2S_WS_SYNC"),
 213         PINCTRL_PIN(149, "vCNV_BT_I2S_SDO"),
 214         PINCTRL_PIN(150, "vCNV_BT_I2S_SDI"),
 215         PINCTRL_PIN(151, "vSSP2_SCLK"),
 216         PINCTRL_PIN(152, "vSSP2_SFRM"),
 217         PINCTRL_PIN(153, "vSSP2_TXD"),
 218         PINCTRL_PIN(154, "vSSP2_RXD"),
 219         /* GPP_K */
 220         PINCTRL_PIN(155, "FAN_TACH_0"),
 221         PINCTRL_PIN(156, "FAN_TACH_1"),
 222         PINCTRL_PIN(157, "FAN_TACH_2"),
 223         PINCTRL_PIN(158, "FAN_TACH_3"),
 224         PINCTRL_PIN(159, "FAN_TACH_4"),
 225         PINCTRL_PIN(160, "FAN_TACH_5"),
 226         PINCTRL_PIN(161, "FAN_TACH_6"),
 227         PINCTRL_PIN(162, "FAN_TACH_7"),
 228         PINCTRL_PIN(163, "FAN_PWM_0"),
 229         PINCTRL_PIN(164, "FAN_PWM_1"),
 230         PINCTRL_PIN(165, "FAN_PWM_2"),
 231         PINCTRL_PIN(166, "FAN_PWM_3"),
 232         PINCTRL_PIN(167, "GSXDOUT"),
 233         PINCTRL_PIN(168, "GSXSLOAD"),
 234         PINCTRL_PIN(169, "GSXDIN"),
 235         PINCTRL_PIN(170, "GSXSRESETB"),
 236         PINCTRL_PIN(171, "GSXCLK"),
 237         PINCTRL_PIN(172, "ADR_COMPLETE"),
 238         PINCTRL_PIN(173, "NMIB"),
 239         PINCTRL_PIN(174, "SMIB"),
 240         PINCTRL_PIN(175, "CORE_VID_0"),
 241         PINCTRL_PIN(176, "CORE_VID_1"),
 242         PINCTRL_PIN(177, "IMGCLKOUT_0"),
 243         PINCTRL_PIN(178, "IMGCLKOUT_1"),
 244         /* GPP_H */
 245         PINCTRL_PIN(179, "SRCCLKREQB_6"),
 246         PINCTRL_PIN(180, "SRCCLKREQB_7"),
 247         PINCTRL_PIN(181, "SRCCLKREQB_8"),
 248         PINCTRL_PIN(182, "SRCCLKREQB_9"),
 249         PINCTRL_PIN(183, "SRCCLKREQB_10"),
 250         PINCTRL_PIN(184, "SRCCLKREQB_11"),
 251         PINCTRL_PIN(185, "SRCCLKREQB_12"),
 252         PINCTRL_PIN(186, "SRCCLKREQB_13"),
 253         PINCTRL_PIN(187, "SRCCLKREQB_14"),
 254         PINCTRL_PIN(188, "SRCCLKREQB_15"),
 255         PINCTRL_PIN(189, "SML2CLK"),
 256         PINCTRL_PIN(190, "SML2DATA"),
 257         PINCTRL_PIN(191, "SML2ALERTB"),
 258         PINCTRL_PIN(192, "SML3CLK"),
 259         PINCTRL_PIN(193, "SML3DATA"),
 260         PINCTRL_PIN(194, "SML3ALERTB"),
 261         PINCTRL_PIN(195, "SML4CLK"),
 262         PINCTRL_PIN(196, "SML4DATA"),
 263         PINCTRL_PIN(197, "SML4ALERTB"),
 264         PINCTRL_PIN(198, "ISH_I2C0_SDA"),
 265         PINCTRL_PIN(199, "ISH_I2C0_SCL"),
 266         PINCTRL_PIN(200, "ISH_I2C1_SDA"),
 267         PINCTRL_PIN(201, "ISH_I2C1_SCL"),
 268         PINCTRL_PIN(202, "TIME_SYNC_0"),
 269         /* GPP_E */
 270         PINCTRL_PIN(203, "SATAXPCIE_0"),
 271         PINCTRL_PIN(204, "SATAXPCIE_1"),
 272         PINCTRL_PIN(205, "SATAXPCIE_2"),
 273         PINCTRL_PIN(206, "CPU_GP_0"),
 274         PINCTRL_PIN(207, "SATA_DEVSLP_0"),
 275         PINCTRL_PIN(208, "SATA_DEVSLP_1"),
 276         PINCTRL_PIN(209, "SATA_DEVSLP_2"),
 277         PINCTRL_PIN(210, "CPU_GP_1"),
 278         PINCTRL_PIN(211, "SATA_LEDB"),
 279         PINCTRL_PIN(212, "USB2_OCB_0"),
 280         PINCTRL_PIN(213, "USB2_OCB_1"),
 281         PINCTRL_PIN(214, "USB2_OCB_2"),
 282         PINCTRL_PIN(215, "USB2_OCB_3"),
 283         /* GPP_F */
 284         PINCTRL_PIN(216, "SATAXPCIE_3"),
 285         PINCTRL_PIN(217, "SATAXPCIE_4"),
 286         PINCTRL_PIN(218, "SATAXPCIE_5"),
 287         PINCTRL_PIN(219, "SATAXPCIE_6"),
 288         PINCTRL_PIN(220, "SATAXPCIE_7"),
 289         PINCTRL_PIN(221, "SATA_DEVSLP_3"),
 290         PINCTRL_PIN(222, "SATA_DEVSLP_4"),
 291         PINCTRL_PIN(223, "SATA_DEVSLP_5"),
 292         PINCTRL_PIN(224, "SATA_DEVSLP_6"),
 293         PINCTRL_PIN(225, "SATA_DEVSLP_7"),
 294         PINCTRL_PIN(226, "SATA_SCLOCK"),
 295         PINCTRL_PIN(227, "SATA_SLOAD"),
 296         PINCTRL_PIN(228, "SATA_SDATAOUT1"),
 297         PINCTRL_PIN(229, "SATA_SDATAOUT0"),
 298         PINCTRL_PIN(230, "EXT_PWR_GATEB"),
 299         PINCTRL_PIN(231, "USB2_OCB_4"),
 300         PINCTRL_PIN(232, "USB2_OCB_5"),
 301         PINCTRL_PIN(233, "USB2_OCB_6"),
 302         PINCTRL_PIN(234, "USB2_OCB_7"),
 303         PINCTRL_PIN(235, "L_VDDEN"),
 304         PINCTRL_PIN(236, "L_BKLTEN"),
 305         PINCTRL_PIN(237, "L_BKLTCTL"),
 306         PINCTRL_PIN(238, "DDPF_CTRLCLK"),
 307         PINCTRL_PIN(239, "DDPF_CTRLDATA"),
 308         /* SPI */
 309         PINCTRL_PIN(240, "SPI0_IO_2"),
 310         PINCTRL_PIN(241, "SPI0_IO_3"),
 311         PINCTRL_PIN(242, "SPI0_MOSI_IO_0"),
 312         PINCTRL_PIN(243, "SPI0_MISO_IO_1"),
 313         PINCTRL_PIN(244, "SPI0_TPM_CSB"),
 314         PINCTRL_PIN(245, "SPI0_FLASH_0_CSB"),
 315         PINCTRL_PIN(246, "SPI0_FLASH_1_CSB"),
 316         PINCTRL_PIN(247, "SPI0_CLK"),
 317         PINCTRL_PIN(248, "SPI0_CLK_LOOPBK"),
 318         /* CPU */
 319         PINCTRL_PIN(249, "HDACPU_SDI"),
 320         PINCTRL_PIN(250, "HDACPU_SDO"),
 321         PINCTRL_PIN(251, "HDACPU_SCLK"),
 322         PINCTRL_PIN(252, "PM_SYNC"),
 323         PINCTRL_PIN(253, "PECI"),
 324         PINCTRL_PIN(254, "CPUPWRGD"),
 325         PINCTRL_PIN(255, "THRMTRIPB"),
 326         PINCTRL_PIN(256, "PLTRST_CPUB"),
 327         PINCTRL_PIN(257, "PM_DOWN"),
 328         PINCTRL_PIN(258, "TRIGGER_IN"),
 329         PINCTRL_PIN(259, "TRIGGER_OUT"),
 330         /* JTAG */
 331         PINCTRL_PIN(260, "JTAG_TDO"),
 332         PINCTRL_PIN(261, "JTAGX"),
 333         PINCTRL_PIN(262, "PRDYB"),
 334         PINCTRL_PIN(263, "PREQB"),
 335         PINCTRL_PIN(264, "CPU_TRSTB"),
 336         PINCTRL_PIN(265, "JTAG_TDI"),
 337         PINCTRL_PIN(266, "JTAG_TMS"),
 338         PINCTRL_PIN(267, "JTAG_TCK"),
 339         PINCTRL_PIN(268, "ITP_PMODE"),
 340         /* GPP_I */
 341         PINCTRL_PIN(269, "DDSP_HPD_0"),
 342         PINCTRL_PIN(270, "DDSP_HPD_1"),
 343         PINCTRL_PIN(271, "DDSP_HPD_2"),
 344         PINCTRL_PIN(272, "DDSP_HPD_3"),
 345         PINCTRL_PIN(273, "EDP_HPD"),
 346         PINCTRL_PIN(274, "DDPB_CTRLCLK"),
 347         PINCTRL_PIN(275, "DDPB_CTRLDATA"),
 348         PINCTRL_PIN(276, "DDPC_CTRLCLK"),
 349         PINCTRL_PIN(277, "DDPC_CTRLDATA"),
 350         PINCTRL_PIN(278, "DDPD_CTRLCLK"),
 351         PINCTRL_PIN(279, "DDPD_CTRLDATA"),
 352         PINCTRL_PIN(280, "M2_SKT2_CFG_0"),
 353         PINCTRL_PIN(281, "M2_SKT2_CFG_1"),
 354         PINCTRL_PIN(282, "M2_SKT2_CFG_2"),
 355         PINCTRL_PIN(283, "M2_SKT2_CFG_3"),
 356         PINCTRL_PIN(284, "SYS_PWROK"),
 357         PINCTRL_PIN(285, "SYS_RESETB"),
 358         PINCTRL_PIN(286, "MLK_RSTB"),
 359         /* GPP_J */
 360         PINCTRL_PIN(287, "CNV_PA_BLANKING"),
 361         PINCTRL_PIN(288, "CNV_GNSS_FTA"),
 362         PINCTRL_PIN(289, "CNV_GNSS_SYSCK"),
 363         PINCTRL_PIN(290, "CNV_RF_RESET_B"),
 364         PINCTRL_PIN(291, "CNV_BRI_DT"),
 365         PINCTRL_PIN(292, "CNV_BRI_RSP"),
 366         PINCTRL_PIN(293, "CNV_RGI_DT"),
 367         PINCTRL_PIN(294, "CNV_RGI_RSP"),
 368         PINCTRL_PIN(295, "CNV_MFUART2_RXD"),
 369         PINCTRL_PIN(296, "CNV_MFUART2_TXD"),
 370         PINCTRL_PIN(297, "CNV_MODEM_CLKREQ"),
 371         PINCTRL_PIN(298, "A4WP_PRESENT"),
 372 };
 373
 374 static const struct intel_padgroup cnlh_community0_gpps[] = {
 375         CNL_GPP(0, 0, 24, 0),                   /* GPP_A */
 376         CNL_GPP(1, 25, 50, 32),                 /* GPP_B */
 377 };
 378
 379 static const struct intel_padgroup cnlh_community1_gpps[] = {
 380         CNL_GPP(0, 51, 74, 64),                 /* GPP_C */
 381         CNL_GPP(1, 75, 98, 96),                 /* GPP_D */
 382         CNL_GPP(2, 99, 106, 128),               /* GPP_G */
 383         CNL_GPP(3, 107, 114, CNL_NO_GPIO),      /* AZA */
 384         CNL_GPP(4, 115, 146, 160),              /* vGPIO_0 */
 385         CNL_GPP(5, 147, 154, CNL_NO_GPIO),      /* vGPIO_1 */
 386 };
 387
 388 static const struct intel_padgroup cnlh_community3_gpps[] = {
 389         CNL_GPP(0, 155, 178, 192),              /* GPP_K */
 390         CNL_GPP(1, 179, 202, 224),              /* GPP_H */
 391         CNL_GPP(2, 203, 215, 256),              /* GPP_E */
 392         CNL_GPP(3, 216, 239, 288),              /* GPP_F */
 393         CNL_GPP(4, 240, 248, CNL_NO_GPIO),      /* SPI */
 394 };
 395
 396 static const struct intel_padgroup cnlh_community4_gpps[] = {
 397         CNL_GPP(0, 249, 259, CNL_NO_GPIO),      /* CPU */
 398         CNL_GPP(1, 260, 268, CNL_NO_GPIO),      /* JTAG */
 399         CNL_GPP(2, 269, 286, 320),              /* GPP_I */
 400         CNL_GPP(3, 287, 298, 352),              /* GPP_J */
 401 };
 402
 403 static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
 404 static const unsigned int cnlh_spi1_pins[] = { 44, 45, 46, 47 };
 405 static const unsigned int cnlh_spi2_pins[] = { 84, 85, 86, 87 };
 406
 407 static const unsigned int cnlh_uart0_pins[] = { 59, 60, 61, 62 };
 408 static const unsigned int cnlh_uart1_pins[] = { 63, 64, 65, 66 };
 409 static const unsigned int cnlh_uart2_pins[] = { 71, 72, 73, 74 };
 410
 411 static const unsigned int cnlh_i2c0_pins[] = { 67, 68 };
 412 static const unsigned int cnlh_i2c1_pins[] = { 69, 70 };
 413 static const unsigned int cnlh_i2c2_pins[] = { 88, 89 };
 414 static const unsigned int cnlh_i2c3_pins[] = { 79, 98 };
 415
 416 static const struct intel_pingroup cnlh_groups[] = {
 417         PIN_GROUP("spi0_grp", cnlh_spi0_pins, 1),
 418         PIN_GROUP("spi1_grp", cnlh_spi1_pins, 1),
 419         PIN_GROUP("spi2_grp", cnlh_spi2_pins, 3),
 420         PIN_GROUP("uart0_grp", cnlh_uart0_pins, 1),
 421         PIN_GROUP("uart1_grp", cnlh_uart1_pins, 1),
 422         PIN_GROUP("uart2_grp", cnlh_uart2_pins, 1),
 423         PIN_GROUP("i2c0_grp", cnlh_i2c0_pins, 1),
 424         PIN_GROUP("i2c1_grp", cnlh_i2c1_pins, 1),
 425         PIN_GROUP("i2c2_grp", cnlh_i2c2_pins, 3),
 426         PIN_GROUP("i2c3_grp", cnlh_i2c3_pins, 2),
 427 };
 428
 429 static const char * const cnlh_spi0_groups[] = { "spi0_grp" };
 430 static const char * const cnlh_spi1_groups[] = { "spi1_grp" };
 431 static const char * const cnlh_spi2_groups[] = { "spi2_grp" };
 432 static const char * const cnlh_uart0_groups[] = { "uart0_grp" };
 433 static const char * const cnlh_uart1_groups[] = { "uart1_grp" };
 434 static const char * const cnlh_uart2_groups[] = { "uart2_grp" };
 435 static const char * const cnlh_i2c0_groups[] = { "i2c0_grp" };
 436 static const char * const cnlh_i2c1_groups[] = { "i2c1_grp" };
 437 static const char * const cnlh_i2c2_groups[] = { "i2c2_grp" };
 438 static const char * const cnlh_i2c3_groups[] = { "i2c3_grp" };
 439
 440 static const struct intel_function cnlh_functions[] = {
 441         FUNCTION("spi0", cnlh_spi0_groups),
 442         FUNCTION("spi1", cnlh_spi1_groups),
 443         FUNCTION("spi2", cnlh_spi2_groups),
 444         FUNCTION("uart0", cnlh_uart0_groups),
 445         FUNCTION("uart1", cnlh_uart1_groups),
 446         FUNCTION("uart2", cnlh_uart2_groups),
 447         FUNCTION("i2c0", cnlh_i2c0_groups),
 448         FUNCTION("i2c1", cnlh_i2c1_groups),
 449         FUNCTION("i2c2", cnlh_i2c2_groups),
 450         FUNCTION("i2c3", cnlh_i2c3_groups),
 451 };
 452
 453 static const struct intel_community cnlh_communities[] = {
 454         CNLH_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
 455         CNLH_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
 456         CNLH_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
 457         CNLH_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
 458 };
 459
 460 static const struct intel_pinctrl_soc_data cnlh_soc_data = {
 461         .pins = cnlh_pins,
 462         .npins = ARRAY_SIZE(cnlh_pins),
 463         .groups = cnlh_groups,
 464         .ngroups = ARRAY_SIZE(cnlh_groups),
 465         .functions = cnlh_functions,
 466         .nfunctions = ARRAY_SIZE(cnlh_functions),
 467         .communities = cnlh_communities,
 468         .ncommunities = ARRAY_SIZE(cnlh_communities),
 469 };
 470
 471 /* Cannon Lake-LP */
 472 static const struct pinctrl_pin_desc cnllp_pins[] = {
 473         /* GPP_A */
 474         PINCTRL_PIN(0, "RCINB"),
 475         PINCTRL_PIN(1, "LAD_0"),
 476         PINCTRL_PIN(2, "LAD_1"),
 477         PINCTRL_PIN(3, "LAD_2"),
 478         PINCTRL_PIN(4, "LAD_3"),
 479         PINCTRL_PIN(5, "LFRAMEB"),
 480         PINCTRL_PIN(6, "SERIRQ"),
 481         PINCTRL_PIN(7, "PIRQAB"),
 482         PINCTRL_PIN(8, "CLKRUNB"),
 483         PINCTRL_PIN(9, "CLKOUT_LPC_0"),
 484         PINCTRL_PIN(10, "CLKOUT_LPC_1"),
 485         PINCTRL_PIN(11, "PMEB"),
 486         PINCTRL_PIN(12, "BM_BUSYB"),
 487         PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
 488         PINCTRL_PIN(14, "SUS_STATB"),
 489         PINCTRL_PIN(15, "SUSACKB"),
 490         PINCTRL_PIN(16, "SD_1P8_SEL"),
 491         PINCTRL_PIN(17, "SD_PWR_EN_B"),
 492         PINCTRL_PIN(18, "ISH_GP_0"),
 493         PINCTRL_PIN(19, "ISH_GP_1"),
 494         PINCTRL_PIN(20, "ISH_GP_2"),
 495         PINCTRL_PIN(21, "ISH_GP_3"),
 496         PINCTRL_PIN(22, "ISH_GP_4"),
 497         PINCTRL_PIN(23, "ISH_GP_5"),
 498         PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
 499         /* GPP_B */
 500         PINCTRL_PIN(25, "CORE_VID_0"),
 501         PINCTRL_PIN(26, "CORE_VID_1"),
 502         PINCTRL_PIN(27, "VRALERTB"),
 503         PINCTRL_PIN(28, "CPU_GP_2"),
 504         PINCTRL_PIN(29, "CPU_GP_3"),
 505         PINCTRL_PIN(30, "SRCCLKREQB_0"),
 506         PINCTRL_PIN(31, "SRCCLKREQB_1"),
 507         PINCTRL_PIN(32, "SRCCLKREQB_2"),
 508         PINCTRL_PIN(33, "SRCCLKREQB_3"),
 509         PINCTRL_PIN(34, "SRCCLKREQB_4"),
 510         PINCTRL_PIN(35, "SRCCLKREQB_5"),
 511         PINCTRL_PIN(36, "EXT_PWR_GATEB"),
 512         PINCTRL_PIN(37, "SLP_S0B"),
 513         PINCTRL_PIN(38, "PLTRSTB"),
 514         PINCTRL_PIN(39, "SPKR"),
 515         PINCTRL_PIN(40, "GSPI0_CS0B"),
 516         PINCTRL_PIN(41, "GSPI0_CLK"),
 517         PINCTRL_PIN(42, "GSPI0_MISO"),
 518         PINCTRL_PIN(43, "GSPI0_MOSI"),
 519         PINCTRL_PIN(44, "GSPI1_CS0B"),
 520         PINCTRL_PIN(45, "GSPI1_CLK"),
 521         PINCTRL_PIN(46, "GSPI1_MISO"),
 522         PINCTRL_PIN(47, "GSPI1_MOSI"),
 523         PINCTRL_PIN(48, "SML1ALERTB"),
 524         PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"),
 525         PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"),
 526         /* GPP_G */
 527         PINCTRL_PIN(51, "SD3_CMD"),
 528         PINCTRL_PIN(52, "SD3_D0_SD4_RCLK_P"),
 529         PINCTRL_PIN(53, "SD3_D1_SD4_RCLK_N"),
 530         PINCTRL_PIN(54, "SD3_D2"),
 531         PINCTRL_PIN(55, "SD3_D3"),
 532         PINCTRL_PIN(56, "SD3_CDB"),
 533         PINCTRL_PIN(57, "SD3_CLK"),
 534         PINCTRL_PIN(58, "SD3_WP"),
 535         /* SPI */
 536         PINCTRL_PIN(59, "SPI0_IO_2"),
 537         PINCTRL_PIN(60, "SPI0_IO_3"),
 538         PINCTRL_PIN(61, "SPI0_MOSI_IO_0"),
 539         PINCTRL_PIN(62, "SPI0_MISO_IO_1"),
 540         PINCTRL_PIN(63, "SPI0_TPM_CSB"),
 541         PINCTRL_PIN(64, "SPI0_FLASH_0_CSB"),
 542         PINCTRL_PIN(65, "SPI0_FLASH_1_CSB"),
 543         PINCTRL_PIN(66, "SPI0_CLK"),
 544         PINCTRL_PIN(67, "SPI0_CLK_LOOPBK"),
 545         /* GPP_D */
 546         PINCTRL_PIN(68, "SPI1_CSB"),
 547         PINCTRL_PIN(69, "SPI1_CLK"),
 548         PINCTRL_PIN(70, "SPI1_MISO_IO_1"),
 549         PINCTRL_PIN(71, "SPI1_MOSI_IO_0"),
 550         PINCTRL_PIN(72, "IMGCLKOUT_0"),
 551         PINCTRL_PIN(73, "ISH_I2C0_SDA"),
 552         PINCTRL_PIN(74, "ISH_I2C0_SCL"),
 553         PINCTRL_PIN(75, "ISH_I2C1_SDA"),
 554         PINCTRL_PIN(76, "ISH_I2C1_SCL"),
 555         PINCTRL_PIN(77, "ISH_SPI_CSB"),
 556         PINCTRL_PIN(78, "ISH_SPI_CLK"),
 557         PINCTRL_PIN(79, "ISH_SPI_MISO"),
 558         PINCTRL_PIN(80, "ISH_SPI_MOSI"),
 559         PINCTRL_PIN(81, "ISH_UART0_RXD"),
 560         PINCTRL_PIN(82, "ISH_UART0_TXD"),
 561         PINCTRL_PIN(83, "ISH_UART0_RTSB"),
 562         PINCTRL_PIN(84, "ISH_UART0_CTSB"),
 563         PINCTRL_PIN(85, "DMIC_CLK_1"),
 564         PINCTRL_PIN(86, "DMIC_DATA_1"),
 565         PINCTRL_PIN(87, "DMIC_CLK_0"),
 566         PINCTRL_PIN(88, "DMIC_DATA_0"),
 567         PINCTRL_PIN(89, "SPI1_IO_2"),
 568         PINCTRL_PIN(90, "SPI1_IO_3"),
 569         PINCTRL_PIN(91, "SSP_MCLK"),
 570         PINCTRL_PIN(92, "GSPI2_CLK_LOOPBK"),
 571         /* GPP_F */
 572         PINCTRL_PIN(93, "CNV_GNSS_PA_BLANKING"),
 573         PINCTRL_PIN(94, "CNV_GNSS_FTA"),
 574         PINCTRL_PIN(95, "CNV_GNSS_SYSCK"),
 575         PINCTRL_PIN(96, "EMMC_HIP_MON"),
 576         PINCTRL_PIN(97, "CNV_BRI_DT"),
 577         PINCTRL_PIN(98, "CNV_BRI_RSP"),
 578         PINCTRL_PIN(99, "CNV_RGI_DT"),
 579         PINCTRL_PIN(100, "CNV_RGI_RSP"),
 580         PINCTRL_PIN(101, "CNV_MFUART2_RXD"),
 581         PINCTRL_PIN(102, "CNV_MFUART2_TXD"),
 582         PINCTRL_PIN(103, "GPP_F_10"),
 583         PINCTRL_PIN(104, "EMMC_CMD"),
 584         PINCTRL_PIN(105, "EMMC_DATA_0"),
 585         PINCTRL_PIN(106, "EMMC_DATA_1"),
 586         PINCTRL_PIN(107, "EMMC_DATA_2"),
 587         PINCTRL_PIN(108, "EMMC_DATA_3"),
 588         PINCTRL_PIN(109, "EMMC_DATA_4"),
 589         PINCTRL_PIN(110, "EMMC_DATA_5"),
 590         PINCTRL_PIN(111, "EMMC_DATA_6"),
 591         PINCTRL_PIN(112, "EMMC_DATA_7"),
 592         PINCTRL_PIN(113, "EMMC_RCLK"),
 593         PINCTRL_PIN(114, "EMMC_CLK"),
 594         PINCTRL_PIN(115, "EMMC_RESETB"),
 595         PINCTRL_PIN(116, "A4WP_PRESENT"),
 596         /* GPP_H */
 597         PINCTRL_PIN(117, "SSP2_SCLK"),
 598         PINCTRL_PIN(118, "SSP2_SFRM"),
 599         PINCTRL_PIN(119, "SSP2_TXD"),
 600         PINCTRL_PIN(120, "SSP2_RXD"),
 601         PINCTRL_PIN(121, "I2C2_SDA"),
 602         PINCTRL_PIN(122, "I2C2_SCL"),
 603         PINCTRL_PIN(123, "I2C3_SDA"),
 604         PINCTRL_PIN(124, "I2C3_SCL"),
 605         PINCTRL_PIN(125, "I2C4_SDA"),
 606         PINCTRL_PIN(126, "I2C4_SCL"),
 607         PINCTRL_PIN(127, "I2C5_SDA"),
 608         PINCTRL_PIN(128, "I2C5_SCL"),
 609         PINCTRL_PIN(129, "M2_SKT2_CFG_0"),
 610         PINCTRL_PIN(130, "M2_SKT2_CFG_1"),
 611         PINCTRL_PIN(131, "M2_SKT2_CFG_2"),
 612         PINCTRL_PIN(132, "M2_SKT2_CFG_3"),
 613         PINCTRL_PIN(133, "DDPF_CTRLCLK"),
 614         PINCTRL_PIN(134, "DDPF_CTRLDATA"),
 615         PINCTRL_PIN(135, "CPU_VCCIO_PWR_GATEB"),
 616         PINCTRL_PIN(136, "TIMESYNC_0"),
 617         PINCTRL_PIN(137, "IMGCLKOUT_1"),
 618         PINCTRL_PIN(138, "GPPC_H_21"),
 619         PINCTRL_PIN(139, "GPPC_H_22"),
 620         PINCTRL_PIN(140, "GPPC_H_23"),
 621         /* vGPIO */
 622         PINCTRL_PIN(141, "CNV_BTEN"),
 623         PINCTRL_PIN(142, "CNV_GNEN"),
 624         PINCTRL_PIN(143, "CNV_WFEN"),
 625         PINCTRL_PIN(144, "CNV_WCEN"),
 626         PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"),
 627         PINCTRL_PIN(146, "CNV_BT_IF_SELECT"),
 628         PINCTRL_PIN(147, "vCNV_BT_UART_TXD"),
 629         PINCTRL_PIN(148, "vCNV_BT_UART_RXD"),
 630         PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"),
 631         PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"),
 632         PINCTRL_PIN(151, "vCNV_MFUART1_TXD"),
 633         PINCTRL_PIN(152, "vCNV_MFUART1_RXD"),
 634         PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"),
 635         PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"),
 636         PINCTRL_PIN(155, "vCNV_GNSS_UART_TXD"),
 637         PINCTRL_PIN(156, "vCNV_GNSS_UART_RXD"),
 638         PINCTRL_PIN(157, "vCNV_GNSS_UART_CTS_B"),
 639         PINCTRL_PIN(158, "vCNV_GNSS_UART_RTS_B"),
 640         PINCTRL_PIN(159, "vUART0_TXD"),
 641         PINCTRL_PIN(160, "vUART0_RXD"),
 642         PINCTRL_PIN(161, "vUART0_CTS_B"),
 643         PINCTRL_PIN(162, "vUART0_RTS_B"),
 644         PINCTRL_PIN(163, "vISH_UART0_TXD"),
 645         PINCTRL_PIN(164, "vISH_UART0_RXD"),
 646         PINCTRL_PIN(165, "vISH_UART0_CTS_B"),
 647         PINCTRL_PIN(166, "vISH_UART0_RTS_B"),
 648         PINCTRL_PIN(167, "vISH_UART1_TXD"),
 649         PINCTRL_PIN(168, "vISH_UART1_RXD"),
 650         PINCTRL_PIN(169, "vISH_UART1_CTS_B"),
 651         PINCTRL_PIN(170, "vISH_UART1_RTS_B"),
 652         PINCTRL_PIN(171, "vCNV_BT_I2S_BCLK"),
 653         PINCTRL_PIN(172, "vCNV_BT_I2S_WS_SYNC"),
 654         PINCTRL_PIN(173, "vCNV_BT_I2S_SDO"),
 655         PINCTRL_PIN(174, "vCNV_BT_I2S_SDI"),
 656         PINCTRL_PIN(175, "vSSP2_SCLK"),
 657         PINCTRL_PIN(176, "vSSP2_SFRM"),
 658         PINCTRL_PIN(177, "vSSP2_TXD"),
 659         PINCTRL_PIN(178, "vSSP2_RXD"),
 660         PINCTRL_PIN(179, "vCNV_GNSS_HOST_WAKEB"),
 661         PINCTRL_PIN(180, "vSD3_CD_B"),
 662         /* GPP_C */
 663         PINCTRL_PIN(181, "SMBCLK"),
 664         PINCTRL_PIN(182, "SMBDATA"),
 665         PINCTRL_PIN(183, "SMBALERTB"),
 666         PINCTRL_PIN(184, "SML0CLK"),
 667         PINCTRL_PIN(185, "SML0DATA"),
 668         PINCTRL_PIN(186, "SML0ALERTB"),
 669         PINCTRL_PIN(187, "SML1CLK"),
 670         PINCTRL_PIN(188, "SML1DATA"),
 671         PINCTRL_PIN(189, "UART0_RXD"),
 672         PINCTRL_PIN(190, "UART0_TXD"),
 673         PINCTRL_PIN(191, "UART0_RTSB"),
 674         PINCTRL_PIN(192, "UART0_CTSB"),
 675         PINCTRL_PIN(193, "UART1_RXD"),
 676         PINCTRL_PIN(194, "UART1_TXD"),
 677         PINCTRL_PIN(195, "UART1_RTSB"),
 678         PINCTRL_PIN(196, "UART1_CTSB"),
 679         PINCTRL_PIN(197, "I2C0_SDA"),
 680         PINCTRL_PIN(198, "I2C0_SCL"),
 681         PINCTRL_PIN(199, "I2C1_SDA"),
 682         PINCTRL_PIN(200, "I2C1_SCL"),
 683         PINCTRL_PIN(201, "UART2_RXD"),
 684         PINCTRL_PIN(202, "UART2_TXD"),
 685         PINCTRL_PIN(203, "UART2_RTSB"),
 686         PINCTRL_PIN(204, "UART2_CTSB"),
 687         /* GPP_E */
 688         PINCTRL_PIN(205, "SATAXPCIE_0"),
 689         PINCTRL_PIN(206, "SATAXPCIE_1"),
 690         PINCTRL_PIN(207, "SATAXPCIE_2"),
 691         PINCTRL_PIN(208, "CPU_GP_0"),
 692         PINCTRL_PIN(209, "SATA_DEVSLP_0"),
 693         PINCTRL_PIN(210, "SATA_DEVSLP_1"),
 694         PINCTRL_PIN(211, "SATA_DEVSLP_2"),
 695         PINCTRL_PIN(212, "CPU_GP_1"),
 696         PINCTRL_PIN(213, "SATA_LEDB"),
 697         PINCTRL_PIN(214, "USB2_OCB_0"),
 698         PINCTRL_PIN(215, "USB2_OCB_1"),
 699         PINCTRL_PIN(216, "USB2_OCB_2"),
 700         PINCTRL_PIN(217, "USB2_OCB_3"),
 701         PINCTRL_PIN(218, "DDSP_HPD_0"),
 702         PINCTRL_PIN(219, "DDSP_HPD_1"),
 703         PINCTRL_PIN(220, "DDSP_HPD_2"),
 704         PINCTRL_PIN(221, "DDSP_HPD_3"),
 705         PINCTRL_PIN(222, "EDP_HPD"),
 706         PINCTRL_PIN(223, "DDPB_CTRLCLK"),
 707         PINCTRL_PIN(224, "DDPB_CTRLDATA"),
 708         PINCTRL_PIN(225, "DDPC_CTRLCLK"),
 709         PINCTRL_PIN(226, "DDPC_CTRLDATA"),
 710         PINCTRL_PIN(227, "DDPD_CTRLCLK"),
 711         PINCTRL_PIN(228, "DDPD_CTRLDATA"),
 712         /* JTAG */
 713         PINCTRL_PIN(229, "JTAG_TDO"),
 714         PINCTRL_PIN(230, "JTAGX"),
 715         PINCTRL_PIN(231, "PRDYB"),
 716         PINCTRL_PIN(232, "PREQB"),
 717         PINCTRL_PIN(233, "CPU_TRSTB"),
 718         PINCTRL_PIN(234, "JTAG_TDI"),
 719         PINCTRL_PIN(235, "JTAG_TMS"),
 720         PINCTRL_PIN(236, "JTAG_TCK"),
 721         PINCTRL_PIN(237, "ITP_PMODE"),
 722         /* HVCMOS */
 723         PINCTRL_PIN(238, "L_BKLTEN"),
 724         PINCTRL_PIN(239, "L_BKLTCTL"),
 725         PINCTRL_PIN(240, "L_VDDEN"),
 726         PINCTRL_PIN(241, "SYS_PWROK"),
 727         PINCTRL_PIN(242, "SYS_RESETB"),
 728         PINCTRL_PIN(243, "MLK_RSTB"),
 729 };
 730
 731 static const unsigned int cnllp_spi0_pins[] = { 40, 41, 42, 43, 7 };
 732 static const unsigned int cnllp_spi0_modes[] = { 1, 1, 1, 1, 2 };
 733 static const unsigned int cnllp_spi1_pins[] = { 44, 45, 46, 47, 11 };
 734 static const unsigned int cnllp_spi1_modes[] = { 1, 1, 1, 1, 2 };
 735 static const unsigned int cnllp_spi2_pins[] = { 77, 78, 79, 80, 83 };
 736 static const unsigned int cnllp_spi2_modes[] = { 3, 3, 3, 3, 2 };
 737
 738 static const unsigned int cnllp_i2c0_pins[] = { 197, 198 };
 739 static const unsigned int cnllp_i2c1_pins[] = { 199, 200 };
 740 static const unsigned int cnllp_i2c2_pins[] = { 121, 122 };
 741 static const unsigned int cnllp_i2c3_pins[] = { 123, 124 };
 742 static const unsigned int cnllp_i2c4_pins[] = { 125, 126 };
 743 static const unsigned int cnllp_i2c5_pins[] = { 127, 128 };
 744
 745 static const unsigned int cnllp_uart0_pins[] = { 189, 190, 191, 192 };
 746 static const unsigned int cnllp_uart1_pins[] = { 193, 194, 195, 196 };
 747 static const unsigned int cnllp_uart2_pins[] = { 201, 202, 203, 204 };
 748
 749 static const struct intel_pingroup cnllp_groups[] = {
 750         PIN_GROUP("spi0_grp", cnllp_spi0_pins, cnllp_spi0_modes),
 751         PIN_GROUP("spi1_grp", cnllp_spi1_pins, cnllp_spi1_modes),
 752         PIN_GROUP("spi2_grp", cnllp_spi2_pins, cnllp_spi2_modes),
 753         PIN_GROUP("i2c0_grp", cnllp_i2c0_pins, 1),
 754         PIN_GROUP("i2c1_grp", cnllp_i2c1_pins, 1),
 755         PIN_GROUP("i2c2_grp", cnllp_i2c2_pins, 1),
 756         PIN_GROUP("i2c3_grp", cnllp_i2c3_pins, 1),
 757         PIN_GROUP("i2c4_grp", cnllp_i2c4_pins, 1),
 758         PIN_GROUP("i2c5_grp", cnllp_i2c5_pins, 1),
 759         PIN_GROUP("uart0_grp", cnllp_uart0_pins, 1),
 760         PIN_GROUP("uart1_grp", cnllp_uart1_pins, 1),
 761         PIN_GROUP("uart2_grp", cnllp_uart2_pins, 1),
 762 };
 763
 764 static const char * const cnllp_spi0_groups[] = { "spi0_grp" };
 765 static const char * const cnllp_spi1_groups[] = { "spi1_grp" };
 766 static const char * const cnllp_spi2_groups[] = { "spi2_grp" };
 767 static const char * const cnllp_i2c0_groups[] = { "i2c0_grp" };
 768 static const char * const cnllp_i2c1_groups[] = { "i2c1_grp" };
 769 static const char * const cnllp_i2c2_groups[] = { "i2c2_grp" };
 770 static const char * const cnllp_i2c3_groups[] = { "i2c3_grp" };
 771 static const char * const cnllp_i2c4_groups[] = { "i2c4_grp" };
 772 static const char * const cnllp_i2c5_groups[] = { "i2c5_grp" };
 773 static const char * const cnllp_uart0_groups[] = { "uart0_grp" };
 774 static const char * const cnllp_uart1_groups[] = { "uart1_grp" };
 775 static const char * const cnllp_uart2_groups[] = { "uart2_grp" };
 776
 777 static const struct intel_function cnllp_functions[] = {
 778         FUNCTION("spi0", cnllp_spi0_groups),
 779         FUNCTION("spi1", cnllp_spi1_groups),
 780         FUNCTION("spi2", cnllp_spi2_groups),
 781         FUNCTION("i2c0", cnllp_i2c0_groups),
 782         FUNCTION("i2c1", cnllp_i2c1_groups),
 783         FUNCTION("i2c2", cnllp_i2c2_groups),
 784         FUNCTION("i2c3", cnllp_i2c3_groups),
 785         FUNCTION("i2c4", cnllp_i2c4_groups),
 786         FUNCTION("i2c5", cnllp_i2c5_groups),
 787         FUNCTION("uart0", cnllp_uart0_groups),
 788         FUNCTION("uart1", cnllp_uart1_groups),
 789         FUNCTION("uart2", cnllp_uart2_groups),
 790 };
 791
 792 static const struct intel_padgroup cnllp_community0_gpps[] = {
 793         CNL_GPP(0, 0, 24, 0),                   /* GPP_A */
 794         CNL_GPP(1, 25, 50, 32),                 /* GPP_B */
 795         CNL_GPP(2, 51, 58, 64),                 /* GPP_G */
 796         CNL_GPP(3, 59, 67, CNL_NO_GPIO),        /* SPI */
 797 };
 798
 799 static const struct intel_padgroup cnllp_community1_gpps[] = {
 800         CNL_GPP(0, 68, 92, 96),                 /* GPP_D */
 801         CNL_GPP(1, 93, 116, 128),               /* GPP_F */
 802         CNL_GPP(2, 117, 140, 160),              /* GPP_H */
 803         CNL_GPP(3, 141, 172, 192),              /* vGPIO */
 804         CNL_GPP(4, 173, 180, 224),              /* vGPIO */
 805 };
 806
 807 static const struct intel_padgroup cnllp_community4_gpps[] = {
 808         CNL_GPP(0, 181, 204, 256),              /* GPP_C */
 809         CNL_GPP(1, 205, 228, 288),              /* GPP_E */
 810         CNL_GPP(2, 229, 237, CNL_NO_GPIO),      /* JTAG */
 811         CNL_GPP(3, 238, 243, CNL_NO_GPIO),      /* HVCMOS */
 812 };
 813
 814 static const struct intel_community cnllp_communities[] = {
 815         CNLLP_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
 816         CNLLP_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
 817         CNLLP_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
 818 };
 819
 820 static const struct intel_pinctrl_soc_data cnllp_soc_data = {
 821         .pins = cnllp_pins,
 822         .npins = ARRAY_SIZE(cnllp_pins),
 823         .groups = cnllp_groups,
 824         .ngroups = ARRAY_SIZE(cnllp_groups),
 825         .functions = cnllp_functions,
 826         .nfunctions = ARRAY_SIZE(cnllp_functions),
 827         .communities = cnllp_communities,
 828         .ncommunities = ARRAY_SIZE(cnllp_communities),
 829 };
 830
 831 static const struct acpi_device_id cnl_pinctrl_acpi_match[] = {
 832         { "INT3450", (kernel_ulong_t)&cnlh_soc_data },
 833         { "INT34BB", (kernel_ulong_t)&cnllp_soc_data },
 834         { }
 835 };
 836 MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match);
 837
 838 static INTEL_PINCTRL_PM_OPS(cnl_pinctrl_pm_ops);
 839
 840 static struct platform_driver cnl_pinctrl_driver = {
 841         .probe = intel_pinctrl_probe_by_hid,
 842         .driver = {
 843                 .name = "cannonlake-pinctrl",
 844                 .acpi_match_table = cnl_pinctrl_acpi_match,
 845                 .pm = &cnl_pinctrl_pm_ops,
 846         },
 847 };
 848
 849 module_platform_driver(cnl_pinctrl_driver);
 850
 851 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
 852 MODULE_DESCRIPTION("Intel Cannon Lake PCH pinctrl/GPIO driver");
 853 MODULE_LICENSE("GPL v2");