drivers/pinctrl/intel/pinctrl-cherryview.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Cherryview/Braswell pinctrl driver
   4  *
   5  * Copyright (C) 2014, Intel Corporation
   6  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
   7  *
   8  * This driver is based on the original Cherryview GPIO driver by
   9  *   Ning Li <ning.li@intel.com>
  10  *   Alan Cox <alan@linux.intel.com>
  11  */
  12
  13 #include <linux/acpi.h>
  14 #include <linux/dmi.h>
  15 #include <linux/gpio/driver.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/types.h>
  20
  21 #include <linux/pinctrl/pinctrl.h>
  22 #include <linux/pinctrl/pinmux.h>
  23 #include <linux/pinctrl/pinconf.h>
  24 #include <linux/pinctrl/pinconf-generic.h>
  25
  26 #include "pinctrl-intel.h"
  27
  28 #define CHV_INTSTAT                     0x300
  29 #define CHV_INTMASK                     0x380
  30
  31 #define FAMILY_PAD_REGS_OFF             0x4400
  32 #define FAMILY_PAD_REGS_SIZE            0x400
  33 #define MAX_FAMILY_PAD_GPIO_NO          15
  34 #define GPIO_REGS_SIZE                  8
  35
  36 #define CHV_PADCTRL0                    0x000
  37 #define CHV_PADCTRL0_INTSEL_SHIFT       28
  38 #define CHV_PADCTRL0_INTSEL_MASK        (0xf << CHV_PADCTRL0_INTSEL_SHIFT)
  39 #define CHV_PADCTRL0_TERM_UP            BIT(23)
  40 #define CHV_PADCTRL0_TERM_SHIFT         20
  41 #define CHV_PADCTRL0_TERM_MASK          (7 << CHV_PADCTRL0_TERM_SHIFT)
  42 #define CHV_PADCTRL0_TERM_20K           1
  43 #define CHV_PADCTRL0_TERM_5K            2
  44 #define CHV_PADCTRL0_TERM_1K            4
  45 #define CHV_PADCTRL0_PMODE_SHIFT        16
  46 #define CHV_PADCTRL0_PMODE_MASK         (0xf << CHV_PADCTRL0_PMODE_SHIFT)
  47 #define CHV_PADCTRL0_GPIOEN             BIT(15)
  48 #define CHV_PADCTRL0_GPIOCFG_SHIFT      8
  49 #define CHV_PADCTRL0_GPIOCFG_MASK       (7 << CHV_PADCTRL0_GPIOCFG_SHIFT)
  50 #define CHV_PADCTRL0_GPIOCFG_GPIO       0
  51 #define CHV_PADCTRL0_GPIOCFG_GPO        1
  52 #define CHV_PADCTRL0_GPIOCFG_GPI        2
  53 #define CHV_PADCTRL0_GPIOCFG_HIZ        3
  54 #define CHV_PADCTRL0_GPIOTXSTATE        BIT(1)
  55 #define CHV_PADCTRL0_GPIORXSTATE        BIT(0)
  56
  57 #define CHV_PADCTRL1                    0x004
  58 #define CHV_PADCTRL1_CFGLOCK            BIT(31)
  59 #define CHV_PADCTRL1_INVRXTX_SHIFT      4
  60 #define CHV_PADCTRL1_INVRXTX_MASK       (0xf << CHV_PADCTRL1_INVRXTX_SHIFT)
  61 #define CHV_PADCTRL1_INVRXTX_TXENABLE   (2 << CHV_PADCTRL1_INVRXTX_SHIFT)
  62 #define CHV_PADCTRL1_ODEN               BIT(3)
  63 #define CHV_PADCTRL1_INVRXTX_RXDATA     (4 << CHV_PADCTRL1_INVRXTX_SHIFT)
  64 #define CHV_PADCTRL1_INTWAKECFG_MASK    7
  65 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
  66 #define CHV_PADCTRL1_INTWAKECFG_RISING  2
  67 #define CHV_PADCTRL1_INTWAKECFG_BOTH    3
  68 #define CHV_PADCTRL1_INTWAKECFG_LEVEL   4
  69
  70 /**
  71  * struct chv_alternate_function - A per group or per pin alternate function
  72  * @pin: Pin number (only used in per pin configs)
  73  * @mode: Mode the pin should be set in
  74  * @invert_oe: Invert OE for this pin
  75  */
  76 struct chv_alternate_function {
  77         unsigned int pin;
  78         u8 mode;
  79         bool invert_oe;
  80 };
  81
  82 /**
  83  * struct chv_pincgroup - describes a CHV pin group
  84  * @name: Name of the group
  85  * @pins: An array of pins in this group
  86  * @npins: Number of pins in this group
  87  * @altfunc: Alternate function applied to all pins in this group
  88  * @overrides: Alternate function override per pin or %NULL if not used
  89  * @noverrides: Number of per pin alternate function overrides if
  90  *              @overrides != NULL.
  91  */
  92 struct chv_pingroup {
  93         const char *name;
  94         const unsigned int *pins;
  95         size_t npins;
  96         struct chv_alternate_function altfunc;
  97         const struct chv_alternate_function *overrides;
  98         size_t noverrides;
  99 };
 100
 101 /**
 102  * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs
 103  * @base: Start pin number
 104  * @npins: Number of pins in this range
 105  */
 106 struct chv_gpio_pinrange {
 107         unsigned int base;
 108         unsigned int npins;
 109 };
 110
 111 /**
 112  * struct chv_community - A community specific configuration
 113  * @uid: ACPI _UID used to match the community
 114  * @pins: All pins in this community
 115  * @npins: Number of pins
 116  * @groups: All groups in this community
 117  * @ngroups: Number of groups
 118  * @functions: All functions in this community
 119  * @nfunctions: Number of functions
 120  * @gpio_ranges: An array of GPIO ranges in this community
 121  * @ngpio_ranges: Number of GPIO ranges
 122  * @nirqs: Total number of IRQs this community can generate
 123  * @acpi_space_id: An address space ID for ACPI OpRegion handler
 124  */
 125 struct chv_community {
 126         const char *uid;
 127         const struct pinctrl_pin_desc *pins;
 128         size_t npins;
 129         const struct chv_pingroup *groups;
 130         size_t ngroups;
 131         const struct intel_function *functions;
 132         size_t nfunctions;
 133         const struct chv_gpio_pinrange *gpio_ranges;
 134         size_t ngpio_ranges;
 135         size_t nirqs;
 136         acpi_adr_space_type acpi_space_id;
 137 };
 138
 139 struct chv_pin_context {
 140         u32 padctrl0;
 141         u32 padctrl1;
 142 };
 143
 144 /**
 145  * struct chv_pinctrl - CHV pinctrl private structure
 146  * @dev: Pointer to the parent device
 147  * @pctldesc: Pin controller description
 148  * @pctldev: Pointer to the pin controller device
 149  * @chip: GPIO chip in this pin controller
 150  * @irqchip: IRQ chip in this pin controller
 151  * @regs: MMIO registers
 152  * @irq: Our parent irq
 153  * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
 154  *              offset (in GPIO number space)
 155  * @community: Community this pinctrl instance represents
 156  * @saved_intmask: Interrupt mask saved for system sleep
 157  * @saved_pin_context: Pointer to a context of the pins saved for system sleep
 158  *
 159  * The first group in @groups is expected to contain all pins that can be
 160  * used as GPIOs.
 161  */
 162 struct chv_pinctrl {
 163         struct device *dev;
 164         struct pinctrl_desc pctldesc;
 165         struct pinctrl_dev *pctldev;
 166         struct gpio_chip chip;
 167         struct irq_chip irqchip;
 168         void __iomem *regs;
 169         unsigned int irq;
 170         unsigned int intr_lines[16];
 171         const struct chv_community *community;
 172         u32 saved_intmask;
 173         struct chv_pin_context *saved_pin_context;
 174 };
 175
 176 #define ALTERNATE_FUNCTION(p, m, i)             \
 177         {                                       \
 178                 .pin = (p),                     \
 179                 .mode = (m),                    \
 180                 .invert_oe = (i),               \
 181         }
 182
 183 #define PIN_GROUP_WITH_ALT(n, p, m, i)          \
 184         {                                       \
 185                 .name = (n),                    \
 186                 .pins = (p),                    \
 187                 .npins = ARRAY_SIZE((p)),       \
 188                 .altfunc.mode = (m),            \
 189                 .altfunc.invert_oe = (i),       \
 190         }
 191
 192 #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o)  \
 193         {                                       \
 194                 .name = (n),                    \
 195                 .pins = (p),                    \
 196                 .npins = ARRAY_SIZE((p)),       \
 197                 .altfunc.mode = (m),            \
 198                 .altfunc.invert_oe = (i),       \
 199                 .overrides = (o),               \
 200                 .noverrides = ARRAY_SIZE((o)),  \
 201         }
 202
 203 #define GPIO_PINRANGE(start, end)               \
 204         {                                       \
 205                 .base = (start),                \
 206                 .npins = (end) - (start) + 1,   \
 207         }
 208
 209 static const struct pinctrl_pin_desc southwest_pins[] = {
 210         PINCTRL_PIN(0, "FST_SPI_D2"),
 211         PINCTRL_PIN(1, "FST_SPI_D0"),
 212         PINCTRL_PIN(2, "FST_SPI_CLK"),
 213         PINCTRL_PIN(3, "FST_SPI_D3"),
 214         PINCTRL_PIN(4, "FST_SPI_CS1_B"),
 215         PINCTRL_PIN(5, "FST_SPI_D1"),
 216         PINCTRL_PIN(6, "FST_SPI_CS0_B"),
 217         PINCTRL_PIN(7, "FST_SPI_CS2_B"),
 218
 219         PINCTRL_PIN(15, "UART1_RTS_B"),
 220         PINCTRL_PIN(16, "UART1_RXD"),
 221         PINCTRL_PIN(17, "UART2_RXD"),
 222         PINCTRL_PIN(18, "UART1_CTS_B"),
 223         PINCTRL_PIN(19, "UART2_RTS_B"),
 224         PINCTRL_PIN(20, "UART1_TXD"),
 225         PINCTRL_PIN(21, "UART2_TXD"),
 226         PINCTRL_PIN(22, "UART2_CTS_B"),
 227
 228         PINCTRL_PIN(30, "MF_HDA_CLK"),
 229         PINCTRL_PIN(31, "MF_HDA_RSTB"),
 230         PINCTRL_PIN(32, "MF_HDA_SDIO"),
 231         PINCTRL_PIN(33, "MF_HDA_SDO"),
 232         PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
 233         PINCTRL_PIN(35, "MF_HDA_SYNC"),
 234         PINCTRL_PIN(36, "MF_HDA_SDI1"),
 235         PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
 236
 237         PINCTRL_PIN(45, "I2C5_SDA"),
 238         PINCTRL_PIN(46, "I2C4_SDA"),
 239         PINCTRL_PIN(47, "I2C6_SDA"),
 240         PINCTRL_PIN(48, "I2C5_SCL"),
 241         PINCTRL_PIN(49, "I2C_NFC_SDA"),
 242         PINCTRL_PIN(50, "I2C4_SCL"),
 243         PINCTRL_PIN(51, "I2C6_SCL"),
 244         PINCTRL_PIN(52, "I2C_NFC_SCL"),
 245
 246         PINCTRL_PIN(60, "I2C1_SDA"),
 247         PINCTRL_PIN(61, "I2C0_SDA"),
 248         PINCTRL_PIN(62, "I2C2_SDA"),
 249         PINCTRL_PIN(63, "I2C1_SCL"),
 250         PINCTRL_PIN(64, "I2C3_SDA"),
 251         PINCTRL_PIN(65, "I2C0_SCL"),
 252         PINCTRL_PIN(66, "I2C2_SCL"),
 253         PINCTRL_PIN(67, "I2C3_SCL"),
 254
 255         PINCTRL_PIN(75, "SATA_GP0"),
 256         PINCTRL_PIN(76, "SATA_GP1"),
 257         PINCTRL_PIN(77, "SATA_LEDN"),
 258         PINCTRL_PIN(78, "SATA_GP2"),
 259         PINCTRL_PIN(79, "MF_SMB_ALERTB"),
 260         PINCTRL_PIN(80, "SATA_GP3"),
 261         PINCTRL_PIN(81, "MF_SMB_CLK"),
 262         PINCTRL_PIN(82, "MF_SMB_DATA"),
 263
 264         PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
 265         PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
 266         PINCTRL_PIN(92, "GP_SSP_2_CLK"),
 267         PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
 268         PINCTRL_PIN(94, "GP_SSP_2_RXD"),
 269         PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
 270         PINCTRL_PIN(96, "GP_SSP_2_FS"),
 271         PINCTRL_PIN(97, "GP_SSP_2_TXD"),
 272 };
 273
 274 static const unsigned southwest_uart0_pins[] = { 16, 20 };
 275 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
 276 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
 277 static const unsigned southwest_i2c0_pins[] = { 61, 65 };
 278 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
 279 static const unsigned southwest_lpe_pins[] = {
 280         30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
 281 };
 282 static const unsigned southwest_i2c1_pins[] = { 60, 63 };
 283 static const unsigned southwest_i2c2_pins[] = { 62, 66 };
 284 static const unsigned southwest_i2c3_pins[] = { 64, 67 };
 285 static const unsigned southwest_i2c4_pins[] = { 46, 50 };
 286 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
 287 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
 288 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
 289 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
 290
 291 /* LPE I2S TXD pins need to have invert_oe set */
 292 static const struct chv_alternate_function southwest_lpe_altfuncs[] = {
 293         ALTERNATE_FUNCTION(30, 1, true),
 294         ALTERNATE_FUNCTION(34, 1, true),
 295         ALTERNATE_FUNCTION(97, 1, true),
 296 };
 297
 298 /*
 299  * Two spi3 chipselects are available in different mode than the main spi3
 300  * functionality, which is using mode 1.
 301  */
 302 static const struct chv_alternate_function southwest_spi3_altfuncs[] = {
 303         ALTERNATE_FUNCTION(76, 3, false),
 304         ALTERNATE_FUNCTION(80, 3, false),
 305 };
 306
 307 static const struct chv_pingroup southwest_groups[] = {
 308         PIN_GROUP_WITH_ALT("uart0_grp", southwest_uart0_pins, 2, false),
 309         PIN_GROUP_WITH_ALT("uart1_grp", southwest_uart1_pins, 1, false),
 310         PIN_GROUP_WITH_ALT("uart2_grp", southwest_uart2_pins, 1, false),
 311         PIN_GROUP_WITH_ALT("hda_grp", southwest_hda_pins, 2, false),
 312         PIN_GROUP_WITH_ALT("i2c0_grp", southwest_i2c0_pins, 1, true),
 313         PIN_GROUP_WITH_ALT("i2c1_grp", southwest_i2c1_pins, 1, true),
 314         PIN_GROUP_WITH_ALT("i2c2_grp", southwest_i2c2_pins, 1, true),
 315         PIN_GROUP_WITH_ALT("i2c3_grp", southwest_i2c3_pins, 1, true),
 316         PIN_GROUP_WITH_ALT("i2c4_grp", southwest_i2c4_pins, 1, true),
 317         PIN_GROUP_WITH_ALT("i2c5_grp", southwest_i2c5_pins, 1, true),
 318         PIN_GROUP_WITH_ALT("i2c6_grp", southwest_i2c6_pins, 1, true),
 319         PIN_GROUP_WITH_ALT("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true),
 320
 321         PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false,
 322                                 southwest_lpe_altfuncs),
 323         PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false,
 324                                 southwest_spi3_altfuncs),
 325 };
 326
 327 static const char * const southwest_uart0_groups[] = { "uart0_grp" };
 328 static const char * const southwest_uart1_groups[] = { "uart1_grp" };
 329 static const char * const southwest_uart2_groups[] = { "uart2_grp" };
 330 static const char * const southwest_hda_groups[] = { "hda_grp" };
 331 static const char * const southwest_lpe_groups[] = { "lpe_grp" };
 332 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
 333 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
 334 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
 335 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
 336 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
 337 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
 338 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
 339 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
 340 static const char * const southwest_spi3_groups[] = { "spi3_grp" };
 341
 342 /*
 343  * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
 344  * enabled only as GPIOs.
 345  */
 346 static const struct intel_function southwest_functions[] = {
 347         FUNCTION("uart0", southwest_uart0_groups),
 348         FUNCTION("uart1", southwest_uart1_groups),
 349         FUNCTION("uart2", southwest_uart2_groups),
 350         FUNCTION("hda", southwest_hda_groups),
 351         FUNCTION("lpe", southwest_lpe_groups),
 352         FUNCTION("i2c0", southwest_i2c0_groups),
 353         FUNCTION("i2c1", southwest_i2c1_groups),
 354         FUNCTION("i2c2", southwest_i2c2_groups),
 355         FUNCTION("i2c3", southwest_i2c3_groups),
 356         FUNCTION("i2c4", southwest_i2c4_groups),
 357         FUNCTION("i2c5", southwest_i2c5_groups),
 358         FUNCTION("i2c6", southwest_i2c6_groups),
 359         FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
 360         FUNCTION("spi3", southwest_spi3_groups),
 361 };
 362
 363 static const struct chv_gpio_pinrange southwest_gpio_ranges[] = {
 364         GPIO_PINRANGE(0, 7),
 365         GPIO_PINRANGE(15, 22),
 366         GPIO_PINRANGE(30, 37),
 367         GPIO_PINRANGE(45, 52),
 368         GPIO_PINRANGE(60, 67),
 369         GPIO_PINRANGE(75, 82),
 370         GPIO_PINRANGE(90, 97),
 371 };
 372
 373 static const struct chv_community southwest_community = {
 374         .uid = "1",
 375         .pins = southwest_pins,
 376         .npins = ARRAY_SIZE(southwest_pins),
 377         .groups = southwest_groups,
 378         .ngroups = ARRAY_SIZE(southwest_groups),
 379         .functions = southwest_functions,
 380         .nfunctions = ARRAY_SIZE(southwest_functions),
 381         .gpio_ranges = southwest_gpio_ranges,
 382         .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges),
 383         /*
 384          * Southwest community can generate GPIO interrupts only for the
 385          * first 8 interrupts. The upper half (8-15) can only be used to
 386          * trigger GPEs.
 387          */
 388         .nirqs = 8,
 389         .acpi_space_id = 0x91,
 390 };
 391
 392 static const struct pinctrl_pin_desc north_pins[] = {
 393         PINCTRL_PIN(0, "GPIO_DFX_0"),
 394         PINCTRL_PIN(1, "GPIO_DFX_3"),
 395         PINCTRL_PIN(2, "GPIO_DFX_7"),
 396         PINCTRL_PIN(3, "GPIO_DFX_1"),
 397         PINCTRL_PIN(4, "GPIO_DFX_5"),
 398         PINCTRL_PIN(5, "GPIO_DFX_4"),
 399         PINCTRL_PIN(6, "GPIO_DFX_8"),
 400         PINCTRL_PIN(7, "GPIO_DFX_2"),
 401         PINCTRL_PIN(8, "GPIO_DFX_6"),
 402
 403         PINCTRL_PIN(15, "GPIO_SUS0"),
 404         PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
 405         PINCTRL_PIN(17, "GPIO_SUS3"),
 406         PINCTRL_PIN(18, "GPIO_SUS7"),
 407         PINCTRL_PIN(19, "GPIO_SUS1"),
 408         PINCTRL_PIN(20, "GPIO_SUS5"),
 409         PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
 410         PINCTRL_PIN(22, "GPIO_SUS4"),
 411         PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
 412         PINCTRL_PIN(24, "GPIO_SUS2"),
 413         PINCTRL_PIN(25, "GPIO_SUS6"),
 414         PINCTRL_PIN(26, "CX_PREQ_B"),
 415         PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
 416
 417         PINCTRL_PIN(30, "TRST_B"),
 418         PINCTRL_PIN(31, "TCK"),
 419         PINCTRL_PIN(32, "PROCHOT_B"),
 420         PINCTRL_PIN(33, "SVIDO_DATA"),
 421         PINCTRL_PIN(34, "TMS"),
 422         PINCTRL_PIN(35, "CX_PRDY_B_2"),
 423         PINCTRL_PIN(36, "TDO_2"),
 424         PINCTRL_PIN(37, "CX_PRDY_B"),
 425         PINCTRL_PIN(38, "SVIDO_ALERT_B"),
 426         PINCTRL_PIN(39, "TDO"),
 427         PINCTRL_PIN(40, "SVIDO_CLK"),
 428         PINCTRL_PIN(41, "TDI"),
 429
 430         PINCTRL_PIN(45, "GP_CAMERASB_05"),
 431         PINCTRL_PIN(46, "GP_CAMERASB_02"),
 432         PINCTRL_PIN(47, "GP_CAMERASB_08"),
 433         PINCTRL_PIN(48, "GP_CAMERASB_00"),
 434         PINCTRL_PIN(49, "GP_CAMERASB_06"),
 435         PINCTRL_PIN(50, "GP_CAMERASB_10"),
 436         PINCTRL_PIN(51, "GP_CAMERASB_03"),
 437         PINCTRL_PIN(52, "GP_CAMERASB_09"),
 438         PINCTRL_PIN(53, "GP_CAMERASB_01"),
 439         PINCTRL_PIN(54, "GP_CAMERASB_07"),
 440         PINCTRL_PIN(55, "GP_CAMERASB_11"),
 441         PINCTRL_PIN(56, "GP_CAMERASB_04"),
 442
 443         PINCTRL_PIN(60, "PANEL0_BKLTEN"),
 444         PINCTRL_PIN(61, "HV_DDI0_HPD"),
 445         PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
 446         PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
 447         PINCTRL_PIN(64, "HV_DDI1_HPD"),
 448         PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
 449         PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
 450         PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
 451         PINCTRL_PIN(68, "HV_DDI2_HPD"),
 452         PINCTRL_PIN(69, "PANEL1_VDDEN"),
 453         PINCTRL_PIN(70, "PANEL1_BKLTEN"),
 454         PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
 455         PINCTRL_PIN(72, "PANEL0_VDDEN"),
 456 };
 457
 458 static const struct chv_gpio_pinrange north_gpio_ranges[] = {
 459         GPIO_PINRANGE(0, 8),
 460         GPIO_PINRANGE(15, 27),
 461         GPIO_PINRANGE(30, 41),
 462         GPIO_PINRANGE(45, 56),
 463         GPIO_PINRANGE(60, 72),
 464 };
 465
 466 static const struct chv_community north_community = {
 467         .uid = "2",
 468         .pins = north_pins,
 469         .npins = ARRAY_SIZE(north_pins),
 470         .gpio_ranges = north_gpio_ranges,
 471         .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges),
 472         /*
 473          * North community can generate GPIO interrupts only for the first
 474          * 8 interrupts. The upper half (8-15) can only be used to trigger
 475          * GPEs.
 476          */
 477         .nirqs = 8,
 478         .acpi_space_id = 0x92,
 479 };
 480
 481 static const struct pinctrl_pin_desc east_pins[] = {
 482         PINCTRL_PIN(0, "PMU_SLP_S3_B"),
 483         PINCTRL_PIN(1, "PMU_BATLOW_B"),
 484         PINCTRL_PIN(2, "SUS_STAT_B"),
 485         PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
 486         PINCTRL_PIN(4, "PMU_AC_PRESENT"),
 487         PINCTRL_PIN(5, "PMU_PLTRST_B"),
 488         PINCTRL_PIN(6, "PMU_SUSCLK"),
 489         PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
 490         PINCTRL_PIN(8, "PMU_PWRBTN_B"),
 491         PINCTRL_PIN(9, "PMU_SLP_S4_B"),
 492         PINCTRL_PIN(10, "PMU_WAKE_B"),
 493         PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
 494
 495         PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
 496         PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
 497         PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
 498         PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
 499         PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
 500         PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
 501         PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
 502         PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
 503         PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
 504         PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
 505         PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
 506         PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
 507 };
 508
 509 static const struct chv_gpio_pinrange east_gpio_ranges[] = {
 510         GPIO_PINRANGE(0, 11),
 511         GPIO_PINRANGE(15, 26),
 512 };
 513
 514 static const struct chv_community east_community = {
 515         .uid = "3",
 516         .pins = east_pins,
 517         .npins = ARRAY_SIZE(east_pins),
 518         .gpio_ranges = east_gpio_ranges,
 519         .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges),
 520         .nirqs = 16,
 521         .acpi_space_id = 0x93,
 522 };
 523
 524 static const struct pinctrl_pin_desc southeast_pins[] = {
 525         PINCTRL_PIN(0, "MF_PLT_CLK0"),
 526         PINCTRL_PIN(1, "PWM1"),
 527         PINCTRL_PIN(2, "MF_PLT_CLK1"),
 528         PINCTRL_PIN(3, "MF_PLT_CLK4"),
 529         PINCTRL_PIN(4, "MF_PLT_CLK3"),
 530         PINCTRL_PIN(5, "PWM0"),
 531         PINCTRL_PIN(6, "MF_PLT_CLK5"),
 532         PINCTRL_PIN(7, "MF_PLT_CLK2"),
 533
 534         PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
 535         PINCTRL_PIN(16, "SDMMC1_CLK"),
 536         PINCTRL_PIN(17, "SDMMC1_D0"),
 537         PINCTRL_PIN(18, "SDMMC2_D1"),
 538         PINCTRL_PIN(19, "SDMMC2_CLK"),
 539         PINCTRL_PIN(20, "SDMMC1_D2"),
 540         PINCTRL_PIN(21, "SDMMC2_D2"),
 541         PINCTRL_PIN(22, "SDMMC2_CMD"),
 542         PINCTRL_PIN(23, "SDMMC1_CMD"),
 543         PINCTRL_PIN(24, "SDMMC1_D1"),
 544         PINCTRL_PIN(25, "SDMMC2_D0"),
 545         PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
 546
 547         PINCTRL_PIN(30, "SDMMC3_D1"),
 548         PINCTRL_PIN(31, "SDMMC3_CLK"),
 549         PINCTRL_PIN(32, "SDMMC3_D3"),
 550         PINCTRL_PIN(33, "SDMMC3_D2"),
 551         PINCTRL_PIN(34, "SDMMC3_CMD"),
 552         PINCTRL_PIN(35, "SDMMC3_D0"),
 553
 554         PINCTRL_PIN(45, "MF_LPC_AD2"),
 555         PINCTRL_PIN(46, "LPC_CLKRUNB"),
 556         PINCTRL_PIN(47, "MF_LPC_AD0"),
 557         PINCTRL_PIN(48, "LPC_FRAMEB"),
 558         PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
 559         PINCTRL_PIN(50, "MF_LPC_AD3"),
 560         PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
 561         PINCTRL_PIN(52, "MF_LPC_AD1"),
 562
 563         PINCTRL_PIN(60, "SPI1_MISO"),
 564         PINCTRL_PIN(61, "SPI1_CSO_B"),
 565         PINCTRL_PIN(62, "SPI1_CLK"),
 566         PINCTRL_PIN(63, "MMC1_D6"),
 567         PINCTRL_PIN(64, "SPI1_MOSI"),
 568         PINCTRL_PIN(65, "MMC1_D5"),
 569         PINCTRL_PIN(66, "SPI1_CS1_B"),
 570         PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
 571         PINCTRL_PIN(68, "MMC1_D7"),
 572         PINCTRL_PIN(69, "MMC1_RCLK"),
 573
 574         PINCTRL_PIN(75, "USB_OC1_B"),
 575         PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
 576         PINCTRL_PIN(77, "GPIO_ALERT"),
 577         PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
 578         PINCTRL_PIN(79, "ILB_SERIRQ"),
 579         PINCTRL_PIN(80, "USB_OC0_B"),
 580         PINCTRL_PIN(81, "SDMMC3_CD_B"),
 581         PINCTRL_PIN(82, "SPKR"),
 582         PINCTRL_PIN(83, "SUSPWRDNACK"),
 583         PINCTRL_PIN(84, "SPARE_PIN"),
 584         PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
 585 };
 586
 587 static const unsigned southeast_pwm0_pins[] = { 5 };
 588 static const unsigned southeast_pwm1_pins[] = { 1 };
 589 static const unsigned southeast_sdmmc1_pins[] = {
 590         16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
 591 };
 592 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
 593 static const unsigned southeast_sdmmc3_pins[] = {
 594         30, 31, 32, 33, 34, 35, 78, 81, 85,
 595 };
 596 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
 597 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
 598
 599 static const struct chv_pingroup southeast_groups[] = {
 600         PIN_GROUP_WITH_ALT("pwm0_grp", southeast_pwm0_pins, 1, false),
 601         PIN_GROUP_WITH_ALT("pwm1_grp", southeast_pwm1_pins, 1, false),
 602         PIN_GROUP_WITH_ALT("sdmmc1_grp", southeast_sdmmc1_pins, 1, false),
 603         PIN_GROUP_WITH_ALT("sdmmc2_grp", southeast_sdmmc2_pins, 1, false),
 604         PIN_GROUP_WITH_ALT("sdmmc3_grp", southeast_sdmmc3_pins, 1, false),
 605         PIN_GROUP_WITH_ALT("spi1_grp", southeast_spi1_pins, 1, false),
 606         PIN_GROUP_WITH_ALT("spi2_grp", southeast_spi2_pins, 4, false),
 607 };
 608
 609 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
 610 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
 611 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
 612 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
 613 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
 614 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
 615 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
 616
 617 static const struct intel_function southeast_functions[] = {
 618         FUNCTION("pwm0", southeast_pwm0_groups),
 619         FUNCTION("pwm1", southeast_pwm1_groups),
 620         FUNCTION("sdmmc1", southeast_sdmmc1_groups),
 621         FUNCTION("sdmmc2", southeast_sdmmc2_groups),
 622         FUNCTION("sdmmc3", southeast_sdmmc3_groups),
 623         FUNCTION("spi1", southeast_spi1_groups),
 624         FUNCTION("spi2", southeast_spi2_groups),
 625 };
 626
 627 static const struct chv_gpio_pinrange southeast_gpio_ranges[] = {
 628         GPIO_PINRANGE(0, 7),
 629         GPIO_PINRANGE(15, 26),
 630         GPIO_PINRANGE(30, 35),
 631         GPIO_PINRANGE(45, 52),
 632         GPIO_PINRANGE(60, 69),
 633         GPIO_PINRANGE(75, 85),
 634 };
 635
 636 static const struct chv_community southeast_community = {
 637         .uid = "4",
 638         .pins = southeast_pins,
 639         .npins = ARRAY_SIZE(southeast_pins),
 640         .groups = southeast_groups,
 641         .ngroups = ARRAY_SIZE(southeast_groups),
 642         .functions = southeast_functions,
 643         .nfunctions = ARRAY_SIZE(southeast_functions),
 644         .gpio_ranges = southeast_gpio_ranges,
 645         .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges),
 646         .nirqs = 16,
 647         .acpi_space_id = 0x94,
 648 };
 649
 650 static const struct chv_community *chv_communities[] = {
 651         &southwest_community,
 652         &north_community,
 653         &east_community,
 654         &southeast_community,
 655 };
 656
 657 /*
 658  * Lock to serialize register accesses
 659  *
 660  * Due to a silicon issue, a shared lock must be used to prevent
 661  * concurrent accesses across the 4 GPIO controllers.
 662  *
 663  * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
 664  * errata #CHT34, for further information.
 665  */
 666 static DEFINE_RAW_SPINLOCK(chv_lock);
 667
 668 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset,
 669                                 unsigned int reg)
 670 {
 671         unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
 672         unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
 673
 674         offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no +
 675                  GPIO_REGS_SIZE * pad_no;
 676
 677         return pctrl->regs + offset + reg;
 678 }
 679
 680 static void chv_writel(u32 value, void __iomem *reg)
 681 {
 682         writel(value, reg);
 683         /* simple readback to confirm the bus transferring done */
 684         readl(reg);
 685 }
 686
 687 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
 688 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned int offset)
 689 {
 690         void __iomem *reg;
 691
 692         reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
 693         return readl(reg) & CHV_PADCTRL1_CFGLOCK;
 694 }
 695
 696 static int chv_get_groups_count(struct pinctrl_dev *pctldev)
 697 {
 698         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 699
 700         return pctrl->community->ngroups;
 701 }
 702
 703 static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
 704                                       unsigned int group)
 705 {
 706         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 707
 708         return pctrl->community->groups[group].name;
 709 }
 710
 711 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 712                               const unsigned int **pins, unsigned int *npins)
 713 {
 714         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 715
 716         *pins = pctrl->community->groups[group].pins;
 717         *npins = pctrl->community->groups[group].npins;
 718         return 0;
 719 }
 720
 721 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 722                              unsigned int offset)
 723 {
 724         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 725         unsigned long flags;
 726         u32 ctrl0, ctrl1;
 727         bool locked;
 728
 729         raw_spin_lock_irqsave(&chv_lock, flags);
 730
 731         ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
 732         ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
 733         locked = chv_pad_locked(pctrl, offset);
 734
 735         raw_spin_unlock_irqrestore(&chv_lock, flags);
 736
 737         if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
 738                 seq_puts(s, "GPIO ");
 739         } else {
 740                 u32 mode;
 741
 742                 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
 743                 mode >>= CHV_PADCTRL0_PMODE_SHIFT;
 744
 745                 seq_printf(s, "mode %d ", mode);
 746         }
 747
 748         seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
 749
 750         if (locked)
 751                 seq_puts(s, " [LOCKED]");
 752 }
 753
 754 static const struct pinctrl_ops chv_pinctrl_ops = {
 755         .get_groups_count = chv_get_groups_count,
 756         .get_group_name = chv_get_group_name,
 757         .get_group_pins = chv_get_group_pins,
 758         .pin_dbg_show = chv_pin_dbg_show,
 759 };
 760
 761 static int chv_get_functions_count(struct pinctrl_dev *pctldev)
 762 {
 763         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 764
 765         return pctrl->community->nfunctions;
 766 }
 767
 768 static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
 769                                          unsigned int function)
 770 {
 771         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 772
 773         return pctrl->community->functions[function].name;
 774 }
 775
 776 static int chv_get_function_groups(struct pinctrl_dev *pctldev,
 777                                    unsigned int function,
 778                                    const char * const **groups,
 779                                    unsigned int * const ngroups)
 780 {
 781         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 782
 783         *groups = pctrl->community->functions[function].groups;
 784         *ngroups = pctrl->community->functions[function].ngroups;
 785         return 0;
 786 }
 787
 788 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
 789                               unsigned int function, unsigned int group)
 790 {
 791         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 792         const struct chv_pingroup *grp;
 793         unsigned long flags;
 794         int i;
 795
 796         grp = &pctrl->community->groups[group];
 797
 798         raw_spin_lock_irqsave(&chv_lock, flags);
 799
 800         /* Check first that the pad is not locked */
 801         for (i = 0; i < grp->npins; i++) {
 802                 if (chv_pad_locked(pctrl, grp->pins[i])) {
 803                         dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
 804                                  grp->pins[i]);
 805                         raw_spin_unlock_irqrestore(&chv_lock, flags);
 806                         return -EBUSY;
 807                 }
 808         }
 809
 810         for (i = 0; i < grp->npins; i++) {
 811                 const struct chv_alternate_function *altfunc = &grp->altfunc;
 812                 int pin = grp->pins[i];
 813                 void __iomem *reg;
 814                 u32 value;
 815
 816                 /* Check if there is pin-specific config */
 817                 if (grp->overrides) {
 818                         int j;
 819
 820                         for (j = 0; j < grp->noverrides; j++) {
 821                                 if (grp->overrides[j].pin == pin) {
 822                                         altfunc = &grp->overrides[j];
 823                                         break;
 824                                 }
 825                         }
 826                 }
 827
 828                 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
 829                 value = readl(reg);
 830                 /* Disable GPIO mode */
 831                 value &= ~CHV_PADCTRL0_GPIOEN;
 832                 /* Set to desired mode */
 833                 value &= ~CHV_PADCTRL0_PMODE_MASK;
 834                 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT;
 835                 chv_writel(value, reg);
 836
 837                 /* Update for invert_oe */
 838                 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
 839                 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK;
 840                 if (altfunc->invert_oe)
 841                         value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
 842                 chv_writel(value, reg);
 843
 844                 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
 845                         pin, altfunc->mode, altfunc->invert_oe ? "" : "not ");
 846         }
 847
 848         raw_spin_unlock_irqrestore(&chv_lock, flags);
 849
 850         return 0;
 851 }
 852
 853 static void chv_gpio_clear_triggering(struct chv_pinctrl *pctrl,
 854                                       unsigned int offset)
 855 {
 856         void __iomem *reg;
 857         u32 value;
 858
 859         reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
 860         value = readl(reg);
 861         value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
 862         value &= ~CHV_PADCTRL1_INVRXTX_MASK;
 863         chv_writel(value, reg);
 864 }
 865
 866 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
 867                                    struct pinctrl_gpio_range *range,
 868                                    unsigned int offset)
 869 {
 870         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 871         unsigned long flags;
 872         void __iomem *reg;
 873         u32 value;
 874
 875         raw_spin_lock_irqsave(&chv_lock, flags);
 876
 877         if (chv_pad_locked(pctrl, offset)) {
 878                 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
 879                 if (!(value & CHV_PADCTRL0_GPIOEN)) {
 880                         /* Locked so cannot enable */
 881                         raw_spin_unlock_irqrestore(&chv_lock, flags);
 882                         return -EBUSY;
 883                 }
 884         } else {
 885                 int i;
 886
 887                 /* Reset the interrupt mapping */
 888                 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) {
 889                         if (pctrl->intr_lines[i] == offset) {
 890                                 pctrl->intr_lines[i] = 0;
 891                                 break;
 892                         }
 893                 }
 894
 895                 /* Disable interrupt generation */
 896                 chv_gpio_clear_triggering(pctrl, offset);
 897
 898                 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
 899                 value = readl(reg);
 900
 901                 /*
 902                  * If the pin is in HiZ mode (both TX and RX buffers are
 903                  * disabled) we turn it to be input now.
 904                  */
 905                 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
 906                      (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
 907                         value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
 908                         value |= CHV_PADCTRL0_GPIOCFG_GPI <<
 909                                 CHV_PADCTRL0_GPIOCFG_SHIFT;
 910                 }
 911
 912                 /* Switch to a GPIO mode */
 913                 value |= CHV_PADCTRL0_GPIOEN;
 914                 chv_writel(value, reg);
 915         }
 916
 917         raw_spin_unlock_irqrestore(&chv_lock, flags);
 918
 919         return 0;
 920 }
 921
 922 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
 923                                   struct pinctrl_gpio_range *range,
 924                                   unsigned int offset)
 925 {
 926         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 927         unsigned long flags;
 928
 929         raw_spin_lock_irqsave(&chv_lock, flags);
 930
 931         if (!chv_pad_locked(pctrl, offset))
 932                 chv_gpio_clear_triggering(pctrl, offset);
 933
 934         raw_spin_unlock_irqrestore(&chv_lock, flags);
 935 }
 936
 937 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
 938                                   struct pinctrl_gpio_range *range,
 939                                   unsigned int offset, bool input)
 940 {
 941         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 942         void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
 943         unsigned long flags;
 944         u32 ctrl0;
 945
 946         raw_spin_lock_irqsave(&chv_lock, flags);
 947
 948         ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
 949         if (input)
 950                 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
 951         else
 952                 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
 953         chv_writel(ctrl0, reg);
 954
 955         raw_spin_unlock_irqrestore(&chv_lock, flags);
 956
 957         return 0;
 958 }
 959
 960 static const struct pinmux_ops chv_pinmux_ops = {
 961         .get_functions_count = chv_get_functions_count,
 962         .get_function_name = chv_get_function_name,
 963         .get_function_groups = chv_get_function_groups,
 964         .set_mux = chv_pinmux_set_mux,
 965         .gpio_request_enable = chv_gpio_request_enable,
 966         .gpio_disable_free = chv_gpio_disable_free,
 967         .gpio_set_direction = chv_gpio_set_direction,
 968 };
 969
 970 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
 971                           unsigned long *config)
 972 {
 973         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 974         enum pin_config_param param = pinconf_to_config_param(*config);
 975         unsigned long flags;
 976         u32 ctrl0, ctrl1;
 977         u16 arg = 0;
 978         u32 term;
 979
 980         raw_spin_lock_irqsave(&chv_lock, flags);
 981         ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
 982         ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
 983         raw_spin_unlock_irqrestore(&chv_lock, flags);
 984
 985         term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
 986
 987         switch (param) {
 988         case PIN_CONFIG_BIAS_DISABLE:
 989                 if (term)
 990                         return -EINVAL;
 991                 break;
 992
 993         case PIN_CONFIG_BIAS_PULL_UP:
 994                 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
 995                         return -EINVAL;
 996
 997                 switch (term) {
 998                 case CHV_PADCTRL0_TERM_20K:
 999                         arg = 20000;
1000                         break;
1001                 case CHV_PADCTRL0_TERM_5K:
1002                         arg = 5000;
1003                         break;
1004                 case CHV_PADCTRL0_TERM_1K:
1005                         arg = 1000;
1006                         break;
1007                 }
1008
1009                 break;
1010
1011         case PIN_CONFIG_BIAS_PULL_DOWN:
1012                 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
1013                         return -EINVAL;
1014
1015                 switch (term) {
1016                 case CHV_PADCTRL0_TERM_20K:
1017                         arg = 20000;
1018                         break;
1019                 case CHV_PADCTRL0_TERM_5K:
1020                         arg = 5000;
1021                         break;
1022                 }
1023
1024                 break;
1025
1026         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1027                 if (!(ctrl1 & CHV_PADCTRL1_ODEN))
1028                         return -EINVAL;
1029                 break;
1030
1031         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
1032                 u32 cfg;
1033
1034                 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1035                 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1036                 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
1037                         return -EINVAL;
1038
1039                 break;
1040         }
1041
1042         default:
1043                 return -ENOTSUPP;
1044         }
1045
1046         *config = pinconf_to_config_packed(param, arg);
1047         return 0;
1048 }
1049
1050 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin,
1051                                enum pin_config_param param, u32 arg)
1052 {
1053         void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1054         unsigned long flags;
1055         u32 ctrl0, pull;
1056
1057         raw_spin_lock_irqsave(&chv_lock, flags);
1058         ctrl0 = readl(reg);
1059
1060         switch (param) {
1061         case PIN_CONFIG_BIAS_DISABLE:
1062                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1063                 break;
1064
1065         case PIN_CONFIG_BIAS_PULL_UP:
1066                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1067
1068                 switch (arg) {
1069                 case 1000:
1070                         /* For 1k there is only pull up */
1071                         pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
1072                         break;
1073                 case 5000:
1074                         pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1075                         break;
1076                 case 20000:
1077                         pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1078                         break;
1079                 default:
1080                         raw_spin_unlock_irqrestore(&chv_lock, flags);
1081                         return -EINVAL;
1082                 }
1083
1084                 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1085                 break;
1086
1087         case PIN_CONFIG_BIAS_PULL_DOWN:
1088                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1089
1090                 switch (arg) {
1091                 case 5000:
1092                         pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1093                         break;
1094                 case 20000:
1095                         pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1096                         break;
1097                 default:
1098                         raw_spin_unlock_irqrestore(&chv_lock, flags);
1099                         return -EINVAL;
1100                 }
1101
1102                 ctrl0 |= pull;
1103                 break;
1104
1105         default:
1106                 raw_spin_unlock_irqrestore(&chv_lock, flags);
1107                 return -EINVAL;
1108         }
1109
1110         chv_writel(ctrl0, reg);
1111         raw_spin_unlock_irqrestore(&chv_lock, flags);
1112
1113         return 0;
1114 }
1115
1116 static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
1117                                bool enable)
1118 {
1119         void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1120         unsigned long flags;
1121         u32 ctrl1;
1122
1123         raw_spin_lock_irqsave(&chv_lock, flags);
1124         ctrl1 = readl(reg);
1125
1126         if (enable)
1127                 ctrl1 |= CHV_PADCTRL1_ODEN;
1128         else
1129                 ctrl1 &= ~CHV_PADCTRL1_ODEN;
1130
1131         chv_writel(ctrl1, reg);
1132         raw_spin_unlock_irqrestore(&chv_lock, flags);
1133
1134         return 0;
1135 }
1136
1137 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
1138                           unsigned long *configs, unsigned int nconfigs)
1139 {
1140         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1141         enum pin_config_param param;
1142         int i, ret;
1143         u32 arg;
1144
1145         if (chv_pad_locked(pctrl, pin))
1146                 return -EBUSY;
1147
1148         for (i = 0; i < nconfigs; i++) {
1149                 param = pinconf_to_config_param(configs[i]);
1150                 arg = pinconf_to_config_argument(configs[i]);
1151
1152                 switch (param) {
1153                 case PIN_CONFIG_BIAS_DISABLE:
1154                 case PIN_CONFIG_BIAS_PULL_UP:
1155                 case PIN_CONFIG_BIAS_PULL_DOWN:
1156                         ret = chv_config_set_pull(pctrl, pin, param, arg);
1157                         if (ret)
1158                                 return ret;
1159                         break;
1160
1161                 case PIN_CONFIG_DRIVE_PUSH_PULL:
1162                         ret = chv_config_set_oden(pctrl, pin, false);
1163                         if (ret)
1164                                 return ret;
1165                         break;
1166
1167                 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1168                         ret = chv_config_set_oden(pctrl, pin, true);
1169                         if (ret)
1170                                 return ret;
1171                         break;
1172
1173                 default:
1174                         return -ENOTSUPP;
1175                 }
1176
1177                 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
1178                         param, arg);
1179         }
1180
1181         return 0;
1182 }
1183
1184 static int chv_config_group_get(struct pinctrl_dev *pctldev,
1185                                 unsigned int group,
1186                                 unsigned long *config)
1187 {
1188         const unsigned int *pins;
1189         unsigned int npins;
1190         int ret;
1191
1192         ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1193         if (ret)
1194                 return ret;
1195
1196         ret = chv_config_get(pctldev, pins[0], config);
1197         if (ret)
1198                 return ret;
1199
1200         return 0;
1201 }
1202
1203 static int chv_config_group_set(struct pinctrl_dev *pctldev,
1204                                 unsigned int group, unsigned long *configs,
1205                                 unsigned int num_configs)
1206 {
1207         const unsigned int *pins;
1208         unsigned int npins;
1209         int i, ret;
1210
1211         ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1212         if (ret)
1213                 return ret;
1214
1215         for (i = 0; i < npins; i++) {
1216                 ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1217                 if (ret)
1218                         return ret;
1219         }
1220
1221         return 0;
1222 }
1223
1224 static const struct pinconf_ops chv_pinconf_ops = {
1225         .is_generic = true,
1226         .pin_config_set = chv_config_set,
1227         .pin_config_get = chv_config_get,
1228         .pin_config_group_get = chv_config_group_get,
1229         .pin_config_group_set = chv_config_group_set,
1230 };
1231
1232 static struct pinctrl_desc chv_pinctrl_desc = {
1233         .pctlops = &chv_pinctrl_ops,
1234         .pmxops = &chv_pinmux_ops,
1235         .confops = &chv_pinconf_ops,
1236         .owner = THIS_MODULE,
1237 };
1238
1239 static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
1240 {
1241         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1242         unsigned long flags;
1243         u32 ctrl0, cfg;
1244
1245         raw_spin_lock_irqsave(&chv_lock, flags);
1246         ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
1247         raw_spin_unlock_irqrestore(&chv_lock, flags);
1248
1249         cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1250         cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1251
1252         if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1253                 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1254         return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1255 }
1256
1257 static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1258 {
1259         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1260         unsigned long flags;
1261         void __iomem *reg;
1262         u32 ctrl0;
1263
1264         raw_spin_lock_irqsave(&chv_lock, flags);
1265
1266         reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
1267         ctrl0 = readl(reg);
1268
1269         if (value)
1270                 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1271         else
1272                 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1273
1274         chv_writel(ctrl0, reg);
1275
1276         raw_spin_unlock_irqrestore(&chv_lock, flags);
1277 }
1278
1279 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1280 {
1281         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1282         u32 ctrl0, direction;
1283         unsigned long flags;
1284
1285         raw_spin_lock_irqsave(&chv_lock, flags);
1286         ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
1287         raw_spin_unlock_irqrestore(&chv_lock, flags);
1288
1289         direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1290         direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1291
1292         if (direction == CHV_PADCTRL0_GPIOCFG_GPO)
1293                 return GPIO_LINE_DIRECTION_OUT;
1294
1295         return GPIO_LINE_DIRECTION_IN;
1296 }
1297
1298 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1299 {
1300         return pinctrl_gpio_direction_input(chip->base + offset);
1301 }
1302
1303 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1304                                      int value)
1305 {
1306         chv_gpio_set(chip, offset, value);
1307         return pinctrl_gpio_direction_output(chip->base + offset);
1308 }
1309
1310 static const struct gpio_chip chv_gpio_chip = {
1311         .owner = THIS_MODULE,
1312         .request = gpiochip_generic_request,
1313         .free = gpiochip_generic_free,
1314         .get_direction = chv_gpio_get_direction,
1315         .direction_input = chv_gpio_direction_input,
1316         .direction_output = chv_gpio_direction_output,
1317         .get = chv_gpio_get,
1318         .set = chv_gpio_set,
1319 };
1320
1321 static void chv_gpio_irq_ack(struct irq_data *d)
1322 {
1323         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1324         struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1325         int pin = irqd_to_hwirq(d);
1326         u32 intr_line;
1327
1328         raw_spin_lock(&chv_lock);
1329
1330         intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1331         intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1332         intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1333         chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
1334
1335         raw_spin_unlock(&chv_lock);
1336 }
1337
1338 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1339 {
1340         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1341         struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1342         int pin = irqd_to_hwirq(d);
1343         u32 value, intr_line;
1344         unsigned long flags;
1345
1346         raw_spin_lock_irqsave(&chv_lock, flags);
1347
1348         intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1349         intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1350         intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1351
1352         value = readl(pctrl->regs + CHV_INTMASK);
1353         if (mask)
1354                 value &= ~BIT(intr_line);
1355         else
1356                 value |= BIT(intr_line);
1357         chv_writel(value, pctrl->regs + CHV_INTMASK);
1358
1359         raw_spin_unlock_irqrestore(&chv_lock, flags);
1360 }
1361
1362 static void chv_gpio_irq_mask(struct irq_data *d)
1363 {
1364         chv_gpio_irq_mask_unmask(d, true);
1365 }
1366
1367 static void chv_gpio_irq_unmask(struct irq_data *d)
1368 {
1369         chv_gpio_irq_mask_unmask(d, false);
1370 }
1371
1372 static unsigned chv_gpio_irq_startup(struct irq_data *d)
1373 {
1374         /*
1375          * Check if the interrupt has been requested with 0 as triggering
1376          * type. In that case it is assumed that the current values
1377          * programmed to the hardware are used (e.g BIOS configured
1378          * defaults).
1379          *
1380          * In that case ->irq_set_type() will never be called so we need to
1381          * read back the values from hardware now, set correct flow handler
1382          * and update mappings before the interrupt is being used.
1383          */
1384         if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1385                 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1386                 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1387                 unsigned int pin = irqd_to_hwirq(d);
1388                 irq_flow_handler_t handler;
1389                 unsigned long flags;
1390                 u32 intsel, value;
1391
1392                 raw_spin_lock_irqsave(&chv_lock, flags);
1393                 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1394                 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1395                 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1396
1397                 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
1398                 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1399                         handler = handle_level_irq;
1400                 else
1401                         handler = handle_edge_irq;
1402
1403                 if (!pctrl->intr_lines[intsel]) {
1404                         irq_set_handler_locked(d, handler);
1405                         pctrl->intr_lines[intsel] = pin;
1406                 }
1407                 raw_spin_unlock_irqrestore(&chv_lock, flags);
1408         }
1409
1410         chv_gpio_irq_unmask(d);
1411         return 0;
1412 }
1413
1414 static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
1415 {
1416         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1417         struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1418         unsigned int pin = irqd_to_hwirq(d);
1419         unsigned long flags;
1420         u32 value;
1421
1422         raw_spin_lock_irqsave(&chv_lock, flags);
1423
1424         /*
1425          * Pins which can be used as shared interrupt are configured in
1426          * BIOS. Driver trusts BIOS configurations and assigns different
1427          * handler according to the irq type.
1428          *
1429          * Driver needs to save the mapping between each pin and
1430          * its interrupt line.
1431          * 1. If the pin cfg is locked in BIOS:
1432          *      Trust BIOS has programmed IntWakeCfg bits correctly,
1433          *      driver just needs to save the mapping.
1434          * 2. If the pin cfg is not locked in BIOS:
1435          *      Driver programs the IntWakeCfg bits and save the mapping.
1436          */
1437         if (!chv_pad_locked(pctrl, pin)) {
1438                 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1439
1440                 value = readl(reg);
1441                 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1442                 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1443
1444                 if (type & IRQ_TYPE_EDGE_BOTH) {
1445                         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1446                                 value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1447                         else if (type & IRQ_TYPE_EDGE_RISING)
1448                                 value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1449                         else if (type & IRQ_TYPE_EDGE_FALLING)
1450                                 value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1451                 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1452                         value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1453                         if (type & IRQ_TYPE_LEVEL_LOW)
1454                                 value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1455                 }
1456
1457                 chv_writel(value, reg);
1458         }
1459
1460         value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1461         value &= CHV_PADCTRL0_INTSEL_MASK;
1462         value >>= CHV_PADCTRL0_INTSEL_SHIFT;
1463
1464         pctrl->intr_lines[value] = pin;
1465
1466         if (type & IRQ_TYPE_EDGE_BOTH)
1467                 irq_set_handler_locked(d, handle_edge_irq);
1468         else if (type & IRQ_TYPE_LEVEL_MASK)
1469                 irq_set_handler_locked(d, handle_level_irq);
1470
1471         raw_spin_unlock_irqrestore(&chv_lock, flags);
1472
1473         return 0;
1474 }
1475
1476 static void chv_gpio_irq_handler(struct irq_desc *desc)
1477 {
1478         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1479         struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1480         struct irq_chip *chip = irq_desc_get_chip(desc);
1481         unsigned long pending;
1482         u32 intr_line;
1483
1484         chained_irq_enter(chip, desc);
1485
1486         pending = readl(pctrl->regs + CHV_INTSTAT);
1487         for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
1488                 unsigned int irq, offset;
1489
1490                 offset = pctrl->intr_lines[intr_line];
1491                 irq = irq_find_mapping(gc->irq.domain, offset);
1492                 generic_handle_irq(irq);
1493         }
1494
1495         chained_irq_exit(chip, desc);
1496 }
1497
1498 /*
1499  * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
1500  * tables. Since we leave GPIOs that are not capable of generating
1501  * interrupts out of the irqdomain the numbering will be different and
1502  * cause devices using the hardcoded IRQ numbers fail. In order not to
1503  * break such machines we will only mask pins from irqdomain if the machine
1504  * is not listed below.
1505  */
1506 static const struct dmi_system_id chv_no_valid_mask[] = {
1507         /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
1508         {
1509                 .ident = "Intel_Strago based Chromebooks (All models)",
1510                 .matches = {
1511                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1512                         DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
1513                 },
1514         },
1515         {
1516                 .ident = "HP Chromebook 11 G5 (Setzer)",
1517                 .matches = {
1518                         DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1519                         DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
1520                 },
1521         },
1522         {
1523                 .ident = "Acer Chromebook R11 (Cyan)",
1524                 .matches = {
1525                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1526                         DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
1527                 },
1528         },
1529         {
1530                 .ident = "Samsung Chromebook 3 (Celes)",
1531                 .matches = {
1532                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1533                         DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
1534                 },
1535         },
1536         {}
1537 };
1538
1539 static void chv_init_irq_valid_mask(struct gpio_chip *chip,
1540                                     unsigned long *valid_mask,
1541                                     unsigned int ngpios)
1542 {
1543         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1544         const struct chv_community *community = pctrl->community;
1545         int i;
1546
1547         /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1548         for (i = 0; i < community->npins; i++) {
1549                 const struct pinctrl_pin_desc *desc;
1550                 u32 intsel;
1551
1552                 desc = &community->pins[i];
1553
1554                 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
1555                 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1556                 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1557
1558                 if (intsel >= community->nirqs)
1559                         clear_bit(desc->number, valid_mask);
1560         }
1561 }
1562
1563 static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
1564 {
1565         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1566
1567         /*
1568          * The same set of machines in chv_no_valid_mask[] have incorrectly
1569          * configured GPIOs that generate spurious interrupts so we use
1570          * this same list to apply another quirk for them.
1571          *
1572          * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
1573          */
1574         if (!pctrl->chip.irq.init_valid_mask) {
1575                 /*
1576                  * Mask all interrupts the community is able to generate
1577                  * but leave the ones that can only generate GPEs unmasked.
1578                  */
1579                 chv_writel(GENMASK(31, pctrl->community->nirqs),
1580                            pctrl->regs + CHV_INTMASK);
1581         }
1582
1583         /* Clear all interrupts */
1584         chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1585
1586         return 0;
1587 }
1588
1589 static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
1590 {
1591         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1592         const struct chv_community *community = pctrl->community;
1593         const struct chv_gpio_pinrange *range;
1594         int ret, i;
1595
1596         for (i = 0; i < community->ngpio_ranges; i++) {
1597                 range = &community->gpio_ranges[i];
1598                 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
1599                                              range->base, range->base,
1600                                              range->npins);
1601                 if (ret) {
1602                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1603                         return ret;
1604                 }
1605         }
1606
1607         return 0;
1608 }
1609
1610 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1611 {
1612         const struct chv_gpio_pinrange *range;
1613         struct gpio_chip *chip = &pctrl->chip;
1614         bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1615         const struct chv_community *community = pctrl->community;
1616         int ret, i, irq_base;
1617
1618         *chip = chv_gpio_chip;
1619
1620         chip->ngpio = community->pins[community->npins - 1].number + 1;
1621         chip->label = dev_name(pctrl->dev);
1622         chip->add_pin_ranges = chv_gpio_add_pin_ranges;
1623         chip->parent = pctrl->dev;
1624         chip->base = -1;
1625
1626         pctrl->irq = irq;
1627         pctrl->irqchip.name = "chv-gpio";
1628         pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
1629         pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
1630         pctrl->irqchip.irq_mask = chv_gpio_irq_mask;
1631         pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask;
1632         pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
1633         pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
1634
1635         chip->irq.chip = &pctrl->irqchip;
1636         chip->irq.init_hw = chv_gpio_irq_init_hw;
1637         chip->irq.parent_handler = chv_gpio_irq_handler;
1638         chip->irq.num_parents = 1;
1639         chip->irq.parents = &pctrl->irq;
1640         chip->irq.default_type = IRQ_TYPE_NONE;
1641         chip->irq.handler = handle_bad_irq;
1642         if (need_valid_mask) {
1643                 chip->irq.init_valid_mask = chv_init_irq_valid_mask;
1644         } else {
1645                 irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
1646                                                 community->npins, NUMA_NO_NODE);
1647                 if (irq_base < 0) {
1648                         dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
1649                         return irq_base;
1650                 }
1651         }
1652
1653         ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1654         if (ret) {
1655                 dev_err(pctrl->dev, "Failed to register gpiochip\n");
1656                 return ret;
1657         }
1658
1659         if (!need_valid_mask) {
1660                 for (i = 0; i < community->ngpio_ranges; i++) {
1661                         range = &community->gpio_ranges[i];
1662
1663                         irq_domain_associate_many(chip->irq.domain, irq_base,
1664                                                   range->base, range->npins);
1665                         irq_base += range->npins;
1666                 }
1667         }
1668
1669         return 0;
1670 }
1671
1672 static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
1673         acpi_physical_address address, u32 bits, u64 *value,
1674         void *handler_context, void *region_context)
1675 {
1676         struct chv_pinctrl *pctrl = region_context;
1677         unsigned long flags;
1678         acpi_status ret = AE_OK;
1679
1680         raw_spin_lock_irqsave(&chv_lock, flags);
1681
1682         if (function == ACPI_WRITE)
1683                 chv_writel((u32)(*value), pctrl->regs + (u32)address);
1684         else if (function == ACPI_READ)
1685                 *value = readl(pctrl->regs + (u32)address);
1686         else
1687                 ret = AE_BAD_PARAMETER;
1688
1689         raw_spin_unlock_irqrestore(&chv_lock, flags);
1690
1691         return ret;
1692 }
1693
1694 static int chv_pinctrl_probe(struct platform_device *pdev)
1695 {
1696         struct chv_pinctrl *pctrl;
1697         struct acpi_device *adev;
1698         acpi_status status;
1699         int ret, irq, i;
1700
1701         adev = ACPI_COMPANION(&pdev->dev);
1702         if (!adev)
1703                 return -ENODEV;
1704
1705         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1706         if (!pctrl)
1707                 return -ENOMEM;
1708
1709         for (i = 0; i < ARRAY_SIZE(chv_communities); i++)
1710                 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) {
1711                         pctrl->community = chv_communities[i];
1712                         break;
1713                 }
1714         if (i == ARRAY_SIZE(chv_communities))
1715                 return -ENODEV;
1716
1717         pctrl->dev = &pdev->dev;
1718
1719 #ifdef CONFIG_PM_SLEEP
1720         pctrl->saved_pin_context = devm_kcalloc(pctrl->dev,
1721                 pctrl->community->npins, sizeof(*pctrl->saved_pin_context),
1722                 GFP_KERNEL);
1723         if (!pctrl->saved_pin_context)
1724                 return -ENOMEM;
1725 #endif
1726
1727         pctrl->regs = devm_platform_ioremap_resource(pdev, 0);
1728         if (IS_ERR(pctrl->regs))
1729                 return PTR_ERR(pctrl->regs);
1730
1731         irq = platform_get_irq(pdev, 0);
1732         if (irq < 0)
1733                 return irq;
1734
1735         pctrl->pctldesc = chv_pinctrl_desc;
1736         pctrl->pctldesc.name = dev_name(&pdev->dev);
1737         pctrl->pctldesc.pins = pctrl->community->pins;
1738         pctrl->pctldesc.npins = pctrl->community->npins;
1739
1740         pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1741                                                pctrl);
1742         if (IS_ERR(pctrl->pctldev)) {
1743                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1744                 return PTR_ERR(pctrl->pctldev);
1745         }
1746
1747         ret = chv_gpio_probe(pctrl, irq);
1748         if (ret)
1749                 return ret;
1750
1751         status = acpi_install_address_space_handler(adev->handle,
1752                                         pctrl->community->acpi_space_id,
1753                                         chv_pinctrl_mmio_access_handler,
1754                                         NULL, pctrl);
1755         if (ACPI_FAILURE(status))
1756                 dev_err(&pdev->dev, "failed to install ACPI addr space handler\n");
1757
1758         platform_set_drvdata(pdev, pctrl);
1759
1760         return 0;
1761 }
1762
1763 static int chv_pinctrl_remove(struct platform_device *pdev)
1764 {
1765         struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1766
1767         acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
1768                                           pctrl->community->acpi_space_id,
1769                                           chv_pinctrl_mmio_access_handler);
1770
1771         return 0;
1772 }
1773
1774 #ifdef CONFIG_PM_SLEEP
1775 static int chv_pinctrl_suspend_noirq(struct device *dev)
1776 {
1777         struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
1778         unsigned long flags;
1779         int i;
1780
1781         raw_spin_lock_irqsave(&chv_lock, flags);
1782
1783         pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
1784
1785         for (i = 0; i < pctrl->community->npins; i++) {
1786                 const struct pinctrl_pin_desc *desc;
1787                 struct chv_pin_context *ctx;
1788                 void __iomem *reg;
1789
1790                 desc = &pctrl->community->pins[i];
1791                 if (chv_pad_locked(pctrl, desc->number))
1792                         continue;
1793
1794                 ctx = &pctrl->saved_pin_context[i];
1795
1796                 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1797                 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1798
1799                 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1800                 ctx->padctrl1 = readl(reg);
1801         }
1802
1803         raw_spin_unlock_irqrestore(&chv_lock, flags);
1804
1805         return 0;
1806 }
1807
1808 static int chv_pinctrl_resume_noirq(struct device *dev)
1809 {
1810         struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
1811         unsigned long flags;
1812         int i;
1813
1814         raw_spin_lock_irqsave(&chv_lock, flags);
1815
1816         /*
1817          * Mask all interrupts before restoring per-pin configuration
1818          * registers because we don't know in which state BIOS left them
1819          * upon exiting suspend.
1820          */
1821         chv_writel(0, pctrl->regs + CHV_INTMASK);
1822
1823         for (i = 0; i < pctrl->community->npins; i++) {
1824                 const struct pinctrl_pin_desc *desc;
1825                 const struct chv_pin_context *ctx;
1826                 void __iomem *reg;
1827                 u32 val;
1828
1829                 desc = &pctrl->community->pins[i];
1830                 if (chv_pad_locked(pctrl, desc->number))
1831                         continue;
1832
1833                 ctx = &pctrl->saved_pin_context[i];
1834
1835                 /* Only restore if our saved state differs from the current */
1836                 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1837                 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1838                 if (ctx->padctrl0 != val) {
1839                         chv_writel(ctx->padctrl0, reg);
1840                         dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1841                                 desc->number, readl(reg));
1842                 }
1843
1844                 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1845                 val = readl(reg);
1846                 if (ctx->padctrl1 != val) {
1847                         chv_writel(ctx->padctrl1, reg);
1848                         dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1849                                 desc->number, readl(reg));
1850                 }
1851         }
1852
1853         /*
1854          * Now that all pins are restored to known state, we can restore
1855          * the interrupt mask register as well.
1856          */
1857         chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1858         chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
1859
1860         raw_spin_unlock_irqrestore(&chv_lock, flags);
1861
1862         return 0;
1863 }
1864 #endif
1865
1866 static const struct dev_pm_ops chv_pinctrl_pm_ops = {
1867         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
1868                                       chv_pinctrl_resume_noirq)
1869 };
1870
1871 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1872         { "INT33FF" },
1873         { }
1874 };
1875 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1876
1877 static struct platform_driver chv_pinctrl_driver = {
1878         .probe = chv_pinctrl_probe,
1879         .remove = chv_pinctrl_remove,
1880         .driver = {
1881                 .name = "cherryview-pinctrl",
1882                 .pm = &chv_pinctrl_pm_ops,
1883                 .acpi_match_table = chv_pinctrl_acpi_match,
1884         },
1885 };
1886
1887 static int __init chv_pinctrl_init(void)
1888 {
1889         return platform_driver_register(&chv_pinctrl_driver);
1890 }
1891 subsys_initcall(chv_pinctrl_init);
1892
1893 static void __exit chv_pinctrl_exit(void)
1894 {
1895         platform_driver_unregister(&chv_pinctrl_driver);
1896 }
1897 module_exit(chv_pinctrl_exit);
1898
1899 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1900 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1901 MODULE_LICENSE("GPL v2");