1 // SPDX-License-Identifier: GPL-2.0
3 * Intel pinctrl/GPIO core driver.
5 * Copyright (C) 2015, Intel Corporation
6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
10 #include <linux/acpi.h>
11 #include <linux/interrupt.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/log2.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/property.h>
17 #include <linux/time.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/pinctrl/pinconf-generic.h>
25 #include "pinctrl-intel.h"
27 /* Offset from regs */
29 #define REVID_SHIFT 16
30 #define REVID_MASK GENMASK(31, 16)
35 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
36 #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p))
37 #define PADOWN_GPP(p) ((p) / 8)
39 /* Offset from pad_regs */
41 #define PADCFG0_RXEVCFG_SHIFT 25
42 #define PADCFG0_RXEVCFG_MASK GENMASK(26, 25)
43 #define PADCFG0_RXEVCFG_LEVEL 0
44 #define PADCFG0_RXEVCFG_EDGE 1
45 #define PADCFG0_RXEVCFG_DISABLED 2
46 #define PADCFG0_RXEVCFG_EDGE_BOTH 3
47 #define PADCFG0_PREGFRXSEL BIT(24)
48 #define PADCFG0_RXINV BIT(23)
49 #define PADCFG0_GPIROUTIOXAPIC BIT(20)
50 #define PADCFG0_GPIROUTSCI BIT(19)
51 #define PADCFG0_GPIROUTSMI BIT(18)
52 #define PADCFG0_GPIROUTNMI BIT(17)
53 #define PADCFG0_PMODE_SHIFT 10
54 #define PADCFG0_PMODE_MASK GENMASK(13, 10)
55 #define PADCFG0_PMODE_GPIO 0
56 #define PADCFG0_GPIORXDIS BIT(9)
57 #define PADCFG0_GPIOTXDIS BIT(8)
58 #define PADCFG0_GPIORXSTATE BIT(1)
59 #define PADCFG0_GPIOTXSTATE BIT(0)
62 #define PADCFG1_TERM_UP BIT(13)
63 #define PADCFG1_TERM_SHIFT 10
64 #define PADCFG1_TERM_MASK GENMASK(12, 10)
65 #define PADCFG1_TERM_20K 4
66 #define PADCFG1_TERM_2K 3
67 #define PADCFG1_TERM_5K 2
68 #define PADCFG1_TERM_1K 1
71 #define PADCFG2_DEBEN BIT(0)
72 #define PADCFG2_DEBOUNCE_SHIFT 1
73 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
75 #define DEBOUNCE_PERIOD_NSEC 31250
77 struct intel_pad_context {
83 struct intel_community_context {
88 struct intel_pinctrl_context {
89 struct intel_pad_context *pads;
90 struct intel_community_context *communities;
94 * struct intel_pinctrl - Intel pinctrl private structure
95 * @dev: Pointer to the device structure
96 * @lock: Lock to serialize register access
97 * @pctldesc: Pin controller description
98 * @pctldev: Pointer to the pin controller device
99 * @chip: GPIO chip in this pin controller
100 * @irqchip: IRQ chip in this pin controller
101 * @soc: SoC/PCH specific pin configuration data
102 * @communities: All communities in this pin controller
103 * @ncommunities: Number of communities in this pin controller
104 * @context: Configuration saved over system sleep
105 * @irq: pinctrl/GPIO chip irq number
107 struct intel_pinctrl {
110 struct pinctrl_desc pctldesc;
111 struct pinctrl_dev *pctldev;
112 struct gpio_chip chip;
113 struct irq_chip irqchip;
114 const struct intel_pinctrl_soc_data *soc;
115 struct intel_community *communities;
117 struct intel_pinctrl_context context;
121 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
122 #define padgroup_offset(g, p) ((p) - (g)->base)
124 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
127 struct intel_community *community;
130 for (i = 0; i < pctrl->ncommunities; i++) {
131 community = &pctrl->communities[i];
132 if (pin >= community->pin_base &&
133 pin < community->pin_base + community->npins)
137 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
141 static const struct intel_padgroup *
142 intel_community_get_padgroup(const struct intel_community *community,
147 for (i = 0; i < community->ngpps; i++) {
148 const struct intel_padgroup *padgrp = &community->gpps[i];
150 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
157 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
158 unsigned int pin, unsigned int reg)
160 const struct intel_community *community;
164 community = intel_get_community(pctrl, pin);
168 padno = pin_to_padno(community, pin);
169 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
171 if (reg >= nregs * 4)
174 return community->pad_regs + reg + padno * nregs * 4;
177 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
179 const struct intel_community *community;
180 const struct intel_padgroup *padgrp;
181 unsigned int gpp, offset, gpp_offset;
182 void __iomem *padown;
184 community = intel_get_community(pctrl, pin);
187 if (!community->padown_offset)
190 padgrp = intel_community_get_padgroup(community, pin);
194 gpp_offset = padgroup_offset(padgrp, pin);
195 gpp = PADOWN_GPP(gpp_offset);
196 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
197 padown = community->regs + offset;
199 return !(readl(padown) & PADOWN_MASK(gpp_offset));
202 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
204 const struct intel_community *community;
205 const struct intel_padgroup *padgrp;
206 unsigned int offset, gpp_offset;
207 void __iomem *hostown;
209 community = intel_get_community(pctrl, pin);
212 if (!community->hostown_offset)
215 padgrp = intel_community_get_padgroup(community, pin);
219 gpp_offset = padgroup_offset(padgrp, pin);
220 offset = community->hostown_offset + padgrp->reg_num * 4;
221 hostown = community->regs + offset;
223 return !(readl(hostown) & BIT(gpp_offset));
227 * enum - Locking variants of the pad configuration
229 * @PAD_UNLOCKED: pad is fully controlled by the configuration registers
230 * @PAD_LOCKED: pad configuration registers, except TX state, are locked
231 * @PAD_LOCKED_TX: pad configuration TX state is locked
232 * @PAD_LOCKED_FULL: pad configuration registers are locked completely
234 * Locking is considered as read-only mode for corresponding registers and
235 * their respective fields. That said, TX state bit is locked separately from
236 * the main locking scheme.
242 PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
245 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
247 struct intel_community *community;
248 const struct intel_padgroup *padgrp;
249 unsigned int offset, gpp_offset;
251 int ret = PAD_UNLOCKED;
253 community = intel_get_community(pctrl, pin);
255 return PAD_LOCKED_FULL;
256 if (!community->padcfglock_offset)
259 padgrp = intel_community_get_padgroup(community, pin);
261 return PAD_LOCKED_FULL;
263 gpp_offset = padgroup_offset(padgrp, pin);
266 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
267 * the pad is considered unlocked. Any other case means that it is
268 * either fully or partially locked.
270 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
271 value = readl(community->regs + offset);
272 if (value & BIT(gpp_offset))
275 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
276 value = readl(community->regs + offset);
277 if (value & BIT(gpp_offset))
278 ret |= PAD_LOCKED_TX;
283 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
285 return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
288 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
290 return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
293 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
295 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
297 return pctrl->soc->ngroups;
300 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
303 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
305 return pctrl->soc->groups[group].name;
308 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
309 const unsigned int **pins, unsigned int *npins)
311 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
313 *pins = pctrl->soc->groups[group].pins;
314 *npins = pctrl->soc->groups[group].npins;
318 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
321 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
322 void __iomem *padcfg;
323 u32 cfg0, cfg1, mode;
327 if (!intel_pad_owned_by_host(pctrl, pin)) {
328 seq_puts(s, "not available");
332 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
333 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
335 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
336 if (mode == PADCFG0_PMODE_GPIO)
337 seq_puts(s, "GPIO ");
339 seq_printf(s, "mode %d ", mode);
341 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
343 /* Dump the additional PADCFG registers if available */
344 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
346 seq_printf(s, " 0x%08x", readl(padcfg));
348 locked = intel_pad_locked(pctrl, pin);
349 acpi = intel_pad_acpi_mode(pctrl, pin);
351 if (locked || acpi) {
354 seq_puts(s, "LOCKED");
355 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
357 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
358 seq_puts(s, " full");
369 static const struct pinctrl_ops intel_pinctrl_ops = {
370 .get_groups_count = intel_get_groups_count,
371 .get_group_name = intel_get_group_name,
372 .get_group_pins = intel_get_group_pins,
373 .pin_dbg_show = intel_pin_dbg_show,
376 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
378 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
380 return pctrl->soc->nfunctions;
383 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
384 unsigned int function)
386 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
388 return pctrl->soc->functions[function].name;
391 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
392 unsigned int function,
393 const char * const **groups,
394 unsigned int * const ngroups)
396 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
398 *groups = pctrl->soc->functions[function].groups;
399 *ngroups = pctrl->soc->functions[function].ngroups;
403 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
404 unsigned int function, unsigned int group)
406 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
407 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
411 raw_spin_lock_irqsave(&pctrl->lock, flags);
414 * All pins in the groups needs to be accessible and writable
415 * before we can enable the mux for this group.
417 for (i = 0; i < grp->npins; i++) {
418 if (!intel_pad_usable(pctrl, grp->pins[i])) {
419 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
424 /* Now enable the mux setting for each pin in the group */
425 for (i = 0; i < grp->npins; i++) {
426 void __iomem *padcfg0;
429 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
430 value = readl(padcfg0);
432 value &= ~PADCFG0_PMODE_MASK;
435 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
437 value |= grp->mode << PADCFG0_PMODE_SHIFT;
439 writel(value, padcfg0);
442 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
447 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
451 value = readl(padcfg0);
453 value &= ~PADCFG0_GPIORXDIS;
454 value |= PADCFG0_GPIOTXDIS;
456 value &= ~PADCFG0_GPIOTXDIS;
457 value |= PADCFG0_GPIORXDIS;
459 writel(value, padcfg0);
462 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
464 return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
467 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
471 /* Put the pad into GPIO mode */
472 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
473 /* Disable SCI/SMI/NMI generation */
474 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
475 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
476 writel(value, padcfg0);
479 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
480 struct pinctrl_gpio_range *range,
483 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
484 void __iomem *padcfg0;
487 raw_spin_lock_irqsave(&pctrl->lock, flags);
489 if (!intel_pad_owned_by_host(pctrl, pin)) {
490 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
494 if (!intel_pad_is_unlocked(pctrl, pin)) {
495 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
499 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
502 * If pin is already configured in GPIO mode, we assume that
503 * firmware provides correct settings. In such case we avoid
504 * potential glitches on the pin. Otherwise, for the pin in
505 * alternative mode, consumer has to supply respective flags.
507 if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
508 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
512 intel_gpio_set_gpio_mode(padcfg0);
514 /* Disable TX buffer and enable RX (this will be input) */
515 __intel_gpio_set_direction(padcfg0, true);
517 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
522 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
523 struct pinctrl_gpio_range *range,
524 unsigned int pin, bool input)
526 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
527 void __iomem *padcfg0;
530 raw_spin_lock_irqsave(&pctrl->lock, flags);
532 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
533 __intel_gpio_set_direction(padcfg0, input);
535 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
540 static const struct pinmux_ops intel_pinmux_ops = {
541 .get_functions_count = intel_get_functions_count,
542 .get_function_name = intel_get_function_name,
543 .get_function_groups = intel_get_function_groups,
544 .set_mux = intel_pinmux_set_mux,
545 .gpio_request_enable = intel_gpio_request_enable,
546 .gpio_set_direction = intel_gpio_set_direction,
549 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
550 unsigned long *config)
552 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
553 enum pin_config_param param = pinconf_to_config_param(*config);
554 const struct intel_community *community;
558 if (!intel_pad_owned_by_host(pctrl, pin))
561 community = intel_get_community(pctrl, pin);
562 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
563 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
566 case PIN_CONFIG_BIAS_DISABLE:
571 case PIN_CONFIG_BIAS_PULL_UP:
572 if (!term || !(value & PADCFG1_TERM_UP))
576 case PADCFG1_TERM_1K:
579 case PADCFG1_TERM_2K:
582 case PADCFG1_TERM_5K:
585 case PADCFG1_TERM_20K:
592 case PIN_CONFIG_BIAS_PULL_DOWN:
593 if (!term || value & PADCFG1_TERM_UP)
597 case PADCFG1_TERM_1K:
598 if (!(community->features & PINCTRL_FEATURE_1K_PD))
602 case PADCFG1_TERM_5K:
605 case PADCFG1_TERM_20K:
612 case PIN_CONFIG_INPUT_DEBOUNCE: {
613 void __iomem *padcfg2;
616 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
621 if (!(v & PADCFG2_DEBEN))
624 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
625 arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
634 *config = pinconf_to_config_packed(param, arg);
638 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
639 unsigned long config)
641 unsigned int param = pinconf_to_config_param(config);
642 unsigned int arg = pinconf_to_config_argument(config);
643 const struct intel_community *community;
644 void __iomem *padcfg1;
649 raw_spin_lock_irqsave(&pctrl->lock, flags);
651 community = intel_get_community(pctrl, pin);
652 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
653 value = readl(padcfg1);
656 case PIN_CONFIG_BIAS_DISABLE:
657 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
660 case PIN_CONFIG_BIAS_PULL_UP:
661 value &= ~PADCFG1_TERM_MASK;
663 value |= PADCFG1_TERM_UP;
667 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
670 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
673 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
676 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
684 case PIN_CONFIG_BIAS_PULL_DOWN:
685 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
689 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
692 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
695 if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
699 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
709 writel(value, padcfg1);
711 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
716 static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
717 unsigned int pin, unsigned int debounce)
719 void __iomem *padcfg0, *padcfg2;
724 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
728 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
730 raw_spin_lock_irqsave(&pctrl->lock, flags);
732 value0 = readl(padcfg0);
733 value2 = readl(padcfg2);
735 /* Disable glitch filter and debouncer */
736 value0 &= ~PADCFG0_PREGFRXSEL;
737 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
742 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
743 if (v < 3 || v > 15) {
747 /* Enable glitch filter and debouncer */
748 value0 |= PADCFG0_PREGFRXSEL;
749 value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
750 value2 |= PADCFG2_DEBEN;
754 writel(value0, padcfg0);
755 writel(value2, padcfg2);
758 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
763 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
764 unsigned long *configs, unsigned int nconfigs)
766 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
769 if (!intel_pad_usable(pctrl, pin))
772 for (i = 0; i < nconfigs; i++) {
773 switch (pinconf_to_config_param(configs[i])) {
774 case PIN_CONFIG_BIAS_DISABLE:
775 case PIN_CONFIG_BIAS_PULL_UP:
776 case PIN_CONFIG_BIAS_PULL_DOWN:
777 ret = intel_config_set_pull(pctrl, pin, configs[i]);
782 case PIN_CONFIG_INPUT_DEBOUNCE:
783 ret = intel_config_set_debounce(pctrl, pin,
784 pinconf_to_config_argument(configs[i]));
797 static const struct pinconf_ops intel_pinconf_ops = {
799 .pin_config_get = intel_config_get,
800 .pin_config_set = intel_config_set,
803 static const struct pinctrl_desc intel_pinctrl_desc = {
804 .pctlops = &intel_pinctrl_ops,
805 .pmxops = &intel_pinmux_ops,
806 .confops = &intel_pinconf_ops,
807 .owner = THIS_MODULE,
811 * intel_gpio_to_pin() - Translate from GPIO offset to pin number
812 * @pctrl: Pinctrl structure
813 * @offset: GPIO offset from gpiolib
814 * @community: Community is filled here if not %NULL
815 * @padgrp: Pad group is filled here if not %NULL
817 * When coming through gpiolib irqchip, the GPIO offset is not
818 * automatically translated to pinctrl pin number. This function can be
819 * used to find out the corresponding pinctrl pin.
821 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
822 const struct intel_community **community,
823 const struct intel_padgroup **padgrp)
827 for (i = 0; i < pctrl->ncommunities; i++) {
828 const struct intel_community *comm = &pctrl->communities[i];
831 for (j = 0; j < comm->ngpps; j++) {
832 const struct intel_padgroup *pgrp = &comm->gpps[j];
834 if (pgrp->gpio_base < 0)
837 if (offset >= pgrp->gpio_base &&
838 offset < pgrp->gpio_base + pgrp->size) {
841 pin = pgrp->base + offset - pgrp->gpio_base;
856 * intel_pin_to_gpio() - Translate from pin number to GPIO offset
857 * @pctrl: Pinctrl structure
860 * Translate the pin number of pinctrl to GPIO offset
862 static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
864 const struct intel_community *community;
865 const struct intel_padgroup *padgrp;
867 community = intel_get_community(pctrl, pin);
871 padgrp = intel_community_get_padgroup(community, pin);
875 return pin - padgrp->base + padgrp->gpio_base;
878 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
880 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
885 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
889 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
893 padcfg0 = readl(reg);
894 if (!(padcfg0 & PADCFG0_GPIOTXDIS))
895 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
897 return !!(padcfg0 & PADCFG0_GPIORXSTATE);
900 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
903 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
909 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
913 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
917 raw_spin_lock_irqsave(&pctrl->lock, flags);
918 padcfg0 = readl(reg);
920 padcfg0 |= PADCFG0_GPIOTXSTATE;
922 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
923 writel(padcfg0, reg);
924 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
927 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
929 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
934 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
938 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
942 padcfg0 = readl(reg);
944 if (padcfg0 & PADCFG0_PMODE_MASK)
947 return !!(padcfg0 & PADCFG0_GPIOTXDIS);
950 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
952 return pinctrl_gpio_direction_input(chip->base + offset);
955 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
958 intel_gpio_set(chip, offset, value);
959 return pinctrl_gpio_direction_output(chip->base + offset);
962 static const struct gpio_chip intel_gpio_chip = {
963 .owner = THIS_MODULE,
964 .request = gpiochip_generic_request,
965 .free = gpiochip_generic_free,
966 .get_direction = intel_gpio_get_direction,
967 .direction_input = intel_gpio_direction_input,
968 .direction_output = intel_gpio_direction_output,
969 .get = intel_gpio_get,
970 .set = intel_gpio_set,
971 .set_config = gpiochip_generic_config,
974 static void intel_gpio_irq_ack(struct irq_data *d)
976 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
977 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
978 const struct intel_community *community;
979 const struct intel_padgroup *padgrp;
982 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
984 unsigned int gpp, gpp_offset, is_offset;
986 gpp = padgrp->reg_num;
987 gpp_offset = padgroup_offset(padgrp, pin);
988 is_offset = community->is_offset + gpp * 4;
990 raw_spin_lock(&pctrl->lock);
991 writel(BIT(gpp_offset), community->regs + is_offset);
992 raw_spin_unlock(&pctrl->lock);
996 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
998 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
999 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1000 const struct intel_community *community;
1001 const struct intel_padgroup *padgrp;
1004 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
1006 unsigned int gpp, gpp_offset;
1007 unsigned long flags;
1008 void __iomem *reg, *is;
1011 gpp = padgrp->reg_num;
1012 gpp_offset = padgroup_offset(padgrp, pin);
1014 reg = community->regs + community->ie_offset + gpp * 4;
1015 is = community->regs + community->is_offset + gpp * 4;
1017 raw_spin_lock_irqsave(&pctrl->lock, flags);
1019 /* Clear interrupt status first to avoid unexpected interrupt */
1020 writel(BIT(gpp_offset), is);
1024 value &= ~BIT(gpp_offset);
1026 value |= BIT(gpp_offset);
1028 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1032 static void intel_gpio_irq_mask(struct irq_data *d)
1034 intel_gpio_irq_mask_unmask(d, true);
1037 static void intel_gpio_irq_unmask(struct irq_data *d)
1039 intel_gpio_irq_mask_unmask(d, false);
1042 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1044 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1045 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1046 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1047 unsigned long flags;
1051 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1056 * If the pin is in ACPI mode it is still usable as a GPIO but it
1057 * cannot be used as IRQ because GPI_IS status bit will not be
1058 * updated by the host controller hardware.
1060 if (intel_pad_acpi_mode(pctrl, pin)) {
1061 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1065 raw_spin_lock_irqsave(&pctrl->lock, flags);
1067 intel_gpio_set_gpio_mode(reg);
1071 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1073 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1074 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1075 } else if (type & IRQ_TYPE_EDGE_FALLING) {
1076 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1077 value |= PADCFG0_RXINV;
1078 } else if (type & IRQ_TYPE_EDGE_RISING) {
1079 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1080 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1081 if (type & IRQ_TYPE_LEVEL_LOW)
1082 value |= PADCFG0_RXINV;
1084 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1089 if (type & IRQ_TYPE_EDGE_BOTH)
1090 irq_set_handler_locked(d, handle_edge_irq);
1091 else if (type & IRQ_TYPE_LEVEL_MASK)
1092 irq_set_handler_locked(d, handle_level_irq);
1094 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1099 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1101 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1102 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1103 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1106 enable_irq_wake(pctrl->irq);
1108 disable_irq_wake(pctrl->irq);
1110 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1114 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1115 const struct intel_community *community)
1117 struct gpio_chip *gc = &pctrl->chip;
1118 irqreturn_t ret = IRQ_NONE;
1121 for (gpp = 0; gpp < community->ngpps; gpp++) {
1122 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1123 unsigned long pending, enabled, gpp_offset;
1125 pending = readl(community->regs + community->is_offset +
1126 padgrp->reg_num * 4);
1127 enabled = readl(community->regs + community->ie_offset +
1128 padgrp->reg_num * 4);
1130 /* Only interrupts that are enabled */
1133 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1136 irq = irq_find_mapping(gc->irq.domain,
1137 padgrp->gpio_base + gpp_offset);
1138 generic_handle_irq(irq);
1147 static irqreturn_t intel_gpio_irq(int irq, void *data)
1149 const struct intel_community *community;
1150 struct intel_pinctrl *pctrl = data;
1151 irqreturn_t ret = IRQ_NONE;
1154 /* Need to check all communities for pending interrupts */
1155 for (i = 0; i < pctrl->ncommunities; i++) {
1156 community = &pctrl->communities[i];
1157 ret |= intel_gpio_community_irq_handler(pctrl, community);
1163 static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
1164 const struct intel_community *community)
1168 for (i = 0; i < community->ngpps; i++) {
1169 const struct intel_padgroup *gpp = &community->gpps[i];
1171 if (gpp->gpio_base < 0)
1174 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1175 gpp->gpio_base, gpp->base,
1184 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1186 const struct intel_community *community;
1187 unsigned int ngpio = 0;
1190 for (i = 0; i < pctrl->ncommunities; i++) {
1191 community = &pctrl->communities[i];
1192 for (j = 0; j < community->ngpps; j++) {
1193 const struct intel_padgroup *gpp = &community->gpps[j];
1195 if (gpp->gpio_base < 0)
1198 if (gpp->gpio_base + gpp->size > ngpio)
1199 ngpio = gpp->gpio_base + gpp->size;
1206 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1210 pctrl->chip = intel_gpio_chip;
1212 /* Setup GPIO chip */
1213 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1214 pctrl->chip.label = dev_name(pctrl->dev);
1215 pctrl->chip.parent = pctrl->dev;
1216 pctrl->chip.base = -1;
1219 /* Setup IRQ chip */
1220 pctrl->irqchip.name = dev_name(pctrl->dev);
1221 pctrl->irqchip.irq_ack = intel_gpio_irq_ack;
1222 pctrl->irqchip.irq_mask = intel_gpio_irq_mask;
1223 pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask;
1224 pctrl->irqchip.irq_set_type = intel_gpio_irq_type;
1225 pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake;
1226 pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND;
1228 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1230 dev_err(pctrl->dev, "failed to register gpiochip\n");
1234 for (i = 0; i < pctrl->ncommunities; i++) {
1235 struct intel_community *community = &pctrl->communities[i];
1237 ret = intel_gpio_add_pin_ranges(pctrl, community);
1239 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1245 * We need to request the interrupt here (instead of providing chip
1246 * to the irq directly) because on some platforms several GPIO
1247 * controllers share the same interrupt line.
1249 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1250 IRQF_SHARED | IRQF_NO_THREAD,
1251 dev_name(pctrl->dev), pctrl);
1253 dev_err(pctrl->dev, "failed to request interrupt\n");
1257 ret = gpiochip_irqchip_add(&pctrl->chip, &pctrl->irqchip, 0,
1258 handle_bad_irq, IRQ_TYPE_NONE);
1260 dev_err(pctrl->dev, "failed to add irqchip\n");
1264 gpiochip_set_chained_irqchip(&pctrl->chip, &pctrl->irqchip, irq, NULL);
1268 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1269 struct intel_community *community)
1271 struct intel_padgroup *gpps;
1272 unsigned int npins = community->npins;
1273 unsigned int padown_num = 0;
1276 if (community->gpps)
1277 ngpps = community->ngpps;
1279 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1281 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1285 for (i = 0; i < ngpps; i++) {
1286 if (community->gpps) {
1287 gpps[i] = community->gpps[i];
1289 unsigned int gpp_size = community->gpp_size;
1291 gpps[i].reg_num = i;
1292 gpps[i].base = community->pin_base + i * gpp_size;
1293 gpps[i].size = min(gpp_size, npins);
1294 npins -= gpps[i].size;
1297 if (gpps[i].size > 32)
1300 if (!gpps[i].gpio_base)
1301 gpps[i].gpio_base = gpps[i].base;
1303 gpps[i].padown_num = padown_num;
1306 * In older hardware the number of padown registers per
1307 * group is fixed regardless of the group size.
1309 if (community->gpp_num_padown_regs)
1310 padown_num += community->gpp_num_padown_regs;
1312 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1315 community->ngpps = ngpps;
1316 community->gpps = gpps;
1321 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1323 #ifdef CONFIG_PM_SLEEP
1324 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1325 struct intel_community_context *communities;
1326 struct intel_pad_context *pads;
1329 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1333 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1334 sizeof(*communities), GFP_KERNEL);
1339 for (i = 0; i < pctrl->ncommunities; i++) {
1340 struct intel_community *community = &pctrl->communities[i];
1341 u32 *intmask, *hostown;
1343 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1344 sizeof(*intmask), GFP_KERNEL);
1348 communities[i].intmask = intmask;
1350 hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1351 sizeof(*hostown), GFP_KERNEL);
1355 communities[i].hostown = hostown;
1358 pctrl->context.pads = pads;
1359 pctrl->context.communities = communities;
1365 static int intel_pinctrl_probe(struct platform_device *pdev,
1366 const struct intel_pinctrl_soc_data *soc_data)
1368 struct intel_pinctrl *pctrl;
1374 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1378 pctrl->dev = &pdev->dev;
1379 pctrl->soc = soc_data;
1380 raw_spin_lock_init(&pctrl->lock);
1383 * Make a copy of the communities which we can use to hold pointers
1386 pctrl->ncommunities = pctrl->soc->ncommunities;
1387 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1388 sizeof(*pctrl->communities), GFP_KERNEL);
1389 if (!pctrl->communities)
1392 for (i = 0; i < pctrl->ncommunities; i++) {
1393 struct intel_community *community = &pctrl->communities[i];
1397 *community = pctrl->soc->communities[i];
1399 regs = devm_platform_ioremap_resource(pdev, community->barno);
1401 return PTR_ERR(regs);
1404 * Determine community features based on the revision if
1405 * not specified already.
1407 if (!community->features) {
1410 rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1412 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1413 community->features |= PINCTRL_FEATURE_1K_PD;
1417 /* Read offset of the pad configuration registers */
1418 padbar = readl(regs + PADBAR);
1420 community->regs = regs;
1421 community->pad_regs = regs + padbar;
1423 ret = intel_pinctrl_add_padgroups(pctrl, community);
1428 irq = platform_get_irq(pdev, 0);
1432 ret = intel_pinctrl_pm_init(pctrl);
1436 pctrl->pctldesc = intel_pinctrl_desc;
1437 pctrl->pctldesc.name = dev_name(&pdev->dev);
1438 pctrl->pctldesc.pins = pctrl->soc->pins;
1439 pctrl->pctldesc.npins = pctrl->soc->npins;
1441 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1443 if (IS_ERR(pctrl->pctldev)) {
1444 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1445 return PTR_ERR(pctrl->pctldev);
1448 ret = intel_gpio_probe(pctrl, irq);
1452 platform_set_drvdata(pdev, pctrl);
1457 int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1459 const struct intel_pinctrl_soc_data *data;
1461 data = device_get_match_data(&pdev->dev);
1462 return intel_pinctrl_probe(pdev, data);
1464 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid);
1466 int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
1468 const struct intel_pinctrl_soc_data *data = NULL;
1469 const struct intel_pinctrl_soc_data **table;
1470 struct acpi_device *adev;
1473 adev = ACPI_COMPANION(&pdev->dev);
1475 const void *match = device_get_match_data(&pdev->dev);
1477 table = (const struct intel_pinctrl_soc_data **)match;
1478 for (i = 0; table[i]; i++) {
1479 if (!strcmp(adev->pnp.unique_id, table[i]->uid)) {
1485 const struct platform_device_id *id;
1487 id = platform_get_device_id(pdev);
1491 table = (const struct intel_pinctrl_soc_data **)id->driver_data;
1492 data = table[pdev->id];
1495 return intel_pinctrl_probe(pdev, data);
1497 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
1499 #ifdef CONFIG_PM_SLEEP
1500 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1502 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1504 if (!pd || !intel_pad_usable(pctrl, pin))
1508 * Only restore the pin if it is actually in use by the kernel (or
1509 * by userspace). It is possible that some pins are used by the
1510 * BIOS during resume and those are not always locked down so leave
1513 if (pd->mux_owner || pd->gpio_owner ||
1514 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))
1520 int intel_pinctrl_suspend_noirq(struct device *dev)
1522 struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1523 struct intel_community_context *communities;
1524 struct intel_pad_context *pads;
1527 pads = pctrl->context.pads;
1528 for (i = 0; i < pctrl->soc->npins; i++) {
1529 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1530 void __iomem *padcfg;
1533 if (!intel_pinctrl_should_save(pctrl, desc->number))
1536 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1537 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1538 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1539 pads[i].padcfg1 = val;
1541 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1543 pads[i].padcfg2 = readl(padcfg);
1546 communities = pctrl->context.communities;
1547 for (i = 0; i < pctrl->ncommunities; i++) {
1548 struct intel_community *community = &pctrl->communities[i];
1552 base = community->regs + community->ie_offset;
1553 for (gpp = 0; gpp < community->ngpps; gpp++)
1554 communities[i].intmask[gpp] = readl(base + gpp * 4);
1556 base = community->regs + community->hostown_offset;
1557 for (gpp = 0; gpp < community->ngpps; gpp++)
1558 communities[i].hostown[gpp] = readl(base + gpp * 4);
1563 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
1565 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1569 for (i = 0; i < pctrl->ncommunities; i++) {
1570 const struct intel_community *community;
1574 community = &pctrl->communities[i];
1575 base = community->regs;
1577 for (gpp = 0; gpp < community->ngpps; gpp++) {
1578 /* Mask and clear all interrupts */
1579 writel(0, base + community->ie_offset + gpp * 4);
1580 writel(0xffff, base + community->is_offset + gpp * 4);
1586 intel_gpio_is_requested(struct gpio_chip *chip, int base, unsigned int size)
1591 for (i = 0; i < size; i++)
1592 if (gpiochip_is_requested(chip, base + i))
1593 requested |= BIT(i);
1598 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
1604 updated = (curr & ~mask) | (value & mask);
1605 if (curr == updated)
1608 writel(updated, reg);
1612 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
1613 void __iomem *base, unsigned int gpp, u32 saved)
1615 const struct intel_community *community = &pctrl->communities[c];
1616 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1617 struct device *dev = pctrl->dev;
1620 if (padgrp->gpio_base < 0)
1623 requested = intel_gpio_is_requested(&pctrl->chip, padgrp->gpio_base, padgrp->size);
1624 if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
1627 dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1630 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c,
1631 void __iomem *base, unsigned int gpp, u32 saved)
1633 struct device *dev = pctrl->dev;
1635 if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved))
1638 dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1641 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
1642 unsigned int reg, u32 saved)
1644 u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0;
1645 unsigned int n = reg / sizeof(u32);
1646 struct device *dev = pctrl->dev;
1647 void __iomem *padcfg;
1649 padcfg = intel_get_padcfg(pctrl, pin, reg);
1653 if (!intel_gpio_update_reg(padcfg, ~mask, saved))
1656 dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
1659 int intel_pinctrl_resume_noirq(struct device *dev)
1661 struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1662 const struct intel_community_context *communities;
1663 const struct intel_pad_context *pads;
1666 /* Mask all interrupts */
1667 intel_gpio_irq_init(pctrl);
1669 pads = pctrl->context.pads;
1670 for (i = 0; i < pctrl->soc->npins; i++) {
1671 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1673 if (!intel_pinctrl_should_save(pctrl, desc->number))
1676 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
1677 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);
1678 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);
1681 communities = pctrl->context.communities;
1682 for (i = 0; i < pctrl->ncommunities; i++) {
1683 struct intel_community *community = &pctrl->communities[i];
1687 base = community->regs + community->ie_offset;
1688 for (gpp = 0; gpp < community->ngpps; gpp++)
1689 intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]);
1691 base = community->regs + community->hostown_offset;
1692 for (gpp = 0; gpp < community->ngpps; gpp++)
1693 intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]);
1698 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
1701 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1702 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1703 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1704 MODULE_LICENSE("GPL v2");